[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.h

/** @file\r
  CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.\r
\r
  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _CPU_DXE_H_\r
#define _CPU_DXE_H_\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/Cpu.h>\r
#include <Protocol/MpService.h>\r
#include <Register/Intel/Msr.h>\r
\r
#include <Ppi/SecPlatformInformation.h>\r
#include <Ppi/SecPlatformInformation2.h>\r
\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/CpuLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MtrrLib.h>\r
#include <Library/LocalApicLib.h>\r
#include <Library/UefiCpuLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/CpuExceptionHandlerLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/MpInitLib.h>\r
#include <Library/TimerLib.h>\r
\r
#include <Guid/IdleLoopEvent.h>\r
#include <Guid/VectorHandoffTable.h>\r
\r
#define HEAP_GUARD_NONSTOP_MODE       \\r
        ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT4|BIT1|BIT0)) > BIT6)\r
\r
#define NULL_DETECTION_NONSTOP_MODE   \\r
        ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT0)) > BIT6)\r
\r
/**\r
  Flush CPU data cache. If the instruction cache is fully coherent\r
  with all DMA operations then function can just return EFI_SUCCESS.\r
\r
  @param  This              Protocol instance structure\r
  @param  Start             Physical address to start flushing from.\r
  @param  Length            Number of bytes to flush. Round up to chipset\r
                            granularity.\r
  @param  FlushType         Specifies the type of flush operation to perform.\r
\r
  @retval EFI_SUCCESS       If cache was flushed\r
  @retval EFI_UNSUPPORTED   If flush type is not supported.\r
  @retval EFI_DEVICE_ERROR  If requested range could not be flushed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
  IN EFI_PHYSICAL_ADDRESS   Start,\r
  IN UINT64                 Length,\r
  IN EFI_CPU_FLUSH_TYPE     FlushType\r
  );\r
\r
/**\r
  Enables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were enabled in the CPU\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL  *This\r
  );\r
\r
/**\r
  Disables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were disabled in the CPU.\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL  *This\r
  );\r
\r
/**\r
  Return the state of interrupts.\r
\r
  @param  This                   Protocol instance structure\r
  @param  State                  Pointer to the CPU's current interrupt state\r
\r
  @retval EFI_SUCCESS            If interrupts were disabled in the CPU.\r
  @retval EFI_INVALID_PARAMETER  State is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
  IN  EFI_CPU_ARCH_PROTOCOL  *This,\r
  OUT BOOLEAN                *State\r
  );\r
\r
/**\r
  Generates an INIT to the CPU.\r
\r
  @param  This              Protocol instance structure\r
  @param  InitType          Type of CPU INIT to perform\r
\r
  @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be\r
                            seen.\r
  @retval EFI_DEVICE_ERROR  If CPU INIT failed.\r
  @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
  IN EFI_CPU_INIT_TYPE      InitType\r
  );\r
\r
/**\r
  Registers a function to be called from the CPU interrupt handler.\r
\r
  @param  This                   Protocol instance structure\r
  @param  InterruptType          Defines which interrupt to hook. IA-32\r
                                 valid range is 0x00 through 0xFF\r
  @param  InterruptHandler       A pointer to a function of type\r
                                 EFI_CPU_INTERRUPT_HANDLER that is called\r
                                 when a processor interrupt occurs.  A null\r
                                 pointer is an error condition.\r
\r
  @retval EFI_SUCCESS            If handler installed or uninstalled.\r
  @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler\r
                                 for InterruptType was previously installed.\r
  @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for\r
                                 InterruptType was not previously installed.\r
  @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType\r
                                 is not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
  IN EFI_EXCEPTION_TYPE         InterruptType,\r
  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler\r
  );\r
\r
/**\r
  Returns a timer value from one of the CPU's internal timers. There is no\r
  inherent time interval between ticks but is a function of the CPU frequency.\r
\r
  @param  This                - Protocol instance structure.\r
  @param  TimerIndex          - Specifies which CPU timer is requested.\r
  @param  TimerValue          - Pointer to the returned timer value.\r
  @param  TimerPeriod         - A pointer to the amount of time that passes\r
                                in femtoseconds (10-15) for each increment\r
                                of TimerValue. If TimerValue does not\r
                                increment at a predictable rate, then 0 is\r
                                returned.  The amount of time that has\r
                                passed between two calls to GetTimerValue()\r
                                can be calculated with the formula\r
                                (TimerValue2 - TimerValue1) * TimerPeriod.\r
                                This parameter is optional and may be NULL.\r
\r
  @retval EFI_SUCCESS           - If the CPU timer count was returned.\r
  @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.\r
  @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.\r
  @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
  IN  EFI_CPU_ARCH_PROTOCOL  *This,\r
  IN  UINT32                 TimerIndex,\r
  OUT UINT64                 *TimerValue,\r
  OUT UINT64                 *TimerPeriod OPTIONAL\r
  );\r
\r
/**\r
  Set memory cacheability attributes for given range of memory.\r
\r
  @param  This                   Protocol instance structure\r
  @param  BaseAddress            Specifies the start address of the\r
                                 memory range\r
  @param  Length                 Specifies the length of the memory range\r
  @param  Attributes             The memory cacheability for the memory range\r
\r
  @retval EFI_SUCCESS            If the cacheability of that memory range is\r
                                 set successfully\r
  @retval EFI_UNSUPPORTED        If the desired operation cannot be done\r
  @retval EFI_INVALID_PARAMETER  The input parameter is not correct,\r
                                 such as Length = 0\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuSetMemoryAttributes (\r
  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
  IN EFI_PHYSICAL_ADDRESS   BaseAddress,\r
  IN UINT64                 Length,\r
  IN UINT64                 Attributes\r
  );\r
\r
/**\r
  Initialize Global Descriptor Table.\r
\r
**/\r
VOID\r
InitGlobalDescriptorTable (\r
  VOID\r
  );\r
\r
/**\r
  Sets the code selector (CS).\r
\r
  @param  Selector  Value of code selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetCodeSelector (\r
  UINT16  Selector\r
  );\r
\r
/**\r
  Sets the data selector (DS).\r
\r
  @param  Selector  Value of data selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetDataSelectors (\r
  UINT16  Selector\r
  );\r
\r
/**\r
  Update GCD memory space attributes according to current page table setup.\r
**/\r
VOID\r
RefreshGcdMemoryAttributesFromPaging (\r
  VOID\r
  );\r
\r
/**\r
  Special handler for #DB exception, which will restore the page attributes\r
  (not-present). It should work with #PF handler which will set pages to\r
  'present'.\r
\r
  @param ExceptionType  Exception type.\r
  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.\r
\r
**/\r
VOID\r
EFIAPI\r
DebugExceptionHandler (\r
  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
  IN EFI_SYSTEM_CONTEXT  SystemContext\r
  );\r
\r
/**\r
  Special handler for #PF exception, which will set the pages which caused\r
  #PF to be 'present'. The attribute of those pages should be restored in\r
  the subsequent #DB handler.\r
\r
  @param ExceptionType  Exception type.\r
  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.\r
\r
**/\r
VOID\r
EFIAPI\r
PageFaultExceptionHandler (\r
  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
  IN EFI_SYSTEM_CONTEXT  SystemContext\r
  );\r
\r
extern BOOLEAN  mIsAllocatingPageTable;\r
extern UINTN    mNumberOfProcessors;\r
\r
#endif\r
Commit	Line	Data
a47463f2	1	/** @file\r
7fadaacd	2	CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.\r
a47463f2	3	\r
01acb06c	4	Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
a47463f2	6	\r
	7	**/\r
	8	\r
430fbbe0	9	#ifndef _CPU_DXE_H_\r
430fbbe0	10	#define _CPU_DXE_H_\r
a47463f2	11	\r
	12	#include <PiDxe.h>\r
	13	\r
	14	#include <Protocol/Cpu.h>\r
7fadaacd	15	#include <Protocol/MpService.h>\r
01acb06c	16	#include <Register/Intel/Msr.h>\r
7fadaacd JF	17	\r
	18	#include <Ppi/SecPlatformInformation.h>\r
	19	#include <Ppi/SecPlatformInformation2.h>\r
a47463f2	20	\r
	21	#include <Library/UefiDriverEntryPoint.h>\r
	22	#include <Library/UefiBootServicesTableLib.h>\r
	23	#include <Library/DxeServicesTableLib.h>\r
	24	#include <Library/BaseLib.h>\r
	25	#include <Library/CpuLib.h>\r
	26	#include <Library/BaseMemoryLib.h>\r
	27	#include <Library/MemoryAllocationLib.h>\r
	28	#include <Library/DebugLib.h>\r
	29	#include <Library/MtrrLib.h>\r
d4605c23	30	#include <Library/LocalApicLib.h>\r
661cab5d	31	#include <Library/UefiCpuLib.h>\r
e41aad15 JF	32	#include <Library/UefiLib.h>\r
e41aad15 JF	33	#include <Library/CpuExceptionHandlerLib.h>\r
7fadaacd JF	34	#include <Library/HobLib.h>\r
	35	#include <Library/ReportStatusCodeLib.h>\r
	36	#include <Library/MpInitLib.h>\r
7537f8c0	37	#include <Library/TimerLib.h>\r
7fadaacd	38	\r
32394027	39	#include <Guid/IdleLoopEvent.h>\r
e41aad15	40	#include <Guid/VectorHandoffTable.h>\r
a47463f2	41	\r
dcc02621	42	#define HEAP_GUARD_NONSTOP_MODE \\r
02ba936d	43	((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6\|BIT4\|BIT1\|BIT0)) > BIT6)\r
dcc02621 JW	44	\r
	45	#define NULL_DETECTION_NONSTOP_MODE \\r
	46	((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6\|BIT0)) > BIT6)\r
	47	\r
430fbbe0	48	/**\r
	49	Flush CPU data cache. If the instruction cache is fully coherent\r
	50	with all DMA operations then function can just return EFI_SUCCESS.\r
	51	\r
	52	@param This Protocol instance structure\r
	53	@param Start Physical address to start flushing from.\r
	54	@param Length Number of bytes to flush. Round up to chipset\r
	55	granularity.\r
	56	@param FlushType Specifies the type of flush operation to perform.\r
	57	\r
	58	@retval EFI_SUCCESS If cache was flushed\r
	59	@retval EFI_UNSUPPORTED If flush type is not supported.\r
	60	@retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
	61	\r
	62	**/\r
a47463f2	63	EFI_STATUS\r
	64	EFIAPI\r
	65	CpuFlushCpuDataCache (\r
053e878b MK	66	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	67	IN EFI_PHYSICAL_ADDRESS Start,\r
	68	IN UINT64 Length,\r
	69	IN EFI_CPU_FLUSH_TYPE FlushType\r
a47463f2	70	);\r
a47463f2	71	\r
430fbbe0	72	/**\r
	73	Enables CPU interrupts.\r
	74	\r
	75	@param This Protocol instance structure\r
	76	\r
	77	@retval EFI_SUCCESS If interrupts were enabled in the CPU\r
	78	@retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
	79	\r
	80	**/\r
a47463f2	81	EFI_STATUS\r
	82	EFIAPI\r
	83	CpuEnableInterrupt (\r
053e878b	84	IN EFI_CPU_ARCH_PROTOCOL *This\r
a47463f2	85	);\r
a47463f2	86	\r
430fbbe0	87	/**\r
	88	Disables CPU interrupts.\r
	89	\r
	90	@param This Protocol instance structure\r
	91	\r
	92	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	93	@retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
	94	\r
	95	**/\r
a47463f2	96	EFI_STATUS\r
	97	EFIAPI\r
	98	CpuDisableInterrupt (\r
053e878b	99	IN EFI_CPU_ARCH_PROTOCOL *This\r
a47463f2	100	);\r
a47463f2	101	\r
430fbbe0	102	/**\r
	103	Return the state of interrupts.\r
	104	\r
	105	@param This Protocol instance structure\r
	106	@param State Pointer to the CPU's current interrupt state\r
	107	\r
	108	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	109	@retval EFI_INVALID_PARAMETER State is NULL.\r
	110	\r
	111	**/\r
a47463f2	112	EFI_STATUS\r
	113	EFIAPI\r
	114	CpuGetInterruptState (\r
053e878b MK	115	IN EFI_CPU_ARCH_PROTOCOL *This,\r
053e878b MK	116	OUT BOOLEAN *State\r
a47463f2	117	);\r
a47463f2	118	\r
430fbbe0	119	/**\r
	120	Generates an INIT to the CPU.\r
	121	\r
	122	@param This Protocol instance structure\r
	123	@param InitType Type of CPU INIT to perform\r
	124	\r
	125	@retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
	126	seen.\r
	127	@retval EFI_DEVICE_ERROR If CPU INIT failed.\r
	128	@retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
	129	\r
	130	**/\r
a47463f2	131	EFI_STATUS\r
	132	EFIAPI\r
	133	CpuInit (\r
053e878b MK	134	IN EFI_CPU_ARCH_PROTOCOL *This,\r
053e878b MK	135	IN EFI_CPU_INIT_TYPE InitType\r
a47463f2	136	);\r
a47463f2	137	\r
430fbbe0	138	/**\r
	139	Registers a function to be called from the CPU interrupt handler.\r
	140	\r
	141	@param This Protocol instance structure\r
	142	@param InterruptType Defines which interrupt to hook. IA-32\r
	143	valid range is 0x00 through 0xFF\r
	144	@param InterruptHandler A pointer to a function of type\r
	145	EFI_CPU_INTERRUPT_HANDLER that is called\r
	146	when a processor interrupt occurs. A null\r
	147	pointer is an error condition.\r
	148	\r
	149	@retval EFI_SUCCESS If handler installed or uninstalled.\r
	150	@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
	151	for InterruptType was previously installed.\r
	152	@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
	153	InterruptType was not previously installed.\r
	154	@retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
	155	is not supported.\r
	156	\r
	157	**/\r
a47463f2	158	EFI_STATUS\r
	159	EFIAPI\r
	160	CpuRegisterInterruptHandler (\r
053e878b MK	161	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	162	IN EFI_EXCEPTION_TYPE InterruptType,\r
	163	IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
a47463f2	164	);\r
a47463f2	165	\r
430fbbe0	166	/**\r
	167	Returns a timer value from one of the CPU's internal timers. There is no\r
	168	inherent time interval between ticks but is a function of the CPU frequency.\r
	169	\r
	170	@param This - Protocol instance structure.\r
	171	@param TimerIndex - Specifies which CPU timer is requested.\r
	172	@param TimerValue - Pointer to the returned timer value.\r
	173	@param TimerPeriod - A pointer to the amount of time that passes\r
	174	in femtoseconds (10-15) for each increment\r
	175	of TimerValue. If TimerValue does not\r
	176	increment at a predictable rate, then 0 is\r
	177	returned. The amount of time that has\r
	178	passed between two calls to GetTimerValue()\r
	179	can be calculated with the formula\r
	180	(TimerValue2 - TimerValue1) * TimerPeriod.\r
	181	This parameter is optional and may be NULL.\r
	182	\r
	183	@retval EFI_SUCCESS - If the CPU timer count was returned.\r
	184	@retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
	185	@retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
	186	@retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
	187	\r
	188	**/\r
a47463f2	189	EFI_STATUS\r
	190	EFIAPI\r
	191	CpuGetTimerValue (\r
053e878b MK	192	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	193	IN UINT32 TimerIndex,\r
	194	OUT UINT64 *TimerValue,\r
	195	OUT UINT64 *TimerPeriod OPTIONAL\r
a47463f2	196	);\r
a47463f2	197	\r
430fbbe0	198	/**\r
f60f4cfe	199	Set memory cacheability attributes for given range of memory.\r
430fbbe0	200	\r
	201	@param This Protocol instance structure\r
	202	@param BaseAddress Specifies the start address of the\r
	203	memory range\r
	204	@param Length Specifies the length of the memory range\r
	205	@param Attributes The memory cacheability for the memory range\r
	206	\r
	207	@retval EFI_SUCCESS If the cacheability of that memory range is\r
	208	set successfully\r
	209	@retval EFI_UNSUPPORTED If the desired operation cannot be done\r
	210	@retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
	211	such as Length = 0\r
	212	\r
	213	**/\r
a47463f2	214	EFI_STATUS\r
	215	EFIAPI\r
	216	CpuSetMemoryAttributes (\r
053e878b MK	217	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	218	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	219	IN UINT64 Length,\r
	220	IN UINT64 Attributes\r
a47463f2	221	);\r
a47463f2	222	\r
430fbbe0	223	/**\r
	224	Initialize Global Descriptor Table.\r
	225	\r
	226	**/\r
a47463f2	227	VOID\r
	228	InitGlobalDescriptorTable (\r
	229	VOID\r
	230	);\r
	231	\r
430fbbe0	232	/**\r
	233	Sets the code selector (CS).\r
	234	\r
	235	@param Selector Value of code selector.\r
	236	\r
	237	**/\r
a47463f2	238	VOID\r
	239	EFIAPI\r
	240	SetCodeSelector (\r
053e878b	241	UINT16 Selector\r
a47463f2	242	);\r
a47463f2	243	\r
430fbbe0	244	/**\r
	245	Sets the data selector (DS).\r
	246	\r
	247	@param Selector Value of data selector.\r
	248	\r
	249	**/\r
a47463f2	250	VOID\r
	251	EFIAPI\r
	252	SetDataSelectors (\r
053e878b	253	UINT16 Selector\r
a47463f2	254	);\r
a47463f2	255	\r
cbd7300c DB	256	/**\r
	257	Update GCD memory space attributes according to current page table setup.\r
	258	**/\r
c1cab54c JW	259	VOID\r
	260	RefreshGcdMemoryAttributesFromPaging (\r
	261	VOID\r
	262	);\r
	263	\r
dcc02621 JW	264	/**\r
	265	Special handler for #DB exception, which will restore the page attributes\r
	266	(not-present). It should work with #PF handler which will set pages to\r
	267	'present'.\r
	268	\r
	269	@param ExceptionType Exception type.\r
	270	@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.\r
	271	\r
	272	**/\r
	273	VOID\r
	274	EFIAPI\r
	275	DebugExceptionHandler (\r
053e878b MK	276	IN EFI_EXCEPTION_TYPE ExceptionType,\r
053e878b MK	277	IN EFI_SYSTEM_CONTEXT SystemContext\r
dcc02621 JW	278	);\r
	279	\r
	280	/**\r
	281	Special handler for #PF exception, which will set the pages which caused\r
	282	#PF to be 'present'. The attribute of those pages should be restored in\r
	283	the subsequent #DB handler.\r
	284	\r
	285	@param ExceptionType Exception type.\r
	286	@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.\r
	287	\r
	288	**/\r
	289	VOID\r
	290	EFIAPI\r
	291	PageFaultExceptionHandler (\r
053e878b MK	292	IN EFI_EXCEPTION_TYPE ExceptionType,\r
053e878b MK	293	IN EFI_SYSTEM_CONTEXT SystemContext\r
dcc02621 JW	294	);\r
dcc02621 JW	295	\r
053e878b MK	296	extern BOOLEAN mIsAllocatingPageTable;\r
053e878b MK	297	extern UINTN mNumberOfProcessors;\r
147fd35c	298	\r
a47463f2	299	#endif\r