[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.h

/** @file\r
  CPU DXE Module.\r
\r
  Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _CPU_DXE_H_\r
#define _CPU_DXE_H_\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/Cpu.h>\r
\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/CpuLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MtrrLib.h>\r
#include <Library/LocalApicLib.h>\r
#include <Library/UefiCpuLib.h>\r
#include <Guid/IdleLoopEvent.h>\r
\r
//\r
//\r
//\r
#define INTERRUPT_VECTOR_NUMBER   256\r
\r
#define EFI_MEMORY_CACHETYPE_MASK     (EFI_MEMORY_UC  | \\r
                                       EFI_MEMORY_WC  | \\r
                                       EFI_MEMORY_WT  | \\r
                                       EFI_MEMORY_WB  | \\r
                                       EFI_MEMORY_UCE   \\r
                                       )\r
\r
\r
/**\r
  Flush CPU data cache. If the instruction cache is fully coherent\r
  with all DMA operations then function can just return EFI_SUCCESS.\r
\r
  @param  This              Protocol instance structure\r
  @param  Start             Physical address to start flushing from.\r
  @param  Length            Number of bytes to flush. Round up to chipset\r
                            granularity.\r
  @param  FlushType         Specifies the type of flush operation to perform.\r
\r
  @retval EFI_SUCCESS       If cache was flushed\r
  @retval EFI_UNSUPPORTED   If flush type is not supported.\r
  @retval EFI_DEVICE_ERROR  If requested range could not be flushed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
  IN EFI_PHYSICAL_ADDRESS      Start,\r
  IN UINT64                    Length,\r
  IN EFI_CPU_FLUSH_TYPE        FlushType\r
  );\r
\r
/**\r
  Enables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were enabled in the CPU\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This\r
  );\r
\r
/**\r
  Disables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were disabled in the CPU.\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This\r
  );\r
\r
/**\r
  Return the state of interrupts.\r
\r
  @param  This                   Protocol instance structure\r
  @param  State                  Pointer to the CPU's current interrupt state\r
\r
  @retval EFI_SUCCESS            If interrupts were disabled in the CPU.\r
  @retval EFI_INVALID_PARAMETER  State is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
  IN  EFI_CPU_ARCH_PROTOCOL     *This,\r
  OUT BOOLEAN                   *State\r
  );\r
\r
/**\r
  Generates an INIT to the CPU.\r
\r
  @param  This              Protocol instance structure\r
  @param  InitType          Type of CPU INIT to perform\r
\r
  @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be\r
                            seen.\r
  @retval EFI_DEVICE_ERROR  If CPU INIT failed.\r
  @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
  IN EFI_CPU_INIT_TYPE         InitType\r
  );\r
\r
/**\r
  Registers a function to be called from the CPU interrupt handler.\r
\r
  @param  This                   Protocol instance structure\r
  @param  InterruptType          Defines which interrupt to hook. IA-32\r
                                 valid range is 0x00 through 0xFF\r
  @param  InterruptHandler       A pointer to a function of type\r
                                 EFI_CPU_INTERRUPT_HANDLER that is called\r
                                 when a processor interrupt occurs.  A null\r
                                 pointer is an error condition.\r
\r
  @retval EFI_SUCCESS            If handler installed or uninstalled.\r
  @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler\r
                                 for InterruptType was previously installed.\r
  @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for\r
                                 InterruptType was not previously installed.\r
  @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType\r
                                 is not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
  IN EFI_CPU_ARCH_PROTOCOL         *This,\r
  IN EFI_EXCEPTION_TYPE            InterruptType,\r
  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
  );\r
\r
/**\r
  Returns a timer value from one of the CPU's internal timers. There is no\r
  inherent time interval between ticks but is a function of the CPU frequency.\r
\r
  @param  This                - Protocol instance structure.\r
  @param  TimerIndex          - Specifies which CPU timer is requested.\r
  @param  TimerValue          - Pointer to the returned timer value.\r
  @param  TimerPeriod         - A pointer to the amount of time that passes\r
                                in femtoseconds (10-15) for each increment\r
                                of TimerValue. If TimerValue does not\r
                                increment at a predictable rate, then 0 is\r
                                returned.  The amount of time that has\r
                                passed between two calls to GetTimerValue()\r
                                can be calculated with the formula\r
                                (TimerValue2 - TimerValue1) * TimerPeriod.\r
                                This parameter is optional and may be NULL.\r
\r
  @retval EFI_SUCCESS           - If the CPU timer count was returned.\r
  @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.\r
  @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.\r
  @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
  IN  EFI_CPU_ARCH_PROTOCOL       *This,\r
  IN  UINT32                      TimerIndex,\r
  OUT UINT64                      *TimerValue,\r
  OUT UINT64                      *TimerPeriod OPTIONAL\r
  );\r
\r
/**\r
  Set memory cacheability attributes for given range of memeory.\r
\r
  @param  This                   Protocol instance structure\r
  @param  BaseAddress            Specifies the start address of the\r
                                 memory range\r
  @param  Length                 Specifies the length of the memory range\r
  @param  Attributes             The memory cacheability for the memory range\r
\r
  @retval EFI_SUCCESS            If the cacheability of that memory range is\r
                                 set successfully\r
  @retval EFI_UNSUPPORTED        If the desired operation cannot be done\r
  @retval EFI_INVALID_PARAMETER  The input parameter is not correct,\r
                                 such as Length = 0\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuSetMemoryAttributes (\r
  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
  IN EFI_PHYSICAL_ADDRESS       BaseAddress,\r
  IN UINT64                     Length,\r
  IN UINT64                     Attributes\r
  );\r
\r
/**\r
  Label of base address of IDT vector 0.\r
\r
  This is just a label of base address of IDT vector 0.\r
\r
**/\r
VOID\r
EFIAPI\r
AsmIdtVector00 (\r
  VOID\r
  );\r
\r
/**\r
  Initializes the pointer to the external interrupt vector table.\r
\r
  @param  VectorTable  Address of the external interrupt vector table.\r
\r
**/\r
VOID\r
EFIAPI\r
InitializeExternalVectorTablePtr (\r
  EFI_CPU_INTERRUPT_HANDLER  *VectorTable\r
  );\r
\r
/**\r
  Initialize Global Descriptor Table.\r
\r
**/\r
VOID\r
InitGlobalDescriptorTable (\r
  VOID\r
  );\r
\r
/**\r
  Sets the code selector (CS).\r
\r
  @param  Selector  Value of code selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetCodeSelector (\r
  UINT16 Selector\r
  );\r
\r
/**\r
  Sets the data selector (DS).\r
\r
  @param  Selector  Value of data selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetDataSelectors (\r
  UINT16 Selector\r
  );\r
\r
/**\r
  Restore original Interrupt Descriptor Table Handler Address.\r
\r
  @param Index        The Index of the interrupt descriptor table handle.\r
\r
**/\r
VOID\r
RestoreInterruptDescriptorTableHandlerAddress (\r
  IN UINTN       Index\r
  );\r
\r
#endif\r
\r
Commit	Line	Data
a47463f2	1	/** @file\r
	2	CPU DXE Module.\r
	3	\r
d4605c23	4	Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc	5	This program and the accompanying materials\r
a47463f2	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
430fbbe0	15	#ifndef _CPU_DXE_H_\r
430fbbe0	16	#define _CPU_DXE_H_\r
a47463f2	17	\r
	18	#include <PiDxe.h>\r
	19	\r
	20	#include <Protocol/Cpu.h>\r
	21	\r
	22	#include <Library/UefiDriverEntryPoint.h>\r
	23	#include <Library/UefiBootServicesTableLib.h>\r
	24	#include <Library/DxeServicesTableLib.h>\r
	25	#include <Library/BaseLib.h>\r
	26	#include <Library/CpuLib.h>\r
	27	#include <Library/BaseMemoryLib.h>\r
	28	#include <Library/MemoryAllocationLib.h>\r
	29	#include <Library/DebugLib.h>\r
	30	#include <Library/MtrrLib.h>\r
d4605c23	31	#include <Library/LocalApicLib.h>\r
661cab5d	32	#include <Library/UefiCpuLib.h>\r
32394027	33	#include <Guid/IdleLoopEvent.h>\r
a47463f2	34	\r
	35	//\r
	36	//\r
	37	//\r
	38	#define INTERRUPT_VECTOR_NUMBER 256\r
	39	\r
	40	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| \\r
	41	EFI_MEMORY_WC \| \\r
	42	EFI_MEMORY_WT \| \\r
	43	EFI_MEMORY_WB \| \\r
	44	EFI_MEMORY_UCE \\r
	45	)\r
	46	\r
	47	\r
430fbbe0	48	/**\r
	49	Flush CPU data cache. If the instruction cache is fully coherent\r
	50	with all DMA operations then function can just return EFI_SUCCESS.\r
	51	\r
	52	@param This Protocol instance structure\r
	53	@param Start Physical address to start flushing from.\r
	54	@param Length Number of bytes to flush. Round up to chipset\r
	55	granularity.\r
	56	@param FlushType Specifies the type of flush operation to perform.\r
	57	\r
	58	@retval EFI_SUCCESS If cache was flushed\r
	59	@retval EFI_UNSUPPORTED If flush type is not supported.\r
	60	@retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
	61	\r
	62	**/\r
a47463f2	63	EFI_STATUS\r
	64	EFIAPI\r
	65	CpuFlushCpuDataCache (\r
	66	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	67	IN EFI_PHYSICAL_ADDRESS Start,\r
	68	IN UINT64 Length,\r
	69	IN EFI_CPU_FLUSH_TYPE FlushType\r
	70	);\r
	71	\r
430fbbe0	72	/**\r
	73	Enables CPU interrupts.\r
	74	\r
	75	@param This Protocol instance structure\r
	76	\r
	77	@retval EFI_SUCCESS If interrupts were enabled in the CPU\r
	78	@retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
	79	\r
	80	**/\r
a47463f2	81	EFI_STATUS\r
	82	EFIAPI\r
	83	CpuEnableInterrupt (\r
	84	IN EFI_CPU_ARCH_PROTOCOL *This\r
	85	);\r
	86	\r
430fbbe0	87	/**\r
	88	Disables CPU interrupts.\r
	89	\r
	90	@param This Protocol instance structure\r
	91	\r
	92	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	93	@retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
	94	\r
	95	**/\r
a47463f2	96	EFI_STATUS\r
	97	EFIAPI\r
	98	CpuDisableInterrupt (\r
	99	IN EFI_CPU_ARCH_PROTOCOL *This\r
	100	);\r
	101	\r
430fbbe0	102	/**\r
	103	Return the state of interrupts.\r
	104	\r
	105	@param This Protocol instance structure\r
	106	@param State Pointer to the CPU's current interrupt state\r
	107	\r
	108	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	109	@retval EFI_INVALID_PARAMETER State is NULL.\r
	110	\r
	111	**/\r
a47463f2	112	EFI_STATUS\r
	113	EFIAPI\r
	114	CpuGetInterruptState (\r
	115	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	116	OUT BOOLEAN *State\r
	117	);\r
	118	\r
430fbbe0	119	/**\r
	120	Generates an INIT to the CPU.\r
	121	\r
	122	@param This Protocol instance structure\r
	123	@param InitType Type of CPU INIT to perform\r
	124	\r
	125	@retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
	126	seen.\r
	127	@retval EFI_DEVICE_ERROR If CPU INIT failed.\r
	128	@retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
	129	\r
	130	**/\r
a47463f2	131	EFI_STATUS\r
	132	EFIAPI\r
	133	CpuInit (\r
	134	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	135	IN EFI_CPU_INIT_TYPE InitType\r
	136	);\r
	137	\r
430fbbe0	138	/**\r
	139	Registers a function to be called from the CPU interrupt handler.\r
	140	\r
	141	@param This Protocol instance structure\r
	142	@param InterruptType Defines which interrupt to hook. IA-32\r
	143	valid range is 0x00 through 0xFF\r
	144	@param InterruptHandler A pointer to a function of type\r
	145	EFI_CPU_INTERRUPT_HANDLER that is called\r
	146	when a processor interrupt occurs. A null\r
	147	pointer is an error condition.\r
	148	\r
	149	@retval EFI_SUCCESS If handler installed or uninstalled.\r
	150	@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
	151	for InterruptType was previously installed.\r
	152	@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
	153	InterruptType was not previously installed.\r
	154	@retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
	155	is not supported.\r
	156	\r
	157	**/\r
a47463f2	158	EFI_STATUS\r
	159	EFIAPI\r
	160	CpuRegisterInterruptHandler (\r
	161	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	162	IN EFI_EXCEPTION_TYPE InterruptType,\r
	163	IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
	164	);\r
	165	\r
430fbbe0	166	/**\r
	167	Returns a timer value from one of the CPU's internal timers. There is no\r
	168	inherent time interval between ticks but is a function of the CPU frequency.\r
	169	\r
	170	@param This - Protocol instance structure.\r
	171	@param TimerIndex - Specifies which CPU timer is requested.\r
	172	@param TimerValue - Pointer to the returned timer value.\r
	173	@param TimerPeriod - A pointer to the amount of time that passes\r
	174	in femtoseconds (10-15) for each increment\r
	175	of TimerValue. If TimerValue does not\r
	176	increment at a predictable rate, then 0 is\r
	177	returned. The amount of time that has\r
	178	passed between two calls to GetTimerValue()\r
	179	can be calculated with the formula\r
	180	(TimerValue2 - TimerValue1) * TimerPeriod.\r
	181	This parameter is optional and may be NULL.\r
	182	\r
	183	@retval EFI_SUCCESS - If the CPU timer count was returned.\r
	184	@retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
	185	@retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
	186	@retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
	187	\r
	188	**/\r
a47463f2	189	EFI_STATUS\r
	190	EFIAPI\r
	191	CpuGetTimerValue (\r
	192	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	193	IN UINT32 TimerIndex,\r
	194	OUT UINT64 *TimerValue,\r
	195	OUT UINT64 *TimerPeriod OPTIONAL\r
	196	);\r
	197	\r
430fbbe0	198	/**\r
	199	Set memory cacheability attributes for given range of memeory.\r
	200	\r
	201	@param This Protocol instance structure\r
	202	@param BaseAddress Specifies the start address of the\r
	203	memory range\r
	204	@param Length Specifies the length of the memory range\r
	205	@param Attributes The memory cacheability for the memory range\r
	206	\r
	207	@retval EFI_SUCCESS If the cacheability of that memory range is\r
	208	set successfully\r
	209	@retval EFI_UNSUPPORTED If the desired operation cannot be done\r
	210	@retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
	211	such as Length = 0\r
	212	\r
	213	**/\r
a47463f2	214	EFI_STATUS\r
	215	EFIAPI\r
	216	CpuSetMemoryAttributes (\r
	217	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	218	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	219	IN UINT64 Length,\r
	220	IN UINT64 Attributes\r
	221	);\r
	222	\r
430fbbe0	223	/**\r
	224	Label of base address of IDT vector 0.\r
	225	\r
	226	This is just a label of base address of IDT vector 0.\r
	227	\r
	228	**/\r
a47463f2	229	VOID\r
	230	EFIAPI\r
	231	AsmIdtVector00 (\r
	232	VOID\r
	233	);\r
	234	\r
430fbbe0	235	/**\r
	236	Initializes the pointer to the external interrupt vector table.\r
	237	\r
	238	@param VectorTable Address of the external interrupt vector table.\r
	239	\r
	240	**/\r
a47463f2	241	VOID\r
	242	EFIAPI\r
	243	InitializeExternalVectorTablePtr (\r
	244	EFI_CPU_INTERRUPT_HANDLER *VectorTable\r
	245	);\r
	246	\r
430fbbe0	247	/**\r
	248	Initialize Global Descriptor Table.\r
	249	\r
	250	**/\r
a47463f2	251	VOID\r
	252	InitGlobalDescriptorTable (\r
	253	VOID\r
	254	);\r
	255	\r
430fbbe0	256	/**\r
	257	Sets the code selector (CS).\r
	258	\r
	259	@param Selector Value of code selector.\r
	260	\r
	261	**/\r
a47463f2	262	VOID\r
	263	EFIAPI\r
	264	SetCodeSelector (\r
	265	UINT16 Selector\r
	266	);\r
	267	\r
430fbbe0	268	/**\r
	269	Sets the data selector (DS).\r
	270	\r
	271	@param Selector Value of data selector.\r
	272	\r
	273	**/\r
a47463f2	274	VOID\r
	275	EFIAPI\r
	276	SetDataSelectors (\r
	277	UINT16 Selector\r
	278	);\r
	279	\r
de4b64f7	280	/**\r
	281	Restore original Interrupt Descriptor Table Handler Address.\r
	282	\r
	283	@param Index The Index of the interrupt descriptor table handle.\r
	284	\r
	285	**/\r
	286	VOID\r
	287	RestoreInterruptDescriptorTableHandlerAddress (\r
	288	IN UINTN Index\r
	289	);\r
a47463f2	290	\r
	291	#endif\r
	292	\r