[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.h

/** @file\r
  CPU DXE Module.\r
\r
  Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _CPU_DXE_H_\r
#define _CPU_DXE_H_\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/Cpu.h>\r
\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/CpuLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MtrrLib.h>\r
\r
//\r
//\r
//\r
#define INTERRUPT_VECTOR_NUMBER   256\r
\r
#define EFI_MEMORY_CACHETYPE_MASK     (EFI_MEMORY_UC  | \\r
                                       EFI_MEMORY_WC  | \\r
                                       EFI_MEMORY_WT  | \\r
                                       EFI_MEMORY_WB  | \\r
                                       EFI_MEMORY_UCE   \\r
                                       )\r
\r
\r
/**\r
  Flush CPU data cache. If the instruction cache is fully coherent\r
  with all DMA operations then function can just return EFI_SUCCESS.\r
\r
  @param  This              Protocol instance structure\r
  @param  Start             Physical address to start flushing from.\r
  @param  Length            Number of bytes to flush. Round up to chipset\r
                            granularity.\r
  @param  FlushType         Specifies the type of flush operation to perform.\r
\r
  @retval EFI_SUCCESS       If cache was flushed\r
  @retval EFI_UNSUPPORTED   If flush type is not supported.\r
  @retval EFI_DEVICE_ERROR  If requested range could not be flushed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
  IN EFI_PHYSICAL_ADDRESS      Start,\r
  IN UINT64                    Length,\r
  IN EFI_CPU_FLUSH_TYPE        FlushType\r
  );\r
\r
/**\r
  Enables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were enabled in the CPU\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This\r
  );\r
\r
/**\r
  Disables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were disabled in the CPU.\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This\r
  );\r
\r
/**\r
  Return the state of interrupts.\r
\r
  @param  This                   Protocol instance structure\r
  @param  State                  Pointer to the CPU's current interrupt state\r
\r
  @retval EFI_SUCCESS            If interrupts were disabled in the CPU.\r
  @retval EFI_INVALID_PARAMETER  State is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
  IN  EFI_CPU_ARCH_PROTOCOL     *This,\r
  OUT BOOLEAN                   *State\r
  );\r
\r
/**\r
  Generates an INIT to the CPU.\r
\r
  @param  This              Protocol instance structure\r
  @param  InitType          Type of CPU INIT to perform\r
\r
  @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be\r
                            seen.\r
  @retval EFI_DEVICE_ERROR  If CPU INIT failed.\r
  @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
  IN EFI_CPU_INIT_TYPE         InitType\r
  );\r
\r
/**\r
  Registers a function to be called from the CPU interrupt handler.\r
\r
  @param  This                   Protocol instance structure\r
  @param  InterruptType          Defines which interrupt to hook. IA-32\r
                                 valid range is 0x00 through 0xFF\r
  @param  InterruptHandler       A pointer to a function of type\r
                                 EFI_CPU_INTERRUPT_HANDLER that is called\r
                                 when a processor interrupt occurs.  A null\r
                                 pointer is an error condition.\r
\r
  @retval EFI_SUCCESS            If handler installed or uninstalled.\r
  @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler\r
                                 for InterruptType was previously installed.\r
  @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for\r
                                 InterruptType was not previously installed.\r
  @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType\r
                                 is not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
  IN EFI_CPU_ARCH_PROTOCOL         *This,\r
  IN EFI_EXCEPTION_TYPE            InterruptType,\r
  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
  );\r
\r
/**\r
  Returns a timer value from one of the CPU's internal timers. There is no\r
  inherent time interval between ticks but is a function of the CPU frequency.\r
\r
  @param  This                - Protocol instance structure.\r
  @param  TimerIndex          - Specifies which CPU timer is requested.\r
  @param  TimerValue          - Pointer to the returned timer value.\r
  @param  TimerPeriod         - A pointer to the amount of time that passes\r
                                in femtoseconds (10-15) for each increment\r
                                of TimerValue. If TimerValue does not\r
                                increment at a predictable rate, then 0 is\r
                                returned.  The amount of time that has\r
                                passed between two calls to GetTimerValue()\r
                                can be calculated with the formula\r
                                (TimerValue2 - TimerValue1) * TimerPeriod.\r
                                This parameter is optional and may be NULL.\r
\r
  @retval EFI_SUCCESS           - If the CPU timer count was returned.\r
  @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.\r
  @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.\r
  @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
  IN  EFI_CPU_ARCH_PROTOCOL       *This,\r
  IN  UINT32                      TimerIndex,\r
  OUT UINT64                      *TimerValue,\r
  OUT UINT64                      *TimerPeriod OPTIONAL\r
  );\r
\r
/**\r
  Set memory cacheability attributes for given range of memeory.\r
\r
  @param  This                   Protocol instance structure\r
  @param  BaseAddress            Specifies the start address of the\r
                                 memory range\r
  @param  Length                 Specifies the length of the memory range\r
  @param  Attributes             The memory cacheability for the memory range\r
\r
  @retval EFI_SUCCESS            If the cacheability of that memory range is\r
                                 set successfully\r
  @retval EFI_UNSUPPORTED        If the desired operation cannot be done\r
  @retval EFI_INVALID_PARAMETER  The input parameter is not correct,\r
                                 such as Length = 0\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuSetMemoryAttributes (\r
  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
  IN EFI_PHYSICAL_ADDRESS       BaseAddress,\r
  IN UINT64                     Length,\r
  IN UINT64                     Attributes\r
  );\r
\r
/**\r
  Label of base address of IDT vector 0.\r
\r
  This is just a label of base address of IDT vector 0.\r
\r
**/\r
VOID\r
EFIAPI\r
AsmIdtVector00 (\r
  VOID\r
  );\r
\r
/**\r
  Initializes the pointer to the external interrupt vector table.\r
\r
  @param  VectorTable  Address of the external interrupt vector table.\r
\r
**/\r
VOID\r
EFIAPI\r
InitializeExternalVectorTablePtr (\r
  EFI_CPU_INTERRUPT_HANDLER  *VectorTable\r
  );\r
\r
/**\r
  Initialize Global Descriptor Table.\r
\r
**/\r
VOID\r
InitGlobalDescriptorTable (\r
  VOID\r
  );\r
\r
/**\r
  Sets the code selector (CS).\r
\r
  @param  Selector  Value of code selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetCodeSelector (\r
  UINT16 Selector\r
  );\r
\r
/**\r
  Sets the data selector (DS).\r
\r
  @param  Selector  Value of data selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetDataSelectors (\r
  UINT16 Selector\r
  );\r
\r
\r
#endif\r
\r
Commit	Line	Data
a47463f2	1	/** @file\r
	2	CPU DXE Module.\r
	3	\r
430fbbe0	4	Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc	5	This program and the accompanying materials\r
a47463f2	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
430fbbe0	15	#ifndef _CPU_DXE_H_\r
430fbbe0	16	#define _CPU_DXE_H_\r
a47463f2	17	\r
	18	#include <PiDxe.h>\r
	19	\r
	20	#include <Protocol/Cpu.h>\r
	21	\r
	22	#include <Library/UefiDriverEntryPoint.h>\r
	23	#include <Library/UefiBootServicesTableLib.h>\r
	24	#include <Library/DxeServicesTableLib.h>\r
	25	#include <Library/BaseLib.h>\r
	26	#include <Library/CpuLib.h>\r
	27	#include <Library/BaseMemoryLib.h>\r
	28	#include <Library/MemoryAllocationLib.h>\r
	29	#include <Library/DebugLib.h>\r
	30	#include <Library/MtrrLib.h>\r
	31	\r
	32	//\r
	33	//\r
	34	//\r
	35	#define INTERRUPT_VECTOR_NUMBER 256\r
	36	\r
	37	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| \\r
	38	EFI_MEMORY_WC \| \\r
	39	EFI_MEMORY_WT \| \\r
	40	EFI_MEMORY_WB \| \\r
	41	EFI_MEMORY_UCE \\r
	42	)\r
	43	\r
	44	\r
430fbbe0	45	/**\r
	46	Flush CPU data cache. If the instruction cache is fully coherent\r
	47	with all DMA operations then function can just return EFI_SUCCESS.\r
	48	\r
	49	@param This Protocol instance structure\r
	50	@param Start Physical address to start flushing from.\r
	51	@param Length Number of bytes to flush. Round up to chipset\r
	52	granularity.\r
	53	@param FlushType Specifies the type of flush operation to perform.\r
	54	\r
	55	@retval EFI_SUCCESS If cache was flushed\r
	56	@retval EFI_UNSUPPORTED If flush type is not supported.\r
	57	@retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
	58	\r
	59	**/\r
a47463f2	60	EFI_STATUS\r
	61	EFIAPI\r
	62	CpuFlushCpuDataCache (\r
	63	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	64	IN EFI_PHYSICAL_ADDRESS Start,\r
	65	IN UINT64 Length,\r
	66	IN EFI_CPU_FLUSH_TYPE FlushType\r
	67	);\r
	68	\r
430fbbe0	69	/**\r
	70	Enables CPU interrupts.\r
	71	\r
	72	@param This Protocol instance structure\r
	73	\r
	74	@retval EFI_SUCCESS If interrupts were enabled in the CPU\r
	75	@retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
	76	\r
	77	**/\r
a47463f2	78	EFI_STATUS\r
	79	EFIAPI\r
	80	CpuEnableInterrupt (\r
	81	IN EFI_CPU_ARCH_PROTOCOL *This\r
	82	);\r
	83	\r
430fbbe0	84	/**\r
	85	Disables CPU interrupts.\r
	86	\r
	87	@param This Protocol instance structure\r
	88	\r
	89	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	90	@retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
	91	\r
	92	**/\r
a47463f2	93	EFI_STATUS\r
	94	EFIAPI\r
	95	CpuDisableInterrupt (\r
	96	IN EFI_CPU_ARCH_PROTOCOL *This\r
	97	);\r
	98	\r
430fbbe0	99	/**\r
	100	Return the state of interrupts.\r
	101	\r
	102	@param This Protocol instance structure\r
	103	@param State Pointer to the CPU's current interrupt state\r
	104	\r
	105	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	106	@retval EFI_INVALID_PARAMETER State is NULL.\r
	107	\r
	108	**/\r
a47463f2	109	EFI_STATUS\r
	110	EFIAPI\r
	111	CpuGetInterruptState (\r
	112	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	113	OUT BOOLEAN *State\r
	114	);\r
	115	\r
430fbbe0	116	/**\r
	117	Generates an INIT to the CPU.\r
	118	\r
	119	@param This Protocol instance structure\r
	120	@param InitType Type of CPU INIT to perform\r
	121	\r
	122	@retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
	123	seen.\r
	124	@retval EFI_DEVICE_ERROR If CPU INIT failed.\r
	125	@retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
	126	\r
	127	**/\r
a47463f2	128	EFI_STATUS\r
	129	EFIAPI\r
	130	CpuInit (\r
	131	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	132	IN EFI_CPU_INIT_TYPE InitType\r
	133	);\r
	134	\r
430fbbe0	135	/**\r
	136	Registers a function to be called from the CPU interrupt handler.\r
	137	\r
	138	@param This Protocol instance structure\r
	139	@param InterruptType Defines which interrupt to hook. IA-32\r
	140	valid range is 0x00 through 0xFF\r
	141	@param InterruptHandler A pointer to a function of type\r
	142	EFI_CPU_INTERRUPT_HANDLER that is called\r
	143	when a processor interrupt occurs. A null\r
	144	pointer is an error condition.\r
	145	\r
	146	@retval EFI_SUCCESS If handler installed or uninstalled.\r
	147	@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
	148	for InterruptType was previously installed.\r
	149	@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
	150	InterruptType was not previously installed.\r
	151	@retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
	152	is not supported.\r
	153	\r
	154	**/\r
a47463f2	155	EFI_STATUS\r
	156	EFIAPI\r
	157	CpuRegisterInterruptHandler (\r
	158	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	159	IN EFI_EXCEPTION_TYPE InterruptType,\r
	160	IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
	161	);\r
	162	\r
430fbbe0	163	/**\r
	164	Returns a timer value from one of the CPU's internal timers. There is no\r
	165	inherent time interval between ticks but is a function of the CPU frequency.\r
	166	\r
	167	@param This - Protocol instance structure.\r
	168	@param TimerIndex - Specifies which CPU timer is requested.\r
	169	@param TimerValue - Pointer to the returned timer value.\r
	170	@param TimerPeriod - A pointer to the amount of time that passes\r
	171	in femtoseconds (10-15) for each increment\r
	172	of TimerValue. If TimerValue does not\r
	173	increment at a predictable rate, then 0 is\r
	174	returned. The amount of time that has\r
	175	passed between two calls to GetTimerValue()\r
	176	can be calculated with the formula\r
	177	(TimerValue2 - TimerValue1) * TimerPeriod.\r
	178	This parameter is optional and may be NULL.\r
	179	\r
	180	@retval EFI_SUCCESS - If the CPU timer count was returned.\r
	181	@retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
	182	@retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
	183	@retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
	184	\r
	185	**/\r
a47463f2	186	EFI_STATUS\r
	187	EFIAPI\r
	188	CpuGetTimerValue (\r
	189	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	190	IN UINT32 TimerIndex,\r
	191	OUT UINT64 *TimerValue,\r
	192	OUT UINT64 *TimerPeriod OPTIONAL\r
	193	);\r
	194	\r
430fbbe0	195	/**\r
	196	Set memory cacheability attributes for given range of memeory.\r
	197	\r
	198	@param This Protocol instance structure\r
	199	@param BaseAddress Specifies the start address of the\r
	200	memory range\r
	201	@param Length Specifies the length of the memory range\r
	202	@param Attributes The memory cacheability for the memory range\r
	203	\r
	204	@retval EFI_SUCCESS If the cacheability of that memory range is\r
	205	set successfully\r
	206	@retval EFI_UNSUPPORTED If the desired operation cannot be done\r
	207	@retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
	208	such as Length = 0\r
	209	\r
	210	**/\r
a47463f2	211	EFI_STATUS\r
	212	EFIAPI\r
	213	CpuSetMemoryAttributes (\r
	214	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	215	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	216	IN UINT64 Length,\r
	217	IN UINT64 Attributes\r
	218	);\r
	219	\r
430fbbe0	220	/**\r
	221	Label of base address of IDT vector 0.\r
	222	\r
	223	This is just a label of base address of IDT vector 0.\r
	224	\r
	225	**/\r
a47463f2	226	VOID\r
	227	EFIAPI\r
	228	AsmIdtVector00 (\r
	229	VOID\r
	230	);\r
	231	\r
430fbbe0	232	/**\r
	233	Initializes the pointer to the external interrupt vector table.\r
	234	\r
	235	@param VectorTable Address of the external interrupt vector table.\r
	236	\r
	237	**/\r
a47463f2	238	VOID\r
	239	EFIAPI\r
	240	InitializeExternalVectorTablePtr (\r
	241	EFI_CPU_INTERRUPT_HANDLER *VectorTable\r
	242	);\r
	243	\r
430fbbe0	244	/**\r
	245	Initialize Global Descriptor Table.\r
	246	\r
	247	**/\r
a47463f2	248	VOID\r
	249	InitGlobalDescriptorTable (\r
	250	VOID\r
	251	);\r
	252	\r
430fbbe0	253	/**\r
	254	Sets the code selector (CS).\r
	255	\r
	256	@param Selector Value of code selector.\r
	257	\r
	258	**/\r
a47463f2	259	VOID\r
	260	EFIAPI\r
	261	SetCodeSelector (\r
	262	UINT16 Selector\r
	263	);\r
	264	\r
430fbbe0	265	/**\r
	266	Sets the data selector (DS).\r
	267	\r
	268	@param Selector Value of data selector.\r
	269	\r
	270	**/\r
a47463f2	271	VOID\r
	272	EFIAPI\r
	273	SetDataSelectors (\r
	274	UINT16 Selector\r
	275	);\r
	276	\r
	277	\r
	278	#endif\r
	279	\r