[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.h

/** @file\r
  CPU DXE Module.\r
\r
  Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _CPU_DXE_H_\r
#define _CPU_DXE_H_\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/Cpu.h>\r
\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/CpuLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MtrrLib.h>\r
#include <Guid/IdleLoopEvent.h>\r
\r
//\r
//\r
//\r
#define INTERRUPT_VECTOR_NUMBER   256\r
\r
#define EFI_MEMORY_CACHETYPE_MASK     (EFI_MEMORY_UC  | \\r
                                       EFI_MEMORY_WC  | \\r
                                       EFI_MEMORY_WT  | \\r
                                       EFI_MEMORY_WB  | \\r
                                       EFI_MEMORY_UCE   \\r
                                       )\r
\r
\r
/**\r
  Flush CPU data cache. If the instruction cache is fully coherent\r
  with all DMA operations then function can just return EFI_SUCCESS.\r
\r
  @param  This              Protocol instance structure\r
  @param  Start             Physical address to start flushing from.\r
  @param  Length            Number of bytes to flush. Round up to chipset\r
                            granularity.\r
  @param  FlushType         Specifies the type of flush operation to perform.\r
\r
  @retval EFI_SUCCESS       If cache was flushed\r
  @retval EFI_UNSUPPORTED   If flush type is not supported.\r
  @retval EFI_DEVICE_ERROR  If requested range could not be flushed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
  IN EFI_PHYSICAL_ADDRESS      Start,\r
  IN UINT64                    Length,\r
  IN EFI_CPU_FLUSH_TYPE        FlushType\r
  );\r
\r
/**\r
  Enables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were enabled in the CPU\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This\r
  );\r
\r
/**\r
  Disables CPU interrupts.\r
\r
  @param  This              Protocol instance structure\r
\r
  @retval EFI_SUCCESS       If interrupts were disabled in the CPU.\r
  @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This\r
  );\r
\r
/**\r
  Return the state of interrupts.\r
\r
  @param  This                   Protocol instance structure\r
  @param  State                  Pointer to the CPU's current interrupt state\r
\r
  @retval EFI_SUCCESS            If interrupts were disabled in the CPU.\r
  @retval EFI_INVALID_PARAMETER  State is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
  IN  EFI_CPU_ARCH_PROTOCOL     *This,\r
  OUT BOOLEAN                   *State\r
  );\r
\r
/**\r
  Generates an INIT to the CPU.\r
\r
  @param  This              Protocol instance structure\r
  @param  InitType          Type of CPU INIT to perform\r
\r
  @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be\r
                            seen.\r
  @retval EFI_DEVICE_ERROR  If CPU INIT failed.\r
  @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
  IN EFI_CPU_INIT_TYPE         InitType\r
  );\r
\r
/**\r
  Registers a function to be called from the CPU interrupt handler.\r
\r
  @param  This                   Protocol instance structure\r
  @param  InterruptType          Defines which interrupt to hook. IA-32\r
                                 valid range is 0x00 through 0xFF\r
  @param  InterruptHandler       A pointer to a function of type\r
                                 EFI_CPU_INTERRUPT_HANDLER that is called\r
                                 when a processor interrupt occurs.  A null\r
                                 pointer is an error condition.\r
\r
  @retval EFI_SUCCESS            If handler installed or uninstalled.\r
  @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler\r
                                 for InterruptType was previously installed.\r
  @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for\r
                                 InterruptType was not previously installed.\r
  @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType\r
                                 is not supported.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
  IN EFI_CPU_ARCH_PROTOCOL         *This,\r
  IN EFI_EXCEPTION_TYPE            InterruptType,\r
  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
  );\r
\r
/**\r
  Returns a timer value from one of the CPU's internal timers. There is no\r
  inherent time interval between ticks but is a function of the CPU frequency.\r
\r
  @param  This                - Protocol instance structure.\r
  @param  TimerIndex          - Specifies which CPU timer is requested.\r
  @param  TimerValue          - Pointer to the returned timer value.\r
  @param  TimerPeriod         - A pointer to the amount of time that passes\r
                                in femtoseconds (10-15) for each increment\r
                                of TimerValue. If TimerValue does not\r
                                increment at a predictable rate, then 0 is\r
                                returned.  The amount of time that has\r
                                passed between two calls to GetTimerValue()\r
                                can be calculated with the formula\r
                                (TimerValue2 - TimerValue1) * TimerPeriod.\r
                                This parameter is optional and may be NULL.\r
\r
  @retval EFI_SUCCESS           - If the CPU timer count was returned.\r
  @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.\r
  @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.\r
  @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
  IN  EFI_CPU_ARCH_PROTOCOL       *This,\r
  IN  UINT32                      TimerIndex,\r
  OUT UINT64                      *TimerValue,\r
  OUT UINT64                      *TimerPeriod OPTIONAL\r
  );\r
\r
/**\r
  Set memory cacheability attributes for given range of memeory.\r
\r
  @param  This                   Protocol instance structure\r
  @param  BaseAddress            Specifies the start address of the\r
                                 memory range\r
  @param  Length                 Specifies the length of the memory range\r
  @param  Attributes             The memory cacheability for the memory range\r
\r
  @retval EFI_SUCCESS            If the cacheability of that memory range is\r
                                 set successfully\r
  @retval EFI_UNSUPPORTED        If the desired operation cannot be done\r
  @retval EFI_INVALID_PARAMETER  The input parameter is not correct,\r
                                 such as Length = 0\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuSetMemoryAttributes (\r
  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
  IN EFI_PHYSICAL_ADDRESS       BaseAddress,\r
  IN UINT64                     Length,\r
  IN UINT64                     Attributes\r
  );\r
\r
/**\r
  Label of base address of IDT vector 0.\r
\r
  This is just a label of base address of IDT vector 0.\r
\r
**/\r
VOID\r
EFIAPI\r
AsmIdtVector00 (\r
  VOID\r
  );\r
\r
/**\r
  Initializes the pointer to the external interrupt vector table.\r
\r
  @param  VectorTable  Address of the external interrupt vector table.\r
\r
**/\r
VOID\r
EFIAPI\r
InitializeExternalVectorTablePtr (\r
  EFI_CPU_INTERRUPT_HANDLER  *VectorTable\r
  );\r
\r
/**\r
  Initialize Global Descriptor Table.\r
\r
**/\r
VOID\r
InitGlobalDescriptorTable (\r
  VOID\r
  );\r
\r
/**\r
  Sets the code selector (CS).\r
\r
  @param  Selector  Value of code selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetCodeSelector (\r
  UINT16 Selector\r
  );\r
\r
/**\r
  Sets the data selector (DS).\r
\r
  @param  Selector  Value of data selector.\r
\r
**/\r
VOID\r
EFIAPI\r
SetDataSelectors (\r
  UINT16 Selector\r
  );\r
\r
/**\r
  Restore original Interrupt Descriptor Table Handler Address.\r
\r
  @param Index        The Index of the interrupt descriptor table handle.\r
\r
**/\r
VOID\r
RestoreInterruptDescriptorTableHandlerAddress (\r
  IN UINTN       Index\r
  );\r
\r
#endif\r
\r
Commit	Line	Data
a47463f2	1	/** @file\r
	2	CPU DXE Module.\r
	3	\r
32394027	4	Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc	5	This program and the accompanying materials\r
a47463f2	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
430fbbe0	15	#ifndef _CPU_DXE_H_\r
430fbbe0	16	#define _CPU_DXE_H_\r
a47463f2	17	\r
	18	#include <PiDxe.h>\r
	19	\r
	20	#include <Protocol/Cpu.h>\r
	21	\r
	22	#include <Library/UefiDriverEntryPoint.h>\r
	23	#include <Library/UefiBootServicesTableLib.h>\r
	24	#include <Library/DxeServicesTableLib.h>\r
	25	#include <Library/BaseLib.h>\r
	26	#include <Library/CpuLib.h>\r
	27	#include <Library/BaseMemoryLib.h>\r
	28	#include <Library/MemoryAllocationLib.h>\r
	29	#include <Library/DebugLib.h>\r
	30	#include <Library/MtrrLib.h>\r
32394027	31	#include <Guid/IdleLoopEvent.h>\r
a47463f2	32	\r
	33	//\r
	34	//\r
	35	//\r
	36	#define INTERRUPT_VECTOR_NUMBER 256\r
	37	\r
	38	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| \\r
	39	EFI_MEMORY_WC \| \\r
	40	EFI_MEMORY_WT \| \\r
	41	EFI_MEMORY_WB \| \\r
	42	EFI_MEMORY_UCE \\r
	43	)\r
	44	\r
	45	\r
430fbbe0	46	/**\r
	47	Flush CPU data cache. If the instruction cache is fully coherent\r
	48	with all DMA operations then function can just return EFI_SUCCESS.\r
	49	\r
	50	@param This Protocol instance structure\r
	51	@param Start Physical address to start flushing from.\r
	52	@param Length Number of bytes to flush. Round up to chipset\r
	53	granularity.\r
	54	@param FlushType Specifies the type of flush operation to perform.\r
	55	\r
	56	@retval EFI_SUCCESS If cache was flushed\r
	57	@retval EFI_UNSUPPORTED If flush type is not supported.\r
	58	@retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
	59	\r
	60	**/\r
a47463f2	61	EFI_STATUS\r
	62	EFIAPI\r
	63	CpuFlushCpuDataCache (\r
	64	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	65	IN EFI_PHYSICAL_ADDRESS Start,\r
	66	IN UINT64 Length,\r
	67	IN EFI_CPU_FLUSH_TYPE FlushType\r
	68	);\r
	69	\r
430fbbe0	70	/**\r
	71	Enables CPU interrupts.\r
	72	\r
	73	@param This Protocol instance structure\r
	74	\r
	75	@retval EFI_SUCCESS If interrupts were enabled in the CPU\r
	76	@retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
	77	\r
	78	**/\r
a47463f2	79	EFI_STATUS\r
	80	EFIAPI\r
	81	CpuEnableInterrupt (\r
	82	IN EFI_CPU_ARCH_PROTOCOL *This\r
	83	);\r
	84	\r
430fbbe0	85	/**\r
	86	Disables CPU interrupts.\r
	87	\r
	88	@param This Protocol instance structure\r
	89	\r
	90	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	91	@retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
	92	\r
	93	**/\r
a47463f2	94	EFI_STATUS\r
	95	EFIAPI\r
	96	CpuDisableInterrupt (\r
	97	IN EFI_CPU_ARCH_PROTOCOL *This\r
	98	);\r
	99	\r
430fbbe0	100	/**\r
	101	Return the state of interrupts.\r
	102	\r
	103	@param This Protocol instance structure\r
	104	@param State Pointer to the CPU's current interrupt state\r
	105	\r
	106	@retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
	107	@retval EFI_INVALID_PARAMETER State is NULL.\r
	108	\r
	109	**/\r
a47463f2	110	EFI_STATUS\r
	111	EFIAPI\r
	112	CpuGetInterruptState (\r
	113	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	114	OUT BOOLEAN *State\r
	115	);\r
	116	\r
430fbbe0	117	/**\r
	118	Generates an INIT to the CPU.\r
	119	\r
	120	@param This Protocol instance structure\r
	121	@param InitType Type of CPU INIT to perform\r
	122	\r
	123	@retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
	124	seen.\r
	125	@retval EFI_DEVICE_ERROR If CPU INIT failed.\r
	126	@retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
	127	\r
	128	**/\r
a47463f2	129	EFI_STATUS\r
	130	EFIAPI\r
	131	CpuInit (\r
	132	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	133	IN EFI_CPU_INIT_TYPE InitType\r
	134	);\r
	135	\r
430fbbe0	136	/**\r
	137	Registers a function to be called from the CPU interrupt handler.\r
	138	\r
	139	@param This Protocol instance structure\r
	140	@param InterruptType Defines which interrupt to hook. IA-32\r
	141	valid range is 0x00 through 0xFF\r
	142	@param InterruptHandler A pointer to a function of type\r
	143	EFI_CPU_INTERRUPT_HANDLER that is called\r
	144	when a processor interrupt occurs. A null\r
	145	pointer is an error condition.\r
	146	\r
	147	@retval EFI_SUCCESS If handler installed or uninstalled.\r
	148	@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
	149	for InterruptType was previously installed.\r
	150	@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
	151	InterruptType was not previously installed.\r
	152	@retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
	153	is not supported.\r
	154	\r
	155	**/\r
a47463f2	156	EFI_STATUS\r
	157	EFIAPI\r
	158	CpuRegisterInterruptHandler (\r
	159	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	160	IN EFI_EXCEPTION_TYPE InterruptType,\r
	161	IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
	162	);\r
	163	\r
430fbbe0	164	/**\r
	165	Returns a timer value from one of the CPU's internal timers. There is no\r
	166	inherent time interval between ticks but is a function of the CPU frequency.\r
	167	\r
	168	@param This - Protocol instance structure.\r
	169	@param TimerIndex - Specifies which CPU timer is requested.\r
	170	@param TimerValue - Pointer to the returned timer value.\r
	171	@param TimerPeriod - A pointer to the amount of time that passes\r
	172	in femtoseconds (10-15) for each increment\r
	173	of TimerValue. If TimerValue does not\r
	174	increment at a predictable rate, then 0 is\r
	175	returned. The amount of time that has\r
	176	passed between two calls to GetTimerValue()\r
	177	can be calculated with the formula\r
	178	(TimerValue2 - TimerValue1) * TimerPeriod.\r
	179	This parameter is optional and may be NULL.\r
	180	\r
	181	@retval EFI_SUCCESS - If the CPU timer count was returned.\r
	182	@retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
	183	@retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
	184	@retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
	185	\r
	186	**/\r
a47463f2	187	EFI_STATUS\r
	188	EFIAPI\r
	189	CpuGetTimerValue (\r
	190	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	191	IN UINT32 TimerIndex,\r
	192	OUT UINT64 *TimerValue,\r
	193	OUT UINT64 *TimerPeriod OPTIONAL\r
	194	);\r
	195	\r
430fbbe0	196	/**\r
	197	Set memory cacheability attributes for given range of memeory.\r
	198	\r
	199	@param This Protocol instance structure\r
	200	@param BaseAddress Specifies the start address of the\r
	201	memory range\r
	202	@param Length Specifies the length of the memory range\r
	203	@param Attributes The memory cacheability for the memory range\r
	204	\r
	205	@retval EFI_SUCCESS If the cacheability of that memory range is\r
	206	set successfully\r
	207	@retval EFI_UNSUPPORTED If the desired operation cannot be done\r
	208	@retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
	209	such as Length = 0\r
	210	\r
	211	**/\r
a47463f2	212	EFI_STATUS\r
	213	EFIAPI\r
	214	CpuSetMemoryAttributes (\r
	215	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	216	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	217	IN UINT64 Length,\r
	218	IN UINT64 Attributes\r
	219	);\r
	220	\r
430fbbe0	221	/**\r
	222	Label of base address of IDT vector 0.\r
	223	\r
	224	This is just a label of base address of IDT vector 0.\r
	225	\r
	226	**/\r
a47463f2	227	VOID\r
	228	EFIAPI\r
	229	AsmIdtVector00 (\r
	230	VOID\r
	231	);\r
	232	\r
430fbbe0	233	/**\r
	234	Initializes the pointer to the external interrupt vector table.\r
	235	\r
	236	@param VectorTable Address of the external interrupt vector table.\r
	237	\r
	238	**/\r
a47463f2	239	VOID\r
	240	EFIAPI\r
	241	InitializeExternalVectorTablePtr (\r
	242	EFI_CPU_INTERRUPT_HANDLER *VectorTable\r
	243	);\r
	244	\r
430fbbe0	245	/**\r
	246	Initialize Global Descriptor Table.\r
	247	\r
	248	**/\r
a47463f2	249	VOID\r
	250	InitGlobalDescriptorTable (\r
	251	VOID\r
	252	);\r
	253	\r
430fbbe0	254	/**\r
	255	Sets the code selector (CS).\r
	256	\r
	257	@param Selector Value of code selector.\r
	258	\r
	259	**/\r
a47463f2	260	VOID\r
	261	EFIAPI\r
	262	SetCodeSelector (\r
	263	UINT16 Selector\r
	264	);\r
	265	\r
430fbbe0	266	/**\r
	267	Sets the data selector (DS).\r
	268	\r
	269	@param Selector Value of data selector.\r
	270	\r
	271	**/\r
a47463f2	272	VOID\r
	273	EFIAPI\r
	274	SetDataSelectors (\r
	275	UINT16 Selector\r
	276	);\r
	277	\r
de4b64f7	278	/**\r
	279	Restore original Interrupt Descriptor Table Handler Address.\r
	280	\r
	281	@param Index The Index of the interrupt descriptor table handle.\r
	282	\r
	283	**/\r
	284	VOID\r
	285	RestoreInterruptDescriptorTableHandlerAddress (\r
	286	IN UINTN Index\r
	287	);\r
a47463f2	288	\r
	289	#endif\r
	290	\r