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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuGdt.c
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a47463f2 1/** @file\r
f60f4cfe 2 C based implementation of IA32 interrupt handling only\r
a47463f2 3 requiring a minimal assembly interrupt entry point.\r
4\r
773b0bc2 5 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
0acd8697 6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
a47463f2 7\r
8**/\r
9\r
10#include "CpuDxe.h"\r
a1e8986d 11#include "CpuGdt.h"\r
a47463f2 12\r
13//\r
14// Global descriptor table (GDT) Template\r
15//\r
053e878b 16STATIC GDT_ENTRIES mGdtTemplate = {\r
a47463f2 17 //\r
18 // NULL_SEL\r
19 //\r
20 {\r
21 0x0, // limit 15:0\r
22 0x0, // base 15:0\r
23 0x0, // base 23:16\r
24 0x0, // type\r
25 0x0, // limit 19:16, flags\r
26 0x0, // base 31:24\r
27 },\r
28 //\r
29 // LINEAR_SEL\r
30 //\r
31 {\r
0d4c1db8
MK
32 0x0FFFF, // limit 15:0\r
33 0x0, // base 15:0\r
34 0x0, // base 23:16\r
35 0x092, // present, ring 0, data, read/write\r
a47463f2 36 0x0CF, // page-granular, 32-bit\r
37 0x0,\r
38 },\r
39 //\r
40 // LINEAR_CODE_SEL\r
41 //\r
42 {\r
0d4c1db8
MK
43 0x0FFFF, // limit 15:0\r
44 0x0, // base 15:0\r
45 0x0, // base 23:16\r
46 0x09F, // present, ring 0, code, execute/read, conforming, accessed\r
a47463f2 47 0x0CF, // page-granular, 32-bit\r
48 0x0,\r
49 },\r
50 //\r
51 // SYS_DATA_SEL\r
52 //\r
53 {\r
0d4c1db8
MK
54 0x0FFFF, // limit 15:0\r
55 0x0, // base 15:0\r
56 0x0, // base 23:16\r
57 0x093, // present, ring 0, data, read/write, accessed\r
a47463f2 58 0x0CF, // page-granular, 32-bit\r
59 0x0,\r
60 },\r
61 //\r
62 // SYS_CODE_SEL\r
63 //\r
64 {\r
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MK
65 0x0FFFF, // limit 15:0\r
66 0x0, // base 15:0\r
67 0x0, // base 23:16\r
68 0x09A, // present, ring 0, code, execute/read\r
a47463f2 69 0x0CF, // page-granular, 32-bit\r
70 0x0,\r
71 },\r
72 //\r
0d7601e5 73 // SYS_CODE16_SEL\r
a47463f2 74 //\r
75 {\r
0d7601e5 76 0x0FFFF, // limit 15:0\r
0d4c1db8
MK
77 0x0, // base 15:0\r
78 0x0, // base 23:16\r
0d7601e5
TL
79 0x09A, // present, ring 0, code, execute/read\r
80 0x08F, // page-granular, 16-bit\r
0d4c1db8 81 0x0, // base 31:24\r
a47463f2 82 },\r
83 //\r
0d4c1db8 84 // LINEAR_DATA64_SEL\r
a47463f2 85 //\r
86 {\r
0d4c1db8
MK
87 0x0FFFF, // limit 15:0\r
88 0x0, // base 15:0\r
89 0x0, // base 23:16\r
90 0x092, // present, ring 0, data, read/write\r
91 0x0CF, // page-granular, 32-bit\r
a47463f2 92 0x0,\r
93 },\r
94 //\r
0d4c1db8
MK
95 // LINEAR_CODE64_SEL\r
96 //\r
97 {\r
98 0x0FFFF, // limit 15:0\r
99 0x0, // base 15:0\r
100 0x0, // base 23:16\r
101 0x09A, // present, ring 0, code, execute/read\r
102 0x0AF, // page-granular, 64-bit code\r
103 0x0, // base (high)\r
104 },\r
105 //\r
a47463f2 106 // SPARE5_SEL\r
107 //\r
108 {\r
0d4c1db8
MK
109 0x0, // limit 15:0\r
110 0x0, // base 15:0\r
111 0x0, // base 23:16\r
112 0x0, // type\r
113 0x0, // limit 19:16, flags\r
114 0x0, // base 31:24\r
a47463f2 115 },\r
116};\r
117\r
118/**\r
430fbbe0 119 Initialize Global Descriptor Table.\r
a47463f2 120\r
121**/\r
122VOID\r
123InitGlobalDescriptorTable (\r
430fbbe0 124 VOID\r
a47463f2 125 )\r
126{\r
313d86c9 127 EFI_STATUS Status;\r
773b0bc2
RN
128 GDT_ENTRIES *Gdt;\r
129 IA32_DESCRIPTOR Gdtr;\r
313d86c9 130 EFI_PHYSICAL_ADDRESS Memory;\r
a47463f2 131\r
132 //\r
313d86c9
RN
133 // Allocate Runtime Data below 4GB for the GDT\r
134 // AP uses the same GDT when it's waken up from real mode so\r
135 // the GDT needs to be below 4GB.\r
136 //\r
137 Memory = SIZE_4GB - 1;\r
138 Status = gBS->AllocatePages (\r
139 AllocateMaxAddress,\r
140 EfiRuntimeServicesData,\r
141 EFI_SIZE_TO_PAGES (sizeof (mGdtTemplate)),\r
142 &Memory\r
143 );\r
144 ASSERT_EFI_ERROR (Status);\r
145 ASSERT ((Memory != 0) && (Memory < SIZE_4GB));\r
053e878b 146 Gdt = (GDT_ENTRIES *)(UINTN)Memory;\r
a47463f2 147\r
148 //\r
149 // Initialize all GDT entries\r
150 //\r
773b0bc2 151 CopyMem (Gdt, &mGdtTemplate, sizeof (mGdtTemplate));\r
a47463f2 152\r
153 //\r
154 // Write GDT register\r
155 //\r
053e878b
MK
156 Gdtr.Base = (UINT32)(UINTN)Gdt;\r
157 Gdtr.Limit = (UINT16)(sizeof (mGdtTemplate) - 1);\r
773b0bc2 158 AsmWriteGdtr (&Gdtr);\r
a47463f2 159\r
160 //\r
161 // Update selector (segment) registers base on new GDT\r
162 //\r
163 SetCodeSelector ((UINT16)CPU_CODE_SEL);\r
164 SetDataSelectors ((UINT16)CPU_DATA_SEL);\r
165}\r