UefiCpuPkg/CpuDxe: Enable protection for newly added page table
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuGdt.c
CommitLineData
a47463f2 1/** @file\r
2 C based implemention of IA32 interrupt handling only\r
3 requiring a minimal assembly interrupt entry point.\r
4\r
0d4c1db8 5 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc 6 This program and the accompanying materials\r
a47463f2 7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "CpuDxe.h"\r
a1e8986d 17#include "CpuGdt.h"\r
a47463f2 18\r
19//\r
20// Global descriptor table (GDT) Template\r
21//\r
22STATIC GDT_ENTRIES GdtTemplate = {\r
23 //\r
24 // NULL_SEL\r
25 //\r
26 {\r
27 0x0, // limit 15:0\r
28 0x0, // base 15:0\r
29 0x0, // base 23:16\r
30 0x0, // type\r
31 0x0, // limit 19:16, flags\r
32 0x0, // base 31:24\r
33 },\r
34 //\r
35 // LINEAR_SEL\r
36 //\r
37 {\r
0d4c1db8
MK
38 0x0FFFF, // limit 15:0\r
39 0x0, // base 15:0\r
40 0x0, // base 23:16\r
41 0x092, // present, ring 0, data, read/write\r
a47463f2 42 0x0CF, // page-granular, 32-bit\r
43 0x0,\r
44 },\r
45 //\r
46 // LINEAR_CODE_SEL\r
47 //\r
48 {\r
0d4c1db8
MK
49 0x0FFFF, // limit 15:0\r
50 0x0, // base 15:0\r
51 0x0, // base 23:16\r
52 0x09F, // present, ring 0, code, execute/read, conforming, accessed\r
a47463f2 53 0x0CF, // page-granular, 32-bit\r
54 0x0,\r
55 },\r
56 //\r
57 // SYS_DATA_SEL\r
58 //\r
59 {\r
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MK
60 0x0FFFF, // limit 15:0\r
61 0x0, // base 15:0\r
62 0x0, // base 23:16\r
63 0x093, // present, ring 0, data, read/write, accessed\r
a47463f2 64 0x0CF, // page-granular, 32-bit\r
65 0x0,\r
66 },\r
67 //\r
68 // SYS_CODE_SEL\r
69 //\r
70 {\r
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MK
71 0x0FFFF, // limit 15:0\r
72 0x0, // base 15:0\r
73 0x0, // base 23:16\r
74 0x09A, // present, ring 0, code, execute/read\r
a47463f2 75 0x0CF, // page-granular, 32-bit\r
76 0x0,\r
77 },\r
78 //\r
0d4c1db8 79 // SPARE4_SEL\r
a47463f2 80 //\r
81 {\r
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MK
82 0x0, // limit 15:0\r
83 0x0, // base 15:0\r
84 0x0, // base 23:16\r
85 0x0, // type\r
86 0x0, // limit 19:16, flags\r
87 0x0, // base 31:24\r
a47463f2 88 },\r
89 //\r
0d4c1db8 90 // LINEAR_DATA64_SEL\r
a47463f2 91 //\r
92 {\r
0d4c1db8
MK
93 0x0FFFF, // limit 15:0\r
94 0x0, // base 15:0\r
95 0x0, // base 23:16\r
96 0x092, // present, ring 0, data, read/write\r
97 0x0CF, // page-granular, 32-bit\r
a47463f2 98 0x0,\r
99 },\r
100 //\r
0d4c1db8
MK
101 // LINEAR_CODE64_SEL\r
102 //\r
103 {\r
104 0x0FFFF, // limit 15:0\r
105 0x0, // base 15:0\r
106 0x0, // base 23:16\r
107 0x09A, // present, ring 0, code, execute/read\r
108 0x0AF, // page-granular, 64-bit code\r
109 0x0, // base (high)\r
110 },\r
111 //\r
a47463f2 112 // SPARE5_SEL\r
113 //\r
114 {\r
0d4c1db8
MK
115 0x0, // limit 15:0\r
116 0x0, // base 15:0\r
117 0x0, // base 23:16\r
118 0x0, // type\r
119 0x0, // limit 19:16, flags\r
120 0x0, // base 31:24\r
a47463f2 121 },\r
122};\r
123\r
124/**\r
430fbbe0 125 Initialize Global Descriptor Table.\r
a47463f2 126\r
127**/\r
128VOID\r
129InitGlobalDescriptorTable (\r
430fbbe0 130 VOID\r
a47463f2 131 )\r
132{\r
133 GDT_ENTRIES *gdt;\r
134 IA32_DESCRIPTOR gdtPtr;\r
135\r
136 //\r
137 // Allocate Runtime Data for the GDT\r
138 //\r
139 gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);\r
140 ASSERT (gdt != NULL);\r
141 gdt = ALIGN_POINTER (gdt, 8);\r
142\r
143 //\r
144 // Initialize all GDT entries\r
145 //\r
146 CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));\r
147\r
148 //\r
149 // Write GDT register\r
150 //\r
151 gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;\r
5b7e61a0 152 gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);\r
a47463f2 153 AsmWriteGdtr (&gdtPtr);\r
154\r
155 //\r
156 // Update selector (segment) registers base on new GDT\r
157 //\r
158 SetCodeSelector ((UINT16)CPU_CODE_SEL);\r
159 SetDataSelectors ((UINT16)CPU_DATA_SEL);\r
160}\r
161\r