[mirror_edk2.git] / UefiCpuPkg / CpuDxe / X64 / CpuAsm.asm

      TITLE   CpuAsm.asm: \r
;------------------------------------------------------------------------------\r
;*\r
;*   Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>\r
;*   This program and the accompanying materials                          \r
;*   are licensed and made available under the terms and conditions of the BSD License         \r
;*   which accompanies this distribution.  The full text of the license may be found at        \r
;*   http://opensource.org/licenses/bsd-license.php                                            \r
;*                                                                                             \r
;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
;*   \r
;*    CpuAsm.asm\r
;*  \r
;*   Abstract:\r
;*\r
;------------------------------------------------------------------------------\r
\r
    .code\r
\r
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions\r
\r
;\r
; point to the external interrupt vector table\r
;\r
ExternalVectorTablePtr QWORD 0\r
\r
InitializeExternalVectorTablePtr PROC PUBLIC\r
    mov  ExternalVectorTablePtr, rcx\r
    ret\r
InitializeExternalVectorTablePtr ENDP\r
\r
;------------------------------------------------------------------------------\r
; VOID\r
; SetCodeSelector (\r
;   UINT16 Selector\r
;   );\r
;------------------------------------------------------------------------------\r
SetCodeSelector PROC PUBLIC\r
    sub     rsp, 0x10\r
    lea     rax, setCodeSelectorLongJump\r
    mov     [rsp], rax\r
    mov     [rsp+4], cx\r
    jmp     fword ptr [rsp]\r
setCodeSelectorLongJump:\r
    add     rsp, 0x10\r
    ret\r
SetCodeSelector ENDP\r
\r
;------------------------------------------------------------------------------\r
; VOID\r
; SetDataSelectors (\r
;   UINT16 Selector\r
;   );\r
;------------------------------------------------------------------------------\r
SetDataSelectors PROC PUBLIC\r
    mov     ss, cx\r
    mov     ds, cx\r
    mov     es, cx\r
    mov     fs, cx\r
    mov     gs, cx\r
    ret\r
SetDataSelectors ENDP\r
\r
;---------------------------------------;\r
; CommonInterruptEntry                  ;\r
;---------------------------------------;\r
; The follow algorithm is used for the common interrupt routine.\r
\r
CommonInterruptEntry PROC PUBLIC  \r
    cli\r
    ;\r
    ; All interrupt handlers are invoked through interrupt gates, so\r
    ; IF flag automatically cleared at the entry point\r
    ;\r
    ;\r
    ; Calculate vector number\r
    ;\r
    xchg    rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.\r
    movzx   ecx, word ptr [rcx]\r
    cmp     ecx, 32         ; Intel reserved vector for exceptions?\r
    jae     NoErrorCode\r
    bt      mErrorCodeFlag, ecx\r
    jc      @F\r
\r
NoErrorCode:\r
\r
    ;\r
    ; Push a dummy error code on the stack\r
    ; to maintain coherent stack map\r
    ;\r
    push    [rsp]\r
    mov     qword ptr [rsp + 8], 0\r
@@:       \r
    push    rbp\r
    mov     rbp, rsp\r
\r
    ;\r
    ; Stack:\r
    ; +---------------------+ <-- 16-byte aligned ensured by processor\r
    ; +    Old SS           +\r
    ; +---------------------+\r
    ; +    Old RSP          +\r
    ; +---------------------+\r
    ; +    RFlags           +\r
    ; +---------------------+\r
    ; +    CS               +\r
    ; +---------------------+\r
    ; +    RIP              +\r
    ; +---------------------+\r
    ; +    Error Code       +\r
    ; +---------------------+\r
    ; + RCX / Vector Number +\r
    ; +---------------------+\r
    ; +    RBP              +\r
    ; +---------------------+ <-- RBP, 16-byte aligned\r
    ;\r
\r
\r
    ;\r
    ; Since here the stack pointer is 16-byte aligned, so\r
    ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64\r
    ; is 16-byte aligned\r
    ;\r
\r
;; UINT64  Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
;; UINT64  R8, R9, R10, R11, R12, R13, R14, R15;\r
    push r15\r
    push r14\r
    push r13\r
    push r12\r
    push r11\r
    push r10\r
    push r9\r
    push r8\r
    push rax\r
    push qword ptr [rbp + 8]   ; RCX\r
    push rdx\r
    push rbx\r
    push qword ptr [rbp + 48]  ; RSP\r
    push qword ptr [rbp]       ; RBP\r
    push rsi\r
    push rdi\r
\r
;; UINT64  Gs, Fs, Es, Ds, Cs, Ss;  insure high 16 bits of each is zero\r
    movzx   rax, word ptr [rbp + 56]\r
    push    rax                      ; for ss\r
    movzx   rax, word ptr [rbp + 32]\r
    push    rax                      ; for cs\r
    mov     rax, ds\r
    push    rax\r
    mov     rax, es\r
    push    rax\r
    mov     rax, fs\r
    push    rax\r
    mov     rax, gs\r
    push    rax\r
\r
    mov     [rbp + 8], rcx               ; save vector number\r
\r
;; UINT64  Rip;\r
    push    qword ptr [rbp + 24]\r
\r
;; UINT64  Gdtr[2], Idtr[2];\r
    xor     rax, rax\r
    push    rax\r
    push    rax\r
    sidt    [rsp]\r
    xchg    rax, [rsp + 2]\r
    xchg    rax, [rsp]\r
    xchg    rax, [rsp + 8]\r
\r
    xor     rax, rax\r
    push    rax\r
    push    rax\r
    sgdt    [rsp]\r
    xchg    rax, [rsp + 2]\r
    xchg    rax, [rsp]\r
    xchg    rax, [rsp + 8]\r
\r
;; UINT64  Ldtr, Tr;\r
    xor     rax, rax\r
    str     ax\r
    push    rax\r
    sldt    ax\r
    push    rax\r
\r
;; UINT64  RFlags;\r
    push    qword ptr [rbp + 40]\r
\r
;; UINT64  Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
    mov     rax, cr8\r
    push    rax\r
    mov     rax, cr4\r
    or      rax, 208h\r
    mov     cr4, rax\r
    push    rax\r
    mov     rax, cr3\r
    push    rax\r
    mov     rax, cr2\r
    push    rax\r
    xor     rax, rax\r
    push    rax\r
    mov     rax, cr0\r
    push    rax\r
\r
;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
    mov     rax, dr7\r
    push    rax\r
    mov     rax, dr6\r
    push    rax\r
    mov     rax, dr3\r
    push    rax\r
    mov     rax, dr2\r
    push    rax\r
    mov     rax, dr1\r
    push    rax\r
    mov     rax, dr0\r
    push    rax\r
\r
;; FX_SAVE_STATE_X64 FxSaveState;\r
    sub rsp, 512\r
    mov rdi, rsp\r
    db 0fh, 0aeh, 07h ;fxsave [rdi]\r
\r
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear\r
    cld\r
\r
;; UINT32  ExceptionData;\r
    push    qword ptr [rbp + 16]\r
\r
;; call into exception handler\r
    mov     rcx, [rbp + 8]\r
    mov     rax, ExternalVectorTablePtr  ; get the interrupt vectors base\r
    mov     rax, [rax + rcx * 8]       \r
    or      rax, rax                        ; NULL?\r
\r
    je    nonNullValue;\r
\r
;; Prepare parameter and call\r
;  mov     rcx, [rbp + 8]\r
    mov     rdx, rsp\r
    ;\r
    ; Per X64 calling convention, allocate maximum parameter stack space\r
    ; and make sure RSP is 16-byte aligned\r
    ;\r
    sub     rsp, 4 * 8 + 8\r
    call    rax\r
    add     rsp, 4 * 8 + 8\r
\r
nonNullValue:\r
    cli\r
;; UINT64  ExceptionData;\r
    add     rsp, 8\r
\r
;; FX_SAVE_STATE_X64 FxSaveState;\r
\r
    mov rsi, rsp\r
    db 0fh, 0aeh, 0Eh ; fxrstor [rsi]\r
    add rsp, 512\r
\r
;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
;; Skip restoration of DRx registers to support in-circuit emualators\r
;; or debuggers set breakpoint in interrupt/exception context\r
    add     rsp, 8 * 6\r
\r
;; UINT64  Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
    pop     rax\r
    mov     cr0, rax\r
    add     rsp, 8   ; not for Cr1\r
    pop     rax\r
    mov     cr2, rax\r
    pop     rax\r
    mov     cr3, rax\r
    pop     rax\r
    mov     cr4, rax\r
    pop     rax\r
    mov     cr8, rax\r
\r
;; UINT64  RFlags;\r
    pop     qword ptr [rbp + 40]\r
\r
;; UINT64  Ldtr, Tr;\r
;; UINT64  Gdtr[2], Idtr[2];\r
;; Best not let anyone mess with these particular registers...\r
    add     rsp, 48\r
\r
;; UINT64  Rip;\r
    pop     qword ptr [rbp + 24]\r
\r
;; UINT64  Gs, Fs, Es, Ds, Cs, Ss;\r
    pop     rax\r
    ; mov     gs, rax ; not for gs\r
    pop     rax\r
    ; mov     fs, rax ; not for fs\r
    ; (X64 will not use fs and gs, so we do not restore it)\r
    pop     rax\r
    mov     es, rax\r
    pop     rax\r
    mov     ds, rax\r
    pop     qword ptr [rbp + 32]  ; for cs\r
    pop     qword ptr [rbp + 56]  ; for ss\r
\r
;; UINT64  Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
;; UINT64  R8, R9, R10, R11, R12, R13, R14, R15;\r
    pop     rdi\r
    pop     rsi\r
    add     rsp, 8               ; not for rbp\r
    pop     qword ptr [rbp + 48] ; for rsp\r
    pop     rbx\r
    pop     rdx\r
    pop     rcx\r
    pop     rax\r
    pop     r8\r
    pop     r9\r
    pop     r10\r
    pop     r11\r
    pop     r12\r
    pop     r13\r
    pop     r14\r
    pop     r15\r
\r
    mov     rsp, rbp\r
    pop     rbp\r
    add     rsp, 16\r
    iretq\r
\r
CommonInterruptEntry ENDP\r
\r
END\r
\r
Commit	Line	Data
a47463f2	1	TITLE CpuAsm.asm: \r
	2	;------------------------------------------------------------------------------\r
	3	;*\r
ad8cbf71	4	;* Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc	5	;* This program and the accompanying materials \r
a47463f2	6	;* are licensed and made available under the terms and conditions of the BSD License \r
	7	;* which accompanies this distribution. The full text of the license may be found at \r
	8	;* http://opensource.org/licenses/bsd-license.php \r
	9	;* \r
	10	;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	;* \r
	13	;* CpuAsm.asm\r
	14	;* \r
	15	;* Abstract:\r
	16	;*\r
	17	;------------------------------------------------------------------------------\r
	18	\r
	19	.code\r
	20	\r
	21	EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions\r
	22	\r
	23	;\r
	24	; point to the external interrupt vector table\r
	25	;\r
	26	ExternalVectorTablePtr QWORD 0\r
	27	\r
	28	InitializeExternalVectorTablePtr PROC PUBLIC\r
	29	mov ExternalVectorTablePtr, rcx\r
	30	ret\r
	31	InitializeExternalVectorTablePtr ENDP\r
	32	\r
	33	;------------------------------------------------------------------------------\r
	34	; VOID\r
	35	; SetCodeSelector (\r
	36	; UINT16 Selector\r
	37	; );\r
	38	;------------------------------------------------------------------------------\r
	39	SetCodeSelector PROC PUBLIC\r
	40	sub rsp, 0x10\r
	41	lea rax, setCodeSelectorLongJump\r
	42	mov [rsp], rax\r
	43	mov [rsp+4], cx\r
	44	jmp fword ptr [rsp]\r
	45	setCodeSelectorLongJump:\r
	46	add rsp, 0x10\r
	47	ret\r
	48	SetCodeSelector ENDP\r
	49	\r
	50	;------------------------------------------------------------------------------\r
	51	; VOID\r
	52	; SetDataSelectors (\r
	53	; UINT16 Selector\r
	54	; );\r
	55	;------------------------------------------------------------------------------\r
	56	SetDataSelectors PROC PUBLIC\r
	57	mov ss, cx\r
	58	mov ds, cx\r
	59	mov es, cx\r
	60	mov fs, cx\r
	61	mov gs, cx\r
	62	ret\r
	63	SetDataSelectors ENDP\r
	64	\r
	65	;---------------------------------------;\r
	66	; CommonInterruptEntry ;\r
	67	;---------------------------------------;\r
	68	; The follow algorithm is used for the common interrupt routine.\r
	69	\r
70	CommonInterruptEntry PROC PUBLIC \r
71	cli\r
72	;\r
73	; All interrupt handlers are invoked through interrupt gates, so\r
74	; IF flag automatically cleared at the entry point\r
75	;\r
76	;\r
77	; Calculate vector number\r
78	;\r
79	xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.\r
80	movzx ecx, word ptr [rcx]\r
81	cmp ecx, 32 ; Intel reserved vector for exceptions?\r
82	jae NoErrorCode\r
83	bt mErrorCodeFlag, ecx\r
84	jc @F\r
85	\r
86	NoErrorCode:\r
87	\r
88	;\r
89	; Push a dummy error code on the stack\r
90	; to maintain coherent stack map\r
91	;\r
92	push [rsp]\r
93	mov qword ptr [rsp + 8], 0\r
94	@@: \r
95	push rbp\r
96	mov rbp, rsp\r
97	\r
98	;\r
99	; Stack:\r
100	; +---------------------+ <-- 16-byte aligned ensured by processor\r
101	; + Old SS +\r
102	; +---------------------+\r
103	; + Old RSP +\r
104	; +---------------------+\r
105	; + RFlags +\r
106	; +---------------------+\r
107	; + CS +\r
108	; +---------------------+\r
109	; + RIP +\r
110	; +---------------------+\r
111	; + Error Code +\r
112	; +---------------------+\r
113	; + RCX / Vector Number +\r
114	; +---------------------+\r
115	; + RBP +\r
116	; +---------------------+ <-- RBP, 16-byte aligned\r
117	;\r
118	\r
119	\r
120	;\r
121	; Since here the stack pointer is 16-byte aligned, so\r
122	; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64\r
123	; is 16-byte aligned\r
124	;\r
125	\r
126	;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
127	;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
128	push r15\r
129	push r14\r
130	push r13\r
131	push r12\r
132	push r11\r
133	push r10\r
134	push r9\r
135	push r8\r
136	push rax\r
137	push qword ptr [rbp + 8] ; RCX\r
138	push rdx\r
139	push rbx\r
140	push qword ptr [rbp + 48] ; RSP\r
141	push qword ptr [rbp] ; RBP\r
142	push rsi\r
143	push rdi\r
144	\r
145	;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero\r
146	movzx rax, word ptr [rbp + 56]\r
147	push rax ; for ss\r
148	movzx rax, word ptr [rbp + 32]\r
149	push rax ; for cs\r
150	mov rax, ds\r
151	push rax\r
152	mov rax, es\r
153	push rax\r
154	mov rax, fs\r
155	push rax\r
156	mov rax, gs\r
157	push rax\r
158	\r
159	mov [rbp + 8], rcx ; save vector number\r
160	\r
161	;; UINT64 Rip;\r
162	push qword ptr [rbp + 24]\r
163	\r
164	;; UINT64 Gdtr[2], Idtr[2];\r
165	xor rax, rax\r
166	push rax\r
167	push rax\r
168	sidt [rsp]\r
169	xchg rax, [rsp + 2]\r
170	xchg rax, [rsp]\r
171	xchg rax, [rsp + 8]\r
172	\r
173	xor rax, rax\r
174	push rax\r
175	push rax\r
176	sgdt [rsp]\r
177	xchg rax, [rsp + 2]\r
178	xchg rax, [rsp]\r
179	xchg rax, [rsp + 8]\r
180	\r
181	;; UINT64 Ldtr, Tr;\r
182	xor rax, rax\r
183	str ax\r
184	push rax\r
185	sldt ax\r
186	push rax\r
187	\r
188	;; UINT64 RFlags;\r
189	push qword ptr [rbp + 40]\r
190	\r
191	;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
192	mov rax, cr8\r
193	push rax\r
194	mov rax, cr4\r
195	or rax, 208h\r
196	mov cr4, rax\r
197	push rax\r
198	mov rax, cr3\r
199	push rax\r
200	mov rax, cr2\r
201	push rax\r
202	xor rax, rax\r
203	push rax\r
204	mov rax, cr0\r
205	push rax\r
206	\r
207	;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
208	mov rax, dr7\r
209	push rax\r
a47463f2	210	mov rax, dr6\r
a47463f2	211	push rax\r
a47463f2	212	mov rax, dr3\r
	213	push rax\r
	214	mov rax, dr2\r
	215	push rax\r
	216	mov rax, dr1\r
	217	push rax\r
	218	mov rax, dr0\r
	219	push rax\r
	220	\r
	221	;; FX_SAVE_STATE_X64 FxSaveState;\r
	222	sub rsp, 512\r
	223	mov rdi, rsp\r
	224	db 0fh, 0aeh, 07h ;fxsave [rdi]\r
	225	\r
ad8cbf71	226	;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear\r
	227	cld\r
	228	\r
a47463f2	229	;; UINT32 ExceptionData;\r
	230	push qword ptr [rbp + 16]\r
	231	\r
	232	;; call into exception handler\r
	233	mov rcx, [rbp + 8]\r
	234	mov rax, ExternalVectorTablePtr ; get the interrupt vectors base\r
	235	mov rax, [rax + rcx * 8] \r
	236	or rax, rax ; NULL?\r
	237	\r
	238	je nonNullValue;\r
	239	\r
	240	;; Prepare parameter and call\r
	241	; mov rcx, [rbp + 8]\r
	242	mov rdx, rsp\r
	243	;\r
	244	; Per X64 calling convention, allocate maximum parameter stack space\r
	245	; and make sure RSP is 16-byte aligned\r
	246	;\r
	247	sub rsp, 4 * 8 + 8\r
	248	call rax\r
	249	add rsp, 4 * 8 + 8\r
	250	\r
	251	nonNullValue:\r
	252	cli\r
	253	;; UINT64 ExceptionData;\r
	254	add rsp, 8\r
	255	\r
	256	;; FX_SAVE_STATE_X64 FxSaveState;\r
	257	\r
	258	mov rsi, rsp\r
	259	db 0fh, 0aeh, 0Eh ; fxrstor [rsi]\r
	260	add rsp, 512\r
	261	\r
	262	;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
61ece967	263	;; Skip restoration of DRx registers to support in-circuit emualators\r
	264	;; or debuggers set breakpoint in interrupt/exception context\r
	265	add rsp, 8 * 6\r
a47463f2	266	\r
	267	;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
	268	pop rax\r
	269	mov cr0, rax\r
	270	add rsp, 8 ; not for Cr1\r
	271	pop rax\r
	272	mov cr2, rax\r
	273	pop rax\r
	274	mov cr3, rax\r
	275	pop rax\r
	276	mov cr4, rax\r
	277	pop rax\r
	278	mov cr8, rax\r
	279	\r
	280	;; UINT64 RFlags;\r
	281	pop qword ptr [rbp + 40]\r
	282	\r
	283	;; UINT64 Ldtr, Tr;\r
	284	;; UINT64 Gdtr[2], Idtr[2];\r
	285	;; Best not let anyone mess with these particular registers...\r
	286	add rsp, 48\r
	287	\r
	288	;; UINT64 Rip;\r
	289	pop qword ptr [rbp + 24]\r
	290	\r
	291	;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;\r
	292	pop rax\r
	293	; mov gs, rax ; not for gs\r
	294	pop rax\r
	295	; mov fs, rax ; not for fs\r
	296	; (X64 will not use fs and gs, so we do not restore it)\r
	297	pop rax\r
	298	mov es, rax\r
	299	pop rax\r
	300	mov ds, rax\r
	301	pop qword ptr [rbp + 32] ; for cs\r
	302	pop qword ptr [rbp + 56] ; for ss\r
	303	\r
	304	;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
	305	;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
	306	pop rdi\r
	307	pop rsi\r
	308	add rsp, 8 ; not for rbp\r
	309	pop qword ptr [rbp + 48] ; for rsp\r
	310	pop rbx\r
	311	pop rdx\r
	312	pop rcx\r
	313	pop rax\r
	314	pop r8\r
	315	pop r9\r
	316	pop r10\r
	317	pop r11\r
	318	pop r12\r
	319	pop r13\r
	320	pop r14\r
	321	pop r15\r
	322	\r
	323	mov rsp, rbp\r
	324	pop rbp\r
	325	add rsp, 16\r
	326	iretq\r
	327	\r
	328	CommonInterruptEntry ENDP\r
	329	\r
330	END\r
331	\r