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1c27f926 MK |
1 | /** @file\r |
2 | Definitions for CPU S3 data.\r | |
3 | \r | |
fcd92f16 | 4 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1c27f926 MK |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #ifndef _ACPI_CPU_DATA_H_\r | |
10 | #define _ACPI_CPU_DATA_H_\r | |
11 | \r | |
12 | //\r | |
13 | // Register types in register table\r | |
14 | //\r | |
af381fda | 15 | typedef enum {\r |
1c27f926 MK |
16 | Msr,\r |
17 | ControlRegister,\r | |
18 | MemoryMapped,\r | |
d5aa2078 ED |
19 | CacheControl,\r |
20 | \r | |
21 | //\r | |
22 | // Semaphore type used to control the execute sequence of the Msr.\r | |
23 | // It will be insert between two Msr which has execute dependence.\r | |
24 | //\r | |
25 | Semaphore,\r | |
26 | InvalidReg\r | |
1c27f926 MK |
27 | } REGISTER_TYPE;\r |
28 | \r | |
d5aa2078 ED |
29 | //\r |
30 | // Describe the dependency type for different features.\r | |
31 | // The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is Semaphore.\r | |
32 | //\r | |
33 | typedef enum {\r | |
34 | NoneDepType,\r | |
35 | ThreadDepType,\r | |
36 | CoreDepType,\r | |
37 | PackageDepType,\r | |
38 | InvalidDepType\r | |
39 | } CPU_FEATURE_DEPENDENCE_TYPE;\r | |
40 | \r | |
41 | //\r | |
42 | // CPU information.\r | |
43 | //\r | |
44 | typedef struct {\r | |
45 | //\r | |
46 | // Record the package count in this CPU.\r | |
47 | //\r | |
48 | UINT32 PackageCount;\r | |
49 | //\r | |
50 | // Record the max core count in this CPU.\r | |
51 | // Different packages may have different core count, this value\r | |
52 | // save the max core count in all the packages.\r | |
53 | //\r | |
54 | UINT32 MaxCoreCount;\r | |
55 | //\r | |
56 | // Record the max thread count in this CPU.\r | |
57 | // Different cores may have different thread count, this value\r | |
58 | // save the max thread count in all the cores.\r | |
59 | //\r | |
60 | UINT32 MaxThreadCount;\r | |
61 | //\r | |
62 | // This field points to an array.\r | |
63 | // This array saves valid core count (type UINT32) of each package.\r | |
64 | // The array has PackageCount elements.\r | |
65 | //\r | |
66 | // If the platform does not support MSR setting at S3 resume, and\r | |
67 | // therefore it doesn't need the dependency semaphores, it should set\r | |
68 | // this field to 0.\r | |
69 | //\r | |
70 | EFI_PHYSICAL_ADDRESS ValidCoreCountPerPackage;\r | |
71 | } CPU_STATUS_INFORMATION;\r | |
72 | \r | |
1c27f926 MK |
73 | //\r |
74 | // Element of register table entry\r | |
75 | //\r | |
76 | typedef struct {\r | |
30b7a50b JF |
77 | REGISTER_TYPE RegisterType; // offset 0 - 3\r |
78 | UINT32 Index; // offset 4 - 7\r | |
79 | UINT8 ValidBitStart; // offset 8\r | |
80 | UINT8 ValidBitLength; // offset 9\r | |
81 | UINT16 Reserved; // offset 10 - 11\r | |
82 | UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped\r | |
83 | UINT64 Value; // offset 16-23\r | |
1c27f926 MK |
84 | } CPU_REGISTER_TABLE_ENTRY;\r |
85 | \r | |
86 | //\r | |
87 | // Register table definition, including current table length,\r | |
88 | // allocated size of this table, and pointer to the list of table entries.\r | |
89 | //\r | |
90 | typedef struct {\r | |
af381fda MK |
91 | //\r |
92 | // The number of valid entries in the RegisterTableEntry buffer\r | |
93 | //\r | |
94 | UINT32 TableLength;\r | |
95 | UINT32 NumberBeforeReset;\r | |
96 | //\r | |
97 | // The size, in bytes, of the RegisterTableEntry buffer\r | |
98 | //\r | |
99 | UINT32 AllocatedSize;\r | |
100 | //\r | |
101 | // The initial APIC ID of the CPU this register table applies to\r | |
102 | //\r | |
103 | UINT32 InitialApicId;\r | |
104 | //\r | |
fcd92f16 | 105 | // Physical address of CPU_REGISTER_TABLE_ENTRY structures.\r |
af381fda | 106 | //\r |
9cc45009 | 107 | EFI_PHYSICAL_ADDRESS RegisterTableEntry;\r |
1c27f926 MK |
108 | } CPU_REGISTER_TABLE;\r |
109 | \r | |
af381fda | 110 | //\r |
fcd92f16 | 111 | // Data structure that is required for ACPI S3 resume. The PCD\r |
af381fda MK |
112 | // PcdCpuS3DataAddress must be set to the physical address where this structure\r |
113 | // is allocated\r | |
114 | //\r | |
1c27f926 | 115 | typedef struct {\r |
af381fda MK |
116 | //\r |
117 | // Physical address of 4KB buffer allocated below 1MB from memory of type\r | |
118 | // EfiReservedMemoryType. The buffer is not required to be initialized, but\r | |
119 | // it is recommended that the buffer be zero-filled. This buffer is used to\r | |
120 | // wake APs during an ACPI S3 resume.\r | |
121 | //\r | |
1c27f926 | 122 | EFI_PHYSICAL_ADDRESS StartupVector;\r |
af381fda | 123 | //\r |
fcd92f16 | 124 | // Physical address of structure of type IA32_DESCRIPTOR. The\r |
af381fda | 125 | // IA32_DESCRIPTOR structure provides the base address and length of a GDT\r |
fcd92f16 | 126 | // The GDT must be filled in with the GDT contents that are\r |
af381fda MK |
127 | // used during an ACPI S3 resume. This is typically the contents of the GDT\r |
128 | // used by the boot processor when the platform is booted.\r | |
129 | //\r | |
1c27f926 | 130 | EFI_PHYSICAL_ADDRESS GdtrProfile;\r |
af381fda | 131 | //\r |
fcd92f16 | 132 | // Physical address of structure of type IA32_DESCRIPTOR. The\r |
af381fda | 133 | // IA32_DESCRIPTOR structure provides the base address and length of an IDT.\r |
fcd92f16 | 134 | // The IDT must be filled in with the IDT contents that are\r |
af381fda MK |
135 | // used during an ACPI S3 resume. This is typically the contents of the IDT\r |
136 | // used by the boot processor when the platform is booted.\r | |
137 | //\r | |
1c27f926 | 138 | EFI_PHYSICAL_ADDRESS IdtrProfile;\r |
af381fda MK |
139 | //\r |
140 | // Physical address of a buffer that is used as stacks during ACPI S3 resume.\r | |
141 | // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This\r | |
fcd92f16 | 142 | // structure must be allocated from memory of type EfiACPIMemoryNVS.\r |
af381fda | 143 | //\r |
1c27f926 | 144 | EFI_PHYSICAL_ADDRESS StackAddress;\r |
af381fda MK |
145 | //\r |
146 | // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.\r | |
147 | //\r | |
1c27f926 | 148 | UINT32 StackSize;\r |
af381fda MK |
149 | //\r |
150 | // The number of CPUs. If a platform does not support hot plug CPUs, then\r | |
151 | // this is the number of CPUs detected when the platform is booted, regardless\r | |
152 | // of being enabled or disabled. If a platform does support hot plug CPUs,\r | |
153 | // then this is the maximum number of CPUs that the platform supports.\r | |
154 | //\r | |
1c27f926 | 155 | UINT32 NumberOfCpus;\r |
af381fda MK |
156 | //\r |
157 | // Physical address of structure of type MTRR_SETTINGS that contains a copy\r | |
158 | // of the MTRR settings that are compatible with the MTRR settings used by\r | |
159 | // the boot processor when the platform was booted. These MTRR settings are\r | |
fcd92f16 | 160 | // used during an ACPI S3 resume.\r |
af381fda | 161 | //\r |
1c27f926 MK |
162 | EFI_PHYSICAL_ADDRESS MtrrTable;\r |
163 | //\r | |
af381fda | 164 | // Physical address of an array of CPU_REGISTER_TABLE structures, with\r |
fcd92f16 | 165 | // NumberOfCpus entries. If a register table is not required, then the\r |
af381fda MK |
166 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r |
167 | // If TableLength is > 0, then elements of RegisterTableEntry are used to\r | |
168 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r | |
169 | // before SMBASE relocation is performed.\r | |
1c27f926 MK |
170 | //\r |
171 | EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;\r | |
172 | //\r | |
af381fda | 173 | // Physical address of an array of CPU_REGISTER_TABLE structures, with\r |
fcd92f16 | 174 | // NumberOfCpus entries. If a register table is not required, then the\r |
af381fda MK |
175 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r |
176 | // If TableLength is > 0, then elements of RegisterTableEntry are used to\r | |
177 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r | |
178 | // after SMBASE relocation is performed.\r | |
1c27f926 MK |
179 | //\r |
180 | EFI_PHYSICAL_ADDRESS RegisterTable;\r | |
af381fda MK |
181 | //\r |
182 | // Physical address of a buffer that contains the machine check handler that\r | |
fcd92f16 | 183 | // is used during an ACPI S3 Resume. In order for this machine check\r |
af381fda MK |
184 | // handler to be active on an AP during an ACPI S3 resume, the machine check\r |
185 | // vector in the IDT provided by IdtrProfile must be initialized to transfer\r | |
186 | // control to this physical address.\r | |
187 | //\r | |
1c27f926 | 188 | EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase;\r |
af381fda MK |
189 | //\r |
190 | // The size, in bytes, of the machine check handler that is used during an\r | |
191 | // ACPI S3 Resume. If this field is 0, then a machine check handler is not\r | |
192 | // provided.\r | |
193 | //\r | |
1c27f926 | 194 | UINT32 ApMachineCheckHandlerSize;\r |
d5aa2078 ED |
195 | //\r |
196 | // CPU information which is required when set the register table.\r | |
197 | //\r | |
198 | CPU_STATUS_INFORMATION CpuStatus;\r | |
199 | //\r | |
200 | // Location info for each AP.\r | |
201 | // It points to an array which saves all APs location info.\r | |
202 | // The array count is the AP count in this CPU.\r | |
203 | //\r | |
204 | // If the platform does not support MSR setting at S3 resume, and\r | |
205 | // therefore it doesn't need the dependency semaphores, it should set\r | |
206 | // this field to 0.\r | |
207 | //\r | |
208 | EFI_PHYSICAL_ADDRESS ApLocation;\r | |
1c27f926 MK |
209 | } ACPI_CPU_DATA;\r |
210 | \r | |
211 | #endif\r |