UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
[mirror_edk2.git] / UefiCpuPkg / Include / Library / LocalApicLib.h
CommitLineData
bf73cc4b 1/** @file\r
2 Public include file for Local APIC library.\r
3\r
4 Local APIC library assumes local APIC is enabled. It does not\r
5 handles cases where local APIC is disabled.\r
6\r
14e4ca25 7 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
bf73cc4b 8 This program and the accompanying materials\r
9 are licensed and made available under the terms and conditions of the BSD License\r
10 which accompanies this distribution. The full text of the license may be found at\r
11 http://opensource.org/licenses/bsd-license.php\r
12\r
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
15\r
16**/\r
17\r
18#ifndef __LOCAL_APIC_LIB_H__\r
19#define __LOCAL_APIC_LIB_H__\r
20\r
21#define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.\r
22#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.\r
23\r
a66e0c7d 24/**\r
25 Retrieve the base address of local APIC.\r
26\r
27 @return The base address of local APIC.\r
28\r
29**/\r
30UINTN\r
31EFIAPI\r
32GetLocalApicBaseAddress (\r
33 VOID\r
34 );\r
35\r
36/**\r
37 Set the base address of local APIC.\r
38\r
39 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
40\r
41 @param[in] BaseAddress Local APIC base address to be set.\r
42\r
43**/\r
44VOID\r
45EFIAPI\r
46SetLocalApicBaseAddress (\r
47 IN UINTN BaseAddress\r
48 );\r
49\r
bf73cc4b 50/**\r
51 Get the current local APIC mode.\r
52\r
53 If local APIC is disabled, then ASSERT.\r
54\r
55 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
56 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
57**/\r
58UINTN\r
59EFIAPI\r
60GetApicMode (\r
61 VOID\r
62 );\r
63\r
64/**\r
65 Set the current local APIC mode.\r
66\r
67 If the specified local APIC mode is not valid, then ASSERT.\r
68 If the specified local APIC mode can't be set as current, then ASSERT.\r
69\r
70 @param ApicMode APIC mode to be set.\r
9c71e1e0
JF
71\r
72 @note This API must not be called from an interrupt handler or SMI handler.\r
73 It may result in unpredictable behavior.\r
bf73cc4b 74**/\r
75VOID\r
76EFIAPI\r
77SetApicMode (\r
78 IN UINTN ApicMode\r
79 );\r
80\r
81/**\r
82 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
83\r
6e3e4d70 84 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
bf73cc4b 85 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
86 the 32-bit local APIC ID is returned as initial APIC ID.\r
87\r
88 @return 32-bit initial local APIC ID of the executing processor.\r
89**/\r
90UINT32\r
91EFIAPI\r
92GetInitialApicId (\r
93 VOID\r
94 );\r
95\r
96/**\r
97 Get the local APIC ID of the executing processor.\r
98\r
99 @return 32-bit local APIC ID of the executing processor.\r
100**/\r
101UINT32\r
102EFIAPI\r
103GetApicId (\r
104 VOID\r
105 );\r
106\r
ae40aef1 107/**\r
108 Get the value of the local APIC version register.\r
109\r
110 @return the value of the local APIC version register.\r
111**/\r
112UINT32\r
113EFIAPI\r
114GetApicVersion (\r
115 VOID\r
116 );\r
117\r
118/**\r
119 Send a Fixed IPI to a specified target processor.\r
120\r
121 This function returns after the IPI has been accepted by the target processor. \r
122\r
123 @param ApicId The local APIC ID of the target processor.\r
124 @param Vector The vector number of the interrupt being sent.\r
125**/\r
126VOID\r
127EFIAPI\r
128SendFixedIpi (\r
129 IN UINT32 ApicId,\r
130 IN UINT8 Vector\r
131 );\r
132\r
133/**\r
134 Send a Fixed IPI to all processors excluding self.\r
135\r
136 This function returns after the IPI has been accepted by the target processors. \r
137\r
138 @param Vector The vector number of the interrupt being sent.\r
139**/\r
140VOID\r
141EFIAPI\r
142SendFixedIpiAllExcludingSelf (\r
143 IN UINT8 Vector\r
144 );\r
145\r
bf73cc4b 146/**\r
147 Send a SMI IPI to a specified target processor.\r
148\r
149 This function returns after the IPI has been accepted by the target processor. \r
150\r
151 @param ApicId Specify the local APIC ID of the target processor.\r
152**/\r
153VOID\r
154EFIAPI\r
155SendSmiIpi (\r
156 IN UINT32 ApicId\r
157 );\r
158\r
159/**\r
160 Send a SMI IPI to all processors excluding self.\r
161\r
162 This function returns after the IPI has been accepted by the target processors. \r
163**/\r
164VOID\r
165EFIAPI\r
166SendSmiIpiAllExcludingSelf (\r
167 VOID\r
168 );\r
169\r
170/**\r
171 Send an INIT IPI to a specified target processor.\r
172\r
173 This function returns after the IPI has been accepted by the target processor. \r
174\r
175 @param ApicId Specify the local APIC ID of the target processor.\r
176**/\r
177VOID\r
178EFIAPI\r
179SendInitIpi (\r
180 IN UINT32 ApicId\r
181 );\r
182\r
183/**\r
184 Send an INIT IPI to all processors excluding self.\r
185\r
186 This function returns after the IPI has been accepted by the target processors. \r
187**/\r
188VOID\r
189EFIAPI\r
190SendInitIpiAllExcludingSelf (\r
191 VOID\r
192 );\r
193\r
194/**\r
195 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
196\r
197 This function returns after the IPI has been accepted by the target processor. \r
198\r
199 if StartupRoutine >= 1M, then ASSERT.\r
200 if StartupRoutine is not multiple of 4K, then ASSERT.\r
201\r
202 @param ApicId Specify the local APIC ID of the target processor.\r
203 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
204 address and 4K aligned.\r
205**/\r
206VOID\r
207EFIAPI\r
208SendInitSipiSipi (\r
209 IN UINT32 ApicId,\r
210 IN UINT32 StartupRoutine\r
211 );\r
212\r
213/**\r
214 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
215\r
216 This function returns after the IPI has been accepted by the target processors. \r
217\r
218 if StartupRoutine >= 1M, then ASSERT.\r
219 if StartupRoutine is not multiple of 4K, then ASSERT.\r
220\r
221 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
222 address and 4K aligned.\r
223**/\r
224VOID\r
225EFIAPI\r
226SendInitSipiSipiAllExcludingSelf (\r
227 IN UINT32 StartupRoutine\r
228 );\r
229\r
14e4ca25
MK
230/**\r
231 Initialize the state of the SoftwareEnable bit in the Local APIC\r
232 Spurious Interrupt Vector register.\r
233\r
234 @param Enable If TRUE, then set SoftwareEnable to 1\r
235 If FALSE, then set SoftwareEnable to 0.\r
236\r
237**/\r
238VOID\r
239EFIAPI\r
240InitializeLocalApicSoftwareEnable (\r
241 IN BOOLEAN Enable\r
242 );\r
243\r
bf73cc4b 244/**\r
245 Programming Virtual Wire Mode.\r
246\r
247 This function programs the local APIC for virtual wire mode following\r
248 the example described in chapter A.3 of the MP 1.4 spec.\r
249\r
250 IOxAPIC is not involved in this type of virtual wire mode.\r
251**/\r
252VOID\r
253EFIAPI\r
254ProgramVirtualWireMode (\r
255 VOID\r
256 );\r
257\r
b1b8c631 258/**\r
259 Disable LINT0 & LINT1 interrupts.\r
260\r
261 This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
262**/\r
263VOID\r
264EFIAPI\r
265DisableLvtInterrupts (\r
266 VOID\r
267 );\r
268\r
bf73cc4b 269/**\r
270 Read the initial count value from the init-count register.\r
271\r
272 @return The initial count value read from the init-count register.\r
273**/\r
274UINT32\r
275EFIAPI\r
276GetApicTimerInitCount (\r
277 VOID\r
278 );\r
279\r
280/**\r
281 Read the current count value from the current-count register.\r
282\r
283 @return The current count value read from the current-count register.\r
284**/\r
285UINT32\r
286EFIAPI\r
287GetApicTimerCurrentCount (\r
288 VOID\r
289 );\r
290\r
291/**\r
292 Initialize the local APIC timer.\r
293\r
294 The local APIC timer is initialized and enabled.\r
295\r
296 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
297 If it is 0, then use the current divide value in the DCR.\r
298 @param InitCount The initial count value.\r
299 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
300 @param Vector The timer interrupt vector number.\r
301**/\r
302VOID\r
303EFIAPI\r
304InitializeApicTimer (\r
305 IN UINTN DivideValue,\r
306 IN UINT32 InitCount,\r
307 IN BOOLEAN PeriodicMode,\r
308 IN UINT8 Vector\r
309 );\r
310\r
ae40aef1 311/**\r
312 Get the state of the local APIC timer.\r
313\r
314 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
315 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
316 @param Vector Return the timer interrupt vector number.\r
317**/\r
318VOID\r
319EFIAPI\r
320GetApicTimerState (\r
321 OUT UINTN *DivideValue OPTIONAL,\r
322 OUT BOOLEAN *PeriodicMode OPTIONAL,\r
323 OUT UINT8 *Vector OPTIONAL\r
324 );\r
325\r
bf73cc4b 326/**\r
327 Enable the local APIC timer interrupt.\r
328**/\r
329VOID\r
330EFIAPI\r
331EnableApicTimerInterrupt (\r
332 VOID\r
333 );\r
334\r
335/**\r
336 Disable the local APIC timer interrupt.\r
337**/\r
338VOID\r
339EFIAPI\r
340DisableApicTimerInterrupt (\r
341 VOID\r
342 );\r
343\r
344/**\r
345 Get the local APIC timer interrupt state.\r
346\r
347 @retval TRUE The local APIC timer interrupt is enabled.\r
348 @retval FALSE The local APIC timer interrupt is disabled.\r
349**/\r
350BOOLEAN\r
351EFIAPI\r
352GetApicTimerInterruptState (\r
353 VOID\r
354 );\r
355\r
356/**\r
357 Send EOI to the local APIC.\r
358**/\r
359VOID\r
360EFIAPI\r
361SendApicEoi (\r
362 VOID\r
363 );\r
364\r
5f867ad0 365/**\r
366 Get the 32-bit address that a device should use to send a Message Signaled \r
367 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
368\r
369 @return 32-bit address used to send an MSI to the Local APIC.\r
370**/\r
371UINT32\r
372EFIAPI \r
373GetApicMsiAddress (\r
374 VOID\r
375 );\r
376 \r
377/**\r
378 Get the 64-bit data value that a device should use to send a Message Signaled \r
379 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
380\r
381 If Vector is not in range 0x10..0xFE, then ASSERT().\r
382 If DeliveryMode is not supported, then ASSERT().\r
383 \r
384 @param Vector The 8-bit interrupt vector associated with the MSI. \r
385 Must be in the range 0x10..0xFE\r
386 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
387 is handled. The only supported values are:\r
388 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
389 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
390 2: LOCAL_APIC_DELIVERY_MODE_SMI\r
391 4: LOCAL_APIC_DELIVERY_MODE_NMI\r
392 5: LOCAL_APIC_DELIVERY_MODE_INIT\r
393 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
394 \r
395 @param LevelTriggered TRUE specifies a level triggered interrupt. \r
396 FALSE specifies an edge triggered interrupt.\r
397 @param AssertionLevel Ignored if LevelTriggered is FALSE.\r
398 TRUE specifies a level triggered interrupt that active \r
399 when the interrupt line is asserted.\r
400 FALSE specifies a level triggered interrupt that active \r
401 when the interrupt line is deasserted.\r
402\r
403 @return 64-bit data value used to send an MSI to the Local APIC.\r
404**/\r
405UINT64\r
406EFIAPI \r
407GetApicMsiValue (\r
408 IN UINT8 Vector,\r
409 IN UINTN DeliveryMode,\r
410 IN BOOLEAN LevelTriggered,\r
411 IN BOOLEAN AssertionLevel\r
412 );\r
73152f19
LD
413\r
414/**\r
415 Get Package ID/Core ID/Thread ID of a processor.\r
416\r
417 The algorithm assumes the target system has symmetry across physical\r
418 package boundaries with respect to the number of logical processors\r
419 per package, number of cores per package.\r
420\r
421 @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
422 @param[out] Package Returns the processor package ID.\r
423 @param[out] Core Returns the processor core ID.\r
424 @param[out] Thread Returns the processor thread ID.\r
425**/\r
426VOID\r
427GetProcessorLocation(\r
428 IN UINT32 InitialApicId,\r
429 OUT UINT32 *Package OPTIONAL,\r
430 OUT UINT32 *Core OPTIONAL,\r
431 OUT UINT32 *Thread OPTIONAL\r
432 );\r
5f867ad0 433 \r
bf73cc4b 434#endif\r
435\r