[mirror_edk2.git] / UefiCpuPkg / Include / Library / SmmCpuFeaturesLib.h

/** @file\r
Library that provides CPU specific functions to support the PiSmmCpuDxeSmm module.\r
\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __SMM_FEATURES_LIB_H__\r
#define __SMM_FEATURES_LIB_H__\r
\r
#include <Protocol/MpService.h>\r
#include <Protocol/SmmCpu.h>\r
#include <Register/SmramSaveStateMap.h>\r
#include <CpuHotPlugData.h>\r
\r
///\r
/// Enumeration of SMM registers that are accessed using the library functions\r
/// SmmCpuFeaturesIsSmmRegisterSupported (), SmmCpuFeaturesGetSmmRegister (),\r
/// and SmmCpuFeaturesSetSmmRegister ().\r
///\r
typedef enum {\r
  ///\r
  /// Read-write register to provides access to MSR_SMM_FEATURE_CONTROL if the\r
  /// CPU supports this MSR.\r
  ///\r
  SmmRegFeatureControl,\r
  ///\r
  /// Read-only register that returns a non-zero value if the CPU is able to\r
  /// respond to SMIs.\r
  ///\r
  SmmRegSmmEnable,\r
  ///\r
  /// Read-only register that returns a non-zero value if the CPU is able to\r
  /// respond to SMIs, but is busy with other actions that are causing a delay\r
  /// in responding to an SMI.  This register abstracts access to MSR_SMM_DELAYED\r
  /// if the CPU supports this MSR.\r
  ///\r
  SmmRegSmmDelayed,\r
  ///\r
  /// Read-only register that returns a non-zero value if the CPU is able to\r
  /// respond to SMIs, but is busy with other actions that are blocking its\r
  /// ability to respond to an SMI.  This register abstracts access to\r
  /// MSR_SMM_BLOCKED if the CPU supports this MSR.\r
  ///\r
  SmmRegSmmBlocked\r
} SMM_REG_NAME;\r
\r
/**\r
  Called during the very first SMI into System Management Mode to initialize\r
  CPU features, including SMBASE, for the currently executing CPU.  Since this\r
  is the first SMI, the SMRAM Save State Map is at the default address of\r
  SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing\r
  CPU is specified by CpuIndex and CpuIndex can be used to access information\r
  about the currently executing CPU in the ProcessorInfo array and the\r
  HotPlugCpuData data structure.\r
\r
  @param[in] CpuIndex        The index of the CPU to initialize.  The value\r
                             must be between 0 and the NumberOfCpus field in\r
                             the System Management System Table (SMST).\r
  @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that\r
                             was elected as monarch during System Management\r
                             Mode initialization.\r
                             FALSE if the CpuIndex is not the index of the CPU\r
                             that was elected as monarch during System\r
                             Management Mode initialization.\r
  @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION\r
                             structures.  ProcessorInfo[CpuIndex] contains the\r
                             information for the currently executing CPU.\r
  @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that\r
                             contains the ApidId and SmBase arrays.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInitializeProcessor (\r
  IN UINTN                      CpuIndex,\r
  IN BOOLEAN                    IsMonarch,\r
  IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,\r
  IN CPU_HOT_PLUG_DATA          *CpuHotPlugData\r
  );\r
\r
/**\r
  This function updates the SMRAM save state on the currently executing CPU\r
  to resume execution at a specific address after an RSM instruction.  This\r
  function must evaluate the SMRAM save state to determine the execution mode\r
  the RSM instruction resumes and update the resume execution address with\r
  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart\r
  flag in the SMRAM save state must always be cleared.  This function returns\r
  the value of the instruction pointer from the SMRAM save state that was\r
  replaced.  If this function returns 0, then the SMRAM save state was not\r
  modified.\r
\r
  This function is called during the very first SMI on each CPU after\r
  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
  to signal that the SMBASE of each CPU has been updated before the default\r
  SMBASE address is used for the first SMI to the next CPU.\r
\r
  @param[in] CpuIndex                 The index of the CPU to hook.  The value\r
                                      must be between 0 and the NumberOfCpus\r
                                      field in the System Management System Table\r
                                      (SMST).\r
  @param[in] CpuState                 Pointer to SMRAM Save State Map for the\r
                                      currently executing CPU.\r
  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to\r
                                      32-bit execution mode from 64-bit SMM.\r
  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to\r
                                      same execution mode as SMM.\r
\r
  @retval 0    This function did modify the SMRAM save state.\r
  @retval > 0  The original instruction pointer value from the SMRAM save state\r
               before it was replaced.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesHookReturnFromSmm (\r
  IN UINTN                 CpuIndex,\r
  IN SMRAM_SAVE_STATE_MAP  *CpuState,\r
  IN UINT64                NewInstructionPointer32,\r
  IN UINT64                NewInstructionPointer\r
  );\r
\r
/**\r
  Hook point in normal execution mode that allows the one CPU that was elected\r
  as monarch during System Management Mode initialization to perform additional\r
  initialization actions immediately after all of the CPUs have processed their\r
  first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
  into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSmmRelocationComplete (\r
  VOID\r
  );\r
\r
/**\r
  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is\r
  returned, then a custom SMI handler is not provided by this library,\r
  and the default SMI handler must be used.\r
\r
  @retval 0    Use the default SMI handler.\r
  @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
               The caller is required to allocate enough SMRAM for each CPU to\r
               support the size of the custom SMI handler.\r
**/\r
UINTN\r
EFIAPI\r
SmmCpuFeaturesGetSmiHandlerSize (\r
  VOID\r
  );\r
\r
/**\r
  Install a custom SMI handler for the CPU specified by CpuIndex.  This function\r
  is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
  than zero and is called by the CPU that was elected as monarch during System\r
  Management Mode initialization.\r
\r
  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.\r
                        The value must be between 0 and the NumberOfCpus field\r
                        in the System Management System Table (SMST).\r
  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.\r
  @param[in] SmiStack   The stack to use when an SMI is processed by the\r
                        the CPU specified by CpuIndex.\r
  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtBase    The base address of the GDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtBase    The base address of the IDT to use when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is\r
                        processed by the CPU specified by CpuIndex.\r
  @param[in] Cr3        The base address of the page tables to use when an SMI\r
                        is processed by the CPU specified by CpuIndex.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesInstallSmiHandler (\r
  IN UINTN   CpuIndex,\r
  IN UINT32  SmBase,\r
  IN VOID    *SmiStack,\r
  IN UINTN   StackSize,\r
  IN UINTN   GdtBase,\r
  IN UINTN   GdtSize,\r
  IN UINTN   IdtBase,\r
  IN UINTN   IdtSize,\r
  IN UINT32  Cr3\r
  );\r
\r
/**\r
  Determines if MTRR registers must be configured to set SMRAM cache-ability\r
  when executing in System Management Mode.\r
\r
  @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.\r
  @retval FALSE  MTRR registers do not need to be configured to set SMRAM\r
                 cache-ability.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesNeedConfigureMtrrs (\r
  VOID\r
  );\r
\r
/**\r
  Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesDisableSmrr (\r
  VOID\r
  );\r
\r
/**\r
  Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
  returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesReenableSmrr (\r
  VOID\r
  );\r
\r
/**\r
  Processor specific hook point each time a CPU enters System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value\r
                       must be between 0 and the NumberOfCpus field in the\r
                       System Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousEntry (\r
  IN UINTN  CpuIndex\r
  );\r
\r
/**\r
  Processor specific hook point each time a CPU exits System Management Mode.\r
\r
  @param[in] CpuIndex  The index of the CPU that is exiting SMM.  The value must\r
                       be between 0 and the NumberOfCpus field in the System\r
                       Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesRendezvousExit (\r
  IN UINTN  CpuIndex\r
  );\r
\r
/**\r
  Check to see if an SMM register is supported by a specified CPU.\r
\r
  @param[in] CpuIndex  The index of the CPU to check for SMM register support.\r
                       The value must be between 0 and the NumberOfCpus field\r
                       in the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to check for support.\r
\r
  @retval TRUE   The SMM register specified by RegName is supported by the CPU\r
                 specified by CpuIndex.\r
  @retval FALSE  The SMM register specified by RegName is not supported by the\r
                 CPU specified by CpuIndex.\r
**/\r
BOOLEAN\r
EFIAPI\r
SmmCpuFeaturesIsSmmRegisterSupported (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  );\r
\r
/**\r
  Returns the current value of the SMM register for the specified CPU.\r
  If the SMM register is not supported, then 0 is returned.\r
\r
  @param[in] CpuIndex  The index of the CPU to read the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to read.\r
\r
  @return  The value of the SMM register specified by RegName from the CPU\r
           specified by CpuIndex.\r
**/\r
UINT64\r
EFIAPI\r
SmmCpuFeaturesGetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName\r
  );\r
\r
/**\r
  Sets the value of an SMM register on a specified CPU.\r
  If the SMM register is not supported, then no action is performed.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM register.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] RegName   Identifies the SMM register to write.\r
                       registers are read-only.\r
  @param[in] Value     The value to write to the SMM register.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesSetSmmRegister (\r
  IN UINTN         CpuIndex,\r
  IN SMM_REG_NAME  RegName,\r
  IN UINT64        Value\r
  );\r
\r
/**\r
  Read an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
  SMM Save Sate register.\r
\r
  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The\r
                        value must be between 0 and the NumberOfCpus field in\r
                        the System Management System Table (SMST).\r
  @param[in]  Register  The SMM Save State register to read.\r
  @param[in]  Width     The number of bytes to read from the CPU save state.\r
  @param[out] Buffer    Upon return, this holds the CPU register value read\r
                        from the save state.\r
\r
  @retval EFI_SUCCESS           The register was read from Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support reading Register.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesReadSaveStateRegister (\r
  IN  UINTN                        CpuIndex,\r
  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN  UINTN                        Width,\r
  OUT VOID                         *Buffer\r
  );\r
\r
/**\r
  Writes an SMM Save State register on the target processor.  If this function\r
  returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
  SMM Save Sate register.\r
\r
  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The\r
                       value must be between 0 and the NumberOfCpus field in\r
                       the System Management System Table (SMST).\r
  @param[in] Register  The SMM Save State register to write.\r
  @param[in] Width     The number of bytes to write to the CPU save state.\r
  @param[in] Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS           The register was written to Save State.\r
  @retval EFI_INVALID_PARAMTER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED       This function does not support writing Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmCpuFeaturesWriteSaveStateRegister (\r
  IN UINTN                        CpuIndex,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        Width,\r
  IN CONST VOID                   *Buffer\r
  );\r
\r
/**\r
  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
  notification is completely processed.\r
**/\r
VOID\r
EFIAPI\r
SmmCpuFeaturesCompleteSmmReadyToLock (\r
  VOID\r
  );\r
\r
/**\r
  This API provides a method for a CPU to allocate a specific region for storing page tables.\r
\r
  This API can be called more once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL\r
  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is\r
  returned.\r
\r
  This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer for page tables.\r
  @retval NULL      Fail to allocate a specific region for storing page tables,\r
                    Or there is no preference on where the page tables are allocated in SMRAM.\r
\r
**/\r
VOID *\r
EFIAPI\r
SmmCpuFeaturesAllocatePageTableMemory (\r
  IN UINTN           Pages\r
  );\r
\r
#endif\r
Commit	Line	Data
a9764e68 MK	1	/** @file\r
	2	Library that provides CPU specific functions to support the PiSmmCpuDxeSmm module.\r
	3	\r
	4	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __SMM_FEATURES_LIB_H__\r
	16	#define __SMM_FEATURES_LIB_H__\r
	17	\r
	18	#include <Protocol/MpService.h>\r
	19	#include <Protocol/SmmCpu.h>\r
	20	#include <Register/SmramSaveStateMap.h>\r
	21	#include <CpuHotPlugData.h>\r
	22	\r
	23	///\r
	24	/// Enumeration of SMM registers that are accessed using the library functions\r
	25	/// SmmCpuFeaturesIsSmmRegisterSupported (), SmmCpuFeaturesGetSmmRegister (),\r
	26	/// and SmmCpuFeaturesSetSmmRegister ().\r
	27	///\r
	28	typedef enum {\r
	29	///\r
	30	/// Read-write register to provides access to MSR_SMM_FEATURE_CONTROL if the\r
	31	/// CPU supports this MSR.\r
	32	///\r
	33	SmmRegFeatureControl,\r
	34	///\r
	35	/// Read-only register that returns a non-zero value if the CPU is able to\r
	36	/// respond to SMIs.\r
	37	///\r
	38	SmmRegSmmEnable,\r
	39	///\r
	40	/// Read-only register that returns a non-zero value if the CPU is able to\r
	41	/// respond to SMIs, but is busy with other actions that are causing a delay\r
	42	/// in responding to an SMI. This register abstracts access to MSR_SMM_DELAYED\r
	43	/// if the CPU supports this MSR.\r
	44	///\r
	45	SmmRegSmmDelayed,\r
	46	///\r
	47	/// Read-only register that returns a non-zero value if the CPU is able to\r
	48	/// respond to SMIs, but is busy with other actions that are blocking its\r
	49	/// ability to respond to an SMI. This register abstracts access to\r
	50	/// MSR_SMM_BLOCKED if the CPU supports this MSR.\r
	51	///\r
	52	SmmRegSmmBlocked\r
	53	} SMM_REG_NAME;\r
	54	\r
	55	/**\r
	56	Called during the very first SMI into System Management Mode to initialize\r
	57	CPU features, including SMBASE, for the currently executing CPU. Since this\r
	58	is the first SMI, the SMRAM Save State Map is at the default address of\r
	59	SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
	60	CPU is specified by CpuIndex and CpuIndex can be used to access information\r
	61	about the currently executing CPU in the ProcessorInfo array and the\r
	62	HotPlugCpuData data structure.\r
	63	\r
	64	@param[in] CpuIndex The index of the CPU to initialize. The value\r
65	must be between 0 and the NumberOfCpus field in\r
66	the System Management System Table (SMST).\r
67	@param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
68	was elected as monarch during System Management\r
69	Mode initialization.\r
70	FALSE if the CpuIndex is not the index of the CPU\r
71	that was elected as monarch during System\r
72	Management Mode initialization.\r
73	@param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
74	structures. ProcessorInfo[CpuIndex] contains the\r
75	information for the currently executing CPU.\r
76	@param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
77	contains the ApidId and SmBase arrays.\r
78	**/\r
79	VOID\r
80	EFIAPI\r
81	SmmCpuFeaturesInitializeProcessor (\r
82	IN UINTN CpuIndex,\r
83	IN BOOLEAN IsMonarch,\r
84	IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
85	IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
86	);\r
87	\r
88	/**\r
89	This function updates the SMRAM save state on the currently executing CPU\r
90	to resume execution at a specific address after an RSM instruction. This\r
91	function must evaluate the SMRAM save state to determine the execution mode\r
92	the RSM instruction resumes and update the resume execution address with\r
93	either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
94	flag in the SMRAM save state must always be cleared. This function returns\r
95	the value of the instruction pointer from the SMRAM save state that was\r
96	replaced. If this function returns 0, then the SMRAM save state was not\r
97	modified.\r
98	\r
99	This function is called during the very first SMI on each CPU after\r
100	SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
101	to signal that the SMBASE of each CPU has been updated before the default\r
102	SMBASE address is used for the first SMI to the next CPU.\r
103	\r
104	@param[in] CpuIndex The index of the CPU to hook. The value\r
105	must be between 0 and the NumberOfCpus\r
106	field in the System Management System Table\r
107	(SMST).\r
108	@param[in] CpuState Pointer to SMRAM Save State Map for the\r
109	currently executing CPU.\r
110	@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
111	32-bit execution mode from 64-bit SMM.\r
112	@param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
113	same execution mode as SMM.\r
114	\r
115	@retval 0 This function did modify the SMRAM save state.\r
116	@retval > 0 The original instruction pointer value from the SMRAM save state\r
117	before it was replaced.\r
118	**/\r
119	UINT64\r
120	EFIAPI\r
121	SmmCpuFeaturesHookReturnFromSmm (\r
122	IN UINTN CpuIndex,\r
123	IN SMRAM_SAVE_STATE_MAP *CpuState,\r
124	IN UINT64 NewInstructionPointer32,\r
125	IN UINT64 NewInstructionPointer\r
126	);\r
127	\r
128	/**\r
129	Hook point in normal execution mode that allows the one CPU that was elected\r
130	as monarch during System Management Mode initialization to perform additional\r
131	initialization actions immediately after all of the CPUs have processed their\r
132	first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
133	into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
134	**/\r
135	VOID\r
136	EFIAPI\r
137	SmmCpuFeaturesSmmRelocationComplete (\r
138	VOID\r
139	);\r
140	\r
141	/**\r
142	Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
143	returned, then a custom SMI handler is not provided by this library,\r
144	and the default SMI handler must be used.\r
145	\r
146	@retval 0 Use the default SMI handler.\r
147	@retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
148	The caller is required to allocate enough SMRAM for each CPU to\r
149	support the size of the custom SMI handler.\r
150	**/\r
151	UINTN\r
152	EFIAPI\r
153	SmmCpuFeaturesGetSmiHandlerSize (\r
154	VOID\r
155	);\r
156	\r
157	/**\r
158	Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
159	is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
160	than zero and is called by the CPU that was elected as monarch during System\r
161	Management Mode initialization.\r
162	\r
163	@param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
164	The value must be between 0 and the NumberOfCpus field\r
165	in the System Management System Table (SMST).\r
166	@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
167	@param[in] SmiStack The stack to use when an SMI is processed by the\r
168	the CPU specified by CpuIndex.\r
169	@param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
170	processed by the CPU specified by CpuIndex.\r
171	@param[in] GdtBase The base address of the GDT to use when an SMI is\r
172	processed by the CPU specified by CpuIndex.\r
173	@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
174	processed by the CPU specified by CpuIndex.\r
175	@param[in] IdtBase The base address of the IDT to use when an SMI is\r
176	processed by the CPU specified by CpuIndex.\r
177	@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
178	processed by the CPU specified by CpuIndex.\r
179	@param[in] Cr3 The base address of the page tables to use when an SMI\r
180	is processed by the CPU specified by CpuIndex.\r
181	**/\r
182	VOID\r
183	EFIAPI\r
184	SmmCpuFeaturesInstallSmiHandler (\r
185	IN UINTN CpuIndex,\r
186	IN UINT32 SmBase,\r
187	IN VOID *SmiStack,\r
188	IN UINTN StackSize,\r
189	IN UINTN GdtBase,\r
190	IN UINTN GdtSize,\r
191	IN UINTN IdtBase,\r
192	IN UINTN IdtSize,\r
193	IN UINT32 Cr3\r
194	);\r
195	\r
196	/**\r
197	Determines if MTRR registers must be configured to set SMRAM cache-ability\r
198	when executing in System Management Mode.\r
199	\r
200	@retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
201	@retval FALSE MTRR registers do not need to be configured to set SMRAM\r
202	cache-ability.\r
203	**/\r
204	BOOLEAN\r
205	EFIAPI\r
206	SmmCpuFeaturesNeedConfigureMtrrs (\r
207	VOID\r
208	);\r
209	\r
210	/**\r
211	Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
212	returns TRUE.\r
213	**/\r
214	VOID\r
215	EFIAPI\r
216	SmmCpuFeaturesDisableSmrr (\r
217	VOID\r
218	);\r
219	\r
220	/**\r
221	Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
222	returns TRUE.\r
223	**/\r
224	VOID\r
225	EFIAPI\r
226	SmmCpuFeaturesReenableSmrr (\r
227	VOID\r
228	);\r
229	\r
230	/**\r
231	Processor specific hook point each time a CPU enters System Management Mode.\r
232	\r
233	@param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
234	must be between 0 and the NumberOfCpus field in the\r
235	System Management System Table (SMST).\r
236	**/\r
237	VOID\r
238	EFIAPI\r
239	SmmCpuFeaturesRendezvousEntry (\r
240	IN UINTN CpuIndex\r
241	);\r
242	\r
243	/**\r
244	Processor specific hook point each time a CPU exits System Management Mode.\r
245	\r
246	@param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
247	be between 0 and the NumberOfCpus field in the System\r
248	Management System Table (SMST).\r
249	**/\r
250	VOID\r
251	EFIAPI\r
252	SmmCpuFeaturesRendezvousExit (\r
253	IN UINTN CpuIndex\r
254	);\r
255	\r
256	/**\r
257	Check to see if an SMM register is supported by a specified CPU.\r
258	\r
259	@param[in] CpuIndex The index of the CPU to check for SMM register support.\r
260	The value must be between 0 and the NumberOfCpus field\r
261	in the System Management System Table (SMST).\r
262	@param[in] RegName Identifies the SMM register to check for support.\r
263	\r
264	@retval TRUE The SMM register specified by RegName is supported by the CPU\r
265	specified by CpuIndex.\r
266	@retval FALSE The SMM register specified by RegName is not supported by the\r
267	CPU specified by CpuIndex.\r
268	**/\r
269	BOOLEAN\r
270	EFIAPI\r
271	SmmCpuFeaturesIsSmmRegisterSupported (\r
272	IN UINTN CpuIndex,\r
273	IN SMM_REG_NAME RegName\r
274	);\r
275	\r
276	/**\r
277	Returns the current value of the SMM register for the specified CPU.\r
278	If the SMM register is not supported, then 0 is returned.\r
279	\r
280	@param[in] CpuIndex The index of the CPU to read the SMM register. The\r
281	value must be between 0 and the NumberOfCpus field in\r
282	the System Management System Table (SMST).\r
283	@param[in] RegName Identifies the SMM register to read.\r
284	\r
285	@return The value of the SMM register specified by RegName from the CPU\r
286	specified by CpuIndex.\r
287	**/\r
288	UINT64\r
289	EFIAPI\r
290	SmmCpuFeaturesGetSmmRegister (\r
291	IN UINTN CpuIndex,\r
292	IN SMM_REG_NAME RegName\r
293	);\r
294	\r
295	/**\r
296	Sets the value of an SMM register on a specified CPU.\r
297	If the SMM register is not supported, then no action is performed.\r
298	\r
299	@param[in] CpuIndex The index of the CPU to write the SMM register. The\r
300	value must be between 0 and the NumberOfCpus field in\r
301	the System Management System Table (SMST).\r
302	@param[in] RegName Identifies the SMM register to write.\r
303	registers are read-only.\r
304	@param[in] Value The value to write to the SMM register.\r
305	**/\r
306	VOID\r
307	EFIAPI\r
308	SmmCpuFeaturesSetSmmRegister (\r
309	IN UINTN CpuIndex,\r
310	IN SMM_REG_NAME RegName,\r
311	IN UINT64 Value\r
312	);\r
313	\r
314	/**\r
315	Read an SMM Save State register on the target processor. If this function\r
316	returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
317	SMM Save Sate register.\r
318	\r
319	@param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
320	value must be between 0 and the NumberOfCpus field in\r
321	the System Management System Table (SMST).\r
322	@param[in] Register The SMM Save State register to read.\r
323	@param[in] Width The number of bytes to read from the CPU save state.\r
324	@param[out] Buffer Upon return, this holds the CPU register value read\r
325	from the save state.\r
326	\r
327	@retval EFI_SUCCESS The register was read from Save State.\r
328	@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
329	@retval EFI_UNSUPPORTED This function does not support reading Register.\r
330	\r
331	**/\r
332	EFI_STATUS\r
333	EFIAPI\r
334	SmmCpuFeaturesReadSaveStateRegister (\r
335	IN UINTN CpuIndex,\r
336	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
337	IN UINTN Width,\r
338	OUT VOID *Buffer\r
339	);\r
340	\r
341	/**\r
342	Writes an SMM Save State register on the target processor. If this function\r
343	returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
344	SMM Save Sate register.\r
345	\r
346	@param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
347	value must be between 0 and the NumberOfCpus field in\r
348	the System Management System Table (SMST).\r
349	@param[in] Register The SMM Save State register to write.\r
350	@param[in] Width The number of bytes to write to the CPU save state.\r
351	@param[in] Buffer Upon entry, this holds the new CPU register value.\r
352	\r
353	@retval EFI_SUCCESS The register was written to Save State.\r
354	@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
355	@retval EFI_UNSUPPORTED This function does not support writing Register.\r
356	**/\r
357	EFI_STATUS\r
358	EFIAPI\r
359	SmmCpuFeaturesWriteSaveStateRegister (\r
360	IN UINTN CpuIndex,\r
361	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
362	IN UINTN Width,\r
363	IN CONST VOID *Buffer\r
364	);\r
365	\r
9daa916d JY	366	/**\r
	367	This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
	368	notification is completely processed.\r
	369	**/\r
	370	VOID\r
	371	EFIAPI\r
	372	SmmCpuFeaturesCompleteSmmReadyToLock (\r
	373	VOID\r
	374	);\r
	375	\r
	376	/**\r
	377	This API provides a method for a CPU to allocate a specific region for storing page tables.\r
	378	\r
	379	This API can be called more once to allocate memory for page tables.\r
	380	\r
	381	Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
	382	allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
	383	is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
	384	returned.\r
	385	\r
	386	This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
	387	\r
	388	@param Pages The number of 4 KB pages to allocate.\r
	389	\r
	390	@return A pointer to the allocated buffer for page tables.\r
	391	@retval NULL Fail to allocate a specific region for storing page tables,\r
	392	Or there is no preference on where the page tables are allocated in SMRAM.\r
	393	\r
	394	**/\r
	395	VOID *\r
	396	EFIAPI\r
	397	SmmCpuFeaturesAllocatePageTableMemory (\r
	398	IN UINTN Pages\r
	399	);\r
	400	\r
a9764e68	401	#endif\r