projects / mirror_edk2.git / blame
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| b15cbd9c BS |
1 | /** @file\r |
| 2 | CPUID leaf definitions.\r | |
| 3 | \r | |
| 4 | Provides defines for CPUID leaf indexes. Data structures are provided for\r | |
| 5 | registers returned by a CPUID leaf that contain one or more bit fields.\r | |
| 6 | If a register returned is a single 32-bit value, then a data structure is\r | |
| 7 | not provided for that register.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r | |
| 890d2bd2 | 10 | \r |
| b15cbd9c BS |
11 | This program and the accompanying materials are licensed and made available\r |
| 12 | under the terms and conditions of the BSD License which accompanies this\r | |
| 13 | distribution. The full text of the license may be found at\r | |
| 14 | http://opensource.org/licenses/bsd-license.php\r | |
| 15 | \r | |
| 16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 17 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 18 | \r | |
| 19 | @par Specification Reference:\r | |
| 20 | AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r | |
| 21 | \r | |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __AMD_CPUID_H__\r | |
| 25 | #define __AMD_CPUID_H__\r | |
| 26 | \r | |
| 27 | /**\r | |
| 890d2bd2 LD |
28 | CPUID Signature Information\r |
| 29 | \r | |
| 30 | @param EAX CPUID_SIGNATURE (0x00)\r | |
| 31 | \r | |
| 32 | @retval EAX Returns the highest value the CPUID instruction recognizes for\r | |
| 33 | returning basic processor information. The value is returned is\r | |
| 34 | processor specific.\r | |
| 35 | @retval EBX First 4 characters of a vendor identification string.\r | |
| 36 | @retval ECX Last 4 characters of a vendor identification string.\r | |
| 37 | @retval EDX Middle 4 characters of a vendor identification string.\r | |
| 38 | \r | |
| 39 | **/\r | |
| 40 | \r | |
| 41 | ///\r | |
| 42 | /// @{ CPUID signature values returned by AMD processors\r | |
| 43 | ///\r | |
| 44 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')\r | |
| 45 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')\r | |
| 46 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')\r | |
| 47 | ///\r | |
| 48 | /// @}\r | |
| 49 | ///\r | |
| 50 | \r | |
| 51 | \r | |
| 52 | /**\r | |
| 53 | CPUID Extended Processor Signature and Features\r | |
| 54 | \r | |
| 55 | @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r | |
| 56 | \r | |
| 57 | @retval EAX Extended Family, Model, Stepping Identifiers\r | |
| 58 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.\r | |
| 59 | @retval EBX Brand Identifier\r | |
| 60 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.\r | |
| 61 | @retval ECX Extended Feature Identifiers\r | |
| 62 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.\r | |
| 63 | @retval EDX Extended Feature Identifiers\r | |
| 64 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.\r | |
| 65 | **/\r | |
| 66 | \r | |
| 67 | /**\r | |
| 68 | CPUID Extended Processor Signature and Features EAX for CPUID leaf\r | |
| 69 | #CPUID_EXTENDED_CPU_SIG.\r | |
| 70 | **/\r | |
| 71 | typedef union {\r | |
| 72 | ///\r | |
| 73 | /// Individual bit fields\r | |
| 74 | ///\r | |
| 75 | struct {\r | |
| 76 | ///\r | |
| 77 | /// [Bits 3:0] Stepping.\r | |
| 78 | ///\r | |
| 79 | UINT32 Stepping:4;\r | |
| 80 | ///\r | |
| 81 | /// [Bits 7:4] Base Model.\r | |
| 82 | ///\r | |
| 83 | UINT32 BaseModel:4;\r | |
| 84 | ///\r | |
| 85 | /// [Bits 11:8] Base Family.\r | |
| 86 | ///\r | |
| 87 | UINT32 BaseFamily:4;\r | |
| 88 | ///\r | |
| 89 | /// [Bit 15:12] Reserved.\r | |
| 90 | ///\r | |
| 91 | UINT32 Reserved1:4;\r | |
| 92 | ///\r | |
| 93 | /// [Bits 19:16] Extended Model.\r | |
| 94 | ///\r | |
| 95 | UINT32 ExtModel:4;\r | |
| 96 | ///\r | |
| 97 | /// [Bits 27:20] Extended Family.\r | |
| 98 | ///\r | |
| 99 | UINT32 ExtFamily:8;\r | |
| 100 | ///\r | |
| 101 | /// [Bit 31:28] Reserved.\r | |
| 102 | ///\r | |
| 103 | UINT32 Reserved2:4;\r | |
| 104 | } Bits;\r | |
| 105 | ///\r | |
| 106 | /// All bit fields as a 32-bit value\r | |
| 107 | ///\r | |
| 108 | UINT32 Uint32;\r | |
| 109 | } CPUID_AMD_EXTENDED_CPU_SIG_EAX;\r | |
| 110 | \r | |
| 111 | /**\r | |
| 112 | CPUID Extended Processor Signature and Features EBX for CPUID leaf\r | |
| 113 | #CPUID_EXTENDED_CPU_SIG.\r | |
| 114 | **/\r | |
| 115 | typedef union {\r | |
| 116 | ///\r | |
| 117 | /// Individual bit fields\r | |
| 118 | ///\r | |
| 119 | struct {\r | |
| 120 | ///\r | |
| 121 | /// [Bits 27:0] Reserved.\r | |
| 122 | ///\r | |
| 123 | UINT32 Reserved:28;\r | |
| 124 | ///\r | |
| 125 | /// [Bit 31:28] Package Type.\r | |
| 126 | ///\r | |
| 127 | UINT32 PkgType:4;\r | |
| 128 | } Bits;\r | |
| 129 | ///\r | |
| 130 | /// All bit fields as a 32-bit value\r | |
| 131 | ///\r | |
| 132 | UINT32 Uint32;\r | |
| 133 | } CPUID_AMD_EXTENDED_CPU_SIG_EBX;\r | |
| 134 | \r | |
| 135 | /**\r | |
| 136 | CPUID Extended Processor Signature and Features ECX for CPUID leaf\r | |
| 137 | #CPUID_EXTENDED_CPU_SIG.\r | |
| 138 | **/\r | |
| 139 | typedef union {\r | |
| 140 | ///\r | |
| 141 | /// Individual bit fields\r | |
| 142 | ///\r | |
| 143 | struct {\r | |
| 144 | ///\r | |
| 145 | /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r | |
| 146 | ///\r | |
| 147 | UINT32 LAHF_SAHF:1;\r | |
| 148 | ///\r | |
| 149 | /// [Bit 1] Core multi-processing legacy mode.\r | |
| 150 | ///\r | |
| 151 | UINT32 CmpLegacy:1;\r | |
| 152 | ///\r | |
| 153 | /// [Bit 2] Secure Virtual Mode feature.\r | |
| 154 | ///\r | |
| 155 | UINT32 SVM:1;\r | |
| 156 | ///\r | |
| 157 | /// [Bit 3] Extended APIC register space.\r | |
| 158 | ///\r | |
| 159 | UINT32 ExtApicSpace:1;\r | |
| 160 | ///\r | |
| 161 | /// [Bit 4] LOCK MOV CR0 means MOV CR8.\r | |
| 162 | ///\r | |
| 163 | UINT32 AltMovCr8:1;\r | |
| 164 | ///\r | |
| 165 | /// [Bit 5] LZCNT instruction support.\r | |
| 166 | ///\r | |
| 167 | UINT32 LZCNT:1;\r | |
| 168 | ///\r | |
| 169 | /// [Bit 6] SSE4A instruction support.\r | |
| 170 | ///\r | |
| 171 | UINT32 SSE4A:1;\r | |
| 172 | ///\r | |
| 173 | /// [Bit 7] Misaligned SSE Mode.\r | |
| 174 | ///\r | |
| 175 | UINT32 MisAlignSse:1;\r | |
| 176 | ///\r | |
| 177 | /// [Bit 8] ThreeDNow Prefetch instructions.\r | |
| 178 | ///\r | |
| 179 | UINT32 PREFETCHW:1;\r | |
| 180 | ///\r | |
| 181 | /// [Bit 9] OS Visible Work-around support.\r | |
| 182 | ///\r | |
| 183 | UINT32 OSVW:1;\r | |
| 184 | ///\r | |
| 185 | /// [Bit 10] Instruction Based Sampling.\r | |
| 186 | ///\r | |
| 187 | UINT32 IBS:1;\r | |
| 188 | ///\r | |
| 189 | /// [Bit 11] Extended Operation Support.\r | |
| 190 | ///\r | |
| 191 | UINT32 XOP:1;\r | |
| 192 | ///\r | |
| 193 | /// [Bit 12] SKINIT and STGI support.\r | |
| 194 | ///\r | |
| 195 | UINT32 SKINIT:1;\r | |
| 196 | ///\r | |
| 197 | /// [Bit 13] Watchdog Timer support.\r | |
| 198 | ///\r | |
| 199 | UINT32 WDT:1;\r | |
| 200 | ///\r | |
| 201 | /// [Bit 14] Reserved.\r | |
| 202 | ///\r | |
| 203 | UINT32 Reserved1:1;\r | |
| 204 | ///\r | |
| 205 | /// [Bit 15] Lightweight Profiling support.\r | |
| 206 | ///\r | |
| 207 | UINT32 LWP:1;\r | |
| 208 | ///\r | |
| 209 | /// [Bit 16] 4-Operand FMA instruction support.\r | |
| 210 | ///\r | |
| 211 | UINT32 FMA4:1;\r | |
| 212 | ///\r | |
| 213 | /// [Bit 17] Translation Cache Extension.\r | |
| 214 | ///\r | |
| 215 | UINT32 TCE:1;\r | |
| 216 | ///\r | |
| 217 | /// [Bit 21:18] Reserved.\r | |
| 218 | ///\r | |
| 219 | UINT32 Reserved2:4;\r | |
| 220 | ///\r | |
| 221 | /// [Bit 22] Topology Extensions support.\r | |
| 222 | ///\r | |
| 223 | UINT32 TopologyExtensions:1;\r | |
| 224 | ///\r | |
| 225 | /// [Bit 23] Core Performance Counter Extensions.\r | |
| 226 | ///\r | |
| 227 | UINT32 PerfCtrExtCore:1;\r | |
| 228 | ///\r | |
| 229 | /// [Bit 25:24] Reserved.\r | |
| 230 | ///\r | |
| 231 | UINT32 Reserved3:2;\r | |
| 232 | ///\r | |
| 233 | /// [Bit 26] Data Breakpoint Extension.\r | |
| 234 | ///\r | |
| 235 | UINT32 DataBreakpointExtension:1;\r | |
| 236 | ///\r | |
| 237 | /// [Bit 27] Performance Time-Stamp Counter.\r | |
| 238 | ///\r | |
| 239 | UINT32 PerfTsc:1;\r | |
| 240 | ///\r | |
| 241 | /// [Bit 28] L3 Performance Counter Extensions.\r | |
| 242 | ///\r | |
| 243 | UINT32 PerfCtrExtL3:1;\r | |
| 244 | ///\r | |
| 245 | /// [Bit 29] MWAITX and MONITORX capability.\r | |
| 246 | ///\r | |
| 247 | UINT32 MwaitExtended:1;\r | |
| 248 | ///\r | |
| 249 | /// [Bit 31:30] Reserved.\r | |
| 250 | ///\r | |
| 251 | UINT32 Reserved4:2;\r | |
| 252 | } Bits;\r | |
| 253 | ///\r | |
| 254 | /// All bit fields as a 32-bit value\r | |
| 255 | ///\r | |
| 256 | UINT32 Uint32;\r | |
| 257 | } CPUID_AMD_EXTENDED_CPU_SIG_ECX;\r | |
| 258 | \r | |
| 259 | /**\r | |
| 260 | CPUID Extended Processor Signature and Features EDX for CPUID leaf\r | |
| 261 | #CPUID_EXTENDED_CPU_SIG.\r | |
| 262 | **/\r | |
| 263 | typedef union {\r | |
| 264 | ///\r | |
| 265 | /// Individual bit fields\r | |
| 266 | ///\r | |
| 267 | struct {\r | |
| 268 | ///\r | |
| 269 | /// [Bit 0] x87 floating point unit on-chip.\r | |
| 270 | ///\r | |
| 271 | UINT32 FPU:1;\r | |
| 272 | ///\r | |
| 273 | /// [Bit 1] Virtual-mode enhancements.\r | |
| 274 | ///\r | |
| 275 | UINT32 VME:1;\r | |
| 276 | ///\r | |
| 277 | /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.\r | |
| 278 | ///\r | |
| 279 | UINT32 DE:1;\r | |
| 280 | ///\r | |
| 281 | /// [Bit 3] Page-size extensions (4 MB pages).\r | |
| 282 | ///\r | |
| 283 | UINT32 PSE:1;\r | |
| 284 | ///\r | |
| 285 | /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.\r | |
| 286 | ///\r | |
| 287 | UINT32 TSC:1;\r | |
| 288 | ///\r | |
| 289 | /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.\r | |
| 290 | ///\r | |
| 291 | UINT32 MSR:1;\r | |
| 292 | ///\r | |
| 293 | /// [Bit 6] Physical-address extensions (PAE).\r | |
| 294 | ///\r | |
| 295 | UINT32 PAE:1;\r | |
| 296 | ///\r | |
| 297 | /// [Bit 7] Machine check exception, CR4.MCE.\r | |
| 298 | ///\r | |
| 299 | UINT32 MCE:1;\r | |
| 300 | ///\r | |
| 301 | /// [Bit 8] CMPXCHG8B instruction.\r | |
| 302 | ///\r | |
| 303 | UINT32 CMPXCHG8B:1;\r | |
| 304 | ///\r | |
| 305 | /// [Bit 9] APIC exists and is enabled.\r | |
| 306 | ///\r | |
| 307 | UINT32 APIC:1;\r | |
| 308 | ///\r | |
| 309 | /// [Bit 10] Reserved.\r | |
| 310 | ///\r | |
| 311 | UINT32 Reserved1:1;\r | |
| 312 | ///\r | |
| 313 | /// [Bit 11] SYSCALL and SYSRET instructions.\r | |
| 314 | ///\r | |
| 315 | UINT32 SYSCALL_SYSRET:1;\r | |
| 316 | ///\r | |
| 317 | /// [Bit 12] Memory-type range registers.\r | |
| 318 | ///\r | |
| 319 | UINT32 MTRR:1;\r | |
| 320 | ///\r | |
| 321 | /// [Bit 13] Page global extension, CR4.PGE.\r | |
| 322 | ///\r | |
| 323 | UINT32 PGE:1;\r | |
| 324 | ///\r | |
| 325 | /// [Bit 14] Machine check architecture, MCG_CAP.\r | |
| 326 | ///\r | |
| 327 | UINT32 MCA:1;\r | |
| 328 | ///\r | |
| 329 | /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.\r | |
| 330 | ///\r | |
| 331 | UINT32 CMOV:1;\r | |
| 332 | ///\r | |
| 333 | /// [Bit 16] Page attribute table.\r | |
| 334 | ///\r | |
| 335 | UINT32 PAT:1;\r | |
| 336 | ///\r | |
| 337 | /// [Bit 17] Page-size extensions.\r | |
| 338 | ///\r | |
| 339 | UINT32 PSE36 : 1;\r | |
| 340 | ///\r | |
| 341 | /// [Bit 19:18] Reserved.\r | |
| 342 | ///\r | |
| 343 | UINT32 Reserved2:2;\r | |
| 344 | ///\r | |
| 345 | /// [Bit 20] No-execute page protection.\r | |
| 346 | ///\r | |
| 347 | UINT32 NX:1;\r | |
| 348 | ///\r | |
| 349 | /// [Bit 21] Reserved.\r | |
| 350 | ///\r | |
| 351 | UINT32 Reserved3:1;\r | |
| 352 | ///\r | |
| 353 | /// [Bit 22] AMD Extensions to MMX instructions.\r | |
| 354 | ///\r | |
| 355 | UINT32 MmxExt:1;\r | |
| 356 | ///\r | |
| 357 | /// [Bit 23] MMX instructions.\r | |
| 358 | ///\r | |
| 359 | UINT32 MMX:1;\r | |
| 360 | ///\r | |
| 361 | /// [Bit 24] FXSAVE and FXRSTOR instructions.\r | |
| 362 | ///\r | |
| 363 | UINT32 FFSR:1;\r | |
| 364 | ///\r | |
| 365 | /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.\r | |
| 366 | ///\r | |
| 367 | UINT32 FFXSR:1;\r | |
| 368 | ///\r | |
| 369 | /// [Bit 26] 1-GByte large page support.\r | |
| 370 | ///\r | |
| 371 | UINT32 Page1GB:1;\r | |
| 372 | ///\r | |
| 373 | /// [Bit 27] RDTSCP intructions.\r | |
| 374 | ///\r | |
| 375 | UINT32 RDTSCP:1;\r | |
| 376 | ///\r | |
| 377 | /// [Bit 28] Reserved.\r | |
| 378 | ///\r | |
| 379 | UINT32 Reserved4:1;\r | |
| 380 | ///\r | |
| 381 | /// [Bit 29] Long Mode.\r | |
| 382 | ///\r | |
| 383 | UINT32 LM:1;\r | |
| 384 | ///\r | |
| 385 | /// [Bit 30] 3DNow! instructions.\r | |
| 386 | ///\r | |
| 387 | UINT32 ThreeDNow:1;\r | |
| 388 | ///\r | |
| 389 | /// [Bit 31] AMD Extensions to 3DNow! instructions.\r | |
| 390 | ///\r | |
| 391 | UINT32 ThreeDNowExt:1;\r | |
| 392 | } Bits;\r | |
| 393 | ///\r | |
| 394 | /// All bit fields as a 32-bit value\r | |
| 395 | ///\r | |
| 396 | UINT32 Uint32;\r | |
| 397 | } CPUID_AMD_EXTENDED_CPU_SIG_EDX;\r | |
| 398 | \r | |
| 399 | \r | |
| 400 | /**\r | |
| 401 | CPUID Linear Physical Address Size\r | |
| 402 | \r | |
| 403 | @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r | |
| b15cbd9c | 404 | \r |
| 890d2bd2 LD |
405 | @retval EAX Linear/Physical Address Size described by the type\r |
| 406 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.\r | |
| 407 | @retval EBX Linear/Physical Address Size described by the type\r | |
| 408 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.\r | |
| 409 | @retval ECX Linear/Physical Address Size described by the type\r | |
| 410 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.\r | |
| 411 | @retval EDX Reserved.\r | |
| 412 | **/\r | |
| 413 | \r | |
| 414 | /**\r | |
| 415 | CPUID Linear Physical Address Size EAX for CPUID leaf\r | |
| 416 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
| 417 | **/\r | |
| 418 | typedef union {\r | |
| 419 | ///\r | |
| 420 | /// Individual bit fields\r | |
| 421 | ///\r | |
| 422 | struct {\r | |
| 423 | ///\r | |
| 424 | /// [Bits 7:0] Maximum physical byte address size in bits.\r | |
| 425 | ///\r | |
| 426 | UINT32 PhysicalAddressBits:8;\r | |
| 427 | ///\r | |
| 428 | /// [Bits 15:8] Maximum linear byte address size in bits.\r | |
| 429 | ///\r | |
| 430 | UINT32 LinearAddressBits:8;\r | |
| 431 | ///\r | |
| 432 | /// [Bits 23:16] Maximum guest physical byte address size in bits.\r | |
| 433 | ///\r | |
| 434 | UINT32 GuestPhysAddrSize:8;\r | |
| 435 | ///\r | |
| 436 | /// [Bit 31:24] Reserved.\r | |
| 437 | ///\r | |
| 438 | UINT32 Reserved:8;\r | |
| 439 | } Bits;\r | |
| 440 | ///\r | |
| 441 | /// All bit fields as a 32-bit value\r | |
| 442 | ///\r | |
| 443 | UINT32 Uint32;\r | |
| 444 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;\r | |
| 445 | \r | |
| 446 | /**\r | |
| 447 | CPUID Linear Physical Address Size EBX for CPUID leaf\r | |
| 448 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
| 449 | **/\r | |
| 450 | typedef union {\r | |
| 451 | ///\r | |
| 452 | /// Individual bit fields\r | |
| 453 | ///\r | |
| 454 | struct {\r | |
| 455 | ///\r | |
| 456 | /// [Bits 0] Clear Zero Instruction.\r | |
| 457 | ///\r | |
| 458 | UINT32 CLZERO:1;\r | |
| 459 | ///\r | |
| 460 | /// [Bits 1] Instructions retired count support.\r | |
| 461 | ///\r | |
| 462 | UINT32 IRPerf:1;\r | |
| 463 | ///\r | |
| 464 | /// [Bits 2] Restore error pointers for XSave instructions.\r | |
| 465 | ///\r | |
| 466 | UINT32 XSaveErPtr:1;\r | |
| 467 | ///\r | |
| 468 | /// [Bit 31:3] Reserved.\r | |
| 469 | ///\r | |
| 470 | UINT32 Reserved:29;\r | |
| 471 | } Bits;\r | |
| 472 | ///\r | |
| 473 | /// All bit fields as a 32-bit value\r | |
| 474 | ///\r | |
| 475 | UINT32 Uint32;\r | |
| 476 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;\r | |
| 477 | \r | |
| 478 | /**\r | |
| 479 | CPUID Linear Physical Address Size ECX for CPUID leaf\r | |
| 480 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
| 481 | **/\r | |
| 482 | typedef union {\r | |
| 483 | ///\r | |
| 484 | /// Individual bit fields\r | |
| 485 | ///\r | |
| 486 | struct {\r | |
| 487 | ///\r | |
| 488 | /// [Bits 7:0] Number of threads - 1.\r | |
| 489 | ///\r | |
| 490 | UINT32 NC:8;\r | |
| 491 | ///\r | |
| 492 | /// [Bit 11:8] Reserved.\r | |
| 493 | ///\r | |
| 494 | UINT32 Reserved1:4;\r | |
| 495 | ///\r | |
| 496 | /// [Bits 15:12] APIC ID size.\r | |
| 497 | ///\r | |
| 498 | UINT32 ApicIdCoreIdSize:4;\r | |
| 499 | ///\r | |
| 500 | /// [Bits 17:16] Performance time-stamp counter size.\r | |
| 501 | ///\r | |
| 502 | UINT32 PerfTscSize:2;\r | |
| 503 | ///\r | |
| 504 | /// [Bit 31:18] Reserved.\r | |
| 505 | ///\r | |
| 506 | UINT32 Reserved2:14;\r | |
| 507 | } Bits;\r | |
| 508 | ///\r | |
| 509 | /// All bit fields as a 32-bit value\r | |
| 510 | ///\r | |
| 511 | UINT32 Uint32;\r | |
| 512 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;\r | |
| 513 | \r | |
| 514 | \r | |
| 515 | /**\r | |
| 516 | CPUID AMD Processor Topology\r | |
| 517 | \r | |
| 518 | @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)\r | |
| 519 | \r | |
| 520 | @retval EAX Extended APIC ID described by the type\r | |
| 521 | CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.\r | |
| 522 | @retval EBX Core Indentifiers described by the type\r | |
| 523 | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.\r | |
| 524 | @retval ECX Node Indentifiers described by the type\r | |
| 525 | CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.\r | |
| 526 | @retval EDX Reserved.\r | |
| 527 | **/\r | |
| 528 | #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E\r | |
| 529 | \r | |
| 530 | /**\r | |
| 531 | CPUID AMD Processor Topology EAX for CPUID leaf\r | |
| 532 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
| 533 | **/\r | |
| 534 | typedef union {\r | |
| 535 | ///\r | |
| 536 | /// Individual bit fields\r | |
| 537 | ///\r | |
| 538 | struct {\r | |
| 539 | ///\r | |
| 540 | /// [Bit 31:0] Extended APIC Id.\r | |
| 541 | ///\r | |
| 542 | UINT32 ExtendedApicId;\r | |
| 543 | } Bits;\r | |
| 544 | ///\r | |
| 545 | /// All bit fields as a 32-bit value\r | |
| 546 | ///\r | |
| 547 | UINT32 Uint32;\r | |
| 548 | } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;\r | |
| 549 | \r | |
| 550 | /**\r | |
| 551 | CPUID AMD Processor Topology EBX for CPUID leaf\r | |
| 552 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
| 553 | **/\r | |
| 554 | typedef union {\r | |
| 555 | ///\r | |
| 556 | /// Individual bit fields\r | |
| 557 | ///\r | |
| 558 | struct {\r | |
| 559 | ///\r | |
| 560 | /// [Bits 7:0] Core Id.\r | |
| 561 | ///\r | |
| 562 | UINT32 CoreId:8;\r | |
| 563 | ///\r | |
| 564 | /// [Bits 15:8] Threads per core.\r | |
| 565 | ///\r | |
| 566 | UINT32 ThreadsPerCore:8;\r | |
| 567 | ///\r | |
| 568 | /// [Bit 31:16] Reserved.\r | |
| 569 | ///\r | |
| 570 | UINT32 Reserved:16;\r | |
| 571 | } Bits;\r | |
| 572 | ///\r | |
| 573 | /// All bit fields as a 32-bit value\r | |
| 574 | ///\r | |
| 575 | UINT32 Uint32;\r | |
| 576 | } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;\r | |
| 577 | \r | |
| 578 | /**\r | |
| 579 | CPUID AMD Processor Topology ECX for CPUID leaf\r | |
| 580 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
| 581 | **/\r | |
| 582 | typedef union {\r | |
| 583 | ///\r | |
| 584 | /// Individual bit fields\r | |
| 585 | ///\r | |
| 586 | struct {\r | |
| 587 | ///\r | |
| 588 | /// [Bits 7:0] Node Id.\r | |
| 589 | ///\r | |
| 590 | UINT32 NodeId:8;\r | |
| 591 | ///\r | |
| 592 | /// [Bits 10:8] Nodes per processor.\r | |
| 593 | ///\r | |
| 594 | UINT32 NodesPerProcessor:3;\r | |
| 595 | ///\r | |
| 596 | /// [Bit 31:11] Reserved.\r | |
| 597 | ///\r | |
| 598 | UINT32 Reserved:21;\r | |
| 599 | } Bits;\r | |
| 600 | ///\r | |
| 601 | /// All bit fields as a 32-bit value\r | |
| 602 | ///\r | |
| 603 | UINT32 Uint32;\r | |
| 604 | } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;\r | |
| 605 | \r | |
| 606 | \r | |
| 607 | /**\r | |
| 608 | CPUID Memory Encryption Information\r | |
| b15cbd9c BS |
609 | \r |
| 610 | @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)\r | |
| 611 | \r | |
| 612 | @retval EAX Returns the memory encryption feature support status.\r | |
| 613 | @retval EBX If memory encryption feature is present then return\r | |
| 614 | the page table bit number used to enable memory encryption support\r | |
| 615 | and reducing of physical address space in bits.\r | |
| 890d2bd2 LD |
616 | @retval ECX Returns number of encrypted guest supported simultaneously.\r |
| 617 | @retval EDX Returns minimum SEV enabled and SEV disabled ASID.\r | |
| b15cbd9c BS |
618 | \r |
| 619 | <b>Example usage</b>\r | |
| 620 | @code\r | |
| 621 | UINT32 Eax;\r | |
| 622 | UINT32 Ebx;\r | |
| 623 | UINT32 Ecx;\r | |
| 624 | UINT32 Edx;\r | |
| 625 | \r | |
| 626 | AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);\r | |
| 627 | @endcode\r | |
| 628 | **/\r | |
| 629 | \r | |
| 630 | #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r | |
| 631 | \r | |
| 632 | /**\r | |
| 633 | CPUID Memory Encryption support information EAX for CPUID leaf\r | |
| 634 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
| 635 | **/\r | |
| 636 | typedef union {\r | |
| 637 | ///\r | |
| 638 | /// Individual bit fields\r | |
| 639 | ///\r | |
| 640 | struct {\r | |
| 641 | ///\r | |
| 642 | /// [Bit 0] Secure Memory Encryption (Sme) Support\r | |
| 643 | ///\r | |
| 644 | UINT32 SmeBit:1;\r | |
| 645 | \r | |
| 646 | ///\r | |
| 647 | /// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r | |
| 648 | ///\r | |
| 649 | UINT32 SevBit:1;\r | |
| 650 | \r | |
| 651 | ///\r | |
| 652 | /// [Bit 2] Page flush MSR support\r | |
| 653 | ///\r | |
| 654 | UINT32 PageFlushMsrBit:1;\r | |
| 655 | \r | |
| 656 | ///\r | |
| 657 | /// [Bit 3] Encrypted state support\r | |
| 658 | ///\r | |
| 659 | UINT32 SevEsBit:1;\r | |
| 660 | \r | |
| 661 | ///\r | |
| 890d2bd2 | 662 | /// [Bit 31:4] Reserved\r |
| b15cbd9c BS |
663 | ///\r |
| 664 | UINT32 ReservedBits:28;\r | |
| 665 | } Bits;\r | |
| 666 | ///\r | |
| 667 | /// All bit fields as a 32-bit value\r | |
| 668 | ///\r | |
| 669 | UINT32 Uint32;\r | |
| 670 | } CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r | |
| 671 | \r | |
| 672 | /**\r | |
| 673 | CPUID Memory Encryption support information EBX for CPUID leaf\r | |
| 674 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
| 675 | **/\r | |
| 676 | typedef union {\r | |
| 677 | ///\r | |
| 678 | /// Individual bit fields\r | |
| 679 | ///\r | |
| 680 | struct {\r | |
| 681 | ///\r | |
| 890d2bd2 | 682 | /// [Bit 5:0] Page table bit number used to enable memory encryption\r |
| b15cbd9c BS |
683 | ///\r |
| 684 | UINT32 PtePosBits:6;\r | |
| 685 | \r | |
| 686 | ///\r | |
| 890d2bd2 LD |
687 | /// [Bit 11:6] Reduction of system physical address space bits when\r |
| 688 | /// memory encryption is enabled\r | |
| b15cbd9c BS |
689 | ///\r |
| 690 | UINT32 ReducedPhysBits:5;\r | |
| 691 | \r | |
| 692 | ///\r | |
| 890d2bd2 | 693 | /// [Bit 31:12] Reserved\r |
| b15cbd9c BS |
694 | ///\r |
| 695 | UINT32 ReservedBits:21;\r | |
| 696 | } Bits;\r | |
| 697 | ///\r | |
| 698 | /// All bit fields as a 32-bit value\r | |
| 699 | ///\r | |
| 700 | UINT32 Uint32;\r | |
| 701 | } CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r | |
| 702 | \r | |
| 703 | /**\r | |
| 704 | CPUID Memory Encryption support information ECX for CPUID leaf\r | |
| 705 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
| 706 | **/\r | |
| 707 | typedef union {\r | |
| 708 | ///\r | |
| 709 | /// Individual bit fields\r | |
| 710 | ///\r | |
| 711 | struct {\r | |
| 712 | ///\r | |
| 890d2bd2 | 713 | /// [Bit 31:0] Number of encrypted guest supported simultaneously\r |
| b15cbd9c BS |
714 | ///\r |
| 715 | UINT32 NumGuests;\r | |
| 716 | } Bits;\r | |
| 717 | ///\r | |
| 718 | /// All bit fields as a 32-bit value\r | |
| 719 | ///\r | |
| 720 | UINT32 Uint32;\r | |
| 721 | } CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r | |
| 722 | \r | |
| 723 | /**\r | |
| 724 | CPUID Memory Encryption support information EDX for CPUID leaf\r | |
| 725 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
| 726 | **/\r | |
| 727 | typedef union {\r | |
| 728 | ///\r | |
| 729 | /// Individual bit fields\r | |
| 730 | ///\r | |
| 731 | struct {\r | |
| 732 | ///\r | |
| 890d2bd2 | 733 | /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID\r |
| b15cbd9c BS |
734 | ///\r |
| 735 | UINT32 MinAsid;\r | |
| 736 | } Bits;\r | |
| 737 | ///\r | |
| 738 | /// All bit fields as a 32-bit value\r | |
| 739 | ///\r | |
| 740 | UINT32 Uint32;\r | |
| 741 | } CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r | |
| 742 | \r | |
| 743 | #endif\r |