projects / mirror_edk2.git / blame
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| 04c980a6 MK |
1 | /** @file\r |
| 2 | Architectural MSR Definitions.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 04c980a6 MK |
11 | \r |
| 12 | @par Specification Reference:\r | |
| ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| 831d287a | 15 | \r |
| 04c980a6 MK |
16 | **/\r |
| 17 | \r | |
| 18 | #ifndef __ARCHITECTURAL_MSR_H__\r | |
| 19 | #define __ARCHITECTURAL_MSR_H__\r | |
| 20 | \r | |
| 21 | /**\r | |
| ba1a2d11 | 22 | See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r |
| 04c980a6 MK |
23 | \r |
| 24 | @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r | |
| 25 | @param EAX Lower 32-bits of MSR value.\r | |
| 26 | @param EDX Upper 32-bits of MSR value.\r | |
| 27 | \r | |
| 28 | <b>Example usage</b>\r | |
| 29 | @code\r | |
| 30 | UINT64 Msr;\r | |
| 31 | \r | |
| 32 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r | |
| 33 | AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r | |
| 34 | @endcode\r | |
| 7de98828 | 35 | @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r |
| 04c980a6 MK |
36 | **/\r |
| 37 | #define MSR_IA32_P5_MC_ADDR 0x00000000\r | |
| 38 | \r | |
| 39 | \r | |
| 40 | /**\r | |
| ba1a2d11 | 41 | See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r |
| 04c980a6 MK |
42 | \r |
| 43 | @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r | |
| 44 | @param EAX Lower 32-bits of MSR value.\r | |
| 45 | @param EDX Upper 32-bits of MSR value.\r | |
| 46 | \r | |
| 47 | <b>Example usage</b>\r | |
| 48 | @code\r | |
| 49 | UINT64 Msr;\r | |
| 50 | \r | |
| 51 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r | |
| 52 | AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r | |
| 53 | @endcode\r | |
| 7de98828 | 54 | @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r |
| 04c980a6 MK |
55 | **/\r |
| 56 | #define MSR_IA32_P5_MC_TYPE 0x00000001\r | |
| 57 | \r | |
| 58 | \r | |
| 59 | /**\r | |
| 60 | See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r | |
| 61 | at Display Family / Display Model 0F_03H.\r | |
| 62 | \r | |
| 63 | @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r | |
| 64 | @param EAX Lower 32-bits of MSR value.\r | |
| 65 | @param EDX Upper 32-bits of MSR value.\r | |
| 66 | \r | |
| 67 | <b>Example usage</b>\r | |
| 68 | @code\r | |
| 69 | UINT64 Msr;\r | |
| 70 | \r | |
| 71 | Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r | |
| 72 | AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r | |
| 73 | @endcode\r | |
| 7de98828 | 74 | @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r |
| 04c980a6 MK |
75 | **/\r |
| 76 | #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r | |
| 77 | \r | |
| 78 | \r | |
| 79 | /**\r | |
| ba1a2d11 | 80 | See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /\r |
| 04c980a6 MK |
81 | Display Model 05_01H.\r |
| 82 | \r | |
| 83 | @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r | |
| 84 | @param EAX Lower 32-bits of MSR value.\r | |
| 85 | @param EDX Upper 32-bits of MSR value.\r | |
| 86 | \r | |
| 87 | <b>Example usage</b>\r | |
| 88 | @code\r | |
| 89 | UINT64 Msr;\r | |
| 90 | \r | |
| 91 | Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r | |
| 92 | AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r | |
| 93 | @endcode\r | |
| 7de98828 | 94 | @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r |
| 04c980a6 MK |
95 | **/\r |
| 96 | #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r | |
| 97 | \r | |
| 98 | \r | |
| 99 | /**\r | |
| 100 | Platform ID (RO) The operating system can use this MSR to determine "slot"\r | |
| 101 | information for the processor and the proper microcode update to load.\r | |
| 102 | Introduced at Display Family / Display Model 06_01H.\r | |
| 103 | \r | |
| 104 | @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r | |
| 105 | @param EAX Lower 32-bits of MSR value.\r | |
| 106 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 107 | @param EDX Upper 32-bits of MSR value.\r | |
| 108 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 109 | \r | |
| 110 | <b>Example usage</b>\r | |
| 111 | @code\r | |
| 112 | MSR_IA32_PLATFORM_ID_REGISTER Msr;\r | |
| 113 | \r | |
| 114 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r | |
| 115 | @endcode\r | |
| 7de98828 | 116 | @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r |
| 04c980a6 MK |
117 | **/\r |
| 118 | #define MSR_IA32_PLATFORM_ID 0x00000017\r | |
| 119 | \r | |
| 120 | /**\r | |
| 121 | MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r | |
| 122 | **/\r | |
| 123 | typedef union {\r | |
| 124 | ///\r | |
| 125 | /// Individual bit fields\r | |
| 126 | ///\r | |
| 127 | struct {\r | |
| 128 | UINT32 Reserved1:32;\r | |
| 129 | UINT32 Reserved2:18;\r | |
| 130 | ///\r | |
| 131 | /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r | |
| 132 | /// intended platform for the processor.\r | |
| 133 | /// 52 51 50\r | |
| 134 | /// -- -- --\r | |
| 135 | /// 0 0 0 Processor Flag 0.\r | |
| 136 | /// 0 0 1 Processor Flag 1\r | |
| 137 | /// 0 1 0 Processor Flag 2\r | |
| 138 | /// 0 1 1 Processor Flag 3\r | |
| 139 | /// 1 0 0 Processor Flag 4\r | |
| 140 | /// 1 0 1 Processor Flag 5\r | |
| 141 | /// 1 1 0 Processor Flag 6\r | |
| 142 | /// 1 1 1 Processor Flag 7\r | |
| 143 | ///\r | |
| 144 | UINT32 PlatformId:3;\r | |
| 145 | UINT32 Reserved3:11;\r | |
| 146 | } Bits;\r | |
| 147 | ///\r | |
| 148 | /// All bit fields as a 64-bit value\r | |
| 149 | ///\r | |
| 150 | UINT64 Uint64;\r | |
| 151 | } MSR_IA32_PLATFORM_ID_REGISTER;\r | |
| 152 | \r | |
| 153 | \r | |
| 154 | /**\r | |
| 155 | 06_01H.\r | |
| 156 | \r | |
| 157 | @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r | |
| 158 | @param EAX Lower 32-bits of MSR value.\r | |
| 159 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 160 | @param EDX Upper 32-bits of MSR value.\r | |
| 161 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 162 | \r | |
| 163 | <b>Example usage</b>\r | |
| 164 | @code\r | |
| 165 | MSR_IA32_APIC_BASE_REGISTER Msr;\r | |
| 166 | \r | |
| 167 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
| 168 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r | |
| 169 | @endcode\r | |
| 7de98828 | 170 | @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r |
| 04c980a6 MK |
171 | **/\r |
| 172 | #define MSR_IA32_APIC_BASE 0x0000001B\r | |
| 173 | \r | |
| 174 | /**\r | |
| 175 | MSR information returned for MSR index #MSR_IA32_APIC_BASE\r | |
| 176 | **/\r | |
| 177 | typedef union {\r | |
| 178 | ///\r | |
| 179 | /// Individual bit fields\r | |
| 180 | ///\r | |
| 181 | struct {\r | |
| 182 | UINT32 Reserved1:8;\r | |
| 183 | ///\r | |
| 184 | /// [Bit 8] BSP flag (R/W).\r | |
| 185 | ///\r | |
| 186 | UINT32 BSP:1;\r | |
| 187 | UINT32 Reserved2:1;\r | |
| 188 | ///\r | |
| 189 | /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r | |
| 190 | /// Model 06_1AH.\r | |
| 191 | ///\r | |
| 192 | UINT32 EXTD:1;\r | |
| 193 | ///\r | |
| 194 | /// [Bit 11] APIC Global Enable (R/W).\r | |
| 195 | ///\r | |
| 196 | UINT32 EN:1;\r | |
| 197 | ///\r | |
| 198 | /// [Bits 31:12] APIC Base (R/W).\r | |
| 199 | ///\r | |
| 200 | UINT32 ApicBase:20;\r | |
| 201 | ///\r | |
| 202 | /// [Bits 63:32] APIC Base (R/W).\r | |
| 203 | ///\r | |
| 204 | UINT32 ApicBaseHi:32;\r | |
| 205 | } Bits;\r | |
| 206 | ///\r | |
| 207 | /// All bit fields as a 64-bit value\r | |
| 208 | ///\r | |
| 209 | UINT64 Uint64;\r | |
| 210 | } MSR_IA32_APIC_BASE_REGISTER;\r | |
| 211 | \r | |
| 212 | \r | |
| 213 | /**\r | |
| 214 | Control Features in Intel 64 Processor (R/W). If any one enumeration\r | |
| 215 | condition for defined bit field holds.\r | |
| 216 | \r | |
| 217 | @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r | |
| 218 | @param EAX Lower 32-bits of MSR value.\r | |
| 219 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 220 | @param EDX Upper 32-bits of MSR value.\r | |
| 221 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 222 | \r | |
| 223 | <b>Example usage</b>\r | |
| 224 | @code\r | |
| 225 | MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r | |
| 226 | \r | |
| 227 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r | |
| 228 | AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r | |
| 229 | @endcode\r | |
| 7de98828 | 230 | @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r |
| 04c980a6 MK |
231 | **/\r |
| 232 | #define MSR_IA32_FEATURE_CONTROL 0x0000003A\r | |
| 233 | \r | |
| 234 | /**\r | |
| 235 | MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r | |
| 236 | **/\r | |
| 237 | typedef union {\r | |
| 238 | ///\r | |
| 239 | /// Individual bit fields\r | |
| 240 | ///\r | |
| 241 | struct {\r | |
| 242 | ///\r | |
| 243 | /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r | |
| 244 | /// being written, writes to this bit will result in GP(0). Note: Once the\r | |
| 245 | /// Lock bit is set, the contents of this register cannot be modified.\r | |
| 246 | /// Therefore the lock bit must be set after configuring support for Intel\r | |
| 247 | /// Virtualization Technology and prior to transferring control to an\r | |
| 248 | /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r | |
| 249 | /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r | |
| 250 | /// is not deasserted. If any one enumeration condition for defined bit\r | |
| 251 | /// field position greater than bit 0 holds.\r | |
| 252 | ///\r | |
| 253 | UINT32 Lock:1;\r | |
| 254 | ///\r | |
| 255 | /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r | |
| 256 | /// system executive to use VMX in conjunction with SMX to support\r | |
| 257 | /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r | |
| 258 | /// when the CPUID function 1 returns VMX feature flag and SMX feature\r | |
| 259 | /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r | |
| 260 | /// CPUID.01H:ECX[6] = 1.\r | |
| 261 | ///\r | |
| 262 | UINT32 EnableVmxInsideSmx:1;\r | |
| 263 | ///\r | |
| 264 | /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r | |
| 265 | /// for system executive that do not require SMX. BIOS must set this bit\r | |
| 266 | /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r | |
| 267 | /// 5). If CPUID.01H:ECX[5] = 1.\r | |
| 268 | ///\r | |
| 269 | UINT32 EnableVmxOutsideSmx:1;\r | |
| 270 | UINT32 Reserved1:5;\r | |
| 271 | ///\r | |
| 272 | /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r | |
| 273 | /// in the field represents an enable control for a corresponding SENTER\r | |
| 274 | /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r | |
| 275 | /// CPUID.01H:ECX[6] = 1.\r | |
| 276 | ///\r | |
| 277 | UINT32 SenterLocalFunctionEnables:7;\r | |
| 278 | ///\r | |
| 279 | /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r | |
| 280 | /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r | |
| 281 | /// 6] is set. If CPUID.01H:ECX[6] = 1.\r | |
| 282 | ///\r | |
| 283 | UINT32 SenterGlobalEnable:1;\r | |
| 0f16be6d HW |
284 | UINT32 Reserved2:1;\r |
| 285 | ///\r | |
| 286 | /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r | |
| 287 | /// enable runtime reconfiguration of SGX Launch Control via\r | |
| 288 | /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r | |
| 289 | ///\r | |
| 290 | UINT32 SgxLaunchControlEnable:1;\r | |
| 04c980a6 MK |
291 | ///\r |
| 292 | /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r | |
| 0f16be6d | 293 | /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r |
| 04c980a6 MK |
294 | ///\r |
| 295 | UINT32 SgxEnable:1;\r | |
| 296 | UINT32 Reserved3:1;\r | |
| 297 | ///\r | |
| 298 | /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r | |
| 299 | /// MSRs associated with LMCE to configure delivery of some machine check\r | |
| 300 | /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r | |
| 301 | ///\r | |
| 302 | UINT32 LmceOn:1;\r | |
| 303 | UINT32 Reserved4:11;\r | |
| 304 | UINT32 Reserved5:32;\r | |
| 305 | } Bits;\r | |
| 306 | ///\r | |
| 307 | /// All bit fields as a 32-bit value\r | |
| 308 | ///\r | |
| 309 | UINT32 Uint32;\r | |
| 310 | ///\r | |
| 311 | /// All bit fields as a 64-bit value\r | |
| 312 | ///\r | |
| 313 | UINT64 Uint64;\r | |
| 314 | } MSR_IA32_FEATURE_CONTROL_REGISTER;\r | |
| 315 | \r | |
| 316 | \r | |
| 317 | /**\r | |
| 318 | Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r | |
| 319 | ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r | |
| 320 | a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r | |
| 321 | the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r | |
| 322 | not affect the internal invariant TSC hardware.\r | |
| 323 | \r | |
| 324 | @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r | |
| 325 | @param EAX Lower 32-bits of MSR value.\r | |
| 326 | @param EDX Upper 32-bits of MSR value.\r | |
| 327 | \r | |
| 328 | <b>Example usage</b>\r | |
| 329 | @code\r | |
| 330 | UINT64 Msr;\r | |
| 331 | \r | |
| 332 | Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r | |
| 333 | AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r | |
| 334 | @endcode\r | |
| 7de98828 | 335 | @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r |
| 04c980a6 MK |
336 | **/\r |
| 337 | #define MSR_IA32_TSC_ADJUST 0x0000003B\r | |
| 338 | \r | |
| 339 | \r | |
| 340 | /**\r | |
| 341 | BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r | |
| 342 | microcode update to be loaded into the processor. See Section 9.11.6,\r | |
| 343 | "Microcode Update Loader." A processor may prevent writing to this MSR when\r | |
| 344 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 345 | Introduced at Display Family / Display Model 06_01H.\r | |
| 346 | \r | |
| 347 | @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r | |
| 348 | @param EAX Lower 32-bits of MSR value.\r | |
| 349 | @param EDX Upper 32-bits of MSR value.\r | |
| 350 | \r | |
| 351 | <b>Example usage</b>\r | |
| 352 | @code\r | |
| 353 | UINT64 Msr;\r | |
| 354 | \r | |
| 355 | Msr = 0;\r | |
| 356 | AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r | |
| 357 | @endcode\r | |
| 7de98828 | 358 | @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r |
| 04c980a6 MK |
359 | **/\r |
| 360 | #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r | |
| 361 | \r | |
| 362 | \r | |
| 363 | /**\r | |
| 364 | BIOS Update Signature (RO) Returns the microcode update signature following\r | |
| 365 | the execution of CPUID.01H. A processor may prevent writing to this MSR when\r | |
| 366 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 367 | Introduced at Display Family / Display Model 06_01H.\r | |
| 368 | \r | |
| 369 | @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r | |
| 370 | @param EAX Lower 32-bits of MSR value.\r | |
| 371 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 372 | @param EDX Upper 32-bits of MSR value.\r | |
| 373 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 374 | \r | |
| 375 | <b>Example usage</b>\r | |
| 376 | @code\r | |
| 377 | MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r | |
| 378 | \r | |
| 379 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r | |
| 380 | @endcode\r | |
| 7de98828 | 381 | @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r |
| 04c980a6 MK |
382 | **/\r |
| 383 | #define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r | |
| 384 | \r | |
| 385 | /**\r | |
| 386 | MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r | |
| 387 | **/\r | |
| 388 | typedef union {\r | |
| 389 | ///\r | |
| 390 | /// Individual bit fields\r | |
| 391 | ///\r | |
| 392 | struct {\r | |
| 393 | UINT32 Reserved:32;\r | |
| 394 | ///\r | |
| 395 | /// [Bits 63:32] Microcode update signature. This field contains the\r | |
| 396 | /// signature of the currently loaded microcode update when read following\r | |
| 397 | /// the execution of the CPUID instruction, function 1. It is required\r | |
| 398 | /// that this register field be pre-loaded with zero prior to executing\r | |
| 399 | /// the CPUID, function 1. If the field remains equal to zero, then there\r | |
| 400 | /// is no microcode update loaded. Another nonzero value will be the\r | |
| 401 | /// signature.\r | |
| 402 | ///\r | |
| 403 | UINT32 MicrocodeUpdateSignature:32;\r | |
| 404 | } Bits;\r | |
| 405 | ///\r | |
| 406 | /// All bit fields as a 64-bit value\r | |
| 407 | ///\r | |
| 408 | UINT64 Uint64;\r | |
| 409 | } MSR_IA32_BIOS_SIGN_ID_REGISTER;\r | |
| 410 | \r | |
| 411 | \r | |
| 0f16be6d HW |
412 | /**\r |
| 413 | IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r | |
| 414 | SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r | |
| 415 | default value is the digest of Intel's signing key. Read permitted If\r | |
| 416 | CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r | |
| 417 | EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r | |
| 418 | \r | |
| 419 | @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r | |
| 420 | @param EAX Lower 32-bits of MSR value.\r | |
| 421 | @param EDX Upper 32-bits of MSR value.\r | |
| 422 | \r | |
| 423 | <b>Example usage</b>\r | |
| 424 | @code\r | |
| 425 | UINT64 Msr;\r | |
| 426 | \r | |
| 427 | Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r | |
| 428 | AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r | |
| 429 | @endcode\r | |
| 430 | @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r | |
| 431 | MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r | |
| 432 | MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r | |
| 433 | MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r | |
| 434 | @{\r | |
| 435 | **/\r | |
| 436 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r | |
| 437 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r | |
| 438 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r | |
| 439 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r | |
| 440 | /// @}\r | |
| 441 | \r | |
| 442 | \r | |
| 04c980a6 | 443 | /**\r |
| 831d287a | 444 | SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r |
| 04c980a6 MK |
445 | 1.\r |
| 446 | \r | |
| 447 | @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r | |
| 448 | @param EAX Lower 32-bits of MSR value.\r | |
| 449 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 450 | @param EDX Upper 32-bits of MSR value.\r | |
| 451 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 452 | \r | |
| 453 | <b>Example usage</b>\r | |
| 454 | @code\r | |
| 455 | MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r | |
| 456 | \r | |
| 457 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r | |
| 458 | AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r | |
| 459 | @endcode\r | |
| 7de98828 | 460 | @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r |
| 04c980a6 MK |
461 | **/\r |
| 462 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r | |
| 463 | \r | |
| 464 | /**\r | |
| 465 | MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r | |
| 466 | **/\r | |
| 467 | typedef union {\r | |
| 468 | ///\r | |
| 469 | /// Individual bit fields\r | |
| 470 | ///\r | |
| 471 | struct {\r | |
| 472 | ///\r | |
| 473 | /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r | |
| 474 | /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r | |
| 475 | /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r | |
| 476 | /// if the bit is 0. This bit is cleared when the logical processor is\r | |
| 477 | /// reset.\r | |
| 478 | ///\r | |
| 479 | UINT32 Valid:1;\r | |
| 480 | UINT32 Reserved1:1;\r | |
| 481 | ///\r | |
| ba1a2d11 ED |
482 | /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If\r |
| 483 | /// IA32_VMX_MISC[28].\r | |
| 04c980a6 MK |
484 | ///\r |
| 485 | UINT32 BlockSmi:1;\r | |
| 486 | UINT32 Reserved2:9;\r | |
| 487 | ///\r | |
| 488 | /// [Bits 31:12] MSEG Base (R/W).\r | |
| 489 | ///\r | |
| 490 | UINT32 MsegBase:20;\r | |
| 491 | UINT32 Reserved3:32;\r | |
| 492 | } Bits;\r | |
| 493 | ///\r | |
| 494 | /// All bit fields as a 32-bit value\r | |
| 495 | ///\r | |
| 496 | UINT32 Uint32;\r | |
| 497 | ///\r | |
| 498 | /// All bit fields as a 64-bit value\r | |
| 499 | ///\r | |
| 500 | UINT64 Uint64;\r | |
| 501 | } MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r | |
| 502 | \r | |
| 831d287a MK |
503 | /**\r |
| 504 | MSEG header that is located at the physical address specified by the MsegBase\r | |
| 505 | field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 506 | **/\r | |
| 507 | typedef struct {\r | |
| a03bb3d2 MK |
508 | ///\r |
| 509 | /// Different processors may use different MSEG revision identifiers. These\r | |
| 510 | /// identifiers enable software to avoid using an MSEG header formatted for\r | |
| 511 | /// one processor on a processor that uses a different format. Software can\r | |
| 512 | /// discover the MSEG revision identifier that a processor uses by reading\r | |
| 513 | /// the VMX capability MSR IA32_VMX_MISC.\r | |
| 514 | //\r | |
| 831d287a | 515 | UINT32 MsegHeaderRevision;\r |
| a03bb3d2 MK |
516 | ///\r |
| 517 | /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r | |
| 518 | /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r | |
| 519 | /// processor will be in IA-32e mode after the STM is activated.\r | |
| 520 | ///\r | |
| 831d287a MK |
521 | UINT32 MonitorFeatures;\r |
| 522 | UINT32 GdtrLimit;\r | |
| 523 | UINT32 GdtrBaseOffset;\r | |
| 524 | UINT32 CsSelector;\r | |
| 525 | UINT32 EipOffset;\r | |
| 526 | UINT32 EspOffset;\r | |
| 527 | UINT32 Cr3Offset;\r | |
| a03bb3d2 MK |
528 | ///\r |
| 529 | /// Pad header so total size is 2KB\r | |
| 530 | ///\r | |
| 831d287a MK |
531 | UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r |
| 532 | } MSEG_HEADER;\r | |
| 533 | \r | |
| a03bb3d2 MK |
534 | ///\r |
| 535 | /// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r | |
| 536 | ///\r | |
| 537 | #define STM_FEATURES_IA32E 0x1\r | |
| 538 | ///\r | |
| 539 | /// @}\r | |
| 540 | ///\r | |
| 04c980a6 MK |
541 | \r |
| 542 | /**\r | |
| 543 | Base address of the logical processor's SMRAM image (RO, SMM only). If\r | |
| 544 | IA32_VMX_MISC[15].\r | |
| 545 | \r | |
| 546 | @param ECX MSR_IA32_SMBASE (0x0000009E)\r | |
| 547 | @param EAX Lower 32-bits of MSR value.\r | |
| 548 | @param EDX Upper 32-bits of MSR value.\r | |
| 549 | \r | |
| 550 | <b>Example usage</b>\r | |
| 551 | @code\r | |
| 552 | UINT64 Msr;\r | |
| 553 | \r | |
| 554 | Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r | |
| 555 | @endcode\r | |
| 7de98828 | 556 | @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r |
| 04c980a6 MK |
557 | **/\r |
| 558 | #define MSR_IA32_SMBASE 0x0000009E\r | |
| 559 | \r | |
| 560 | \r | |
| 561 | /**\r | |
| 562 | General Performance Counters (R/W).\r | |
| 563 | MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r | |
| 564 | \r | |
| 565 | @param ECX MSR_IA32_PMCn\r | |
| 566 | @param EAX Lower 32-bits of MSR value.\r | |
| 567 | @param EDX Upper 32-bits of MSR value.\r | |
| 568 | \r | |
| 569 | <b>Example usage</b>\r | |
| 570 | @code\r | |
| 571 | UINT64 Msr;\r | |
| 572 | \r | |
| 573 | Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r | |
| 574 | AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r | |
| 575 | @endcode\r | |
| 7de98828 JF |
576 | @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r |
| 577 | MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r | |
| 578 | MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r | |
| 579 | MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r | |
| 580 | MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r | |
| 581 | MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r | |
| 582 | MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r | |
| 583 | MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r | |
| 04c980a6 MK |
584 | @{\r |
| 585 | **/\r | |
| 586 | #define MSR_IA32_PMC0 0x000000C1\r | |
| 587 | #define MSR_IA32_PMC1 0x000000C2\r | |
| 588 | #define MSR_IA32_PMC2 0x000000C3\r | |
| 589 | #define MSR_IA32_PMC3 0x000000C4\r | |
| 590 | #define MSR_IA32_PMC4 0x000000C5\r | |
| 591 | #define MSR_IA32_PMC5 0x000000C6\r | |
| 592 | #define MSR_IA32_PMC6 0x000000C7\r | |
| 593 | #define MSR_IA32_PMC7 0x000000C8\r | |
| 594 | /// @}\r | |
| 595 | \r | |
| 596 | \r | |
| 597 | /**\r | |
| 598 | TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r | |
| 599 | C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r | |
| 600 | to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r | |
| 601 | wrap-around of IA32_APERF.\r | |
| 602 | \r | |
| 603 | @param ECX MSR_IA32_MPERF (0x000000E7)\r | |
| 604 | @param EAX Lower 32-bits of MSR value.\r | |
| 605 | @param EDX Upper 32-bits of MSR value.\r | |
| 606 | \r | |
| 607 | <b>Example usage</b>\r | |
| 608 | @code\r | |
| 609 | UINT64 Msr;\r | |
| 610 | \r | |
| 611 | Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r | |
| 612 | AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r | |
| 613 | @endcode\r | |
| 7de98828 | 614 | @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r |
| 04c980a6 MK |
615 | **/\r |
| 616 | #define MSR_IA32_MPERF 0x000000E7\r | |
| 617 | \r | |
| 618 | \r | |
| 619 | /**\r | |
| 620 | Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r | |
| 621 | 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r | |
| 622 | the coordinated clock frequency, when the logical processor is in C0.\r | |
| 623 | Cleared upon overflow / wrap-around of IA32_MPERF.\r | |
| 624 | \r | |
| 625 | @param ECX MSR_IA32_APERF (0x000000E8)\r | |
| 626 | @param EAX Lower 32-bits of MSR value.\r | |
| 627 | @param EDX Upper 32-bits of MSR value.\r | |
| 628 | \r | |
| 629 | <b>Example usage</b>\r | |
| 630 | @code\r | |
| 631 | UINT64 Msr;\r | |
| 632 | \r | |
| 633 | Msr = AsmReadMsr64 (MSR_IA32_APERF);\r | |
| 634 | AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r | |
| 635 | @endcode\r | |
| 7de98828 | 636 | @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r |
| 04c980a6 MK |
637 | **/\r |
| 638 | #define MSR_IA32_APERF 0x000000E8\r | |
| 639 | \r | |
| 640 | \r | |
| 641 | /**\r | |
| 642 | MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r | |
| 643 | Introduced at Display Family / Display Model 06_01H.\r | |
| 644 | \r | |
| 645 | @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r | |
| 646 | @param EAX Lower 32-bits of MSR value.\r | |
| 647 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 648 | @param EDX Upper 32-bits of MSR value.\r | |
| 649 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 650 | \r | |
| 651 | <b>Example usage</b>\r | |
| 652 | @code\r | |
| 653 | MSR_IA32_MTRRCAP_REGISTER Msr;\r | |
| 654 | \r | |
| 655 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r | |
| 656 | @endcode\r | |
| 7de98828 | 657 | @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r |
| 04c980a6 MK |
658 | **/\r |
| 659 | #define MSR_IA32_MTRRCAP 0x000000FE\r | |
| 660 | \r | |
| 661 | /**\r | |
| 662 | MSR information returned for MSR index #MSR_IA32_MTRRCAP\r | |
| 663 | **/\r | |
| 664 | typedef union {\r | |
| 665 | ///\r | |
| 666 | /// Individual bit fields\r | |
| 667 | ///\r | |
| 668 | struct {\r | |
| 669 | ///\r | |
| 670 | /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r | |
| 671 | /// processor.\r | |
| 672 | ///\r | |
| 673 | UINT32 VCNT:8;\r | |
| 674 | ///\r | |
| 675 | /// [Bit 8] Fixed range MTRRs are supported when set.\r | |
| 676 | ///\r | |
| 677 | UINT32 FIX:1;\r | |
| 678 | UINT32 Reserved1:1;\r | |
| 679 | ///\r | |
| 680 | /// [Bit 10] WC Supported when set.\r | |
| 681 | ///\r | |
| 682 | UINT32 WC:1;\r | |
| 683 | ///\r | |
| 684 | /// [Bit 11] SMRR Supported when set.\r | |
| 685 | ///\r | |
| 686 | UINT32 SMRR:1;\r | |
| 687 | UINT32 Reserved2:20;\r | |
| 688 | UINT32 Reserved3:32;\r | |
| 689 | } Bits;\r | |
| 690 | ///\r | |
| 691 | /// All bit fields as a 32-bit value\r | |
| 692 | ///\r | |
| 693 | UINT32 Uint32;\r | |
| 694 | ///\r | |
| 695 | /// All bit fields as a 64-bit value\r | |
| 696 | ///\r | |
| 697 | UINT64 Uint64;\r | |
| 698 | } MSR_IA32_MTRRCAP_REGISTER;\r | |
| 699 | \r | |
| 700 | \r | |
| 701 | /**\r | |
| 702 | SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 703 | \r | |
| 704 | @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r | |
| 705 | @param EAX Lower 32-bits of MSR value.\r | |
| 706 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 707 | @param EDX Upper 32-bits of MSR value.\r | |
| 708 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 709 | \r | |
| 710 | <b>Example usage</b>\r | |
| 711 | @code\r | |
| 712 | MSR_IA32_SYSENTER_CS_REGISTER Msr;\r | |
| 713 | \r | |
| 714 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r | |
| 715 | AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r | |
| 716 | @endcode\r | |
| 7de98828 | 717 | @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r |
| 04c980a6 MK |
718 | **/\r |
| 719 | #define MSR_IA32_SYSENTER_CS 0x00000174\r | |
| 720 | \r | |
| 721 | /**\r | |
| 722 | MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r | |
| 723 | **/\r | |
| 724 | typedef union {\r | |
| 725 | ///\r | |
| 726 | /// Individual bit fields\r | |
| 727 | ///\r | |
| 728 | struct {\r | |
| 729 | ///\r | |
| 730 | /// [Bits 15:0] CS Selector.\r | |
| 731 | ///\r | |
| 732 | UINT32 CS:16;\r | |
| 733 | UINT32 Reserved1:16;\r | |
| 734 | UINT32 Reserved2:32;\r | |
| 735 | } Bits;\r | |
| 736 | ///\r | |
| 737 | /// All bit fields as a 32-bit value\r | |
| 738 | ///\r | |
| 739 | UINT32 Uint32;\r | |
| 740 | ///\r | |
| 741 | /// All bit fields as a 64-bit value\r | |
| 742 | ///\r | |
| 743 | UINT64 Uint64;\r | |
| 744 | } MSR_IA32_SYSENTER_CS_REGISTER;\r | |
| 745 | \r | |
| 746 | \r | |
| 747 | /**\r | |
| 748 | SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 749 | \r | |
| 750 | @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r | |
| 751 | @param EAX Lower 32-bits of MSR value.\r | |
| 752 | @param EDX Upper 32-bits of MSR value.\r | |
| 753 | \r | |
| 754 | <b>Example usage</b>\r | |
| 755 | @code\r | |
| 756 | UINT64 Msr;\r | |
| 757 | \r | |
| 758 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r | |
| 759 | AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r | |
| 760 | @endcode\r | |
| 7de98828 | 761 | @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r |
| 04c980a6 MK |
762 | **/\r |
| 763 | #define MSR_IA32_SYSENTER_ESP 0x00000175\r | |
| 764 | \r | |
| 765 | \r | |
| 766 | /**\r | |
| 767 | SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 768 | \r | |
| 769 | @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r | |
| 770 | @param EAX Lower 32-bits of MSR value.\r | |
| 771 | @param EDX Upper 32-bits of MSR value.\r | |
| 772 | \r | |
| 773 | <b>Example usage</b>\r | |
| 774 | @code\r | |
| 775 | UINT64 Msr;\r | |
| 776 | \r | |
| 777 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r | |
| 778 | AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r | |
| 779 | @endcode\r | |
| 7de98828 | 780 | @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r |
| 04c980a6 MK |
781 | **/\r |
| 782 | #define MSR_IA32_SYSENTER_EIP 0x00000176\r | |
| 783 | \r | |
| 784 | \r | |
| 785 | /**\r | |
| 786 | Global Machine Check Capability (RO). Introduced at Display Family / Display\r | |
| 787 | Model 06_01H.\r | |
| 788 | \r | |
| 789 | @param ECX MSR_IA32_MCG_CAP (0x00000179)\r | |
| 790 | @param EAX Lower 32-bits of MSR value.\r | |
| 791 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 792 | @param EDX Upper 32-bits of MSR value.\r | |
| 793 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 794 | \r | |
| 795 | <b>Example usage</b>\r | |
| 796 | @code\r | |
| 797 | MSR_IA32_MCG_CAP_REGISTER Msr;\r | |
| 798 | \r | |
| 799 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
| 800 | @endcode\r | |
| 7de98828 | 801 | @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r |
| 04c980a6 MK |
802 | **/\r |
| 803 | #define MSR_IA32_MCG_CAP 0x00000179\r | |
| 804 | \r | |
| 805 | /**\r | |
| 806 | MSR information returned for MSR index #MSR_IA32_MCG_CAP\r | |
| 807 | **/\r | |
| 808 | typedef union {\r | |
| 809 | ///\r | |
| 810 | /// Individual bit fields\r | |
| 811 | ///\r | |
| 812 | struct {\r | |
| 813 | ///\r | |
| 814 | /// [Bits 7:0] Count: Number of reporting banks.\r | |
| 815 | ///\r | |
| 816 | UINT32 Count:8;\r | |
| 817 | ///\r | |
| 818 | /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r | |
| 819 | ///\r | |
| 820 | UINT32 MCG_CTL_P:1;\r | |
| 821 | ///\r | |
| 822 | /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r | |
| 823 | /// if this bit is set.\r | |
| 824 | ///\r | |
| 825 | UINT32 MCG_EXT_P:1;\r | |
| 826 | ///\r | |
| 827 | /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r | |
| 828 | /// Introduced at Display Family / Display Model 06_01H.\r | |
| 829 | ///\r | |
| 830 | UINT32 MCP_CMCI_P:1;\r | |
| 831 | ///\r | |
| 832 | /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r | |
| 833 | /// if this bit is set.\r | |
| 834 | ///\r | |
| 835 | UINT32 MCG_TES_P:1;\r | |
| 836 | UINT32 Reserved1:4;\r | |
| 837 | ///\r | |
| 838 | /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r | |
| 839 | /// registers present.\r | |
| 840 | ///\r | |
| 841 | UINT32 MCG_EXT_CNT:8;\r | |
| 842 | ///\r | |
| 843 | /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r | |
| 844 | /// this bit is set.\r | |
| 845 | ///\r | |
| 846 | UINT32 MCG_SER_P:1;\r | |
| 847 | UINT32 Reserved2:1;\r | |
| 848 | ///\r | |
| 849 | /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r | |
| 850 | /// firmware to be invoked when an error is detected so that it may\r | |
| 851 | /// provide additional platform specific information in an ACPI format\r | |
| 852 | /// "Generic Error Data Entry" that augments the data included in machine\r | |
| 853 | /// check bank registers. Introduced at Display Family / Display Model\r | |
| 854 | /// 06_3EH.\r | |
| 855 | ///\r | |
| 856 | UINT32 MCG_ELOG_P:1;\r | |
| 857 | ///\r | |
| 858 | /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r | |
| 859 | /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r | |
| 860 | /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r | |
| 861 | /// Display Model 06_3EH.\r | |
| 862 | ///\r | |
| 863 | UINT32 MCG_LMCE_P:1;\r | |
| 864 | UINT32 Reserved3:4;\r | |
| 865 | UINT32 Reserved4:32;\r | |
| 866 | } Bits;\r | |
| 867 | ///\r | |
| 868 | /// All bit fields as a 32-bit value\r | |
| 869 | ///\r | |
| 870 | UINT32 Uint32;\r | |
| 871 | ///\r | |
| 872 | /// All bit fields as a 64-bit value\r | |
| 873 | ///\r | |
| 874 | UINT64 Uint64;\r | |
| 875 | } MSR_IA32_MCG_CAP_REGISTER;\r | |
| 876 | \r | |
| 877 | \r | |
| 878 | /**\r | |
| 879 | Global Machine Check Status (R/W0). Introduced at Display Family / Display\r | |
| 880 | Model 06_01H.\r | |
| 881 | \r | |
| 882 | @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r | |
| 883 | @param EAX Lower 32-bits of MSR value.\r | |
| 884 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 885 | @param EDX Upper 32-bits of MSR value.\r | |
| 886 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 887 | \r | |
| 888 | <b>Example usage</b>\r | |
| 889 | @code\r | |
| 890 | MSR_IA32_MCG_STATUS_REGISTER Msr;\r | |
| 891 | \r | |
| 892 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r | |
| 893 | AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r | |
| 894 | @endcode\r | |
| 7de98828 | 895 | @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r |
| 04c980a6 MK |
896 | **/\r |
| 897 | #define MSR_IA32_MCG_STATUS 0x0000017A\r | |
| 898 | \r | |
| 899 | /**\r | |
| 900 | MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r | |
| 901 | **/\r | |
| 902 | typedef union {\r | |
| 903 | ///\r | |
| 904 | /// Individual bit fields\r | |
| 905 | ///\r | |
| 906 | struct {\r | |
| 907 | ///\r | |
| 908 | /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r | |
| 909 | /// Model 06_01H.\r | |
| 910 | ///\r | |
| 911 | UINT32 RIPV:1;\r | |
| 912 | ///\r | |
| 913 | /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r | |
| 914 | /// Model 06_01H.\r | |
| 915 | ///\r | |
| 916 | UINT32 EIPV:1;\r | |
| 917 | ///\r | |
| 918 | /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r | |
| 919 | /// / Display Model 06_01H.\r | |
| 920 | ///\r | |
| 921 | UINT32 MCIP:1;\r | |
| 922 | ///\r | |
| 923 | /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r | |
| 924 | ///\r | |
| 925 | UINT32 LMCE_S:1;\r | |
| 926 | UINT32 Reserved1:28;\r | |
| 927 | UINT32 Reserved2:32;\r | |
| 928 | } Bits;\r | |
| 929 | ///\r | |
| 930 | /// All bit fields as a 32-bit value\r | |
| 931 | ///\r | |
| 932 | UINT32 Uint32;\r | |
| 933 | ///\r | |
| 934 | /// All bit fields as a 64-bit value\r | |
| 935 | ///\r | |
| 936 | UINT64 Uint64;\r | |
| 937 | } MSR_IA32_MCG_STATUS_REGISTER;\r | |
| 938 | \r | |
| 939 | \r | |
| 940 | /**\r | |
| 941 | Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r | |
| 942 | \r | |
| 943 | @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r | |
| 944 | @param EAX Lower 32-bits of MSR value.\r | |
| 945 | @param EDX Upper 32-bits of MSR value.\r | |
| 946 | \r | |
| 947 | <b>Example usage</b>\r | |
| 948 | @code\r | |
| 949 | UINT64 Msr;\r | |
| 950 | \r | |
| 951 | Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r | |
| 952 | AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r | |
| 953 | @endcode\r | |
| 7de98828 | 954 | @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r |
| 04c980a6 MK |
955 | **/\r |
| 956 | #define MSR_IA32_MCG_CTL 0x0000017B\r | |
| 957 | \r | |
| 958 | \r | |
| 959 | /**\r | |
| 960 | Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r | |
| 961 | \r | |
| 962 | @param ECX MSR_IA32_PERFEVTSELn\r | |
| 963 | @param EAX Lower 32-bits of MSR value.\r | |
| 964 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 965 | @param EDX Upper 32-bits of MSR value.\r | |
| 966 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 967 | \r | |
| 968 | <b>Example usage</b>\r | |
| 969 | @code\r | |
| 970 | MSR_IA32_PERFEVTSEL_REGISTER Msr;\r | |
| 971 | \r | |
| 972 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r | |
| 973 | AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r | |
| 974 | @endcode\r | |
| 7de98828 JF |
975 | @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r |
| 976 | MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r | |
| 977 | MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r | |
| 978 | MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r | |
| 04c980a6 MK |
979 | @{\r |
| 980 | **/\r | |
| 981 | #define MSR_IA32_PERFEVTSEL0 0x00000186\r | |
| 982 | #define MSR_IA32_PERFEVTSEL1 0x00000187\r | |
| 983 | #define MSR_IA32_PERFEVTSEL2 0x00000188\r | |
| 984 | #define MSR_IA32_PERFEVTSEL3 0x00000189\r | |
| 985 | /// @}\r | |
| 986 | \r | |
| 987 | /**\r | |
| 988 | MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r | |
| 989 | #MSR_IA32_PERFEVTSEL3\r | |
| 990 | **/\r | |
| 991 | typedef union {\r | |
| 992 | ///\r | |
| 993 | /// Individual bit fields\r | |
| 994 | ///\r | |
| 995 | struct {\r | |
| 996 | ///\r | |
| 997 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 998 | ///\r | |
| 999 | UINT32 EventSelect:8;\r | |
| 1000 | ///\r | |
| 1001 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 1002 | /// detect on the selected event logic.\r | |
| 1003 | ///\r | |
| 1004 | UINT32 UMASK:8;\r | |
| 1005 | ///\r | |
| 1006 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 1007 | ///\r | |
| 1008 | UINT32 USR:1;\r | |
| 1009 | ///\r | |
| 1010 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 1011 | ///\r | |
| 1012 | UINT32 OS:1;\r | |
| 1013 | ///\r | |
| 1014 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 1015 | ///\r | |
| 1016 | UINT32 E:1;\r | |
| 1017 | ///\r | |
| 1018 | /// [Bit 19] PC: enables pin control.\r | |
| 1019 | ///\r | |
| 1020 | UINT32 PC:1;\r | |
| 1021 | ///\r | |
| 1022 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 1023 | ///\r | |
| 1024 | UINT32 INT:1;\r | |
| 1025 | ///\r | |
| 1026 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 1027 | /// event conditions occurring across all logical processors sharing a\r | |
| 1028 | /// processor core. When set to 0, the counter only increments the\r | |
| 1029 | /// associated event conditions occurring in the logical processor which\r | |
| 1030 | /// programmed the MSR.\r | |
| 1031 | ///\r | |
| 1032 | UINT32 ANY:1;\r | |
| 1033 | ///\r | |
| 1034 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 1035 | /// counting when this bit is set.\r | |
| 1036 | ///\r | |
| 1037 | UINT32 EN:1;\r | |
| 1038 | ///\r | |
| 1039 | /// [Bit 23] INV: invert the CMASK.\r | |
| 1040 | ///\r | |
| 1041 | UINT32 INV:1;\r | |
| 1042 | ///\r | |
| 1043 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 1044 | /// performance counter increments each cycle if the event count is\r | |
| 1045 | /// greater than or equal to the CMASK.\r | |
| 1046 | ///\r | |
| 1047 | UINT32 CMASK:8;\r | |
| 1048 | UINT32 Reserved:32;\r | |
| 1049 | } Bits;\r | |
| 1050 | ///\r | |
| 1051 | /// All bit fields as a 32-bit value\r | |
| 1052 | ///\r | |
| 1053 | UINT32 Uint32;\r | |
| 1054 | ///\r | |
| 1055 | /// All bit fields as a 64-bit value\r | |
| 1056 | ///\r | |
| 1057 | UINT64 Uint64;\r | |
| 1058 | } MSR_IA32_PERFEVTSEL_REGISTER;\r | |
| 1059 | \r | |
| 1060 | \r | |
| 1061 | /**\r | |
| 1062 | Current performance state(P-State) operating point (RO). Introduced at\r | |
| 1063 | Display Family / Display Model 0F_03H.\r | |
| 1064 | \r | |
| 1065 | @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r | |
| 1066 | @param EAX Lower 32-bits of MSR value.\r | |
| 1067 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1068 | @param EDX Upper 32-bits of MSR value.\r | |
| 1069 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1070 | \r | |
| 1071 | <b>Example usage</b>\r | |
| 1072 | @code\r | |
| 1073 | MSR_IA32_PERF_STATUS_REGISTER Msr;\r | |
| 1074 | \r | |
| 1075 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r | |
| 1076 | @endcode\r | |
| 7de98828 | 1077 | @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r |
| 04c980a6 MK |
1078 | **/\r |
| 1079 | #define MSR_IA32_PERF_STATUS 0x00000198\r | |
| 1080 | \r | |
| 1081 | /**\r | |
| 1082 | MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r | |
| 1083 | **/\r | |
| 1084 | typedef union {\r | |
| 1085 | ///\r | |
| 1086 | /// Individual bit fields\r | |
| 1087 | ///\r | |
| 1088 | struct {\r | |
| 1089 | ///\r | |
| 1090 | /// [Bits 15:0] Current performance State Value.\r | |
| 1091 | ///\r | |
| 1092 | UINT32 State:16;\r | |
| 1093 | UINT32 Reserved1:16;\r | |
| 1094 | UINT32 Reserved2:32;\r | |
| 1095 | } Bits;\r | |
| 1096 | ///\r | |
| 1097 | /// All bit fields as a 32-bit value\r | |
| 1098 | ///\r | |
| 1099 | UINT32 Uint32;\r | |
| 1100 | ///\r | |
| 1101 | /// All bit fields as a 64-bit value\r | |
| 1102 | ///\r | |
| 1103 | UINT64 Uint64;\r | |
| 1104 | } MSR_IA32_PERF_STATUS_REGISTER;\r | |
| 1105 | \r | |
| 1106 | \r | |
| 1107 | /**\r | |
| 1108 | (R/W). Introduced at Display Family / Display Model 0F_03H.\r | |
| 1109 | \r | |
| 1110 | @param ECX MSR_IA32_PERF_CTL (0x00000199)\r | |
| 1111 | @param EAX Lower 32-bits of MSR value.\r | |
| 1112 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1113 | @param EDX Upper 32-bits of MSR value.\r | |
| 1114 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1115 | \r | |
| 1116 | <b>Example usage</b>\r | |
| 1117 | @code\r | |
| 1118 | MSR_IA32_PERF_CTL_REGISTER Msr;\r | |
| 1119 | \r | |
| 1120 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r | |
| 1121 | AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r | |
| 1122 | @endcode\r | |
| 7de98828 | 1123 | @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r |
| 04c980a6 MK |
1124 | **/\r |
| 1125 | #define MSR_IA32_PERF_CTL 0x00000199\r | |
| 1126 | \r | |
| 1127 | /**\r | |
| 1128 | MSR information returned for MSR index #MSR_IA32_PERF_CTL\r | |
| 1129 | **/\r | |
| 1130 | typedef union {\r | |
| 1131 | ///\r | |
| 1132 | /// Individual bit fields\r | |
| 1133 | ///\r | |
| 1134 | struct {\r | |
| 1135 | ///\r | |
| 1136 | /// [Bits 15:0] Target performance State Value.\r | |
| 1137 | ///\r | |
| 1138 | UINT32 TargetState:16;\r | |
| 1139 | UINT32 Reserved1:16;\r | |
| 1140 | ///\r | |
| 1141 | /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r | |
| 1142 | /// (Mobile only).\r | |
| 1143 | ///\r | |
| 1144 | UINT32 IDA:1;\r | |
| 1145 | UINT32 Reserved2:31;\r | |
| 1146 | } Bits;\r | |
| 1147 | ///\r | |
| 1148 | /// All bit fields as a 64-bit value\r | |
| 1149 | ///\r | |
| 1150 | UINT64 Uint64;\r | |
| 1151 | } MSR_IA32_PERF_CTL_REGISTER;\r | |
| 1152 | \r | |
| 1153 | \r | |
| 1154 | /**\r | |
| 1155 | Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r | |
| 0f16be6d | 1156 | Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1157 | \r |
| 1158 | @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r | |
| 1159 | @param EAX Lower 32-bits of MSR value.\r | |
| 1160 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1161 | @param EDX Upper 32-bits of MSR value.\r | |
| 1162 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1163 | \r | |
| 1164 | <b>Example usage</b>\r | |
| 1165 | @code\r | |
| 1166 | MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r | |
| 1167 | \r | |
| 1168 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r | |
| 1169 | AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r | |
| 1170 | @endcode\r | |
| 7de98828 | 1171 | @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r |
| 04c980a6 MK |
1172 | **/\r |
| 1173 | #define MSR_IA32_CLOCK_MODULATION 0x0000019A\r | |
| 1174 | \r | |
| 1175 | /**\r | |
| 1176 | MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r | |
| 1177 | **/\r | |
| 1178 | typedef union {\r | |
| 1179 | ///\r | |
| 1180 | /// Individual bit fields\r | |
| 1181 | ///\r | |
| 1182 | struct {\r | |
| 1183 | ///\r | |
| 1184 | /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r | |
| 1185 | /// CPUID.06H:EAX[5] = 1.\r | |
| 1186 | ///\r | |
| 1187 | UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r | |
| 1188 | ///\r | |
| 1189 | /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r | |
| 0f16be6d | 1190 | /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1191 | ///\r |
| 1192 | UINT32 OnDemandClockModulationDutyCycle:3;\r | |
| 1193 | ///\r | |
| 1194 | /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r | |
| 0f16be6d | 1195 | /// If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1196 | ///\r |
| 1197 | UINT32 OnDemandClockModulationEnable:1;\r | |
| 1198 | UINT32 Reserved1:27;\r | |
| 1199 | UINT32 Reserved2:32;\r | |
| 1200 | } Bits;\r | |
| 1201 | ///\r | |
| 1202 | /// All bit fields as a 32-bit value\r | |
| 1203 | ///\r | |
| 1204 | UINT32 Uint32;\r | |
| 1205 | ///\r | |
| 1206 | /// All bit fields as a 64-bit value\r | |
| 1207 | ///\r | |
| 1208 | UINT64 Uint64;\r | |
| 1209 | } MSR_IA32_CLOCK_MODULATION_REGISTER;\r | |
| 1210 | \r | |
| 1211 | \r | |
| 1212 | /**\r | |
| 1213 | Thermal Interrupt Control (R/W) Enables and disables the generation of an\r | |
| 1214 | interrupt on temperature transitions detected with the processor's thermal\r | |
| 1215 | sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r | |
| 0f16be6d | 1216 | If CPUID.01H:EDX[22] = 1\r |
| 04c980a6 MK |
1217 | \r |
| 1218 | @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r | |
| 1219 | @param EAX Lower 32-bits of MSR value.\r | |
| 1220 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1221 | @param EDX Upper 32-bits of MSR value.\r | |
| 1222 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1223 | \r | |
| 1224 | <b>Example usage</b>\r | |
| 1225 | @code\r | |
| 1226 | MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1227 | \r | |
| 1228 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r | |
| 1229 | AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1230 | @endcode\r | |
| 7de98828 | 1231 | @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1232 | **/\r |
| 1233 | #define MSR_IA32_THERM_INTERRUPT 0x0000019B\r | |
| 1234 | \r | |
| 1235 | /**\r | |
| 1236 | MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r | |
| 1237 | **/\r | |
| 1238 | typedef union {\r | |
| 1239 | ///\r | |
| 1240 | /// Individual bit fields\r | |
| 1241 | ///\r | |
| 1242 | struct {\r | |
| 1243 | ///\r | |
| 0f16be6d | 1244 | /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1245 | ///\r |
| 1246 | UINT32 HighTempEnable:1;\r | |
| 1247 | ///\r | |
| 0f16be6d | 1248 | /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1249 | ///\r |
| 1250 | UINT32 LowTempEnable:1;\r | |
| 1251 | ///\r | |
| 0f16be6d | 1252 | /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1253 | ///\r |
| 1254 | UINT32 PROCHOT_Enable:1;\r | |
| 1255 | ///\r | |
| 0f16be6d | 1256 | /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1257 | ///\r |
| 1258 | UINT32 FORCEPR_Enable:1;\r | |
| 1259 | ///\r | |
| 1260 | /// [Bit 4] Critical Temperature Interrupt Enable.\r | |
| 0f16be6d | 1261 | /// If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1262 | ///\r |
| 1263 | UINT32 CriticalTempEnable:1;\r | |
| 1264 | UINT32 Reserved1:3;\r | |
| 1265 | ///\r | |
| 0f16be6d | 1266 | /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1267 | ///\r |
| 1268 | UINT32 Threshold1:7;\r | |
| 1269 | ///\r | |
| 0f16be6d | 1270 | /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1271 | ///\r |
| 1272 | UINT32 Threshold1Enable:1;\r | |
| 1273 | ///\r | |
| 0f16be6d | 1274 | /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1275 | ///\r |
| 1276 | UINT32 Threshold2:7;\r | |
| 1277 | ///\r | |
| 0f16be6d | 1278 | /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1279 | ///\r |
| 1280 | UINT32 Threshold2Enable:1;\r | |
| 1281 | ///\r | |
| 1282 | /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r | |
| 1283 | ///\r | |
| 1284 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1285 | UINT32 Reserved2:7;\r | |
| 1286 | UINT32 Reserved3:32;\r | |
| 1287 | } Bits;\r | |
| 1288 | ///\r | |
| 1289 | /// All bit fields as a 32-bit value\r | |
| 1290 | ///\r | |
| 1291 | UINT32 Uint32;\r | |
| 1292 | ///\r | |
| 1293 | /// All bit fields as a 64-bit value\r | |
| 1294 | ///\r | |
| 1295 | UINT64 Uint64;\r | |
| 1296 | } MSR_IA32_THERM_INTERRUPT_REGISTER;\r | |
| 1297 | \r | |
| 1298 | \r | |
| 1299 | /**\r | |
| 1300 | Thermal Status Information (RO) Contains status information about the\r | |
| 1301 | processor's thermal sensor and automatic thermal monitoring facilities. See\r | |
| 0f16be6d | 1302 | Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1303 | \r |
| 1304 | @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r | |
| 1305 | @param EAX Lower 32-bits of MSR value.\r | |
| 1306 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1307 | @param EDX Upper 32-bits of MSR value.\r | |
| 1308 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1309 | \r | |
| 1310 | <b>Example usage</b>\r | |
| 1311 | @code\r | |
| 1312 | MSR_IA32_THERM_STATUS_REGISTER Msr;\r | |
| 1313 | \r | |
| 1314 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r | |
| 1315 | @endcode\r | |
| 7de98828 | 1316 | @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1317 | **/\r |
| 1318 | #define MSR_IA32_THERM_STATUS 0x0000019C\r | |
| 1319 | \r | |
| 1320 | /**\r | |
| 1321 | MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r | |
| 1322 | **/\r | |
| 1323 | typedef union {\r | |
| 1324 | ///\r | |
| 1325 | /// Individual bit fields\r | |
| 1326 | ///\r | |
| 1327 | struct {\r | |
| 1328 | ///\r | |
| 0f16be6d | 1329 | /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1330 | ///\r |
| 1331 | UINT32 ThermalStatus:1;\r | |
| 1332 | ///\r | |
| 0f16be6d | 1333 | /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1334 | ///\r |
| 1335 | UINT32 ThermalStatusLog:1;\r | |
| 1336 | ///\r | |
| 0f16be6d | 1337 | /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1338 | ///\r |
| 1339 | UINT32 PROCHOT_FORCEPR_Event:1;\r | |
| 1340 | ///\r | |
| 0f16be6d | 1341 | /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1342 | ///\r |
| 1343 | UINT32 PROCHOT_FORCEPR_Log:1;\r | |
| 1344 | ///\r | |
| 0f16be6d | 1345 | /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1346 | ///\r |
| 1347 | UINT32 CriticalTempStatus:1;\r | |
| 1348 | ///\r | |
| 1349 | /// [Bit 5] Critical Temperature Status log (R/WC0).\r | |
| 0f16be6d | 1350 | /// If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1351 | ///\r |
| 1352 | UINT32 CriticalTempStatusLog:1;\r | |
| 1353 | ///\r | |
| 1354 | /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1355 | ///\r | |
| 1356 | UINT32 ThermalThreshold1Status:1;\r | |
| 1357 | ///\r | |
| 1358 | /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1359 | ///\r | |
| 1360 | UINT32 ThermalThreshold1Log:1;\r | |
| 1361 | ///\r | |
| 1362 | /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1363 | ///\r | |
| 1364 | UINT32 ThermalThreshold2Status:1;\r | |
| 1365 | ///\r | |
| 1366 | /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1367 | ///\r | |
| 1368 | UINT32 ThermalThreshold2Log:1;\r | |
| 1369 | ///\r | |
| 1370 | /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r | |
| 1371 | ///\r | |
| 1372 | UINT32 PowerLimitStatus:1;\r | |
| 1373 | ///\r | |
| 1374 | /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r | |
| 1375 | ///\r | |
| 1376 | UINT32 PowerLimitLog:1;\r | |
| 1377 | ///\r | |
| 1378 | /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1379 | ///\r | |
| 1380 | UINT32 CurrentLimitStatus:1;\r | |
| 1381 | ///\r | |
| 1382 | /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1383 | ///\r | |
| 1384 | UINT32 CurrentLimitLog:1;\r | |
| 1385 | ///\r | |
| 1386 | /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1387 | ///\r | |
| 1388 | UINT32 CrossDomainLimitStatus:1;\r | |
| 1389 | ///\r | |
| 1390 | /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1391 | ///\r | |
| 1392 | UINT32 CrossDomainLimitLog:1;\r | |
| 1393 | ///\r | |
| 1394 | /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1395 | ///\r | |
| 1396 | UINT32 DigitalReadout:7;\r | |
| 1397 | UINT32 Reserved1:4;\r | |
| 1398 | ///\r | |
| 1399 | /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r | |
| 1400 | /// 1.\r | |
| 1401 | ///\r | |
| 1402 | UINT32 ResolutionInDegreesCelsius:4;\r | |
| 1403 | ///\r | |
| 1404 | /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1405 | ///\r | |
| 1406 | UINT32 ReadingValid:1;\r | |
| 1407 | UINT32 Reserved2:32;\r | |
| 1408 | } Bits;\r | |
| 1409 | ///\r | |
| 1410 | /// All bit fields as a 32-bit value\r | |
| 1411 | ///\r | |
| 1412 | UINT32 Uint32;\r | |
| 1413 | ///\r | |
| 1414 | /// All bit fields as a 64-bit value\r | |
| 1415 | ///\r | |
| 1416 | UINT64 Uint64;\r | |
| 1417 | } MSR_IA32_THERM_STATUS_REGISTER;\r | |
| 1418 | \r | |
| 1419 | \r | |
| 1420 | /**\r | |
| 1421 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
| 1422 | functions to be enabled and disabled.\r | |
| 1423 | \r | |
| 1424 | @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r | |
| 1425 | @param EAX Lower 32-bits of MSR value.\r | |
| 1426 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1427 | @param EDX Upper 32-bits of MSR value.\r | |
| 1428 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1429 | \r | |
| 1430 | <b>Example usage</b>\r | |
| 1431 | @code\r | |
| 1432 | MSR_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 1433 | \r | |
| 1434 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r | |
| 1435 | AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 1436 | @endcode\r | |
| 7de98828 | 1437 | @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
| 04c980a6 MK |
1438 | **/\r |
| 1439 | #define MSR_IA32_MISC_ENABLE 0x000001A0\r | |
| 1440 | \r | |
| 1441 | /**\r | |
| 1442 | MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r | |
| 1443 | **/\r | |
| 1444 | typedef union {\r | |
| 1445 | ///\r | |
| 1446 | /// Individual bit fields\r | |
| 1447 | ///\r | |
| 1448 | struct {\r | |
| 1449 | ///\r | |
| 1450 | /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r | |
| 1451 | /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r | |
| 1452 | /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r | |
| 1453 | ///\r | |
| 1454 | UINT32 FastStrings:1;\r | |
| 1455 | UINT32 Reserved1:2;\r | |
| 1456 | ///\r | |
| 1457 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r | |
| 1458 | /// this bit enables the thermal control circuit (TCC) portion of the\r | |
| 1459 | /// Intel Thermal Monitor feature. This allows the processor to\r | |
| 1460 | /// automatically reduce power consumption in response to TCC activation.\r | |
| 1461 | /// 0 = Disabled. Note: In some products clearing this bit might be\r | |
| 1462 | /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r | |
| 0f16be6d HW |
1463 | /// thermal throttling will still be activated. The default value of this\r |
| 1464 | /// field varies with product. See respective tables where default value is\r | |
| 1465 | /// listed. Introduced at Display Family / Display Model 0F_0H.\r | |
| 04c980a6 MK |
1466 | ///\r |
| 1467 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 1468 | UINT32 Reserved2:3;\r | |
| 1469 | ///\r | |
| 1470 | /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r | |
| 1471 | /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r | |
| 1472 | /// Display Family / Display Model 0F_0H.\r | |
| 1473 | ///\r | |
| 1474 | UINT32 PerformanceMonitoring:1;\r | |
| 1475 | UINT32 Reserved3:3;\r | |
| 1476 | ///\r | |
| 1477 | /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r | |
| 1478 | /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r | |
| 1479 | /// Display Family / Display Model 0F_0H.\r | |
| 1480 | ///\r | |
| 1481 | UINT32 BTS:1;\r | |
| 1482 | ///\r | |
| 0f16be6d | 1483 | /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r |
| 04c980a6 MK |
1484 | /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r |
| 1485 | /// Family / Display Model 06_0FH.\r | |
| 1486 | ///\r | |
| 1487 | UINT32 PEBS:1;\r | |
| 1488 | UINT32 Reserved4:3;\r | |
| 1489 | ///\r | |
| 1490 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r | |
| 1491 | /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r | |
| 1492 | /// Technology enabled. If CPUID.01H: ECX[7] =1.\r | |
| 1493 | ///\r | |
| 1494 | UINT32 EIST:1;\r | |
| 1495 | UINT32 Reserved5:1;\r | |
| 1496 | ///\r | |
| 1497 | /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r | |
| 1498 | /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r | |
| 1499 | /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r | |
| 1500 | /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r | |
| 1501 | /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r | |
| 1502 | /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r | |
| 1503 | /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r | |
| 1504 | /// in the default state. Writing this bit when the SSE3 feature flag is\r | |
| 1505 | /// set to 0 may generate a #GP exception. Introduced at Display Family /\r | |
| 1506 | /// Display Model 0F_03H.\r | |
| 1507 | ///\r | |
| 1508 | UINT32 MONITOR:1;\r | |
| 1509 | UINT32 Reserved6:3;\r | |
| 1510 | ///\r | |
| 1511 | /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r | |
| 0f16be6d | 1512 | /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r |
| 04c980a6 | 1513 | /// question that allows users to specify when the installed OS does not\r |
| 0f16be6d | 1514 | /// support CPUID functions greater than 2. Before setting this bit, BIOS\r |
| 04c980a6 | 1515 | /// must execute the CPUID.0H and examine the maximum value returned in\r |
| 0f16be6d HW |
1516 | /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r |
| 1517 | /// supported. Otherwise, this bit is not supported. Setting this bit when\r | |
| 1518 | /// the maximum value is not greater than 2 may generate a #GP exception.\r | |
| 04c980a6 | 1519 | /// Setting this bit may cause unexpected behavior in software that\r |
| 0f16be6d | 1520 | /// depends on the availability of CPUID leaves greater than 2. Introduced\r |
| 04c980a6 MK |
1521 | /// at Display Family / Display Model 0F_03H.\r |
| 1522 | ///\r | |
| 1523 | UINT32 LimitCpuidMaxval:1;\r | |
| 1524 | ///\r | |
| 1525 | /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r | |
| 1526 | /// disabled. xTPR messages are optional messages that allow the processor\r | |
| 1527 | /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r | |
| 1528 | ///\r | |
| 1529 | UINT32 xTPR_Message_Disable:1;\r | |
| 1530 | UINT32 Reserved7:8;\r | |
| 1531 | UINT32 Reserved8:2;\r | |
| 1532 | ///\r | |
| 1533 | /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r | |
| 1534 | /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r | |
| 1535 | /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r | |
| 1536 | /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r | |
| 1537 | /// paging and take advantage of data only pages. BIOS must not alter the\r | |
| 1538 | /// contents of this bit location, if XD bit is not supported. Writing\r | |
| 1539 | /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r | |
| 1540 | /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r | |
| 1541 | ///\r | |
| 1542 | UINT32 XD:1;\r | |
| 1543 | UINT32 Reserved9:29;\r | |
| 1544 | } Bits;\r | |
| 1545 | ///\r | |
| 1546 | /// All bit fields as a 64-bit value\r | |
| 1547 | ///\r | |
| 1548 | UINT64 Uint64;\r | |
| 1549 | } MSR_IA32_MISC_ENABLE_REGISTER;\r | |
| 1550 | \r | |
| 1551 | \r | |
| 1552 | /**\r | |
| 1553 | Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r | |
| 1554 | \r | |
| 1555 | @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r | |
| 1556 | @param EAX Lower 32-bits of MSR value.\r | |
| 1557 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1558 | @param EDX Upper 32-bits of MSR value.\r | |
| 1559 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1560 | \r | |
| 1561 | <b>Example usage</b>\r | |
| 1562 | @code\r | |
| 1563 | MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r | |
| 1564 | \r | |
| 1565 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r | |
| 1566 | AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r | |
| 1567 | @endcode\r | |
| 7de98828 | 1568 | @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r |
| 04c980a6 MK |
1569 | **/\r |
| 1570 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r | |
| 1571 | \r | |
| 1572 | /**\r | |
| 1573 | MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r | |
| 1574 | **/\r | |
| 1575 | typedef union {\r | |
| 1576 | ///\r | |
| 1577 | /// Individual bit fields\r | |
| 1578 | ///\r | |
| 1579 | struct {\r | |
| 1580 | ///\r | |
| 1581 | /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r | |
| 1582 | /// performance. 15 indicates preference to maximize energy saving.\r | |
| 1583 | ///\r | |
| 1584 | UINT32 PowerPolicyPreference:4;\r | |
| 1585 | UINT32 Reserved1:28;\r | |
| 1586 | UINT32 Reserved2:32;\r | |
| 1587 | } Bits;\r | |
| 1588 | ///\r | |
| 1589 | /// All bit fields as a 32-bit value\r | |
| 1590 | ///\r | |
| 1591 | UINT32 Uint32;\r | |
| 1592 | ///\r | |
| 1593 | /// All bit fields as a 64-bit value\r | |
| 1594 | ///\r | |
| 1595 | UINT64 Uint64;\r | |
| 1596 | } MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r | |
| 1597 | \r | |
| 1598 | \r | |
| 1599 | /**\r | |
| 1600 | Package Thermal Status Information (RO) Contains status information about\r | |
| 1601 | the package's thermal sensor. See Section 14.8, "Package Level Thermal\r | |
| 1602 | Management.". If CPUID.06H: EAX[6] = 1.\r | |
| 1603 | \r | |
| 1604 | @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r | |
| 1605 | @param EAX Lower 32-bits of MSR value.\r | |
| 1606 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1607 | @param EDX Upper 32-bits of MSR value.\r | |
| 1608 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1609 | \r | |
| 1610 | <b>Example usage</b>\r | |
| 1611 | @code\r | |
| 1612 | MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r | |
| 1613 | \r | |
| 1614 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r | |
| 1615 | @endcode\r | |
| 7de98828 | 1616 | @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1617 | **/\r |
| 1618 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r | |
| 1619 | \r | |
| 1620 | /**\r | |
| 1621 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r | |
| 1622 | **/\r | |
| 1623 | typedef union {\r | |
| 1624 | ///\r | |
| 1625 | /// Individual bit fields\r | |
| 1626 | ///\r | |
| 1627 | struct {\r | |
| 1628 | ///\r | |
| 1629 | /// [Bit 0] Pkg Thermal Status (RO):.\r | |
| 1630 | ///\r | |
| 1631 | UINT32 ThermalStatus:1;\r | |
| 1632 | ///\r | |
| 1633 | /// [Bit 1] Pkg Thermal Status Log (R/W):.\r | |
| 1634 | ///\r | |
| 1635 | UINT32 ThermalStatusLog:1;\r | |
| 1636 | ///\r | |
| 1637 | /// [Bit 2] Pkg PROCHOT # event (RO).\r | |
| 1638 | ///\r | |
| 1639 | UINT32 PROCHOT_Event:1;\r | |
| 1640 | ///\r | |
| 1641 | /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r | |
| 1642 | ///\r | |
| 1643 | UINT32 PROCHOT_Log:1;\r | |
| 1644 | ///\r | |
| 1645 | /// [Bit 4] Pkg Critical Temperature Status (RO).\r | |
| 1646 | ///\r | |
| 1647 | UINT32 CriticalTempStatus:1;\r | |
| 1648 | ///\r | |
| 1649 | /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r | |
| 1650 | ///\r | |
| 1651 | UINT32 CriticalTempStatusLog:1;\r | |
| 1652 | ///\r | |
| 1653 | /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r | |
| 1654 | ///\r | |
| 1655 | UINT32 ThermalThreshold1Status:1;\r | |
| 1656 | ///\r | |
| 1657 | /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1658 | ///\r | |
| 1659 | UINT32 ThermalThreshold1Log:1;\r | |
| 1660 | ///\r | |
| 1661 | /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r | |
| 1662 | ///\r | |
| 1663 | UINT32 ThermalThreshold2Status:1;\r | |
| 1664 | ///\r | |
| 1665 | /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1666 | ///\r | |
| 1667 | UINT32 ThermalThreshold2Log:1;\r | |
| 1668 | ///\r | |
| 1669 | /// [Bit 10] Pkg Power Limitation Status (RO).\r | |
| 1670 | ///\r | |
| 1671 | UINT32 PowerLimitStatus:1;\r | |
| 1672 | ///\r | |
| 1673 | /// [Bit 11] Pkg Power Limitation log (R/WC0).\r | |
| 1674 | ///\r | |
| 1675 | UINT32 PowerLimitLog:1;\r | |
| 1676 | UINT32 Reserved1:4;\r | |
| 1677 | ///\r | |
| 1678 | /// [Bits 22:16] Pkg Digital Readout (RO).\r | |
| 1679 | ///\r | |
| 1680 | UINT32 DigitalReadout:7;\r | |
| 1681 | UINT32 Reserved2:9;\r | |
| 1682 | UINT32 Reserved3:32;\r | |
| 1683 | } Bits;\r | |
| 1684 | ///\r | |
| 1685 | /// All bit fields as a 32-bit value\r | |
| 1686 | ///\r | |
| 1687 | UINT32 Uint32;\r | |
| 1688 | ///\r | |
| 1689 | /// All bit fields as a 64-bit value\r | |
| 1690 | ///\r | |
| 1691 | UINT64 Uint64;\r | |
| 1692 | } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r | |
| 1693 | \r | |
| 1694 | \r | |
| 1695 | /**\r | |
| 1696 | Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r | |
| 1697 | an interrupt on temperature transitions detected with the package's thermal\r | |
| 1698 | sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r | |
| 1699 | EAX[6] = 1.\r | |
| 1700 | \r | |
| 1701 | @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r | |
| 1702 | @param EAX Lower 32-bits of MSR value.\r | |
| 1703 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1704 | @param EDX Upper 32-bits of MSR value.\r | |
| 1705 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1706 | \r | |
| 1707 | <b>Example usage</b>\r | |
| 1708 | @code\r | |
| 1709 | MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1710 | \r | |
| 1711 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r | |
| 1712 | AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1713 | @endcode\r | |
| 7de98828 | 1714 | @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1715 | **/\r |
| 1716 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r | |
| 1717 | \r | |
| 1718 | /**\r | |
| 1719 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r | |
| 1720 | **/\r | |
| 1721 | typedef union {\r | |
| 1722 | ///\r | |
| 1723 | /// Individual bit fields\r | |
| 1724 | ///\r | |
| 1725 | struct {\r | |
| 1726 | ///\r | |
| 1727 | /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r | |
| 1728 | ///\r | |
| 1729 | UINT32 HighTempEnable:1;\r | |
| 1730 | ///\r | |
| 1731 | /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r | |
| 1732 | ///\r | |
| 1733 | UINT32 LowTempEnable:1;\r | |
| 1734 | ///\r | |
| 1735 | /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r | |
| 1736 | ///\r | |
| 1737 | UINT32 PROCHOT_Enable:1;\r | |
| 1738 | UINT32 Reserved1:1;\r | |
| 1739 | ///\r | |
| 1740 | /// [Bit 4] Pkg Overheat Interrupt Enable.\r | |
| 1741 | ///\r | |
| 1742 | UINT32 OverheatEnable:1;\r | |
| 1743 | UINT32 Reserved2:3;\r | |
| 1744 | ///\r | |
| 1745 | /// [Bits 14:8] Pkg Threshold #1 Value.\r | |
| 1746 | ///\r | |
| 1747 | UINT32 Threshold1:7;\r | |
| 1748 | ///\r | |
| 1749 | /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r | |
| 1750 | ///\r | |
| 1751 | UINT32 Threshold1Enable:1;\r | |
| 1752 | ///\r | |
| 1753 | /// [Bits 22:16] Pkg Threshold #2 Value.\r | |
| 1754 | ///\r | |
| 1755 | UINT32 Threshold2:7;\r | |
| 1756 | ///\r | |
| 1757 | /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r | |
| 1758 | ///\r | |
| 1759 | UINT32 Threshold2Enable:1;\r | |
| 1760 | ///\r | |
| 1761 | /// [Bit 24] Pkg Power Limit Notification Enable.\r | |
| 1762 | ///\r | |
| 1763 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1764 | UINT32 Reserved3:7;\r | |
| 1765 | UINT32 Reserved4:32;\r | |
| 1766 | } Bits;\r | |
| 1767 | ///\r | |
| 1768 | /// All bit fields as a 32-bit value\r | |
| 1769 | ///\r | |
| 1770 | UINT32 Uint32;\r | |
| 1771 | ///\r | |
| 1772 | /// All bit fields as a 64-bit value\r | |
| 1773 | ///\r | |
| 1774 | UINT64 Uint64;\r | |
| 1775 | } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r | |
| 1776 | \r | |
| 1777 | \r | |
| 1778 | /**\r | |
| 1779 | Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r | |
| 1780 | Model 06_0EH.\r | |
| 1781 | \r | |
| 1782 | @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r | |
| 1783 | @param EAX Lower 32-bits of MSR value.\r | |
| 1784 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1785 | @param EDX Upper 32-bits of MSR value.\r | |
| 1786 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1787 | \r | |
| 1788 | <b>Example usage</b>\r | |
| 1789 | @code\r | |
| 1790 | MSR_IA32_DEBUGCTL_REGISTER Msr;\r | |
| 1791 | \r | |
| 1792 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r | |
| 1793 | AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r | |
| 1794 | @endcode\r | |
| 7de98828 | 1795 | @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r |
| 04c980a6 MK |
1796 | **/\r |
| 1797 | #define MSR_IA32_DEBUGCTL 0x000001D9\r | |
| 1798 | \r | |
| 1799 | /**\r | |
| 1800 | MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r | |
| 1801 | **/\r | |
| 1802 | typedef union {\r | |
| 1803 | ///\r | |
| 1804 | /// Individual bit fields\r | |
| 1805 | ///\r | |
| 1806 | struct {\r | |
| 1807 | ///\r | |
| 1808 | /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r | |
| 1809 | /// running trace of the most recent branches taken by the processor in\r | |
| 1810 | /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r | |
| 1811 | ///\r | |
| 1812 | UINT32 LBR:1;\r | |
| 1813 | ///\r | |
| 1814 | /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r | |
| 1815 | /// EFLAGS.TF as single-step on branches instead of single-step on\r | |
| 1816 | /// instructions. Introduced at Display Family / Display Model 06_01H.\r | |
| 1817 | ///\r | |
| 1818 | UINT32 BTF:1;\r | |
| 1819 | UINT32 Reserved1:4;\r | |
| 1820 | ///\r | |
| 1821 | /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r | |
| 1822 | /// sent. Introduced at Display Family / Display Model 06_0EH.\r | |
| 1823 | ///\r | |
| 1824 | UINT32 TR:1;\r | |
| 1825 | ///\r | |
| 1826 | /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r | |
| 1827 | /// be logged in a BTS buffer. Introduced at Display Family / Display\r | |
| 1828 | /// Model 06_0EH.\r | |
| 1829 | ///\r | |
| 1830 | UINT32 BTS:1;\r | |
| 1831 | ///\r | |
| 1832 | /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r | |
| 1833 | /// fashion. When this bit is set, an interrupt is generated by the BTS\r | |
| 1834 | /// facility when the BTS buffer is full. Introduced at Display Family /\r | |
| 1835 | /// Display Model 06_0EH.\r | |
| 1836 | ///\r | |
| 1837 | UINT32 BTINT:1;\r | |
| 1838 | ///\r | |
| 1839 | /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r | |
| 1840 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1841 | ///\r | |
| 1842 | UINT32 BTS_OFF_OS:1;\r | |
| 1843 | ///\r | |
| 1844 | /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r | |
| 1845 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1846 | ///\r | |
| 1847 | UINT32 BTS_OFF_USR:1;\r | |
| 1848 | ///\r | |
| 1849 | /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r | |
| 1850 | /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1851 | ///\r | |
| 1852 | UINT32 FREEZE_LBRS_ON_PMI:1;\r | |
| 1853 | ///\r | |
| 1854 | /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r | |
| 1855 | /// global counter control MSR are frozen (address 38FH) on a PMI request.\r | |
| 1856 | /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1857 | ///\r | |
| 1858 | UINT32 FREEZE_PERFMON_ON_PMI:1;\r | |
| 1859 | ///\r | |
| 1860 | /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r | |
| 1861 | /// receive and generate PMI on behalf of the uncore. Introduced at\r | |
| 1862 | /// Display Family / Display Model 06_1AH.\r | |
| 1863 | ///\r | |
| 1864 | UINT32 ENABLE_UNCORE_PMI:1;\r | |
| 1865 | ///\r | |
| 1866 | /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r | |
| 1867 | /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r | |
| 1868 | ///\r | |
| 1869 | UINT32 FREEZE_WHILE_SMM:1;\r | |
| 1870 | ///\r | |
| 1871 | /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r | |
| 1872 | /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r | |
| 1873 | ///\r | |
| 1874 | UINT32 RTM_DEBUG:1;\r | |
| 1875 | UINT32 Reserved2:16;\r | |
| 1876 | UINT32 Reserved3:32;\r | |
| 1877 | } Bits;\r | |
| 1878 | ///\r | |
| 1879 | /// All bit fields as a 32-bit value\r | |
| 1880 | ///\r | |
| 1881 | UINT32 Uint32;\r | |
| 1882 | ///\r | |
| 1883 | /// All bit fields as a 64-bit value\r | |
| 1884 | ///\r | |
| 1885 | UINT64 Uint64;\r | |
| 1886 | } MSR_IA32_DEBUGCTL_REGISTER;\r | |
| 1887 | \r | |
| 1888 | \r | |
| 1889 | /**\r | |
| 1890 | SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r | |
| 1891 | If IA32_MTRRCAP.SMRR[11] = 1.\r | |
| 1892 | \r | |
| 1893 | @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r | |
| 1894 | @param EAX Lower 32-bits of MSR value.\r | |
| 1895 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1896 | @param EDX Upper 32-bits of MSR value.\r | |
| 1897 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1898 | \r | |
| 1899 | <b>Example usage</b>\r | |
| 1900 | @code\r | |
| 1901 | MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r | |
| 1902 | \r | |
| 1903 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r | |
| 1904 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r | |
| 1905 | @endcode\r | |
| 7de98828 | 1906 | @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r |
| 04c980a6 MK |
1907 | **/\r |
| 1908 | #define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r | |
| 1909 | \r | |
| 1910 | /**\r | |
| 1911 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r | |
| 1912 | **/\r | |
| 1913 | typedef union {\r | |
| 1914 | ///\r | |
| 1915 | /// Individual bit fields\r | |
| 1916 | ///\r | |
| 1917 | struct {\r | |
| 1918 | ///\r | |
| 1919 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 1920 | ///\r | |
| 1921 | UINT32 Type:8;\r | |
| 1922 | UINT32 Reserved1:4;\r | |
| 1923 | ///\r | |
| 1924 | /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r | |
| 1925 | ///\r | |
| 1926 | UINT32 PhysBase:20;\r | |
| 1927 | UINT32 Reserved2:32;\r | |
| 1928 | } Bits;\r | |
| 1929 | ///\r | |
| 1930 | /// All bit fields as a 32-bit value\r | |
| 1931 | ///\r | |
| 1932 | UINT32 Uint32;\r | |
| 1933 | ///\r | |
| 1934 | /// All bit fields as a 64-bit value\r | |
| 1935 | ///\r | |
| 1936 | UINT64 Uint64;\r | |
| 1937 | } MSR_IA32_SMRR_PHYSBASE_REGISTER;\r | |
| 1938 | \r | |
| 1939 | \r | |
| 1940 | /**\r | |
| ba1a2d11 | 1941 | SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If\r |
| 04c980a6 MK |
1942 | IA32_MTRRCAP[SMRR] = 1.\r |
| 1943 | \r | |
| 1944 | @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r | |
| 1945 | @param EAX Lower 32-bits of MSR value.\r | |
| 1946 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1947 | @param EDX Upper 32-bits of MSR value.\r | |
| 1948 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1949 | \r | |
| 1950 | <b>Example usage</b>\r | |
| 1951 | @code\r | |
| 1952 | MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r | |
| 1953 | \r | |
| 1954 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r | |
| 1955 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r | |
| 1956 | @endcode\r | |
| 7de98828 | 1957 | @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r |
| 04c980a6 MK |
1958 | **/\r |
| 1959 | #define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r | |
| 1960 | \r | |
| 1961 | /**\r | |
| 1962 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r | |
| 1963 | **/\r | |
| 1964 | typedef union {\r | |
| 1965 | ///\r | |
| 1966 | /// Individual bit fields\r | |
| 1967 | ///\r | |
| 1968 | struct {\r | |
| 1969 | UINT32 Reserved1:11;\r | |
| 1970 | ///\r | |
| 1971 | /// [Bit 11] Valid Enable range mask.\r | |
| 1972 | ///\r | |
| 1973 | UINT32 Valid:1;\r | |
| 1974 | ///\r | |
| 1975 | /// [Bits 31:12] PhysMask SMRR address range mask.\r | |
| 1976 | ///\r | |
| 1977 | UINT32 PhysMask:20;\r | |
| 1978 | UINT32 Reserved2:32;\r | |
| 1979 | } Bits;\r | |
| 1980 | ///\r | |
| 1981 | /// All bit fields as a 32-bit value\r | |
| 1982 | ///\r | |
| 1983 | UINT32 Uint32;\r | |
| 1984 | ///\r | |
| 1985 | /// All bit fields as a 64-bit value\r | |
| 1986 | ///\r | |
| 1987 | UINT64 Uint64;\r | |
| 1988 | } MSR_IA32_SMRR_PHYSMASK_REGISTER;\r | |
| 1989 | \r | |
| 1990 | \r | |
| 1991 | /**\r | |
| 1992 | DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r | |
| 1993 | \r | |
| 1994 | @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r | |
| 1995 | @param EAX Lower 32-bits of MSR value.\r | |
| 1996 | @param EDX Upper 32-bits of MSR value.\r | |
| 1997 | \r | |
| 1998 | <b>Example usage</b>\r | |
| 1999 | @code\r | |
| 2000 | UINT64 Msr;\r | |
| 2001 | \r | |
| 2002 | Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r | |
| 2003 | @endcode\r | |
| 7de98828 | 2004 | @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r |
| 04c980a6 MK |
2005 | **/\r |
| 2006 | #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r | |
| 2007 | \r | |
| 2008 | \r | |
| 2009 | /**\r | |
| 2010 | If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r | |
| 2011 | \r | |
| 2012 | @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r | |
| 2013 | @param EAX Lower 32-bits of MSR value.\r | |
| 2014 | @param EDX Upper 32-bits of MSR value.\r | |
| 2015 | \r | |
| 2016 | <b>Example usage</b>\r | |
| 2017 | @code\r | |
| 2018 | UINT64 Msr;\r | |
| 2019 | \r | |
| 2020 | Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r | |
| 2021 | AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r | |
| 2022 | @endcode\r | |
| 7de98828 | 2023 | @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r |
| 04c980a6 MK |
2024 | **/\r |
| 2025 | #define MSR_IA32_CPU_DCA_CAP 0x000001F9\r | |
| 2026 | \r | |
| 2027 | \r | |
| 2028 | /**\r | |
| 2029 | DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r | |
| 2030 | \r | |
| 2031 | @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r | |
| 2032 | @param EAX Lower 32-bits of MSR value.\r | |
| 2033 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 2034 | @param EDX Upper 32-bits of MSR value.\r | |
| 2035 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 2036 | \r | |
| 2037 | <b>Example usage</b>\r | |
| 2038 | @code\r | |
| 2039 | MSR_IA32_DCA_0_CAP_REGISTER Msr;\r | |
| 2040 | \r | |
| 2041 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r | |
| 2042 | AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r | |
| 2043 | @endcode\r | |
| 7de98828 | 2044 | @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r |
| 04c980a6 MK |
2045 | **/\r |
| 2046 | #define MSR_IA32_DCA_0_CAP 0x000001FA\r | |
| 2047 | \r | |
| 2048 | /**\r | |
| 2049 | MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r | |
| 2050 | **/\r | |
| 2051 | typedef union {\r | |
| 2052 | ///\r | |
| 2053 | /// Individual bit fields\r | |
| 2054 | ///\r | |
| 2055 | struct {\r | |
| 2056 | ///\r | |
| 2057 | /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r | |
| 2058 | /// defeatures are set.\r | |
| 2059 | ///\r | |
| 2060 | UINT32 DCA_ACTIVE:1;\r | |
| 2061 | ///\r | |
| 2062 | /// [Bits 2:1] TRANSACTION.\r | |
| 2063 | ///\r | |
| 2064 | UINT32 TRANSACTION:2;\r | |
| 2065 | ///\r | |
| 2066 | /// [Bits 6:3] DCA_TYPE.\r | |
| 2067 | ///\r | |
| 2068 | UINT32 DCA_TYPE:4;\r | |
| 2069 | ///\r | |
| 2070 | /// [Bits 10:7] DCA_QUEUE_SIZE.\r | |
| 2071 | ///\r | |
| 2072 | UINT32 DCA_QUEUE_SIZE:4;\r | |
| 2073 | UINT32 Reserved1:2;\r | |
| 2074 | ///\r | |
| 2075 | /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r | |
| 2076 | /// side-effect.\r | |
| 2077 | ///\r | |
| 2078 | UINT32 DCA_DELAY:4;\r | |
| 2079 | UINT32 Reserved2:7;\r | |
| 2080 | ///\r | |
| 2081 | /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r | |
| 2082 | ///\r | |
| 2083 | UINT32 SW_BLOCK:1;\r | |
| 2084 | UINT32 Reserved3:1;\r | |
| 2085 | ///\r | |
| 2086 | /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r | |
| 2087 | ///\r | |
| 2088 | UINT32 HW_BLOCK:1;\r | |
| 2089 | UINT32 Reserved4:5;\r | |
| 2090 | UINT32 Reserved5:32;\r | |
| 2091 | } Bits;\r | |
| 2092 | ///\r | |
| 2093 | /// All bit fields as a 32-bit value\r | |
| 2094 | ///\r | |
| 2095 | UINT32 Uint32;\r | |
| 2096 | ///\r | |
| 2097 | /// All bit fields as a 64-bit value\r | |
| 2098 | ///\r | |
| 2099 | UINT64 Uint64;\r | |
| 2100 | } MSR_IA32_DCA_0_CAP_REGISTER;\r | |
| 2101 | \r | |
| 2102 | \r | |
| 2103 | /**\r | |
| 2104 | MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2105 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2106 | \r | |
| 2107 | @param ECX MSR_IA32_MTRR_PHYSBASEn\r | |
| 2108 | @param EAX Lower 32-bits of MSR value.\r | |
| 2109 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2110 | @param EDX Upper 32-bits of MSR value.\r | |
| 2111 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2112 | \r | |
| 2113 | <b>Example usage</b>\r | |
| 2114 | @code\r | |
| 2115 | MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r | |
| 2116 | \r | |
| 2117 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r | |
| 2118 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r | |
| 2119 | @endcode\r | |
| 7de98828 JF |
2120 | @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r |
| 2121 | MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r | |
| 2122 | MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r | |
| 2123 | MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r | |
| 2124 | MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r | |
| 2125 | MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r | |
| 2126 | MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r | |
| 2127 | MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r | |
| 2128 | MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r | |
| 2129 | MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r | |
| 04c980a6 MK |
2130 | @{\r |
| 2131 | **/\r | |
| 2132 | #define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r | |
| 2133 | #define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r | |
| 2134 | #define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r | |
| 2135 | #define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r | |
| 2136 | #define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r | |
| 2137 | #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r | |
| 2138 | #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r | |
| 2139 | #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r | |
| 2140 | #define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r | |
| 2141 | #define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r | |
| 2142 | /// @}\r | |
| 2143 | \r | |
| 2144 | /**\r | |
| 2145 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r | |
| 2146 | #MSR_IA32_MTRR_PHYSBASE9\r | |
| 2147 | **/\r | |
| 2148 | typedef union {\r | |
| 2149 | ///\r | |
| 2150 | /// Individual bit fields\r | |
| 2151 | ///\r | |
| 2152 | struct {\r | |
| 2153 | ///\r | |
| 2154 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 2155 | ///\r | |
| 2156 | UINT32 Type:8;\r | |
| 2157 | UINT32 Reserved1:4;\r | |
| 2158 | ///\r | |
| 2159 | /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r | |
| 2160 | ///\r | |
| 2161 | UINT32 PhysBase:20;\r | |
| 2162 | ///\r | |
| 2163 | /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r | |
| 2164 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2165 | /// maximum physical address range supported by the processor. It is\r | |
| 2166 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2167 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2168 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2169 | ///\r | |
| 2170 | UINT32 PhysBaseHi:32;\r | |
| 2171 | } Bits;\r | |
| 2172 | ///\r | |
| 2173 | /// All bit fields as a 64-bit value\r | |
| 2174 | ///\r | |
| 2175 | UINT64 Uint64;\r | |
| 2176 | } MSR_IA32_MTRR_PHYSBASE_REGISTER;\r | |
| 2177 | \r | |
| 2178 | \r | |
| 2179 | /**\r | |
| 2180 | MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2181 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2182 | \r | |
| 2183 | @param ECX MSR_IA32_MTRR_PHYSMASKn\r | |
| 2184 | @param EAX Lower 32-bits of MSR value.\r | |
| 2185 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2186 | @param EDX Upper 32-bits of MSR value.\r | |
| 2187 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2188 | \r | |
| 2189 | <b>Example usage</b>\r | |
| 2190 | @code\r | |
| 2191 | MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r | |
| 2192 | \r | |
| 2193 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r | |
| 2194 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r | |
| 2195 | @endcode\r | |
| 7de98828 JF |
2196 | @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r |
| 2197 | MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r | |
| 2198 | MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r | |
| 2199 | MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r | |
| 2200 | MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r | |
| 2201 | MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r | |
| 2202 | MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r | |
| 2203 | MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r | |
| 2204 | MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r | |
| 2205 | MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r | |
| 04c980a6 MK |
2206 | @{\r |
| 2207 | **/\r | |
| 2208 | #define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r | |
| 2209 | #define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r | |
| 2210 | #define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r | |
| 2211 | #define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r | |
| 2212 | #define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r | |
| 2213 | #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r | |
| 2214 | #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r | |
| 2215 | #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r | |
| 2216 | #define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r | |
| 2217 | #define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r | |
| 2218 | /// @}\r | |
| 2219 | \r | |
| 2220 | /**\r | |
| 2221 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r | |
| 2222 | #MSR_IA32_MTRR_PHYSMASK9\r | |
| 2223 | **/\r | |
| 2224 | typedef union {\r | |
| 2225 | ///\r | |
| 2226 | /// Individual bit fields\r | |
| 2227 | ///\r | |
| 2228 | struct {\r | |
| 2229 | UINT32 Reserved1:11;\r | |
| 2230 | ///\r | |
| 2231 | /// [Bit 11] Valid Enable range mask.\r | |
| 2232 | ///\r | |
| 490b048b | 2233 | UINT32 V:1;\r |
| 04c980a6 MK |
2234 | ///\r |
| 2235 | /// [Bits 31:12] PhysMask. MTRR address range mask.\r | |
| 2236 | ///\r | |
| 2237 | UINT32 PhysMask:20;\r | |
| 2238 | ///\r | |
| 2239 | /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r | |
| 2240 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2241 | /// maximum physical address range supported by the processor. It is\r | |
| 2242 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2243 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2244 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2245 | ///\r | |
| 2246 | UINT32 PhysMaskHi:32;\r | |
| 2247 | } Bits;\r | |
| 2248 | ///\r | |
| 2249 | /// All bit fields as a 64-bit value\r | |
| 2250 | ///\r | |
| 2251 | UINT64 Uint64;\r | |
| 2252 | } MSR_IA32_MTRR_PHYSMASK_REGISTER;\r | |
| 2253 | \r | |
| 2254 | \r | |
| 2255 | /**\r | |
| 2256 | MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2257 | \r | |
| 2258 | @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r | |
| 2259 | @param EAX Lower 32-bits of MSR value.\r | |
| 2260 | @param EDX Upper 32-bits of MSR value.\r | |
| 2261 | \r | |
| 2262 | <b>Example usage</b>\r | |
| 2263 | @code\r | |
| 2264 | UINT64 Msr;\r | |
| 2265 | \r | |
| 2266 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r | |
| 2267 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r | |
| 2268 | @endcode\r | |
| 7de98828 | 2269 | @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r |
| 04c980a6 MK |
2270 | **/\r |
| 2271 | #define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r | |
| 2272 | \r | |
| 2273 | \r | |
| 2274 | /**\r | |
| 2275 | MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2276 | \r | |
| 2277 | @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r | |
| 2278 | @param EAX Lower 32-bits of MSR value.\r | |
| 2279 | @param EDX Upper 32-bits of MSR value.\r | |
| 2280 | \r | |
| 2281 | <b>Example usage</b>\r | |
| 2282 | @code\r | |
| 2283 | UINT64 Msr;\r | |
| 2284 | \r | |
| 2285 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r | |
| 2286 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r | |
| 2287 | @endcode\r | |
| 7de98828 | 2288 | @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r |
| 04c980a6 MK |
2289 | **/\r |
| 2290 | #define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r | |
| 2291 | \r | |
| 2292 | \r | |
| 2293 | /**\r | |
| 2294 | MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2295 | \r | |
| 2296 | @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r | |
| 2297 | @param EAX Lower 32-bits of MSR value.\r | |
| 2298 | @param EDX Upper 32-bits of MSR value.\r | |
| 2299 | \r | |
| 2300 | <b>Example usage</b>\r | |
| 2301 | @code\r | |
| 2302 | UINT64 Msr;\r | |
| 2303 | \r | |
| 2304 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r | |
| 2305 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r | |
| 2306 | @endcode\r | |
| 7de98828 | 2307 | @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r |
| 04c980a6 MK |
2308 | **/\r |
| 2309 | #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r | |
| 2310 | \r | |
| 2311 | \r | |
| 2312 | /**\r | |
| 2313 | See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2314 | \r | |
| 2315 | @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r | |
| 2316 | @param EAX Lower 32-bits of MSR value.\r | |
| 2317 | @param EDX Upper 32-bits of MSR value.\r | |
| 2318 | \r | |
| 2319 | <b>Example usage</b>\r | |
| 2320 | @code\r | |
| 2321 | UINT64 Msr;\r | |
| 2322 | \r | |
| 2323 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r | |
| 2324 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r | |
| 2325 | @endcode\r | |
| 7de98828 | 2326 | @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r |
| 04c980a6 MK |
2327 | **/\r |
| 2328 | #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r | |
| 2329 | \r | |
| 2330 | \r | |
| 2331 | /**\r | |
| 2332 | MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2333 | \r | |
| 2334 | @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r | |
| 2335 | @param EAX Lower 32-bits of MSR value.\r | |
| 2336 | @param EDX Upper 32-bits of MSR value.\r | |
| 2337 | \r | |
| 2338 | <b>Example usage</b>\r | |
| 2339 | @code\r | |
| 2340 | UINT64 Msr;\r | |
| 2341 | \r | |
| 2342 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r | |
| 2343 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r | |
| 2344 | @endcode\r | |
| 7de98828 | 2345 | @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r |
| 04c980a6 MK |
2346 | **/\r |
| 2347 | #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r | |
| 2348 | \r | |
| 2349 | \r | |
| 2350 | /**\r | |
| 2351 | MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2352 | \r | |
| 2353 | @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r | |
| 2354 | @param EAX Lower 32-bits of MSR value.\r | |
| 2355 | @param EDX Upper 32-bits of MSR value.\r | |
| 2356 | \r | |
| 2357 | <b>Example usage</b>\r | |
| 2358 | @code\r | |
| 2359 | UINT64 Msr;\r | |
| 2360 | \r | |
| 2361 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r | |
| 2362 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r | |
| 2363 | @endcode\r | |
| 7de98828 | 2364 | @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r |
| 04c980a6 MK |
2365 | **/\r |
| 2366 | #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r | |
| 2367 | \r | |
| 2368 | \r | |
| 2369 | /**\r | |
| 2370 | MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2371 | \r | |
| 2372 | @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r | |
| 2373 | @param EAX Lower 32-bits of MSR value.\r | |
| 2374 | @param EDX Upper 32-bits of MSR value.\r | |
| 2375 | \r | |
| 2376 | <b>Example usage</b>\r | |
| 2377 | @code\r | |
| 2378 | UINT64 Msr;\r | |
| 2379 | \r | |
| 2380 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r | |
| 2381 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r | |
| 2382 | @endcode\r | |
| 7de98828 | 2383 | @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r |
| 04c980a6 MK |
2384 | **/\r |
| 2385 | #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r | |
| 2386 | \r | |
| 2387 | \r | |
| 2388 | /**\r | |
| 2389 | MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2390 | \r | |
| 2391 | @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r | |
| 2392 | @param EAX Lower 32-bits of MSR value.\r | |
| 2393 | @param EDX Upper 32-bits of MSR value.\r | |
| 2394 | \r | |
| 2395 | <b>Example usage</b>\r | |
| 2396 | @code\r | |
| 2397 | UINT64 Msr;\r | |
| 2398 | \r | |
| 2399 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r | |
| 2400 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r | |
| 2401 | @endcode\r | |
| 7de98828 | 2402 | @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r |
| 04c980a6 MK |
2403 | **/\r |
| 2404 | #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r | |
| 2405 | \r | |
| 2406 | \r | |
| 2407 | /**\r | |
| 2408 | MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2409 | \r | |
| 2410 | @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r | |
| 2411 | @param EAX Lower 32-bits of MSR value.\r | |
| 2412 | @param EDX Upper 32-bits of MSR value.\r | |
| 2413 | \r | |
| 2414 | <b>Example usage</b>\r | |
| 2415 | @code\r | |
| 2416 | UINT64 Msr;\r | |
| 2417 | \r | |
| 2418 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r | |
| 2419 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r | |
| 2420 | @endcode\r | |
| 7de98828 | 2421 | @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r |
| 04c980a6 MK |
2422 | **/\r |
| 2423 | #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r | |
| 2424 | \r | |
| 2425 | \r | |
| 2426 | /**\r | |
| 2427 | MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2428 | \r | |
| 2429 | @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r | |
| 2430 | @param EAX Lower 32-bits of MSR value.\r | |
| 2431 | @param EDX Upper 32-bits of MSR value.\r | |
| 2432 | \r | |
| 2433 | <b>Example usage</b>\r | |
| 2434 | @code\r | |
| 2435 | UINT64 Msr;\r | |
| 2436 | \r | |
| 2437 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r | |
| 2438 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r | |
| 2439 | @endcode\r | |
| 7de98828 | 2440 | @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r |
| 04c980a6 MK |
2441 | **/\r |
| 2442 | #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r | |
| 2443 | \r | |
| 2444 | \r | |
| 2445 | /**\r | |
| 2446 | MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2447 | \r | |
| 2448 | @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r | |
| 2449 | @param EAX Lower 32-bits of MSR value.\r | |
| 2450 | @param EDX Upper 32-bits of MSR value.\r | |
| 2451 | \r | |
| 2452 | <b>Example usage</b>\r | |
| 2453 | @code\r | |
| 2454 | UINT64 Msr;\r | |
| 2455 | \r | |
| 2456 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r | |
| 2457 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r | |
| 2458 | @endcode\r | |
| 7de98828 | 2459 | @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r |
| 04c980a6 MK |
2460 | **/\r |
| 2461 | #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r | |
| 2462 | \r | |
| 2463 | \r | |
| 2464 | /**\r | |
| 2465 | IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r | |
| 2466 | \r | |
| 2467 | @param ECX MSR_IA32_PAT (0x00000277)\r | |
| 2468 | @param EAX Lower 32-bits of MSR value.\r | |
| 2469 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2470 | @param EDX Upper 32-bits of MSR value.\r | |
| 2471 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2472 | \r | |
| 2473 | <b>Example usage</b>\r | |
| 2474 | @code\r | |
| 2475 | MSR_IA32_PAT_REGISTER Msr;\r | |
| 2476 | \r | |
| 2477 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r | |
| 2478 | AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r | |
| 2479 | @endcode\r | |
| 7de98828 | 2480 | @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r |
| 04c980a6 MK |
2481 | **/\r |
| 2482 | #define MSR_IA32_PAT 0x00000277\r | |
| 2483 | \r | |
| 2484 | /**\r | |
| 2485 | MSR information returned for MSR index #MSR_IA32_PAT\r | |
| 2486 | **/\r | |
| 2487 | typedef union {\r | |
| 2488 | ///\r | |
| 2489 | /// Individual bit fields\r | |
| 2490 | ///\r | |
| 2491 | struct {\r | |
| 2492 | ///\r | |
| 2493 | /// [Bits 2:0] PA0.\r | |
| 2494 | ///\r | |
| 2495 | UINT32 PA0:3;\r | |
| 2496 | UINT32 Reserved1:5;\r | |
| 2497 | ///\r | |
| 2498 | /// [Bits 10:8] PA1.\r | |
| 2499 | ///\r | |
| 2500 | UINT32 PA1:3;\r | |
| 2501 | UINT32 Reserved2:5;\r | |
| 2502 | ///\r | |
| 2503 | /// [Bits 18:16] PA2.\r | |
| 2504 | ///\r | |
| 2505 | UINT32 PA2:3;\r | |
| 2506 | UINT32 Reserved3:5;\r | |
| 2507 | ///\r | |
| 2508 | /// [Bits 26:24] PA3.\r | |
| 2509 | ///\r | |
| 2510 | UINT32 PA3:3;\r | |
| 2511 | UINT32 Reserved4:5;\r | |
| 2512 | ///\r | |
| 2513 | /// [Bits 34:32] PA4.\r | |
| 2514 | ///\r | |
| 2515 | UINT32 PA4:3;\r | |
| 2516 | UINT32 Reserved5:5;\r | |
| 2517 | ///\r | |
| 2518 | /// [Bits 42:40] PA5.\r | |
| 2519 | ///\r | |
| 2520 | UINT32 PA5:3;\r | |
| 2521 | UINT32 Reserved6:5;\r | |
| 2522 | ///\r | |
| 2523 | /// [Bits 50:48] PA6.\r | |
| 2524 | ///\r | |
| 2525 | UINT32 PA6:3;\r | |
| 2526 | UINT32 Reserved7:5;\r | |
| 2527 | ///\r | |
| 2528 | /// [Bits 58:56] PA7.\r | |
| 2529 | ///\r | |
| 2530 | UINT32 PA7:3;\r | |
| 2531 | UINT32 Reserved8:5;\r | |
| 2532 | } Bits;\r | |
| 2533 | ///\r | |
| 2534 | /// All bit fields as a 64-bit value\r | |
| 2535 | ///\r | |
| 2536 | UINT64 Uint64;\r | |
| 2537 | } MSR_IA32_PAT_REGISTER;\r | |
| 2538 | \r | |
| 2539 | \r | |
| 2540 | /**\r | |
| 2541 | Provides the programming interface to use corrected MC error signaling\r | |
| 2542 | capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r | |
| 2543 | \r | |
| 2544 | @param ECX MSR_IA32_MCn_CTL2\r | |
| 2545 | @param EAX Lower 32-bits of MSR value.\r | |
| 2546 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2547 | @param EDX Upper 32-bits of MSR value.\r | |
| 2548 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2549 | \r | |
| 2550 | <b>Example usage</b>\r | |
| 2551 | @code\r | |
| 2552 | MSR_IA32_MC_CTL2_REGISTER Msr;\r | |
| 2553 | \r | |
| 2554 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r | |
| 2555 | AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r | |
| 2556 | @endcode\r | |
| 7de98828 JF |
2557 | @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r |
| 2558 | MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r | |
| 2559 | MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r | |
| 2560 | MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r | |
| 2561 | MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r | |
| 2562 | MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r | |
| 2563 | MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r | |
| 2564 | MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r | |
| 2565 | MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r | |
| 2566 | MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r | |
| 2567 | MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r | |
| 2568 | MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r | |
| 2569 | MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r | |
| 2570 | MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r | |
| 2571 | MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r | |
| 2572 | MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r | |
| 2573 | MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r | |
| 2574 | MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r | |
| 2575 | MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r | |
| 2576 | MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r | |
| 2577 | MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r | |
| 2578 | MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r | |
| 2579 | MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r | |
| 2580 | MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r | |
| 2581 | MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r | |
| 2582 | MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r | |
| 2583 | MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r | |
| 2584 | MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r | |
| 2585 | MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r | |
| 2586 | MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r | |
| 2587 | MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r | |
| 2588 | MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r | |
| 04c980a6 MK |
2589 | @{\r |
| 2590 | **/\r | |
| 2591 | #define MSR_IA32_MC0_CTL2 0x00000280\r | |
| 2592 | #define MSR_IA32_MC1_CTL2 0x00000281\r | |
| 2593 | #define MSR_IA32_MC2_CTL2 0x00000282\r | |
| 2594 | #define MSR_IA32_MC3_CTL2 0x00000283\r | |
| 2595 | #define MSR_IA32_MC4_CTL2 0x00000284\r | |
| 2596 | #define MSR_IA32_MC5_CTL2 0x00000285\r | |
| 2597 | #define MSR_IA32_MC6_CTL2 0x00000286\r | |
| 2598 | #define MSR_IA32_MC7_CTL2 0x00000287\r | |
| 2599 | #define MSR_IA32_MC8_CTL2 0x00000288\r | |
| 2600 | #define MSR_IA32_MC9_CTL2 0x00000289\r | |
| 2601 | #define MSR_IA32_MC10_CTL2 0x0000028A\r | |
| 2602 | #define MSR_IA32_MC11_CTL2 0x0000028B\r | |
| 2603 | #define MSR_IA32_MC12_CTL2 0x0000028C\r | |
| 2604 | #define MSR_IA32_MC13_CTL2 0x0000028D\r | |
| 2605 | #define MSR_IA32_MC14_CTL2 0x0000028E\r | |
| 2606 | #define MSR_IA32_MC15_CTL2 0x0000028F\r | |
| 2607 | #define MSR_IA32_MC16_CTL2 0x00000290\r | |
| 2608 | #define MSR_IA32_MC17_CTL2 0x00000291\r | |
| 2609 | #define MSR_IA32_MC18_CTL2 0x00000292\r | |
| 2610 | #define MSR_IA32_MC19_CTL2 0x00000293\r | |
| 2611 | #define MSR_IA32_MC20_CTL2 0x00000294\r | |
| 2612 | #define MSR_IA32_MC21_CTL2 0x00000295\r | |
| 2613 | #define MSR_IA32_MC22_CTL2 0x00000296\r | |
| 2614 | #define MSR_IA32_MC23_CTL2 0x00000297\r | |
| 2615 | #define MSR_IA32_MC24_CTL2 0x00000298\r | |
| 2616 | #define MSR_IA32_MC25_CTL2 0x00000299\r | |
| 2617 | #define MSR_IA32_MC26_CTL2 0x0000029A\r | |
| 2618 | #define MSR_IA32_MC27_CTL2 0x0000029B\r | |
| 2619 | #define MSR_IA32_MC28_CTL2 0x0000029C\r | |
| 2620 | #define MSR_IA32_MC29_CTL2 0x0000029D\r | |
| 2621 | #define MSR_IA32_MC30_CTL2 0x0000029E\r | |
| 2622 | #define MSR_IA32_MC31_CTL2 0x0000029F\r | |
| 2623 | /// @}\r | |
| 2624 | \r | |
| 2625 | /**\r | |
| 2626 | MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r | |
| 2627 | to #MSR_IA32_MC31_CTL2\r | |
| 2628 | **/\r | |
| 2629 | typedef union {\r | |
| 2630 | ///\r | |
| 2631 | /// Individual bit fields\r | |
| 2632 | ///\r | |
| 2633 | struct {\r | |
| 2634 | ///\r | |
| 2635 | /// [Bits 14:0] Corrected error count threshold.\r | |
| 2636 | ///\r | |
| 2637 | UINT32 CorrectedErrorCountThreshold:15;\r | |
| 2638 | UINT32 Reserved1:15;\r | |
| 2639 | ///\r | |
| 2640 | /// [Bit 30] CMCI_EN.\r | |
| 2641 | ///\r | |
| 2642 | UINT32 CMCI_EN:1;\r | |
| 2643 | UINT32 Reserved2:1;\r | |
| 2644 | UINT32 Reserved3:32;\r | |
| 2645 | } Bits;\r | |
| 2646 | ///\r | |
| 2647 | /// All bit fields as a 32-bit value\r | |
| 2648 | ///\r | |
| 2649 | UINT32 Uint32;\r | |
| 2650 | ///\r | |
| 2651 | /// All bit fields as a 64-bit value\r | |
| 2652 | ///\r | |
| 2653 | UINT64 Uint64;\r | |
| 2654 | } MSR_IA32_MC_CTL2_REGISTER;\r | |
| 2655 | \r | |
| 2656 | \r | |
| 2657 | /**\r | |
| 2658 | MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2659 | \r | |
| 2660 | @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r | |
| 2661 | @param EAX Lower 32-bits of MSR value.\r | |
| 2662 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2663 | @param EDX Upper 32-bits of MSR value.\r | |
| 2664 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2665 | \r | |
| 2666 | <b>Example usage</b>\r | |
| 2667 | @code\r | |
| 2668 | MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r | |
| 2669 | \r | |
| 2670 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r | |
| 2671 | AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r | |
| 2672 | @endcode\r | |
| 7de98828 | 2673 | @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r |
| 04c980a6 MK |
2674 | **/\r |
| 2675 | #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r | |
| 2676 | \r | |
| 2677 | /**\r | |
| 2678 | MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r | |
| 2679 | **/\r | |
| 2680 | typedef union {\r | |
| 2681 | ///\r | |
| 2682 | /// Individual bit fields\r | |
| 2683 | ///\r | |
| 2684 | struct {\r | |
| 2685 | ///\r | |
| 2686 | /// [Bits 2:0] Default Memory Type.\r | |
| 2687 | ///\r | |
| 2688 | UINT32 Type:3;\r | |
| 2689 | UINT32 Reserved1:7;\r | |
| 2690 | ///\r | |
| 2691 | /// [Bit 10] Fixed Range MTRR Enable.\r | |
| 2692 | ///\r | |
| 2693 | UINT32 FE:1;\r | |
| 2694 | ///\r | |
| 2695 | /// [Bit 11] MTRR Enable.\r | |
| 2696 | ///\r | |
| 2697 | UINT32 E:1;\r | |
| 2698 | UINT32 Reserved2:20;\r | |
| 2699 | UINT32 Reserved3:32;\r | |
| 2700 | } Bits;\r | |
| 2701 | ///\r | |
| 2702 | /// All bit fields as a 32-bit value\r | |
| 2703 | ///\r | |
| 2704 | UINT32 Uint32;\r | |
| 2705 | ///\r | |
| 2706 | /// All bit fields as a 64-bit value\r | |
| 2707 | ///\r | |
| 2708 | UINT64 Uint64;\r | |
| 2709 | } MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r | |
| 2710 | \r | |
| 2711 | \r | |
| 2712 | /**\r | |
| 2713 | Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r | |
| 2714 | CPUID.0AH: EDX[4:0] > 0.\r | |
| 2715 | \r | |
| 2716 | @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r | |
| 2717 | @param EAX Lower 32-bits of MSR value.\r | |
| 2718 | @param EDX Upper 32-bits of MSR value.\r | |
| 2719 | \r | |
| 2720 | <b>Example usage</b>\r | |
| 2721 | @code\r | |
| 2722 | UINT64 Msr;\r | |
| 2723 | \r | |
| 2724 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r | |
| 2725 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r | |
| 2726 | @endcode\r | |
| 7de98828 | 2727 | @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r |
| 04c980a6 MK |
2728 | **/\r |
| 2729 | #define MSR_IA32_FIXED_CTR0 0x00000309\r | |
| 2730 | \r | |
| 2731 | \r | |
| 2732 | /**\r | |
| 0f16be6d HW |
2733 | Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r |
| 2734 | CPUID.0AH: EDX[4:0] > 1.\r | |
| 04c980a6 MK |
2735 | \r |
| 2736 | @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r | |
| 2737 | @param EAX Lower 32-bits of MSR value.\r | |
| 2738 | @param EDX Upper 32-bits of MSR value.\r | |
| 2739 | \r | |
| 2740 | <b>Example usage</b>\r | |
| 2741 | @code\r | |
| 2742 | UINT64 Msr;\r | |
| 2743 | \r | |
| 2744 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r | |
| 2745 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r | |
| 2746 | @endcode\r | |
| 7de98828 | 2747 | @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r |
| 04c980a6 MK |
2748 | **/\r |
| 2749 | #define MSR_IA32_FIXED_CTR1 0x0000030A\r | |
| 2750 | \r | |
| 2751 | \r | |
| 2752 | /**\r | |
| 0f16be6d HW |
2753 | Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r |
| 2754 | CPUID.0AH: EDX[4:0] > 2.\r | |
| 04c980a6 MK |
2755 | \r |
| 2756 | @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r | |
| 2757 | @param EAX Lower 32-bits of MSR value.\r | |
| 2758 | @param EDX Upper 32-bits of MSR value.\r | |
| 2759 | \r | |
| 2760 | <b>Example usage</b>\r | |
| 2761 | @code\r | |
| 2762 | UINT64 Msr;\r | |
| 2763 | \r | |
| 2764 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r | |
| 2765 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r | |
| 2766 | @endcode\r | |
| 7de98828 | 2767 | @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r |
| 04c980a6 MK |
2768 | **/\r |
| 2769 | #define MSR_IA32_FIXED_CTR2 0x0000030B\r | |
| 2770 | \r | |
| 2771 | \r | |
| 2772 | /**\r | |
| 2773 | RO. If CPUID.01H: ECX[15] = 1.\r | |
| 2774 | \r | |
| 2775 | @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r | |
| 2776 | @param EAX Lower 32-bits of MSR value.\r | |
| 2777 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2778 | @param EDX Upper 32-bits of MSR value.\r | |
| 2779 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2780 | \r | |
| 2781 | <b>Example usage</b>\r | |
| 2782 | @code\r | |
| 2783 | MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r | |
| 2784 | \r | |
| 2785 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r | |
| 2786 | AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r | |
| 2787 | @endcode\r | |
| 7de98828 | 2788 | @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r |
| 04c980a6 MK |
2789 | **/\r |
| 2790 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345\r | |
| 2791 | \r | |
| 2792 | /**\r | |
| 2793 | MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r | |
| 2794 | **/\r | |
| 2795 | typedef union {\r | |
| 2796 | ///\r | |
| 2797 | /// Individual bit fields\r | |
| 2798 | ///\r | |
| 2799 | struct {\r | |
| 2800 | ///\r | |
| 2801 | /// [Bits 5:0] LBR format.\r | |
| 2802 | ///\r | |
| 2803 | UINT32 LBR_FMT:6;\r | |
| 2804 | ///\r | |
| 2805 | /// [Bit 6] PEBS Trap.\r | |
| 2806 | ///\r | |
| 2807 | UINT32 PEBS_TRAP:1;\r | |
| 2808 | ///\r | |
| 2809 | /// [Bit 7] PEBSSaveArchRegs.\r | |
| 2810 | ///\r | |
| 2811 | UINT32 PEBS_ARCH_REG:1;\r | |
| 2812 | ///\r | |
| 2813 | /// [Bits 11:8] PEBS Record Format.\r | |
| 2814 | ///\r | |
| 2815 | UINT32 PEBS_REC_FMT:4;\r | |
| 2816 | ///\r | |
| 2817 | /// [Bit 12] 1: Freeze while SMM is supported.\r | |
| 2818 | ///\r | |
| 2819 | UINT32 SMM_FREEZE:1;\r | |
| 2820 | ///\r | |
| 2821 | /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r | |
| 2822 | ///\r | |
| 2823 | UINT32 FW_WRITE:1;\r | |
| 2824 | UINT32 Reserved1:18;\r | |
| 2825 | UINT32 Reserved2:32;\r | |
| 2826 | } Bits;\r | |
| 2827 | ///\r | |
| 2828 | /// All bit fields as a 32-bit value\r | |
| 2829 | ///\r | |
| 2830 | UINT32 Uint32;\r | |
| 2831 | ///\r | |
| 2832 | /// All bit fields as a 64-bit value\r | |
| 2833 | ///\r | |
| 2834 | UINT64 Uint64;\r | |
| 2835 | } MSR_IA32_PERF_CAPABILITIES_REGISTER;\r | |
| 2836 | \r | |
| 2837 | \r | |
| 2838 | /**\r | |
| 2839 | Fixed-Function Performance Counter Control (R/W) Counter increments while\r | |
| 2840 | the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r | |
| 2841 | the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r | |
| 2842 | > 1.\r | |
| 2843 | \r | |
| 2844 | @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r | |
| 2845 | @param EAX Lower 32-bits of MSR value.\r | |
| 2846 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2847 | @param EDX Upper 32-bits of MSR value.\r | |
| 2848 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2849 | \r | |
| 2850 | <b>Example usage</b>\r | |
| 2851 | @code\r | |
| 2852 | MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r | |
| 2853 | \r | |
| 2854 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r | |
| 2855 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r | |
| 2856 | @endcode\r | |
| 7de98828 | 2857 | @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r |
| 04c980a6 MK |
2858 | **/\r |
| 2859 | #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r | |
| 2860 | \r | |
| 2861 | /**\r | |
| 2862 | MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r | |
| 2863 | **/\r | |
| 2864 | typedef union {\r | |
| 2865 | ///\r | |
| 2866 | /// Individual bit fields\r | |
| 2867 | ///\r | |
| 2868 | struct {\r | |
| 2869 | ///\r | |
| 2870 | /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r | |
| 2871 | ///\r | |
| 2872 | UINT32 EN0_OS:1;\r | |
| 2873 | ///\r | |
| 2874 | /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r | |
| 2875 | ///\r | |
| 2876 | UINT32 EN0_Usr:1;\r | |
| 2877 | ///\r | |
| 2878 | /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r | |
| 2879 | /// event conditions occurring across all logical processors sharing a\r | |
| 2880 | /// processor core. When set to 0, the counter only increments the\r | |
| 2881 | /// associated event conditions occurring in the logical processor which\r | |
| 2882 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2883 | ///\r | |
| 2884 | UINT32 AnyThread0:1;\r | |
| 2885 | ///\r | |
| 2886 | /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r | |
| 2887 | ///\r | |
| 2888 | UINT32 EN0_PMI:1;\r | |
| 2889 | ///\r | |
| 2890 | /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r | |
| 2891 | ///\r | |
| 2892 | UINT32 EN1_OS:1;\r | |
| 2893 | ///\r | |
| 2894 | /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r | |
| 2895 | ///\r | |
| 2896 | UINT32 EN1_Usr:1;\r | |
| 2897 | ///\r | |
| 2898 | /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r | |
| 2899 | /// event conditions occurring across all logical processors sharing a\r | |
| 2900 | /// processor core. When set to 0, the counter only increments the\r | |
| 2901 | /// associated event conditions occurring in the logical processor which\r | |
| 2902 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2903 | ///\r | |
| 2904 | UINT32 AnyThread1:1;\r | |
| 2905 | ///\r | |
| 2906 | /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r | |
| 2907 | ///\r | |
| 2908 | UINT32 EN1_PMI:1;\r | |
| 2909 | ///\r | |
| 2910 | /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r | |
| 2911 | ///\r | |
| 2912 | UINT32 EN2_OS:1;\r | |
| 2913 | ///\r | |
| 2914 | /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r | |
| 2915 | ///\r | |
| 2916 | UINT32 EN2_Usr:1;\r | |
| 2917 | ///\r | |
| 2918 | /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r | |
| 2919 | /// event conditions occurring across all logical processors sharing a\r | |
| 2920 | /// processor core. When set to 0, the counter only increments the\r | |
| 2921 | /// associated event conditions occurring in the logical processor which\r | |
| 2922 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2923 | ///\r | |
| 2924 | UINT32 AnyThread2:1;\r | |
| 2925 | ///\r | |
| 2926 | /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r | |
| 2927 | ///\r | |
| 2928 | UINT32 EN2_PMI:1;\r | |
| 2929 | UINT32 Reserved1:20;\r | |
| 2930 | UINT32 Reserved2:32;\r | |
| 2931 | } Bits;\r | |
| 2932 | ///\r | |
| 2933 | /// All bit fields as a 32-bit value\r | |
| 2934 | ///\r | |
| 2935 | UINT32 Uint32;\r | |
| 2936 | ///\r | |
| 2937 | /// All bit fields as a 64-bit value\r | |
| 2938 | ///\r | |
| 2939 | UINT64 Uint64;\r | |
| 2940 | } MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r | |
| 2941 | \r | |
| 2942 | \r | |
| 2943 | /**\r | |
| 2944 | Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r | |
| 2945 | \r | |
| 2946 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r | |
| 2947 | @param EAX Lower 32-bits of MSR value.\r | |
| 2948 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2949 | @param EDX Upper 32-bits of MSR value.\r | |
| 2950 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2951 | \r | |
| 2952 | <b>Example usage</b>\r | |
| 2953 | @code\r | |
| 2954 | MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
| 2955 | \r | |
| 2956 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r | |
| 2957 | @endcode\r | |
| 7de98828 | 2958 | @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r |
| 04c980a6 MK |
2959 | **/\r |
| 2960 | #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r | |
| 2961 | \r | |
| 2962 | /**\r | |
| 2963 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r | |
| 2964 | **/\r | |
| 2965 | typedef union {\r | |
| 2966 | ///\r | |
| 2967 | /// Individual bit fields\r | |
| 2968 | ///\r | |
| 2969 | struct {\r | |
| 2970 | ///\r | |
| 2971 | /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r | |
| 2972 | /// EAX[15:8] > 0.\r | |
| 2973 | ///\r | |
| 2974 | UINT32 Ovf_PMC0:1;\r | |
| 2975 | ///\r | |
| 2976 | /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r | |
| 2977 | /// EAX[15:8] > 1.\r | |
| 2978 | ///\r | |
| 2979 | UINT32 Ovf_PMC1:1;\r | |
| 2980 | ///\r | |
| 2981 | /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r | |
| 2982 | /// EAX[15:8] > 2.\r | |
| 2983 | ///\r | |
| 2984 | UINT32 Ovf_PMC2:1;\r | |
| 2985 | ///\r | |
| 2986 | /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r | |
| 2987 | /// EAX[15:8] > 3.\r | |
| 2988 | ///\r | |
| 2989 | UINT32 Ovf_PMC3:1;\r | |
| 2990 | UINT32 Reserved1:28;\r | |
| 2991 | ///\r | |
| 2992 | /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r | |
| 2993 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2994 | ///\r | |
| 2995 | UINT32 Ovf_FixedCtr0:1;\r | |
| 2996 | ///\r | |
| 2997 | /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r | |
| 2998 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2999 | ///\r | |
| 3000 | UINT32 Ovf_FixedCtr1:1;\r | |
| 3001 | ///\r | |
| 3002 | /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r | |
| 3003 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 3004 | ///\r | |
| 3005 | UINT32 Ovf_FixedCtr2:1;\r | |
| 3006 | UINT32 Reserved2:20;\r | |
| 3007 | ///\r | |
| 3008 | /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r | |
| 3009 | /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
| 3010 | /// && IA32_RTIT_CTL.ToPA = 1.\r | |
| 3011 | ///\r | |
| 3012 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3013 | UINT32 Reserved3:2;\r | |
| 3014 | ///\r | |
| 3015 | /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r | |
| 3016 | /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r | |
| 3017 | /// CPUID.0AH: EAX[7:0] > 3.\r | |
| 3018 | ///\r | |
| 3019 | UINT32 LBR_Frz:1;\r | |
| 3020 | ///\r | |
| 3021 | /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r | |
| 3022 | /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r | |
| 3023 | /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3024 | ///\r | |
| 3025 | UINT32 CTR_Frz:1;\r | |
| 3026 | ///\r | |
| 3027 | /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r | |
| 3028 | /// include contributions from the direct or indirect operation intel SGX\r | |
| 3029 | /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r | |
| 3030 | ///\r | |
| 3031 | UINT32 ASCI:1;\r | |
| 3032 | ///\r | |
| 3033 | /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r | |
| 3034 | /// EAX[7:0] > 2.\r | |
| 3035 | ///\r | |
| 3036 | UINT32 Ovf_Uncore:1;\r | |
| 3037 | ///\r | |
| 3038 | /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r | |
| 3039 | /// EAX[7:0] > 0.\r | |
| 3040 | ///\r | |
| 3041 | UINT32 OvfBuf:1;\r | |
| 3042 | ///\r | |
| 3043 | /// [Bit 63] CondChgd: status bits of this register has changed. If\r | |
| 3044 | /// CPUID.0AH: EAX[7:0] > 0.\r | |
| 3045 | ///\r | |
| 3046 | UINT32 CondChgd:1;\r | |
| 3047 | } Bits;\r | |
| 3048 | ///\r | |
| 3049 | /// All bit fields as a 64-bit value\r | |
| 3050 | ///\r | |
| 3051 | UINT64 Uint64;\r | |
| 3052 | } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r | |
| 3053 | \r | |
| 3054 | \r | |
| 3055 | /**\r | |
| 3056 | Global Performance Counter Control (R/W) Counter increments while the result\r | |
| 3057 | of ANDing respective enable bit in this MSR with the corresponding OS or USR\r | |
| 3058 | bits in the general-purpose or fixed counter control MSR is true. If\r | |
| 3059 | CPUID.0AH: EAX[7:0] > 0.\r | |
| 3060 | \r | |
| 3061 | @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r | |
| 3062 | @param EAX Lower 32-bits of MSR value.\r | |
| 3063 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 3064 | @param EDX Upper 32-bits of MSR value.\r | |
| 3065 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 3066 | \r | |
| 3067 | <b>Example usage</b>\r | |
| 3068 | @code\r | |
| 3069 | MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
| 3070 | \r | |
| 3071 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r | |
| 3072 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
| 3073 | @endcode\r | |
| 7de98828 | 3074 | @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r |
| 04c980a6 MK |
3075 | **/\r |
| 3076 | #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r | |
| 3077 | \r | |
| 3078 | /**\r | |
| 3079 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r | |
| 3080 | **/\r | |
| 3081 | typedef union {\r | |
| 3082 | ///\r | |
| 3083 | /// Individual bit fields\r | |
| 3084 | ///\r | |
| 3085 | struct {\r | |
| 3086 | ///\r | |
| 3087 | /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3088 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3089 | /// Bits n..31 are reserved.\r | |
| 3090 | ///\r | |
| 3091 | UINT32 EN_PMCn:32;\r | |
| 3092 | ///\r | |
| 3093 | /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r | |
| 3094 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3095 | /// Bits 31:n are reserved.\r | |
| 3096 | ///\r | |
| 3097 | UINT32 EN_FIXED_CTRn:32;\r | |
| 3098 | } Bits;\r | |
| 3099 | ///\r | |
| 3100 | /// All bit fields as a 64-bit value\r | |
| 3101 | ///\r | |
| 3102 | UINT64 Uint64;\r | |
| 3103 | } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r | |
| 3104 | \r | |
| 3105 | \r | |
| 3106 | /**\r | |
| 3107 | Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r | |
| 3108 | 0 && CPUID.0AH: EAX[7:0] <= 3.\r | |
| 3109 | \r | |
| 3110 | @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
| 3111 | @param EAX Lower 32-bits of MSR value.\r | |
| 3112 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3113 | @param EDX Upper 32-bits of MSR value.\r | |
| 3114 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3115 | \r | |
| 3116 | <b>Example usage</b>\r | |
| 3117 | @code\r | |
| 3118 | MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r | |
| 3119 | \r | |
| 3120 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r | |
| 3121 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r | |
| 3122 | @endcode\r | |
| 7de98828 | 3123 | @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r |
| 04c980a6 MK |
3124 | **/\r |
| 3125 | #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r | |
| 3126 | \r | |
| 3127 | /**\r | |
| 3128 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r | |
| 3129 | **/\r | |
| 3130 | typedef union {\r | |
| 3131 | ///\r | |
| 3132 | /// Individual bit fields\r | |
| 3133 | ///\r | |
| 3134 | struct {\r | |
| 3135 | ///\r | |
| 3136 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3137 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3138 | /// Bits 31:n are reserved.\r | |
| 3139 | ///\r | |
| 3140 | UINT32 Ovf_PMCn:32;\r | |
| 3141 | ///\r | |
| 3142 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3143 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3144 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3145 | /// Bits 22:n are reserved.\r | |
| 3146 | ///\r | |
| 3147 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3148 | ///\r | |
| 3149 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3150 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r | |
| 3151 | ///\r | |
| 3152 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3153 | UINT32 Reserved2:5;\r | |
| 3154 | ///\r | |
| 3155 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3156 | /// Display Model 06_2EH.\r | |
| 3157 | ///\r | |
| 3158 | UINT32 Ovf_Uncore:1;\r | |
| 3159 | ///\r | |
| 3160 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3161 | ///\r | |
| 3162 | UINT32 OvfBuf:1;\r | |
| 3163 | ///\r | |
| 3164 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3165 | ///\r | |
| 3166 | UINT32 CondChgd:1;\r | |
| 3167 | } Bits;\r | |
| 3168 | ///\r | |
| 3169 | /// All bit fields as a 64-bit value\r | |
| 3170 | ///\r | |
| 3171 | UINT64 Uint64;\r | |
| 3172 | } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r | |
| 3173 | \r | |
| 3174 | \r | |
| 3175 | /**\r | |
| 3176 | Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r | |
| 3177 | EAX[7:0] > 3.\r | |
| 3178 | \r | |
| 3179 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
| 3180 | @param EAX Lower 32-bits of MSR value.\r | |
| 3181 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3182 | @param EDX Upper 32-bits of MSR value.\r | |
| 3183 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3184 | \r | |
| 3185 | <b>Example usage</b>\r | |
| 3186 | @code\r | |
| 3187 | MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
| 3188 | \r | |
| 3189 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
| 3190 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
| 3191 | @endcode\r | |
| 7de98828 | 3192 | @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r |
| 04c980a6 MK |
3193 | **/\r |
| 3194 | #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r | |
| 3195 | \r | |
| 3196 | /**\r | |
| 3197 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r | |
| 3198 | **/\r | |
| 3199 | typedef union {\r | |
| 3200 | ///\r | |
| 3201 | /// Individual bit fields\r | |
| 3202 | ///\r | |
| 3203 | struct {\r | |
| 3204 | ///\r | |
| 3205 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3206 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3207 | /// Bits 31:n are reserved.\r | |
| 3208 | ///\r | |
| 3209 | UINT32 Ovf_PMCn:32;\r | |
| 3210 | ///\r | |
| 3211 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3212 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3213 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3214 | /// Bits 22:n are reserved.\r | |
| 3215 | ///\r | |
| 3216 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3217 | ///\r | |
| 3218 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3219 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r | |
| 3220 | ///\r | |
| 3221 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3222 | UINT32 Reserved2:2;\r | |
| 3223 | ///\r | |
| 3224 | /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3225 | ///\r | |
| 3226 | UINT32 LBR_Frz:1;\r | |
| 3227 | ///\r | |
| 3228 | /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3229 | ///\r | |
| 3230 | UINT32 CTR_Frz:1;\r | |
| 3231 | ///\r | |
| 3232 | /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3233 | ///\r | |
| 3234 | UINT32 ASCI:1;\r | |
| 3235 | ///\r | |
| 3236 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3237 | /// Display Model 06_2EH.\r | |
| 3238 | ///\r | |
| 3239 | UINT32 Ovf_Uncore:1;\r | |
| 3240 | ///\r | |
| 3241 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3242 | ///\r | |
| 3243 | UINT32 OvfBuf:1;\r | |
| 3244 | ///\r | |
| 3245 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3246 | ///\r | |
| 3247 | UINT32 CondChgd:1;\r | |
| 3248 | } Bits;\r | |
| 3249 | ///\r | |
| 3250 | /// All bit fields as a 64-bit value\r | |
| 3251 | ///\r | |
| 3252 | UINT64 Uint64;\r | |
| 3253 | } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r | |
| 3254 | \r | |
| 3255 | \r | |
| 3256 | /**\r | |
| 3257 | Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r | |
| 3258 | EAX[7:0] > 3.\r | |
| 3259 | \r | |
| 3260 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
| 3261 | @param EAX Lower 32-bits of MSR value.\r | |
| 3262 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3263 | @param EDX Upper 32-bits of MSR value.\r | |
| 3264 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3265 | \r | |
| 3266 | <b>Example usage</b>\r | |
| 3267 | @code\r | |
| 3268 | MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
| 3269 | \r | |
| 3270 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r | |
| 3271 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
| 3272 | @endcode\r | |
| 7de98828 | 3273 | @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r |
| 04c980a6 MK |
3274 | **/\r |
| 3275 | #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
| 3276 | \r | |
| 3277 | /**\r | |
| 3278 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r | |
| 3279 | **/\r | |
| 3280 | typedef union {\r | |
| 3281 | ///\r | |
| 3282 | /// Individual bit fields\r | |
| 3283 | ///\r | |
| 3284 | struct {\r | |
| 3285 | ///\r | |
| 3286 | /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3287 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3288 | /// Bits 31:n are reserved.\r | |
| 3289 | ///\r | |
| 3290 | UINT32 Ovf_PMCn:32;\r | |
| 3291 | ///\r | |
| 3292 | /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r | |
| 3293 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3294 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3295 | /// Bits 22:n are reserved.\r | |
| 3296 | ///\r | |
| 3297 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3298 | ///\r | |
| 3299 | /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3300 | ///\r | |
| 3301 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3302 | UINT32 Reserved2:2;\r | |
| 3303 | ///\r | |
| 3304 | /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3305 | ///\r | |
| 3306 | UINT32 LBR_Frz:1;\r | |
| 3307 | ///\r | |
| 3308 | /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3309 | ///\r | |
| 3310 | UINT32 CTR_Frz:1;\r | |
| 3311 | ///\r | |
| 3312 | /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3313 | ///\r | |
| 3314 | UINT32 ASCI:1;\r | |
| 3315 | ///\r | |
| 3316 | /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3317 | ///\r | |
| 3318 | UINT32 Ovf_Uncore:1;\r | |
| 3319 | ///\r | |
| 3320 | /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3321 | ///\r | |
| 3322 | UINT32 OvfBuf:1;\r | |
| 3323 | UINT32 Reserved3:1;\r | |
| 3324 | } Bits;\r | |
| 3325 | ///\r | |
| 3326 | /// All bit fields as a 64-bit value\r | |
| 3327 | ///\r | |
| 3328 | UINT64 Uint64;\r | |
| 3329 | } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r | |
| 3330 | \r | |
| 3331 | \r | |
| 3332 | /**\r | |
| 3333 | Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r | |
| 3334 | 3.\r | |
| 3335 | \r | |
| 3336 | @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r | |
| 3337 | @param EAX Lower 32-bits of MSR value.\r | |
| 3338 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3339 | @param EDX Upper 32-bits of MSR value.\r | |
| 3340 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3341 | \r | |
| 3342 | <b>Example usage</b>\r | |
| 3343 | @code\r | |
| 3344 | MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r | |
| 3345 | \r | |
| 3346 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r | |
| 3347 | @endcode\r | |
| 7de98828 | 3348 | @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r |
| 04c980a6 MK |
3349 | **/\r |
| 3350 | #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r | |
| 3351 | \r | |
| 3352 | /**\r | |
| 3353 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r | |
| 3354 | **/\r | |
| 3355 | typedef union {\r | |
| 3356 | ///\r | |
| 3357 | /// Individual bit fields\r | |
| 3358 | ///\r | |
| 3359 | struct {\r | |
| 3360 | ///\r | |
| 3361 | /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3362 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3363 | /// Bits 31:n are reserved.\r | |
| 3364 | ///\r | |
| 3365 | UINT32 IA32_PERFEVTSELn:32;\r | |
| 3366 | ///\r | |
| 3367 | /// [Bits 62:32] IA32_FIXED_CTRn in use.\r | |
| 3368 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3369 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3370 | /// Bits 30:n are reserved.\r | |
| 3371 | ///\r | |
| 3372 | UINT32 IA32_FIXED_CTRn:31;\r | |
| 3373 | ///\r | |
| 3374 | /// [Bit 63] PMI in use.\r | |
| 3375 | ///\r | |
| 3376 | UINT32 PMI:1;\r | |
| 3377 | } Bits;\r | |
| 3378 | ///\r | |
| 3379 | /// All bit fields as a 64-bit value\r | |
| 3380 | ///\r | |
| 3381 | UINT64 Uint64;\r | |
| 3382 | } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r | |
| 3383 | \r | |
| 3384 | \r | |
| 3385 | /**\r | |
| 3386 | PEBS Control (R/W).\r | |
| 3387 | \r | |
| 3388 | @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r | |
| 3389 | @param EAX Lower 32-bits of MSR value.\r | |
| 3390 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3391 | @param EDX Upper 32-bits of MSR value.\r | |
| 3392 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3393 | \r | |
| 3394 | <b>Example usage</b>\r | |
| 3395 | @code\r | |
| 3396 | MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r | |
| 3397 | \r | |
| 3398 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r | |
| 3399 | AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r | |
| 3400 | @endcode\r | |
| 7de98828 | 3401 | @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r |
| 04c980a6 MK |
3402 | **/\r |
| 3403 | #define MSR_IA32_PEBS_ENABLE 0x000003F1\r | |
| 3404 | \r | |
| 3405 | /**\r | |
| 3406 | MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r | |
| 3407 | **/\r | |
| 3408 | typedef union {\r | |
| 3409 | ///\r | |
| 3410 | /// Individual bit fields\r | |
| 3411 | ///\r | |
| 3412 | struct {\r | |
| 3413 | ///\r | |
| 3414 | /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r | |
| 3415 | /// Display Model 06_0FH.\r | |
| 3416 | ///\r | |
| 3417 | UINT32 Enable:1;\r | |
| 3418 | ///\r | |
| 3419 | /// [Bits 3:1] Reserved or Model specific.\r | |
| 3420 | ///\r | |
| 3421 | UINT32 Reserved1:3;\r | |
| 3422 | UINT32 Reserved2:28;\r | |
| 3423 | ///\r | |
| 3424 | /// [Bits 35:32] Reserved or Model specific.\r | |
| 3425 | ///\r | |
| 3426 | UINT32 Reserved3:4;\r | |
| 3427 | UINT32 Reserved4:28;\r | |
| 3428 | } Bits;\r | |
| 3429 | ///\r | |
| 3430 | /// All bit fields as a 64-bit value\r | |
| 3431 | ///\r | |
| 3432 | UINT64 Uint64;\r | |
| 3433 | } MSR_IA32_PEBS_ENABLE_REGISTER;\r | |
| 3434 | \r | |
| 3435 | \r | |
| 3436 | /**\r | |
| 3437 | MCn_CTL. If IA32_MCG_CAP.CNT > n.\r | |
| 3438 | \r | |
| 3439 | @param ECX MSR_IA32_MCn_CTL\r | |
| 3440 | @param EAX Lower 32-bits of MSR value.\r | |
| 3441 | @param EDX Upper 32-bits of MSR value.\r | |
| 3442 | \r | |
| 3443 | <b>Example usage</b>\r | |
| 3444 | @code\r | |
| 3445 | UINT64 Msr;\r | |
| 3446 | \r | |
| 3447 | Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r | |
| 3448 | AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r | |
| 3449 | @endcode\r | |
| 7de98828 JF |
3450 | @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r |
| 3451 | MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r | |
| 3452 | MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r | |
| 3453 | MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r | |
| 3454 | MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r | |
| 3455 | MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r | |
| 3456 | MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r | |
| 3457 | MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r | |
| 3458 | MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r | |
| 3459 | MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r | |
| 3460 | MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r | |
| 3461 | MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r | |
| 3462 | MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r | |
| 3463 | MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r | |
| 3464 | MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r | |
| 3465 | MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r | |
| 3466 | MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r | |
| 3467 | MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r | |
| 3468 | MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r | |
| 3469 | MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r | |
| 3470 | MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r | |
| 3471 | MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r | |
| 3472 | MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r | |
| 3473 | MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r | |
| 3474 | MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r | |
| 3475 | MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r | |
| 3476 | MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r | |
| 3477 | MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r | |
| 3478 | MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r | |
| 04c980a6 MK |
3479 | @{\r |
| 3480 | **/\r | |
| 3481 | #define MSR_IA32_MC0_CTL 0x00000400\r | |
| 3482 | #define MSR_IA32_MC1_CTL 0x00000404\r | |
| 3483 | #define MSR_IA32_MC2_CTL 0x00000408\r | |
| 3484 | #define MSR_IA32_MC3_CTL 0x0000040C\r | |
| 3485 | #define MSR_IA32_MC4_CTL 0x00000410\r | |
| 3486 | #define MSR_IA32_MC5_CTL 0x00000414\r | |
| 3487 | #define MSR_IA32_MC6_CTL 0x00000418\r | |
| 3488 | #define MSR_IA32_MC7_CTL 0x0000041C\r | |
| 3489 | #define MSR_IA32_MC8_CTL 0x00000420\r | |
| 3490 | #define MSR_IA32_MC9_CTL 0x00000424\r | |
| 3491 | #define MSR_IA32_MC10_CTL 0x00000428\r | |
| 3492 | #define MSR_IA32_MC11_CTL 0x0000042C\r | |
| 3493 | #define MSR_IA32_MC12_CTL 0x00000430\r | |
| 3494 | #define MSR_IA32_MC13_CTL 0x00000434\r | |
| 3495 | #define MSR_IA32_MC14_CTL 0x00000438\r | |
| 3496 | #define MSR_IA32_MC15_CTL 0x0000043C\r | |
| 3497 | #define MSR_IA32_MC16_CTL 0x00000440\r | |
| 3498 | #define MSR_IA32_MC17_CTL 0x00000444\r | |
| 3499 | #define MSR_IA32_MC18_CTL 0x00000448\r | |
| 3500 | #define MSR_IA32_MC19_CTL 0x0000044C\r | |
| 3501 | #define MSR_IA32_MC20_CTL 0x00000450\r | |
| 3502 | #define MSR_IA32_MC21_CTL 0x00000454\r | |
| 3503 | #define MSR_IA32_MC22_CTL 0x00000458\r | |
| 3504 | #define MSR_IA32_MC23_CTL 0x0000045C\r | |
| 3505 | #define MSR_IA32_MC24_CTL 0x00000460\r | |
| 3506 | #define MSR_IA32_MC25_CTL 0x00000464\r | |
| 3507 | #define MSR_IA32_MC26_CTL 0x00000468\r | |
| 3508 | #define MSR_IA32_MC27_CTL 0x0000046C\r | |
| 3509 | #define MSR_IA32_MC28_CTL 0x00000470\r | |
| 3510 | /// @}\r | |
| 3511 | \r | |
| 3512 | \r | |
| 3513 | /**\r | |
| 3514 | MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r | |
| 3515 | \r | |
| 3516 | @param ECX MSR_IA32_MCn_STATUS\r | |
| 3517 | @param EAX Lower 32-bits of MSR value.\r | |
| 3518 | @param EDX Upper 32-bits of MSR value.\r | |
| 3519 | \r | |
| 3520 | <b>Example usage</b>\r | |
| 3521 | @code\r | |
| 3522 | UINT64 Msr;\r | |
| 3523 | \r | |
| 3524 | Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r | |
| 3525 | AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r | |
| 3526 | @endcode\r | |
| 7de98828 JF |
3527 | @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r |
| 3528 | MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r | |
| 3529 | MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r | |
| 3530 | MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r | |
| 3531 | MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r | |
| 3532 | MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r | |
| 3533 | MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r | |
| 3534 | MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r | |
| 3535 | MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r | |
| 3536 | MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r | |
| 3537 | MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r | |
| 3538 | MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r | |
| 3539 | MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r | |
| 3540 | MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r | |
| 3541 | MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r | |
| 3542 | MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r | |
| 3543 | MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r | |
| 3544 | MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r | |
| 3545 | MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r | |
| 3546 | MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r | |
| 3547 | MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r | |
| 3548 | MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r | |
| 3549 | MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r | |
| 3550 | MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r | |
| 3551 | MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r | |
| 3552 | MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r | |
| 3553 | MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r | |
| 3554 | MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r | |
| 3555 | MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r | |
| 04c980a6 MK |
3556 | @{\r |
| 3557 | **/\r | |
| 3558 | #define MSR_IA32_MC0_STATUS 0x00000401\r | |
| 3559 | #define MSR_IA32_MC1_STATUS 0x00000405\r | |
| 3560 | #define MSR_IA32_MC2_STATUS 0x00000409\r | |
| 3561 | #define MSR_IA32_MC3_STATUS 0x0000040D\r | |
| 3562 | #define MSR_IA32_MC4_STATUS 0x00000411\r | |
| 3563 | #define MSR_IA32_MC5_STATUS 0x00000415\r | |
| 3564 | #define MSR_IA32_MC6_STATUS 0x00000419\r | |
| 3565 | #define MSR_IA32_MC7_STATUS 0x0000041D\r | |
| 3566 | #define MSR_IA32_MC8_STATUS 0x00000421\r | |
| 3567 | #define MSR_IA32_MC9_STATUS 0x00000425\r | |
| 3568 | #define MSR_IA32_MC10_STATUS 0x00000429\r | |
| 3569 | #define MSR_IA32_MC11_STATUS 0x0000042D\r | |
| 3570 | #define MSR_IA32_MC12_STATUS 0x00000431\r | |
| 3571 | #define MSR_IA32_MC13_STATUS 0x00000435\r | |
| 3572 | #define MSR_IA32_MC14_STATUS 0x00000439\r | |
| 3573 | #define MSR_IA32_MC15_STATUS 0x0000043D\r | |
| 3574 | #define MSR_IA32_MC16_STATUS 0x00000441\r | |
| 3575 | #define MSR_IA32_MC17_STATUS 0x00000445\r | |
| 3576 | #define MSR_IA32_MC18_STATUS 0x00000449\r | |
| 3577 | #define MSR_IA32_MC19_STATUS 0x0000044D\r | |
| 3578 | #define MSR_IA32_MC20_STATUS 0x00000451\r | |
| 3579 | #define MSR_IA32_MC21_STATUS 0x00000455\r | |
| 3580 | #define MSR_IA32_MC22_STATUS 0x00000459\r | |
| 3581 | #define MSR_IA32_MC23_STATUS 0x0000045D\r | |
| 3582 | #define MSR_IA32_MC24_STATUS 0x00000461\r | |
| 3583 | #define MSR_IA32_MC25_STATUS 0x00000465\r | |
| 3584 | #define MSR_IA32_MC26_STATUS 0x00000469\r | |
| 3585 | #define MSR_IA32_MC27_STATUS 0x0000046D\r | |
| 3586 | #define MSR_IA32_MC28_STATUS 0x00000471\r | |
| 3587 | /// @}\r | |
| 3588 | \r | |
| 3589 | \r | |
| 3590 | /**\r | |
| 3591 | MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r | |
| 3592 | \r | |
| 3593 | @param ECX MSR_IA32_MCn_ADDR\r | |
| 3594 | @param EAX Lower 32-bits of MSR value.\r | |
| 3595 | @param EDX Upper 32-bits of MSR value.\r | |
| 3596 | \r | |
| 3597 | <b>Example usage</b>\r | |
| 3598 | @code\r | |
| 3599 | UINT64 Msr;\r | |
| 3600 | \r | |
| 3601 | Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r | |
| 3602 | AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r | |
| 3603 | @endcode\r | |
| 7de98828 JF |
3604 | @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r |
| 3605 | MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r | |
| 3606 | MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r | |
| 3607 | MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r | |
| 3608 | MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r | |
| 3609 | MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r | |
| 3610 | MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r | |
| 3611 | MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r | |
| 3612 | MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r | |
| 3613 | MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r | |
| 3614 | MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r | |
| 3615 | MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r | |
| 3616 | MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r | |
| 3617 | MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r | |
| 3618 | MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r | |
| 3619 | MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r | |
| 3620 | MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r | |
| 3621 | MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r | |
| 3622 | MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r | |
| 3623 | MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r | |
| 3624 | MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r | |
| 3625 | MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r | |
| 3626 | MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r | |
| 3627 | MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r | |
| 3628 | MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r | |
| 3629 | MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r | |
| 3630 | MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r | |
| 3631 | MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r | |
| 3632 | MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r | |
| 04c980a6 MK |
3633 | @{\r |
| 3634 | **/\r | |
| 3635 | #define MSR_IA32_MC0_ADDR 0x00000402\r | |
| 3636 | #define MSR_IA32_MC1_ADDR 0x00000406\r | |
| 3637 | #define MSR_IA32_MC2_ADDR 0x0000040A\r | |
| 3638 | #define MSR_IA32_MC3_ADDR 0x0000040E\r | |
| 3639 | #define MSR_IA32_MC4_ADDR 0x00000412\r | |
| 3640 | #define MSR_IA32_MC5_ADDR 0x00000416\r | |
| 3641 | #define MSR_IA32_MC6_ADDR 0x0000041A\r | |
| 3642 | #define MSR_IA32_MC7_ADDR 0x0000041E\r | |
| 3643 | #define MSR_IA32_MC8_ADDR 0x00000422\r | |
| 3644 | #define MSR_IA32_MC9_ADDR 0x00000426\r | |
| 3645 | #define MSR_IA32_MC10_ADDR 0x0000042A\r | |
| 3646 | #define MSR_IA32_MC11_ADDR 0x0000042E\r | |
| 3647 | #define MSR_IA32_MC12_ADDR 0x00000432\r | |
| 3648 | #define MSR_IA32_MC13_ADDR 0x00000436\r | |
| 3649 | #define MSR_IA32_MC14_ADDR 0x0000043A\r | |
| 3650 | #define MSR_IA32_MC15_ADDR 0x0000043E\r | |
| 3651 | #define MSR_IA32_MC16_ADDR 0x00000442\r | |
| 3652 | #define MSR_IA32_MC17_ADDR 0x00000446\r | |
| 3653 | #define MSR_IA32_MC18_ADDR 0x0000044A\r | |
| 3654 | #define MSR_IA32_MC19_ADDR 0x0000044E\r | |
| 3655 | #define MSR_IA32_MC20_ADDR 0x00000452\r | |
| 3656 | #define MSR_IA32_MC21_ADDR 0x00000456\r | |
| 3657 | #define MSR_IA32_MC22_ADDR 0x0000045A\r | |
| 3658 | #define MSR_IA32_MC23_ADDR 0x0000045E\r | |
| 3659 | #define MSR_IA32_MC24_ADDR 0x00000462\r | |
| 3660 | #define MSR_IA32_MC25_ADDR 0x00000466\r | |
| 3661 | #define MSR_IA32_MC26_ADDR 0x0000046A\r | |
| 3662 | #define MSR_IA32_MC27_ADDR 0x0000046E\r | |
| 3663 | #define MSR_IA32_MC28_ADDR 0x00000472\r | |
| 3664 | /// @}\r | |
| 3665 | \r | |
| 3666 | \r | |
| 3667 | /**\r | |
| 3668 | MCn_MISC. If IA32_MCG_CAP.CNT > n.\r | |
| 3669 | \r | |
| 3670 | @param ECX MSR_IA32_MCn_MISC\r | |
| 3671 | @param EAX Lower 32-bits of MSR value.\r | |
| 3672 | @param EDX Upper 32-bits of MSR value.\r | |
| 3673 | \r | |
| 3674 | <b>Example usage</b>\r | |
| 3675 | @code\r | |
| 3676 | UINT64 Msr;\r | |
| 3677 | \r | |
| 3678 | Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r | |
| 3679 | AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r | |
| 3680 | @endcode\r | |
| 7de98828 JF |
3681 | @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r |
| 3682 | MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r | |
| 3683 | MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r | |
| 3684 | MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r | |
| 3685 | MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r | |
| 3686 | MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r | |
| 3687 | MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r | |
| 3688 | MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r | |
| 3689 | MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r | |
| 3690 | MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r | |
| 3691 | MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r | |
| 3692 | MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r | |
| 3693 | MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r | |
| 3694 | MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r | |
| 3695 | MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r | |
| 3696 | MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r | |
| 3697 | MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r | |
| 3698 | MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r | |
| 3699 | MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r | |
| 3700 | MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r | |
| 3701 | MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r | |
| 3702 | MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r | |
| 3703 | MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r | |
| 3704 | MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r | |
| 3705 | MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r | |
| 3706 | MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r | |
| 3707 | MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r | |
| 3708 | MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r | |
| 3709 | MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r | |
| 04c980a6 MK |
3710 | @{\r |
| 3711 | **/\r | |
| 3712 | #define MSR_IA32_MC0_MISC 0x00000403\r | |
| 3713 | #define MSR_IA32_MC1_MISC 0x00000407\r | |
| 3714 | #define MSR_IA32_MC2_MISC 0x0000040B\r | |
| 3715 | #define MSR_IA32_MC3_MISC 0x0000040F\r | |
| 3716 | #define MSR_IA32_MC4_MISC 0x00000413\r | |
| 3717 | #define MSR_IA32_MC5_MISC 0x00000417\r | |
| 3718 | #define MSR_IA32_MC6_MISC 0x0000041B\r | |
| 3719 | #define MSR_IA32_MC7_MISC 0x0000041F\r | |
| 3720 | #define MSR_IA32_MC8_MISC 0x00000423\r | |
| 3721 | #define MSR_IA32_MC9_MISC 0x00000427\r | |
| 3722 | #define MSR_IA32_MC10_MISC 0x0000042B\r | |
| 3723 | #define MSR_IA32_MC11_MISC 0x0000042F\r | |
| 3724 | #define MSR_IA32_MC12_MISC 0x00000433\r | |
| 3725 | #define MSR_IA32_MC13_MISC 0x00000437\r | |
| 3726 | #define MSR_IA32_MC14_MISC 0x0000043B\r | |
| 3727 | #define MSR_IA32_MC15_MISC 0x0000043F\r | |
| 3728 | #define MSR_IA32_MC16_MISC 0x00000443\r | |
| 3729 | #define MSR_IA32_MC17_MISC 0x00000447\r | |
| 3730 | #define MSR_IA32_MC18_MISC 0x0000044B\r | |
| 3731 | #define MSR_IA32_MC19_MISC 0x0000044F\r | |
| 3732 | #define MSR_IA32_MC20_MISC 0x00000453\r | |
| 3733 | #define MSR_IA32_MC21_MISC 0x00000457\r | |
| 3734 | #define MSR_IA32_MC22_MISC 0x0000045B\r | |
| 3735 | #define MSR_IA32_MC23_MISC 0x0000045F\r | |
| 3736 | #define MSR_IA32_MC24_MISC 0x00000463\r | |
| 3737 | #define MSR_IA32_MC25_MISC 0x00000467\r | |
| 3738 | #define MSR_IA32_MC26_MISC 0x0000046B\r | |
| 3739 | #define MSR_IA32_MC27_MISC 0x0000046F\r | |
| 3740 | #define MSR_IA32_MC28_MISC 0x00000473\r | |
| 3741 | /// @}\r | |
| 3742 | \r | |
| 3743 | \r | |
| 3744 | /**\r | |
| 3745 | Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r | |
| 3746 | VMX Information.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3747 | \r | |
| 3748 | @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r | |
| 3749 | @param EAX Lower 32-bits of MSR value.\r | |
| 3750 | @param EDX Upper 32-bits of MSR value.\r | |
| 3751 | \r | |
| 3752 | <b>Example usage</b>\r | |
| 3753 | @code\r | |
| 831d287a | 3754 | MSR_IA32_VMX_BASIC_REGISTER Msr;\r |
| 04c980a6 | 3755 | \r |
| 831d287a | 3756 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r |
| 04c980a6 | 3757 | @endcode\r |
| 7de98828 | 3758 | @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r |
| 04c980a6 MK |
3759 | **/\r |
| 3760 | #define MSR_IA32_VMX_BASIC 0x00000480\r | |
| 3761 | \r | |
| 831d287a MK |
3762 | /**\r |
| 3763 | MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r | |
| 3764 | **/\r | |
| 3765 | typedef union {\r | |
| 3766 | ///\r | |
| 3767 | /// Individual bit fields\r | |
| 3768 | ///\r | |
| 3769 | struct {\r | |
| 3770 | ///\r | |
| 3771 | /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r | |
| 3772 | /// that use the same VMCS revision identifier use the same size for VMCS\r | |
| 3773 | /// regions (see subsequent item on bits 44:32).\r | |
| 3774 | ///\r | |
| 3775 | /// @note Earlier versions of this manual specified that the VMCS revision\r | |
| 3776 | /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r | |
| 3777 | /// processors produced prior to this change, bit 31 of this MSR was read\r | |
| 3778 | /// as 0.\r | |
| 3779 | ///\r | |
| 3780 | UINT32 VmcsRevisonId:31;\r | |
| 3781 | UINT32 MustBeZero:1;\r | |
| 3782 | ///\r | |
| 3783 | /// [Bit 44:32] Reports the number of bytes that software should allocate\r | |
| 3784 | /// for the VMXON region and any VMCS region. It is a value greater than\r | |
| 3785 | /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r | |
| 3786 | ///\r | |
| 3787 | UINT32 VmcsSize:13;\r | |
| 3788 | UINT32 Reserved1:3;\r | |
| 3789 | ///\r | |
| 3790 | /// [Bit 48] Indicates the width of the physical addresses that may be used\r | |
| 3791 | /// for the VMXON region, each VMCS, and data structures referenced by\r | |
| 3792 | /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r | |
| 3793 | /// transitions). If the bit is 0, these addresses are limited to the\r | |
| 3794 | /// processor's physical-address width. If the bit is 1, these addresses\r | |
| 3795 | /// are limited to 32 bits. This bit is always 0 for processors that\r | |
| 3796 | /// support Intel 64 architecture.\r | |
| 3797 | ///\r | |
| 3798 | /// @note On processors that support Intel 64 architecture, the pointer\r | |
| 3799 | /// must not set bits beyond the processor's physical address width.\r | |
| 3800 | ///\r | |
| 3801 | UINT32 VmcsAddressWidth:1;\r | |
| 3802 | ///\r | |
| 3803 | /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r | |
| 3804 | /// dual-monitor treatment of system-management interrupts and\r | |
| 3805 | /// system-management mode. See Section 34.15 for details of this treatment.\r | |
| 3806 | ///\r | |
| 3807 | UINT32 DualMonitor:1;\r | |
| 3808 | ///\r | |
| 3809 | /// [Bit 53:50] report the memory type that should be used for the VMCS,\r | |
| 3810 | /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r | |
| 3811 | /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r | |
| 3812 | /// header. If software needs to access these data structures (e.g., to\r | |
| 3813 | /// modify the contents of the MSR bitmaps), it can configure the paging\r | |
| 3814 | /// structures to map them into the linear-address space. If it does so,\r | |
| 3815 | /// it should establish mappings that use the memory type reported bits\r | |
| 3816 | /// 53:50 in this MSR.\r | |
| 3817 | ///\r | |
| 3818 | /// As of this writing, all processors that support VMX operation indicate\r | |
| 3819 | /// the write-back type.\r | |
| 3820 | ///\r | |
| 3821 | /// If software needs to access these data structures (e.g., to modify\r | |
| 3822 | /// the contents of the MSR bitmaps), it can configure the paging\r | |
| 3823 | /// structures to map them into the linear-address space. If it does so,\r | |
| 3824 | /// it should establish mappings that use the memory type reported in this\r | |
| 3825 | /// MSR.\r | |
| 3826 | ///\r | |
| 3827 | /// @note Alternatively, software may map any of these regions or\r | |
| 3828 | /// structures with the UC memory type. (This may be necessary for the MSEG\r | |
| 3829 | /// header.) Doing so is discouraged unless necessary as it will cause the\r | |
| 3830 | /// performance of software accesses to those structures to suffer.\r | |
| 3831 | ///\r | |
| 3832 | ///\r | |
| 3833 | UINT32 MemoryType:4;\r | |
| 3834 | ///\r | |
| 0f16be6d HW |
3835 | /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r |
| 3836 | /// the VM-exit instruction-information field on VM exitsdue to execution\r | |
| 3837 | /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r | |
| 3838 | /// is done only if this bit is read as 1.\r | |
| 831d287a MK |
3839 | ///\r |
| 3840 | UINT32 InsOutsReporting:1;\r | |
| 3841 | ///\r | |
| 3842 | /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r | |
| 3843 | /// be cleared to 0. See Appendix A.2 for details. It also reports support\r | |
| 3844 | /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r | |
| 3845 | /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r | |
| 3846 | /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r | |
| 3847 | /// Appendix A.4, and Appendix A.5 for details.\r | |
| 3848 | ///\r | |
| 3849 | UINT32 VmxControls:1;\r | |
| 3850 | UINT32 Reserved2:8;\r | |
| 3851 | } Bits;\r | |
| 3852 | ///\r | |
| 3853 | /// All bit fields as a 64-bit value\r | |
| 3854 | ///\r | |
| 3855 | UINT64 Uint64;\r | |
| 3856 | } MSR_IA32_VMX_BASIC_REGISTER;\r | |
| 3857 | \r | |
| 3858 | ///\r | |
| 3859 | /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r | |
| 3860 | ///\r | |
| 3861 | #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r | |
| 3862 | #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r | |
| 3863 | ///\r | |
| 3864 | /// @}\r | |
| 3865 | ///\r | |
| 3866 | \r | |
| 04c980a6 MK |
3867 | \r |
| 3868 | /**\r | |
| 3869 | Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r | |
| 3870 | Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3871 | \r | |
| 3872 | @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r | |
| 3873 | @param EAX Lower 32-bits of MSR value.\r | |
| 3874 | @param EDX Upper 32-bits of MSR value.\r | |
| 3875 | \r | |
| 3876 | <b>Example usage</b>\r | |
| 3877 | @code\r | |
| 3878 | UINT64 Msr;\r | |
| 3879 | \r | |
| 3880 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r | |
| 3881 | @endcode\r | |
| 7de98828 | 3882 | @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3883 | **/\r |
| 3884 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r | |
| 3885 | \r | |
| 3886 | \r | |
| 3887 | /**\r | |
| 3888 | Capability Reporting Register of Primary Processor-based VM-execution\r | |
| 3889 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
| 3890 | Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3891 | \r | |
| 3892 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r | |
| 3893 | @param EAX Lower 32-bits of MSR value.\r | |
| 3894 | @param EDX Upper 32-bits of MSR value.\r | |
| 3895 | \r | |
| 3896 | <b>Example usage</b>\r | |
| 3897 | @code\r | |
| 3898 | UINT64 Msr;\r | |
| 3899 | \r | |
| 3900 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r | |
| 3901 | @endcode\r | |
| 7de98828 | 3902 | @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3903 | **/\r |
| 3904 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r | |
| 3905 | \r | |
| 3906 | \r | |
| 3907 | /**\r | |
| 3908 | Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r | |
| 3909 | "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3910 | \r | |
| 3911 | @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r | |
| 3912 | @param EAX Lower 32-bits of MSR value.\r | |
| 3913 | @param EDX Upper 32-bits of MSR value.\r | |
| 3914 | \r | |
| 3915 | <b>Example usage</b>\r | |
| 3916 | @code\r | |
| 3917 | UINT64 Msr;\r | |
| 3918 | \r | |
| 3919 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r | |
| 3920 | @endcode\r | |
| 7de98828 | 3921 | @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r |
| 04c980a6 MK |
3922 | **/\r |
| 3923 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r | |
| 3924 | \r | |
| 3925 | \r | |
| 3926 | /**\r | |
| 3927 | Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r | |
| 3928 | "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3929 | \r | |
| 3930 | @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r | |
| 3931 | @param EAX Lower 32-bits of MSR value.\r | |
| 3932 | @param EDX Upper 32-bits of MSR value.\r | |
| 3933 | \r | |
| 3934 | <b>Example usage</b>\r | |
| 3935 | @code\r | |
| 3936 | UINT64 Msr;\r | |
| 3937 | \r | |
| 3938 | Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r | |
| 3939 | @endcode\r | |
| 7de98828 | 3940 | @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r |
| 04c980a6 MK |
3941 | **/\r |
| 3942 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r | |
| 3943 | \r | |
| 3944 | \r | |
| 3945 | /**\r | |
| 3946 | Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r | |
| 3947 | "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3948 | \r | |
| 3949 | @param ECX MSR_IA32_VMX_MISC (0x00000485)\r | |
| 3950 | @param EAX Lower 32-bits of MSR value.\r | |
| 3951 | @param EDX Upper 32-bits of MSR value.\r | |
| 3952 | \r | |
| 3953 | <b>Example usage</b>\r | |
| 3954 | @code\r | |
| 831d287a | 3955 | IA32_VMX_MISC_REGISTER Msr;\r |
| 04c980a6 | 3956 | \r |
| 831d287a | 3957 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r |
| 04c980a6 | 3958 | @endcode\r |
| 7de98828 | 3959 | @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r |
| 04c980a6 MK |
3960 | **/\r |
| 3961 | #define MSR_IA32_VMX_MISC 0x00000485\r | |
| 3962 | \r | |
| 831d287a MK |
3963 | /**\r |
| 3964 | MSR information returned for MSR index #IA32_VMX_MISC\r | |
| 3965 | **/\r | |
| 3966 | typedef union {\r | |
| 3967 | ///\r | |
| 3968 | /// Individual bit fields\r | |
| 3969 | ///\r | |
| 3970 | struct {\r | |
| 3971 | ///\r | |
| 3972 | /// [Bits 4:0] Reports a value X that specifies the relationship between the\r | |
| 3973 | /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r | |
| 3974 | /// Specifically, the VMX-preemption timer (if it is active) counts down by\r | |
| 3975 | /// 1 every time bit X in the TSC changes due to a TSC increment.\r | |
| 3976 | ///\r | |
| 3977 | UINT32 VmxTimerRatio:5;\r | |
| 3978 | ///\r | |
| 3979 | /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r | |
| 3980 | /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r | |
| 3981 | /// details. This bit is read as 1 on any logical processor that supports\r | |
| 3982 | /// the 1-setting of the "unrestricted guest" VM-execution control.\r | |
| 3983 | ///\r | |
| 3984 | UINT32 VmExitEferLma:1;\r | |
| 3985 | ///\r | |
| 3986 | /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r | |
| 3987 | ///\r | |
| 3988 | UINT32 HltActivityStateSupported:1;\r | |
| 3989 | ///\r | |
| 3990 | /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r | |
| 3991 | ///\r | |
| 3992 | UINT32 ShutdownActivityStateSupported:1;\r | |
| 3993 | ///\r | |
| 3994 | /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r | |
| 3995 | ///\r | |
| 3996 | UINT32 WaitForSipiActivityStateSupported:1;\r | |
| 0f16be6d HW |
3997 | UINT32 Reserved1:5;\r |
| 3998 | ///\r | |
| 3999 | /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r | |
| 4000 | /// in VMX operation. If the processor supports Intel PT but does not allow\r | |
| 4001 | /// it to be used in VMX operation, execution of VMXON clears\r | |
| 3b4640ee | 4002 | /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r |
| 0f16be6d HW |
4003 | /// any attempt to set that bit while in VMX operation (including VMX root\r |
| 4004 | /// operation) using the WRMSR instruction causes a general-protection\r | |
| 4005 | /// exception.\r | |
| 4006 | ///\r | |
| 4007 | UINT32 ProcessorTraceSupported:1;\r | |
| 831d287a MK |
4008 | ///\r |
| 4009 | /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r | |
| 4010 | /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r | |
| 0f16be6d | 4011 | /// See Section 34.15.6.3.\r |
| 831d287a MK |
4012 | ///\r |
| 4013 | UINT32 SmBaseMsrSupported:1;\r | |
| 4014 | ///\r | |
| 4015 | /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r | |
| 4016 | /// processor. This number is a value between 0 and 256, inclusive (bit 24\r | |
| 4017 | /// is set if and only if bits 23:16 are clear).\r | |
| 4018 | ///\r | |
| 4019 | UINT32 NumberOfCr3TargetValues:9;\r | |
| 4020 | ///\r | |
| 4021 | /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r | |
| 4022 | /// number of MSRs that should appear in the VM-exit MSR-store list, the\r | |
| 4023 | /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r | |
| 4024 | /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r | |
| 4025 | /// recommended maximum number of MSRs to be included in each list. If the\r | |
| 4026 | /// limit is exceeded, undefined processor behavior may result (including a\r | |
| 4027 | /// machine check during the VMX transition).\r | |
| 4028 | ///\r | |
| 4029 | UINT32 MsrStoreListMaximum:3;\r | |
| 4030 | ///\r | |
| 4031 | /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r | |
| 4032 | /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r | |
| 4033 | /// (see Section 34.14.4).\r | |
| 4034 | ///\r | |
| 4035 | UINT32 BlockSmiSupported:1;\r | |
| 4036 | ///\r | |
| 4037 | /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r | |
| 4038 | /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r | |
| 4039 | /// information fields.\r | |
| 4040 | ///\r | |
| 4041 | UINT32 VmWriteSupported:1;\r | |
| 0f16be6d HW |
4042 | ///\r |
| 4043 | /// [Bit 30] If read as 1, VM entry allows injection of a software\r | |
| 4044 | /// interrupt, software exception, or privileged software exception with an\r | |
| 4045 | /// instruction length of 0.\r | |
| 4046 | ///\r | |
| 4047 | UINT32 VmInjectSupported:1;\r | |
| 4048 | UINT32 Reserved2:1;\r | |
| 831d287a MK |
4049 | ///\r |
| 4050 | /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r | |
| 4051 | /// processor.\r | |
| 4052 | ///\r | |
| 4053 | UINT32 MsegRevisionIdentifier:32;\r | |
| 4054 | } Bits;\r | |
| 4055 | ///\r | |
| 4056 | /// All bit fields as a 64-bit value\r | |
| 4057 | ///\r | |
| 4058 | UINT64 Uint64;\r | |
| 4059 | } IA32_VMX_MISC_REGISTER;\r | |
| 4060 | \r | |
| 04c980a6 MK |
4061 | \r |
| 4062 | /**\r | |
| 4063 | Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r | |
| 4064 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4065 | \r | |
| 4066 | @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r | |
| 4067 | @param EAX Lower 32-bits of MSR value.\r | |
| 4068 | @param EDX Upper 32-bits of MSR value.\r | |
| 4069 | \r | |
| 4070 | <b>Example usage</b>\r | |
| 4071 | @code\r | |
| 4072 | UINT64 Msr;\r | |
| 4073 | \r | |
| 4074 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r | |
| 4075 | @endcode\r | |
| 7de98828 | 4076 | @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r |
| 04c980a6 MK |
4077 | **/\r |
| 4078 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r | |
| 4079 | \r | |
| 4080 | \r | |
| 4081 | /**\r | |
| 4082 | Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r | |
| 4083 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4084 | \r | |
| 4085 | @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r | |
| 4086 | @param EAX Lower 32-bits of MSR value.\r | |
| 4087 | @param EDX Upper 32-bits of MSR value.\r | |
| 4088 | \r | |
| 4089 | <b>Example usage</b>\r | |
| 4090 | @code\r | |
| 4091 | UINT64 Msr;\r | |
| 4092 | \r | |
| 4093 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r | |
| 4094 | @endcode\r | |
| 7de98828 | 4095 | @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r |
| 04c980a6 MK |
4096 | **/\r |
| 4097 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r | |
| 4098 | \r | |
| 4099 | \r | |
| 4100 | /**\r | |
| 4101 | Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r | |
| 4102 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4103 | \r | |
| 4104 | @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r | |
| 4105 | @param EAX Lower 32-bits of MSR value.\r | |
| 4106 | @param EDX Upper 32-bits of MSR value.\r | |
| 4107 | \r | |
| 4108 | <b>Example usage</b>\r | |
| 4109 | @code\r | |
| 4110 | UINT64 Msr;\r | |
| 4111 | \r | |
| 4112 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r | |
| 4113 | @endcode\r | |
| 7de98828 | 4114 | @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r |
| 04c980a6 MK |
4115 | **/\r |
| 4116 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r | |
| 4117 | \r | |
| 4118 | \r | |
| 4119 | /**\r | |
| 4120 | Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r | |
| 4121 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4122 | \r | |
| 4123 | @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r | |
| 4124 | @param EAX Lower 32-bits of MSR value.\r | |
| 4125 | @param EDX Upper 32-bits of MSR value.\r | |
| 4126 | \r | |
| 4127 | <b>Example usage</b>\r | |
| 4128 | @code\r | |
| 4129 | UINT64 Msr;\r | |
| 4130 | \r | |
| 4131 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r | |
| 4132 | @endcode\r | |
| 7de98828 | 4133 | @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r |
| 04c980a6 MK |
4134 | **/\r |
| 4135 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r | |
| 4136 | \r | |
| 4137 | \r | |
| 4138 | /**\r | |
| 4139 | Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r | |
| 4140 | A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4141 | \r | |
| 4142 | @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r | |
| 4143 | @param EAX Lower 32-bits of MSR value.\r | |
| 4144 | @param EDX Upper 32-bits of MSR value.\r | |
| 4145 | \r | |
| 4146 | <b>Example usage</b>\r | |
| 4147 | @code\r | |
| 4148 | UINT64 Msr;\r | |
| 4149 | \r | |
| 4150 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r | |
| 4151 | @endcode\r | |
| 7de98828 | 4152 | @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r |
| 04c980a6 MK |
4153 | **/\r |
| 4154 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r | |
| 4155 | \r | |
| 4156 | \r | |
| 4157 | /**\r | |
| 4158 | Capability Reporting Register of Secondary Processor-based VM-execution\r | |
| 4159 | Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r | |
| 4160 | Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r | |
| 4161 | \r | |
| 4162 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r | |
| 4163 | @param EAX Lower 32-bits of MSR value.\r | |
| 4164 | @param EDX Upper 32-bits of MSR value.\r | |
| 4165 | \r | |
| 4166 | <b>Example usage</b>\r | |
| 4167 | @code\r | |
| 4168 | UINT64 Msr;\r | |
| 4169 | \r | |
| 4170 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r | |
| 4171 | @endcode\r | |
| 7de98828 | 4172 | @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r |
| 04c980a6 MK |
4173 | **/\r |
| 4174 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r | |
| 4175 | \r | |
| 4176 | \r | |
| 4177 | /**\r | |
| 4178 | Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r | |
| 4179 | "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r | |
| 4180 | TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r | |
| 4181 | \r | |
| 4182 | @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r | |
| 4183 | @param EAX Lower 32-bits of MSR value.\r | |
| 4184 | @param EDX Upper 32-bits of MSR value.\r | |
| 4185 | \r | |
| 4186 | <b>Example usage</b>\r | |
| 4187 | @code\r | |
| 4188 | UINT64 Msr;\r | |
| 4189 | \r | |
| 4190 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r | |
| 4191 | @endcode\r | |
| 7de98828 | 4192 | @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r |
| 04c980a6 MK |
4193 | **/\r |
| 4194 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r | |
| 4195 | \r | |
| 4196 | \r | |
| 4197 | /**\r | |
| 4198 | Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r | |
| 4199 | See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r | |
| 4200 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4201 | \r | |
| 4202 | @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r | |
| 4203 | @param EAX Lower 32-bits of MSR value.\r | |
| 4204 | @param EDX Upper 32-bits of MSR value.\r | |
| 4205 | \r | |
| 4206 | <b>Example usage</b>\r | |
| 4207 | @code\r | |
| 4208 | UINT64 Msr;\r | |
| 4209 | \r | |
| 4210 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r | |
| 4211 | @endcode\r | |
| 7de98828 | 4212 | @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r |
| 04c980a6 MK |
4213 | **/\r |
| 4214 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r | |
| 4215 | \r | |
| 4216 | \r | |
| 4217 | /**\r | |
| 4218 | Capability Reporting Register of Primary Processor-based VM-execution Flex\r | |
| 4219 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
| 4220 | Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4221 | \r | |
| 4222 | @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r | |
| 4223 | @param EAX Lower 32-bits of MSR value.\r | |
| 4224 | @param EDX Upper 32-bits of MSR value.\r | |
| 4225 | \r | |
| 4226 | <b>Example usage</b>\r | |
| 4227 | @code\r | |
| 4228 | UINT64 Msr;\r | |
| 4229 | \r | |
| 4230 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r | |
| 4231 | @endcode\r | |
| 7de98828 | 4232 | @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r |
| 04c980a6 MK |
4233 | **/\r |
| 4234 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r | |
| 4235 | \r | |
| 4236 | \r | |
| 4237 | /**\r | |
| 4238 | Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r | |
| 4239 | A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4240 | \r | |
| 4241 | @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r | |
| 4242 | @param EAX Lower 32-bits of MSR value.\r | |
| 4243 | @param EDX Upper 32-bits of MSR value.\r | |
| 4244 | \r | |
| 4245 | <b>Example usage</b>\r | |
| 4246 | @code\r | |
| 4247 | UINT64 Msr;\r | |
| 4248 | \r | |
| 4249 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r | |
| 4250 | @endcode\r | |
| 7de98828 | 4251 | @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r |
| 04c980a6 MK |
4252 | **/\r |
| 4253 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r | |
| 4254 | \r | |
| 4255 | \r | |
| 4256 | /**\r | |
| 4257 | Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r | |
| 4258 | A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4259 | \r | |
| 4260 | @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r | |
| 4261 | @param EAX Lower 32-bits of MSR value.\r | |
| 4262 | @param EDX Upper 32-bits of MSR value.\r | |
| 4263 | \r | |
| 4264 | <b>Example usage</b>\r | |
| 4265 | @code\r | |
| 4266 | UINT64 Msr;\r | |
| 4267 | \r | |
| 4268 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r | |
| 4269 | @endcode\r | |
| 7de98828 | 4270 | @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r |
| 04c980a6 MK |
4271 | **/\r |
| 4272 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r | |
| 4273 | \r | |
| 4274 | \r | |
| 4275 | /**\r | |
| 4276 | Capability Reporting Register of VMfunction Controls (R/O). If(\r | |
| 4277 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4278 | \r | |
| 4279 | @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)\r | |
| 4280 | @param EAX Lower 32-bits of MSR value.\r | |
| 4281 | @param EDX Upper 32-bits of MSR value.\r | |
| 4282 | \r | |
| 4283 | <b>Example usage</b>\r | |
| 4284 | @code\r | |
| 4285 | UINT64 Msr;\r | |
| 4286 | \r | |
| 4287 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r | |
| 4288 | @endcode\r | |
| 7de98828 | 4289 | @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r |
| 04c980a6 MK |
4290 | **/\r |
| 4291 | #define MSR_IA32_VMX_VMFUNC 0x00000491\r | |
| 4292 | \r | |
| 4293 | \r | |
| 4294 | /**\r | |
| 4295 | Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r | |
| 4296 | IA32_PERF_CAPABILITIES[ 13] = 1.\r | |
| 4297 | \r | |
| 4298 | @param ECX MSR_IA32_A_PMCn\r | |
| 4299 | @param EAX Lower 32-bits of MSR value.\r | |
| 4300 | @param EDX Upper 32-bits of MSR value.\r | |
| 4301 | \r | |
| 4302 | <b>Example usage</b>\r | |
| 4303 | @code\r | |
| 4304 | UINT64 Msr;\r | |
| 4305 | \r | |
| 4306 | Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r | |
| 4307 | AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r | |
| 4308 | @endcode\r | |
| 7de98828 JF |
4309 | @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r |
| 4310 | MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r | |
| 4311 | MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r | |
| 4312 | MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r | |
| 4313 | MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r | |
| 4314 | MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r | |
| 4315 | MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r | |
| 4316 | MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r | |
| 04c980a6 MK |
4317 | @{\r |
| 4318 | **/\r | |
| 4319 | #define MSR_IA32_A_PMC0 0x000004C1\r | |
| 4320 | #define MSR_IA32_A_PMC1 0x000004C2\r | |
| 4321 | #define MSR_IA32_A_PMC2 0x000004C3\r | |
| 4322 | #define MSR_IA32_A_PMC3 0x000004C4\r | |
| 4323 | #define MSR_IA32_A_PMC4 0x000004C5\r | |
| 4324 | #define MSR_IA32_A_PMC5 0x000004C6\r | |
| 4325 | #define MSR_IA32_A_PMC6 0x000004C7\r | |
| 4326 | #define MSR_IA32_A_PMC7 0x000004C8\r | |
| 4327 | /// @}\r | |
| 4328 | \r | |
| 4329 | \r | |
| 4330 | /**\r | |
| 4331 | (R/W). If IA32_MCG_CAP.LMCE_P =1.\r | |
| 4332 | \r | |
| 4333 | @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)\r | |
| 4334 | @param EAX Lower 32-bits of MSR value.\r | |
| 4335 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
| 4336 | @param EDX Upper 32-bits of MSR value.\r | |
| 4337 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
| 4338 | \r | |
| 4339 | <b>Example usage</b>\r | |
| 4340 | @code\r | |
| 4341 | MSR_IA32_MCG_EXT_CTL_REGISTER Msr;\r | |
| 4342 | \r | |
| 4343 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r | |
| 4344 | AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r | |
| 4345 | @endcode\r | |
| 7de98828 | 4346 | @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r |
| 04c980a6 MK |
4347 | **/\r |
| 4348 | #define MSR_IA32_MCG_EXT_CTL 0x000004D0\r | |
| 4349 | \r | |
| 4350 | /**\r | |
| 4351 | MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r | |
| 4352 | **/\r | |
| 4353 | typedef union {\r | |
| 4354 | ///\r | |
| 4355 | /// Individual bit fields\r | |
| 4356 | ///\r | |
| 4357 | struct {\r | |
| 4358 | ///\r | |
| 4359 | /// [Bit 0] LMCE_EN.\r | |
| 4360 | ///\r | |
| 4361 | UINT32 LMCE_EN:1;\r | |
| 4362 | UINT32 Reserved1:31;\r | |
| 4363 | UINT32 Reserved2:32;\r | |
| 4364 | } Bits;\r | |
| 4365 | ///\r | |
| 4366 | /// All bit fields as a 32-bit value\r | |
| 4367 | ///\r | |
| 4368 | UINT32 Uint32;\r | |
| 4369 | ///\r | |
| 4370 | /// All bit fields as a 64-bit value\r | |
| 4371 | ///\r | |
| 4372 | UINT64 Uint64;\r | |
| 4373 | } MSR_IA32_MCG_EXT_CTL_REGISTER;\r | |
| 4374 | \r | |
| 4375 | \r | |
| 4376 | /**\r | |
| 4377 | Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r | |
| 4378 | ECX=0H): EBX[2] = 1.\r | |
| 4379 | \r | |
| 4380 | @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)\r | |
| 4381 | @param EAX Lower 32-bits of MSR value.\r | |
| 4382 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
| 4383 | @param EDX Upper 32-bits of MSR value.\r | |
| 4384 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
| 4385 | \r | |
| 4386 | <b>Example usage</b>\r | |
| 4387 | @code\r | |
| 4388 | MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;\r | |
| 4389 | \r | |
| 4390 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r | |
| 4391 | @endcode\r | |
| 7de98828 | 4392 | @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r |
| 04c980a6 MK |
4393 | **/\r |
| 4394 | #define MSR_IA32_SGX_SVN_STATUS 0x00000500\r | |
| 4395 | \r | |
| 4396 | /**\r | |
| 4397 | MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r | |
| 4398 | **/\r | |
| 4399 | typedef union {\r | |
| 4400 | ///\r | |
| 4401 | /// Individual bit fields\r | |
| 4402 | ///\r | |
| 4403 | struct {\r | |
| 4404 | ///\r | |
| ba1a2d11 | 4405 | /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated\r |
| 04c980a6 MK |
4406 | /// Code Modules (ACMs)".\r |
| 4407 | ///\r | |
| 4408 | UINT32 Lock:1;\r | |
| 4409 | UINT32 Reserved1:15;\r | |
| 4410 | ///\r | |
| ba1a2d11 | 4411 | /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with\r |
| 04c980a6 MK |
4412 | /// Authenticated Code Modules (ACMs)".\r |
| 4413 | ///\r | |
| 4414 | UINT32 SGX_SVN_SINIT:8;\r | |
| 4415 | UINT32 Reserved2:8;\r | |
| 4416 | UINT32 Reserved3:32;\r | |
| 4417 | } Bits;\r | |
| 4418 | ///\r | |
| 4419 | /// All bit fields as a 32-bit value\r | |
| 4420 | ///\r | |
| 4421 | UINT32 Uint32;\r | |
| 4422 | ///\r | |
| 4423 | /// All bit fields as a 64-bit value\r | |
| 4424 | ///\r | |
| 4425 | UINT64 Uint64;\r | |
| 4426 | } MSR_IA32_SGX_SVN_STATUS_REGISTER;\r | |
| 4427 | \r | |
| 4428 | \r | |
| 4429 | /**\r | |
| 4430 | Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
| 4431 | && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r | |
| 4432 | ) ).\r | |
| 4433 | \r | |
| 4434 | @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r | |
| 4435 | @param EAX Lower 32-bits of MSR value.\r | |
| 4436 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
| 4437 | @param EDX Upper 32-bits of MSR value.\r | |
| 4438 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
| 4439 | \r | |
| 4440 | <b>Example usage</b>\r | |
| 4441 | @code\r | |
| 4442 | MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;\r | |
| 4443 | \r | |
| 4444 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r | |
| 4445 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r | |
| 4446 | @endcode\r | |
| 7de98828 | 4447 | @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r |
| 04c980a6 MK |
4448 | **/\r |
| 4449 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r | |
| 4450 | \r | |
| 4451 | /**\r | |
| 4452 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r | |
| 4453 | **/\r | |
| 4454 | typedef union {\r | |
| 4455 | ///\r | |
| 4456 | /// Individual bit fields\r | |
| 4457 | ///\r | |
| 4458 | struct {\r | |
| 4459 | UINT32 Reserved:7;\r | |
| 4460 | ///\r | |
| 4461 | /// [Bits 31:7] Base physical address.\r | |
| 4462 | ///\r | |
| 4463 | UINT32 Base:25;\r | |
| 4464 | ///\r | |
| 4465 | /// [Bits 63:32] Base physical address.\r | |
| 4466 | ///\r | |
| 4467 | UINT32 BaseHi:32;\r | |
| 4468 | } Bits;\r | |
| 4469 | ///\r | |
| 4470 | /// All bit fields as a 64-bit value\r | |
| 4471 | ///\r | |
| 4472 | UINT64 Uint64;\r | |
| 4473 | } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r | |
| 4474 | \r | |
| 4475 | \r | |
| 4476 | /**\r | |
| 4477 | Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r | |
| 4478 | ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r | |
| 4479 | (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r | |
| 4480 | \r | |
| 4481 | @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r | |
| 4482 | @param EAX Lower 32-bits of MSR value.\r | |
| 4483 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
| 4484 | @param EDX Upper 32-bits of MSR value.\r | |
| 4485 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
| 4486 | \r | |
| 4487 | <b>Example usage</b>\r | |
| 4488 | @code\r | |
| 4489 | MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;\r | |
| 4490 | \r | |
| 4491 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r | |
| 4492 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r | |
| 4493 | @endcode\r | |
| 7de98828 | 4494 | @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r |
| 04c980a6 MK |
4495 | **/\r |
| 4496 | #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r | |
| 4497 | \r | |
| 4498 | /**\r | |
| 4499 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r | |
| 4500 | **/\r | |
| 4501 | typedef union {\r | |
| 4502 | ///\r | |
| 4503 | /// Individual bit fields\r | |
| 4504 | ///\r | |
| 4505 | struct {\r | |
| 4506 | UINT32 Reserved:7;\r | |
| 4507 | ///\r | |
| 4508 | /// [Bits 31:7] MaskOrTableOffset.\r | |
| 4509 | ///\r | |
| 4510 | UINT32 MaskOrTableOffset:25;\r | |
| 4511 | ///\r | |
| 4512 | /// [Bits 63:32] Output Offset.\r | |
| 4513 | ///\r | |
| 4514 | UINT32 OutputOffset:32;\r | |
| 4515 | } Bits;\r | |
| 4516 | ///\r | |
| 4517 | /// All bit fields as a 64-bit value\r | |
| 4518 | ///\r | |
| 4519 | UINT64 Uint64;\r | |
| 4520 | } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r | |
| 4521 | \r | |
| a2e24a2a ED |
4522 | /**\r |
| 4523 | Format of ToPA table entries.\r | |
| 4524 | **/\r | |
| 4525 | typedef union {\r | |
| 4526 | ///\r | |
| 4527 | /// Individual bit fields\r | |
| 4528 | ///\r | |
| 4529 | struct {\r | |
| 4530 | ///\r | |
| 4531 | /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r | |
| 4532 | ///\r | |
| 4533 | UINT32 END:1;\r | |
| 4534 | UINT32 Reserved1:1;\r | |
| 4535 | ///\r | |
| 4536 | /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r | |
| 4537 | ///\r | |
| 4538 | UINT32 INT:1;\r | |
| 4539 | UINT32 Reserved2:1;\r | |
| 4540 | ///\r | |
| 4541 | /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r | |
| 4542 | ///\r | |
| 4543 | UINT32 STOP:1;\r | |
| 4544 | UINT32 Reserved3:1;\r | |
| 4545 | ///\r | |
| 4546 | /// [Bit 6:9] Indicates the size of the associated output region. See Section\r | |
| 4547 | /// 35.2.6.2, "Table of Physical Addresses (ToPA)".\r | |
| 4548 | ///\r | |
| 4549 | UINT32 Size:4;\r | |
| 4550 | UINT32 Reserved4:2;\r | |
| 4551 | ///\r | |
| 4552 | /// [Bit 12:31] Output Region Base Physical Address low part.\r | |
| 4553 | /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.\r | |
| 4554 | /// ATTENTION: The size of the address field is determined by the processor's\r | |
| 4555 | /// physical-address width (MAXPHYADDR) in bits, as reported in\r | |
| 4556 | /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r | |
| 4557 | /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r | |
| 4558 | /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r | |
| 4559 | ///\r | |
| 4560 | UINT32 Base:20;\r | |
| 4561 | ///\r | |
| 4562 | /// [Bit 32:63] Output Region Base Physical Address high part.\r | |
| 4563 | /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.\r | |
| 4564 | /// ATTENTION: The size of the address field is determined by the processor's\r | |
| 4565 | /// physical-address width (MAXPHYADDR) in bits, as reported in\r | |
| 4566 | /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r | |
| 4567 | /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r | |
| 4568 | /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r | |
| 4569 | ///\r | |
| 4570 | UINT32 BaseHi:32;\r | |
| 4571 | } Bits;\r | |
| 4572 | ///\r | |
| 4573 | /// All bit fields as a 64-bit value\r | |
| 4574 | ///\r | |
| 4575 | UINT64 Uint64;\r | |
| 4576 | } RTIT_TOPA_TABLE_ENTRY;\r | |
| 4577 | \r | |
| 4578 | ///\r | |
| 4579 | /// The size of the associated output region usd by Topa.\r | |
| 4580 | ///\r | |
| 4581 | typedef enum {\r | |
| 4582 | RtitTopaMemorySize4K = 0,\r | |
| 4583 | RtitTopaMemorySize8K,\r | |
| 4584 | RtitTopaMemorySize16K,\r | |
| 4585 | RtitTopaMemorySize32K,\r | |
| 4586 | RtitTopaMemorySize64K,\r | |
| 4587 | RtitTopaMemorySize128K,\r | |
| 4588 | RtitTopaMemorySize256K,\r | |
| 4589 | RtitTopaMemorySize512K,\r | |
| 4590 | RtitTopaMemorySize1M,\r | |
| 4591 | RtitTopaMemorySize2M,\r | |
| 4592 | RtitTopaMemorySize4M,\r | |
| 4593 | RtitTopaMemorySize8M,\r | |
| 4594 | RtitTopaMemorySize16M,\r | |
| 4595 | RtitTopaMemorySize32M,\r | |
| 4596 | RtitTopaMemorySize64M,\r | |
| 4597 | RtitTopaMemorySize128M\r | |
| 4598 | } RTIT_TOPA_MEMORY_SIZE;\r | |
| 04c980a6 MK |
4599 | \r |
| 4600 | /**\r | |
| 4601 | Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4602 | \r | |
| 4603 | @param ECX MSR_IA32_RTIT_CTL (0x00000570)\r | |
| 4604 | @param EAX Lower 32-bits of MSR value.\r | |
| 4605 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
| 4606 | @param EDX Upper 32-bits of MSR value.\r | |
| 4607 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
| 4608 | \r | |
| 4609 | <b>Example usage</b>\r | |
| 4610 | @code\r | |
| 4611 | MSR_IA32_RTIT_CTL_REGISTER Msr;\r | |
| 4612 | \r | |
| 4613 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r | |
| 4614 | AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r | |
| 4615 | @endcode\r | |
| 7de98828 | 4616 | @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r |
| 04c980a6 MK |
4617 | **/\r |
| 4618 | #define MSR_IA32_RTIT_CTL 0x00000570\r | |
| 4619 | \r | |
| 4620 | /**\r | |
| 4621 | MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r | |
| 4622 | **/\r | |
| 4623 | typedef union {\r | |
| 4624 | ///\r | |
| 4625 | /// Individual bit fields\r | |
| 4626 | ///\r | |
| 4627 | struct {\r | |
| 4628 | ///\r | |
| 4629 | /// [Bit 0] TraceEn.\r | |
| 4630 | ///\r | |
| 4631 | UINT32 TraceEn:1;\r | |
| 4632 | ///\r | |
| 4633 | /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4634 | ///\r | |
| 4635 | UINT32 CYCEn:1;\r | |
| 4636 | ///\r | |
| 4637 | /// [Bit 2] OS.\r | |
| 4638 | ///\r | |
| 4639 | UINT32 OS:1;\r | |
| 4640 | ///\r | |
| 4641 | /// [Bit 3] User.\r | |
| 4642 | ///\r | |
| 4643 | UINT32 User:1;\r | |
| 4382394a ED |
4644 | ///\r |
| 4645 | /// [Bit 4] PwrEvtEn.\r | |
| 4646 | ///\r | |
| 4647 | UINT32 PwrEvtEn:1;\r | |
| 4648 | ///\r | |
| 4649 | /// [Bit 5] FUPonPTW.\r | |
| 4650 | ///\r | |
| 4651 | UINT32 FUPonPTW:1;\r | |
| 04c980a6 MK |
4652 | ///\r |
| 4653 | /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r | |
| 4654 | ///\r | |
| 4655 | UINT32 FabricEn:1;\r | |
| 4656 | ///\r | |
| 4657 | /// [Bit 7] CR3 filter.\r | |
| 4658 | ///\r | |
| 4659 | UINT32 CR3:1;\r | |
| 4660 | ///\r | |
| 4661 | /// [Bit 8] ToPA.\r | |
| 4662 | ///\r | |
| 4663 | UINT32 ToPA:1;\r | |
| 4664 | ///\r | |
| 4665 | /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
| 4666 | ///\r | |
| 4667 | UINT32 MTCEn:1;\r | |
| 4668 | ///\r | |
| 4669 | /// [Bit 10] TSCEn.\r | |
| 4670 | ///\r | |
| 4671 | UINT32 TSCEn:1;\r | |
| 4672 | ///\r | |
| 4673 | /// [Bit 11] DisRETC.\r | |
| 4674 | ///\r | |
| 4675 | UINT32 DisRETC:1;\r | |
| 4382394a ED |
4676 | ///\r |
| 4677 | /// [Bit 12] PTWEn.\r | |
| 4678 | ///\r | |
| 4679 | UINT32 PTWEn:1;\r | |
| 04c980a6 MK |
4680 | ///\r |
| 4681 | /// [Bit 13] BranchEn.\r | |
| 4682 | ///\r | |
| 4683 | UINT32 BranchEn:1;\r | |
| 4684 | ///\r | |
| 4685 | /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
| 4686 | ///\r | |
| 4687 | UINT32 MTCFreq:4;\r | |
| 4688 | UINT32 Reserved3:1;\r | |
| 4689 | ///\r | |
| 4690 | /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4691 | ///\r | |
| 4692 | UINT32 CYCThresh:4;\r | |
| 4693 | UINT32 Reserved4:1;\r | |
| 4694 | ///\r | |
| 4695 | /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4696 | ///\r | |
| 4697 | UINT32 PSBFreq:4;\r | |
| 4698 | UINT32 Reserved5:4;\r | |
| 4699 | ///\r | |
| 4700 | /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r | |
| 4701 | ///\r | |
| 4702 | UINT32 ADDR0_CFG:4;\r | |
| 4703 | ///\r | |
| 4704 | /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r | |
| 4705 | ///\r | |
| 4706 | UINT32 ADDR1_CFG:4;\r | |
| 4707 | ///\r | |
| 4708 | /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r | |
| 4709 | ///\r | |
| 4710 | UINT32 ADDR2_CFG:4;\r | |
| 4711 | ///\r | |
| 4712 | /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r | |
| 4713 | ///\r | |
| 4714 | UINT32 ADDR3_CFG:4;\r | |
| 4715 | UINT32 Reserved6:16;\r | |
| 4716 | } Bits;\r | |
| 4717 | ///\r | |
| 4718 | /// All bit fields as a 64-bit value\r | |
| 4719 | ///\r | |
| 4720 | UINT64 Uint64;\r | |
| 4721 | } MSR_IA32_RTIT_CTL_REGISTER;\r | |
| 4722 | \r | |
| 4723 | \r | |
| 4724 | /**\r | |
| 4725 | Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4726 | \r | |
| 4727 | @param ECX MSR_IA32_RTIT_STATUS (0x00000571)\r | |
| 4728 | @param EAX Lower 32-bits of MSR value.\r | |
| 4729 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
| 4730 | @param EDX Upper 32-bits of MSR value.\r | |
| 4731 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
| 4732 | \r | |
| 4733 | <b>Example usage</b>\r | |
| 4734 | @code\r | |
| 4735 | MSR_IA32_RTIT_STATUS_REGISTER Msr;\r | |
| 4736 | \r | |
| 4737 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r | |
| 4738 | AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r | |
| 4739 | @endcode\r | |
| 7de98828 | 4740 | @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r |
| 04c980a6 MK |
4741 | **/\r |
| 4742 | #define MSR_IA32_RTIT_STATUS 0x00000571\r | |
| 4743 | \r | |
| 4744 | /**\r | |
| 4745 | MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r | |
| 4746 | **/\r | |
| 4747 | typedef union {\r | |
| 4748 | ///\r | |
| 4749 | /// Individual bit fields\r | |
| 4750 | ///\r | |
| 4751 | struct {\r | |
| 4752 | ///\r | |
| 4753 | /// [Bit 0] FilterEn, (writes ignored).\r | |
| 4754 | /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r | |
| 4755 | ///\r | |
| 4756 | UINT32 FilterEn:1;\r | |
| 4757 | ///\r | |
| 4758 | /// [Bit 1] ContexEn, (writes ignored).\r | |
| 4759 | ///\r | |
| 4760 | UINT32 ContexEn:1;\r | |
| 4761 | ///\r | |
| 4762 | /// [Bit 2] TriggerEn, (writes ignored).\r | |
| 4763 | ///\r | |
| 4764 | UINT32 TriggerEn:1;\r | |
| 4765 | UINT32 Reserved1:1;\r | |
| 4766 | ///\r | |
| 4767 | /// [Bit 4] Error.\r | |
| 4768 | ///\r | |
| 4769 | UINT32 Error:1;\r | |
| 4770 | ///\r | |
| 4771 | /// [Bit 5] Stopped.\r | |
| 4772 | ///\r | |
| 4773 | UINT32 Stopped:1;\r | |
| 4774 | UINT32 Reserved2:26;\r | |
| 4775 | ///\r | |
| 4776 | /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r | |
| 4777 | ///\r | |
| 4778 | UINT32 PacketByteCnt:17;\r | |
| 4779 | UINT32 Reserved3:15;\r | |
| 4780 | } Bits;\r | |
| 4781 | ///\r | |
| 4782 | /// All bit fields as a 64-bit value\r | |
| 4783 | ///\r | |
| 4784 | UINT64 Uint64;\r | |
| 4785 | } MSR_IA32_RTIT_STATUS_REGISTER;\r | |
| 4786 | \r | |
| 4787 | \r | |
| 4788 | /**\r | |
| 4789 | Trace Filter CR3 Match Register (R/W).\r | |
| 4790 | If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4791 | \r | |
| 4792 | @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r | |
| 4793 | @param EAX Lower 32-bits of MSR value.\r | |
| 4794 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
| 4795 | @param EDX Upper 32-bits of MSR value.\r | |
| 4796 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
| 4797 | \r | |
| 4798 | <b>Example usage</b>\r | |
| 4799 | @code\r | |
| 4800 | MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;\r | |
| 4801 | \r | |
| 4802 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r | |
| 4803 | AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r | |
| 4804 | @endcode\r | |
| 7de98828 | 4805 | @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r |
| 04c980a6 MK |
4806 | **/\r |
| 4807 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r | |
| 4808 | \r | |
| 4809 | /**\r | |
| 4810 | MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r | |
| 4811 | **/\r | |
| 4812 | typedef union {\r | |
| 4813 | ///\r | |
| 4814 | /// Individual bit fields\r | |
| 4815 | ///\r | |
| 4816 | struct {\r | |
| 4817 | UINT32 Reserved:5;\r | |
| 4818 | ///\r | |
| 4819 | /// [Bits 31:5] CR3[63:5] value to match.\r | |
| 4820 | ///\r | |
| 4821 | UINT32 Cr3:27;\r | |
| 4822 | ///\r | |
| 4823 | /// [Bits 63:32] CR3[63:5] value to match.\r | |
| 4824 | ///\r | |
| 4825 | UINT32 Cr3Hi:32;\r | |
| 4826 | } Bits;\r | |
| 4827 | ///\r | |
| 4828 | /// All bit fields as a 64-bit value\r | |
| 4829 | ///\r | |
| 4830 | UINT64 Uint64;\r | |
| 4831 | } MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r | |
| 4832 | \r | |
| 4833 | \r | |
| 4834 | /**\r | |
| 4835 | Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
| 4836 | \r | |
| 4837 | @param ECX MSR_IA32_RTIT_ADDRn_A\r | |
| 4838 | @param EAX Lower 32-bits of MSR value.\r | |
| 4839 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4840 | @param EDX Upper 32-bits of MSR value.\r | |
| 4841 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4842 | \r | |
| 4843 | <b>Example usage</b>\r | |
| 4844 | @code\r | |
| 4845 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
| 4846 | \r | |
| 4847 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r | |
| 4848 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r | |
| 4849 | @endcode\r | |
| 7de98828 JF |
4850 | @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r |
| 4851 | MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r | |
| 4852 | MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r | |
| 4853 | MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r | |
| 04c980a6 MK |
4854 | @{\r |
| 4855 | **/\r | |
| 4856 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580\r | |
| 4857 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582\r | |
| 4858 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584\r | |
| 4859 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586\r | |
| 4860 | /// @}\r | |
| 4861 | \r | |
| 4862 | \r | |
| 4863 | /**\r | |
| 4864 | Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
| 4865 | \r | |
| 4866 | @param ECX MSR_IA32_RTIT_ADDRn_B\r | |
| 4867 | @param EAX Lower 32-bits of MSR value.\r | |
| 4868 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4869 | @param EDX Upper 32-bits of MSR value.\r | |
| 4870 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4871 | \r | |
| 4872 | <b>Example usage</b>\r | |
| 4873 | @code\r | |
| 4874 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
| 4875 | \r | |
| 4876 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r | |
| 4877 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r | |
| 4878 | @endcode\r | |
| 7de98828 JF |
4879 | @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r |
| 4880 | MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r | |
| 4881 | MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r | |
| 4882 | MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r | |
| 04c980a6 MK |
4883 | @{\r |
| 4884 | **/\r | |
| 4885 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581\r | |
| 4886 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583\r | |
| 4887 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585\r | |
| 4888 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587\r | |
| 4889 | /// @}\r | |
| 4890 | \r | |
| 4891 | \r | |
| 4892 | /**\r | |
| 4893 | MSR information returned for MSR indexes\r | |
| 4894 | #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r | |
| 4895 | #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r | |
| 4896 | **/\r | |
| 4897 | typedef union {\r | |
| 4898 | ///\r | |
| 4899 | /// Individual bit fields\r | |
| 4900 | ///\r | |
| 4901 | struct {\r | |
| 4902 | ///\r | |
| 4903 | /// [Bits 31:0] Virtual Address.\r | |
| 4904 | ///\r | |
| 4905 | UINT32 VirtualAddress:32;\r | |
| 4906 | ///\r | |
| 4907 | /// [Bits 47:32] Virtual Address.\r | |
| 4908 | ///\r | |
| 4909 | UINT32 VirtualAddressHi:16;\r | |
| 4910 | ///\r | |
| 4911 | /// [Bits 63:48] SignExt_VA.\r | |
| 4912 | ///\r | |
| 4913 | UINT32 SignExt_VA:16;\r | |
| 4914 | } Bits;\r | |
| 4915 | ///\r | |
| 4916 | /// All bit fields as a 64-bit value\r | |
| 4917 | ///\r | |
| 4918 | UINT64 Uint64;\r | |
| 4919 | } MSR_IA32_RTIT_ADDR_REGISTER;\r | |
| 4920 | \r | |
| 4921 | \r | |
| 4922 | /**\r | |
| ba1a2d11 | 4923 | DS Save Area (R/W) Points to the linear address of the first byte of the DS\r |
| 04c980a6 | 4924 | buffer management area, which is used to manage the BTS and PEBS buffers.\r |
| ba1a2d11 ED |
4925 | See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(\r |
| 4926 | CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS\r | |
| 4927 | buffer management area, if IA-32e mode is active.\r | |
| 04c980a6 MK |
4928 | \r |
| 4929 | @param ECX MSR_IA32_DS_AREA (0x00000600)\r | |
| 4930 | @param EAX Lower 32-bits of MSR value.\r | |
| 4931 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
| 4932 | @param EDX Upper 32-bits of MSR value.\r | |
| 4933 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
| 4934 | \r | |
| 4935 | <b>Example usage</b>\r | |
| 4936 | @code\r | |
| 4937 | UINT64 Msr;\r | |
| 4938 | \r | |
| 4939 | Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r | |
| 4940 | AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r | |
| 4941 | @endcode\r | |
| 7de98828 | 4942 | @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r |
| 04c980a6 MK |
4943 | **/\r |
| 4944 | #define MSR_IA32_DS_AREA 0x00000600\r | |
| 4945 | \r | |
| 4946 | \r | |
| 4947 | /**\r | |
| 4948 | TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r | |
| 4949 | 1.\r | |
| 4950 | \r | |
| 4951 | @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)\r | |
| 4952 | @param EAX Lower 32-bits of MSR value.\r | |
| 4953 | @param EDX Upper 32-bits of MSR value.\r | |
| 4954 | \r | |
| 4955 | <b>Example usage</b>\r | |
| 4956 | @code\r | |
| 4957 | UINT64 Msr;\r | |
| 4958 | \r | |
| 4959 | Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r | |
| 4960 | AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r | |
| 4961 | @endcode\r | |
| 7de98828 | 4962 | @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r |
| 04c980a6 MK |
4963 | **/\r |
| 4964 | #define MSR_IA32_TSC_DEADLINE 0x000006E0\r | |
| 4965 | \r | |
| 4966 | \r | |
| 4967 | /**\r | |
| 4968 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r | |
| 4969 | \r | |
| 4970 | @param ECX MSR_IA32_PM_ENABLE (0x00000770)\r | |
| 4971 | @param EAX Lower 32-bits of MSR value.\r | |
| 4972 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
| 4973 | @param EDX Upper 32-bits of MSR value.\r | |
| 4974 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
| 4975 | \r | |
| 4976 | <b>Example usage</b>\r | |
| 4977 | @code\r | |
| 4978 | MSR_IA32_PM_ENABLE_REGISTER Msr;\r | |
| 4979 | \r | |
| 4980 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r | |
| 4981 | AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r | |
| 4982 | @endcode\r | |
| 7de98828 | 4983 | @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r |
| 04c980a6 MK |
4984 | **/\r |
| 4985 | #define MSR_IA32_PM_ENABLE 0x00000770\r | |
| 4986 | \r | |
| 4987 | /**\r | |
| 4988 | MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r | |
| 4989 | **/\r | |
| 4990 | typedef union {\r | |
| 4991 | ///\r | |
| 4992 | /// Individual bit fields\r | |
| 4993 | ///\r | |
| 4994 | struct {\r | |
| 4995 | ///\r | |
| 4996 | /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r | |
| 4997 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 4998 | ///\r | |
| 4999 | UINT32 HWP_ENABLE:1;\r | |
| 5000 | UINT32 Reserved1:31;\r | |
| 5001 | UINT32 Reserved2:32;\r | |
| 5002 | } Bits;\r | |
| 5003 | ///\r | |
| 5004 | /// All bit fields as a 32-bit value\r | |
| 5005 | ///\r | |
| 5006 | UINT32 Uint32;\r | |
| 5007 | ///\r | |
| 5008 | /// All bit fields as a 64-bit value\r | |
| 5009 | ///\r | |
| 5010 | UINT64 Uint64;\r | |
| 5011 | } MSR_IA32_PM_ENABLE_REGISTER;\r | |
| 5012 | \r | |
| 5013 | \r | |
| 5014 | /**\r | |
| 5015 | HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r | |
| 5016 | \r | |
| 5017 | @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)\r | |
| 5018 | @param EAX Lower 32-bits of MSR value.\r | |
| 5019 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
| 5020 | @param EDX Upper 32-bits of MSR value.\r | |
| 5021 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
| 5022 | \r | |
| 5023 | <b>Example usage</b>\r | |
| 5024 | @code\r | |
| 5025 | MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;\r | |
| 5026 | \r | |
| 5027 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r | |
| 5028 | @endcode\r | |
| 7de98828 | 5029 | @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r |
| 04c980a6 MK |
5030 | **/\r |
| 5031 | #define MSR_IA32_HWP_CAPABILITIES 0x00000771\r | |
| 5032 | \r | |
| 5033 | /**\r | |
| 5034 | MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r | |
| 5035 | **/\r | |
| 5036 | typedef union {\r | |
| 5037 | ///\r | |
| 5038 | /// Individual bit fields\r | |
| 5039 | ///\r | |
| 5040 | struct {\r | |
| 5041 | ///\r | |
| 5042 | /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r | |
| 5043 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 5044 | ///\r | |
| 5045 | UINT32 Highest_Performance:8;\r | |
| 5046 | ///\r | |
| 5047 | /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r | |
| 5048 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 5049 | ///\r | |
| 5050 | UINT32 Guaranteed_Performance:8;\r | |
| 5051 | ///\r | |
| 5052 | /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r | |
| 5053 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 5054 | ///\r | |
| 5055 | UINT32 Most_Efficient_Performance:8;\r | |
| 5056 | ///\r | |
| 5057 | /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r | |
| 5058 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 5059 | ///\r | |
| 5060 | UINT32 Lowest_Performance:8;\r | |
| 5061 | UINT32 Reserved:32;\r | |
| 5062 | } Bits;\r | |
| 5063 | ///\r | |
| 5064 | /// All bit fields as a 32-bit value\r | |
| 5065 | ///\r | |
| 5066 | UINT32 Uint32;\r | |
| 5067 | ///\r | |
| 5068 | /// All bit fields as a 64-bit value\r | |
| 5069 | ///\r | |
| 5070 | UINT64 Uint64;\r | |
| 5071 | } MSR_IA32_HWP_CAPABILITIES_REGISTER;\r | |
| 5072 | \r | |
| 5073 | \r | |
| 5074 | /**\r | |
| 5075 | Power Management Control Hints for All Logical Processors in a Package\r | |
| 5076 | (R/W). If CPUID.06H:EAX.[11] = 1.\r | |
| 5077 | \r | |
| 5078 | @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r | |
| 5079 | @param EAX Lower 32-bits of MSR value.\r | |
| 5080 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
| 5081 | @param EDX Upper 32-bits of MSR value.\r | |
| 5082 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
| 5083 | \r | |
| 5084 | <b>Example usage</b>\r | |
| 5085 | @code\r | |
| 5086 | MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;\r | |
| 5087 | \r | |
| 5088 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r | |
| 5089 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r | |
| 5090 | @endcode\r | |
| 7de98828 | 5091 | @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r |
| 04c980a6 MK |
5092 | **/\r |
| 5093 | #define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r | |
| 5094 | \r | |
| 5095 | /**\r | |
| 5096 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r | |
| 5097 | **/\r | |
| 5098 | typedef union {\r | |
| 5099 | ///\r | |
| 5100 | /// Individual bit fields\r | |
| 5101 | ///\r | |
| 5102 | struct {\r | |
| 5103 | ///\r | |
| 5104 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 5105 | /// CPUID.06H:EAX.[11] = 1.\r | |
| 5106 | ///\r | |
| 5107 | UINT32 Minimum_Performance:8;\r | |
| 5108 | ///\r | |
| 5109 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 5110 | /// CPUID.06H:EAX.[11] = 1.\r | |
| 5111 | ///\r | |
| 5112 | UINT32 Maximum_Performance:8;\r | |
| 5113 | ///\r | |
| 5114 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
| 5115 | /// If CPUID.06H:EAX.[11] = 1.\r | |
| 5116 | ///\r | |
| 5117 | UINT32 Desired_Performance:8;\r | |
| 5118 | ///\r | |
| 5119 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
| 5120 | /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
| 5121 | ///\r | |
| 5122 | UINT32 Energy_Performance_Preference:8;\r | |
| 5123 | ///\r | |
| 5124 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
| 5125 | /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
| 5126 | ///\r | |
| 5127 | UINT32 Activity_Window:10;\r | |
| 5128 | UINT32 Reserved:22;\r | |
| 5129 | } Bits;\r | |
| 5130 | ///\r | |
| 5131 | /// All bit fields as a 64-bit value\r | |
| 5132 | ///\r | |
| 5133 | UINT64 Uint64;\r | |
| 5134 | } MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r | |
| 5135 | \r | |
| 5136 | \r | |
| 5137 | /**\r | |
| 5138 | Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r | |
| 5139 | \r | |
| 5140 | @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)\r | |
| 5141 | @param EAX Lower 32-bits of MSR value.\r | |
| 5142 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
| 5143 | @param EDX Upper 32-bits of MSR value.\r | |
| 5144 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
| 5145 | \r | |
| 5146 | <b>Example usage</b>\r | |
| 5147 | @code\r | |
| 5148 | MSR_IA32_HWP_INTERRUPT_REGISTER Msr;\r | |
| 5149 | \r | |
| 5150 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r | |
| 5151 | AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r | |
| 5152 | @endcode\r | |
| 7de98828 | 5153 | @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r |
| 04c980a6 MK |
5154 | **/\r |
| 5155 | #define MSR_IA32_HWP_INTERRUPT 0x00000773\r | |
| 5156 | \r | |
| 5157 | /**\r | |
| 5158 | MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r | |
| 5159 | **/\r | |
| 5160 | typedef union {\r | |
| 5161 | ///\r | |
| 5162 | /// Individual bit fields\r | |
| 5163 | ///\r | |
| 5164 | struct {\r | |
| 5165 | ///\r | |
| 5166 | /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r | |
| 5167 | /// Notifications". If CPUID.06H:EAX.[8] = 1.\r | |
| 5168 | ///\r | |
| 5169 | UINT32 EN_Guaranteed_Performance_Change:1;\r | |
| 5170 | ///\r | |
| 5171 | /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r | |
| 5172 | /// If CPUID.06H:EAX.[8] = 1.\r | |
| 5173 | ///\r | |
| 5174 | UINT32 EN_Excursion_Minimum:1;\r | |
| 5175 | UINT32 Reserved1:30;\r | |
| 5176 | UINT32 Reserved2:32;\r | |
| 5177 | } Bits;\r | |
| 5178 | ///\r | |
| 5179 | /// All bit fields as a 32-bit value\r | |
| 5180 | ///\r | |
| 5181 | UINT32 Uint32;\r | |
| 5182 | ///\r | |
| 5183 | /// All bit fields as a 64-bit value\r | |
| 5184 | ///\r | |
| 5185 | UINT64 Uint64;\r | |
| 5186 | } MSR_IA32_HWP_INTERRUPT_REGISTER;\r | |
| 5187 | \r | |
| 5188 | \r | |
| 5189 | /**\r | |
| 5190 | Power Management Control Hints to a Logical Processor (R/W). If\r | |
| 5191 | CPUID.06H:EAX.[7] = 1.\r | |
| 5192 | \r | |
| 5193 | @param ECX MSR_IA32_HWP_REQUEST (0x00000774)\r | |
| 5194 | @param EAX Lower 32-bits of MSR value.\r | |
| 5195 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
| 5196 | @param EDX Upper 32-bits of MSR value.\r | |
| 5197 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
| 5198 | \r | |
| 5199 | <b>Example usage</b>\r | |
| 5200 | @code\r | |
| 5201 | MSR_IA32_HWP_REQUEST_REGISTER Msr;\r | |
| 5202 | \r | |
| 5203 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r | |
| 5204 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r | |
| 5205 | @endcode\r | |
| 7de98828 | 5206 | @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r |
| 04c980a6 MK |
5207 | **/\r |
| 5208 | #define MSR_IA32_HWP_REQUEST 0x00000774\r | |
| 5209 | \r | |
| 5210 | /**\r | |
| 5211 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r | |
| 5212 | **/\r | |
| 5213 | typedef union {\r | |
| 5214 | ///\r | |
| 5215 | /// Individual bit fields\r | |
| 5216 | ///\r | |
| 5217 | struct {\r | |
| 5218 | ///\r | |
| 5219 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 5220 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 5221 | ///\r | |
| 5222 | UINT32 Minimum_Performance:8;\r | |
| 5223 | ///\r | |
| 5224 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 5225 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 5226 | ///\r | |
| 5227 | UINT32 Maximum_Performance:8;\r | |
| 5228 | ///\r | |
| 5229 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
| 5230 | /// If CPUID.06H:EAX.[7] = 1.\r | |
| 5231 | ///\r | |
| 5232 | UINT32 Desired_Performance:8;\r | |
| 5233 | ///\r | |
| 5234 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
| 5235 | /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
| 5236 | ///\r | |
| 5237 | UINT32 Energy_Performance_Preference:8;\r | |
| 5238 | ///\r | |
| 5239 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
| 5240 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
| 5241 | ///\r | |
| 5242 | UINT32 Activity_Window:10;\r | |
| 5243 | ///\r | |
| 5244 | /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r | |
| 5245 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r | |
| 5246 | ///\r | |
| 5247 | UINT32 Package_Control:1;\r | |
| 5248 | UINT32 Reserved:21;\r | |
| 5249 | } Bits;\r | |
| 5250 | ///\r | |
| 5251 | /// All bit fields as a 64-bit value\r | |
| 5252 | ///\r | |
| 5253 | UINT64 Uint64;\r | |
| 5254 | } MSR_IA32_HWP_REQUEST_REGISTER;\r | |
| 5255 | \r | |
| 5256 | \r | |
| 5257 | /**\r | |
| 5258 | Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r | |
| 5259 | CPUID.06H:EAX.[7] = 1.\r | |
| 5260 | \r | |
| 5261 | @param ECX MSR_IA32_HWP_STATUS (0x00000777)\r | |
| 5262 | @param EAX Lower 32-bits of MSR value.\r | |
| 5263 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
| 5264 | @param EDX Upper 32-bits of MSR value.\r | |
| 5265 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
| 5266 | \r | |
| 5267 | <b>Example usage</b>\r | |
| 5268 | @code\r | |
| 5269 | MSR_IA32_HWP_STATUS_REGISTER Msr;\r | |
| 5270 | \r | |
| 5271 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r | |
| 5272 | AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r | |
| 5273 | @endcode\r | |
| 7de98828 | 5274 | @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r |
| 04c980a6 MK |
5275 | **/\r |
| 5276 | #define MSR_IA32_HWP_STATUS 0x00000777\r | |
| 5277 | \r | |
| 5278 | /**\r | |
| 5279 | MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r | |
| 5280 | **/\r | |
| 5281 | typedef union {\r | |
| 5282 | ///\r | |
| 5283 | /// Individual bit fields\r | |
| 5284 | ///\r | |
| 5285 | struct {\r | |
| 5286 | ///\r | |
| 5287 | /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r | |
| 5288 | /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
| 5289 | ///\r | |
| 5290 | UINT32 Guaranteed_Performance_Change:1;\r | |
| 5291 | UINT32 Reserved1:1;\r | |
| 5292 | ///\r | |
| 5293 | /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r | |
| 5294 | /// Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
| 5295 | ///\r | |
| 5296 | UINT32 Excursion_To_Minimum:1;\r | |
| 5297 | UINT32 Reserved2:29;\r | |
| 5298 | UINT32 Reserved3:32;\r | |
| 5299 | } Bits;\r | |
| 5300 | ///\r | |
| 5301 | /// All bit fields as a 32-bit value\r | |
| 5302 | ///\r | |
| 5303 | UINT32 Uint32;\r | |
| 5304 | ///\r | |
| 5305 | /// All bit fields as a 64-bit value\r | |
| 5306 | ///\r | |
| 5307 | UINT64 Uint64;\r | |
| 5308 | } MSR_IA32_HWP_STATUS_REGISTER;\r | |
| 5309 | \r | |
| 5310 | \r | |
| 5311 | /**\r | |
| 5312 | x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r | |
| 5313 | && IA32_APIC_BASE.[10] = 1.\r | |
| 5314 | \r | |
| 5315 | @param ECX MSR_IA32_X2APIC_APICID (0x00000802)\r | |
| 5316 | @param EAX Lower 32-bits of MSR value.\r | |
| 5317 | @param EDX Upper 32-bits of MSR value.\r | |
| 5318 | \r | |
| 5319 | <b>Example usage</b>\r | |
| 5320 | @code\r | |
| 5321 | UINT64 Msr;\r | |
| 5322 | \r | |
| 5323 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r | |
| 5324 | @endcode\r | |
| 7de98828 | 5325 | @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r |
| 04c980a6 MK |
5326 | **/\r |
| 5327 | #define MSR_IA32_X2APIC_APICID 0x00000802\r | |
| 5328 | \r | |
| 5329 | \r | |
| 5330 | /**\r | |
| 5331 | x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5332 | IA32_APIC_BASE.[10] = 1.\r | |
| 5333 | \r | |
| 5334 | @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)\r | |
| 5335 | @param EAX Lower 32-bits of MSR value.\r | |
| 5336 | @param EDX Upper 32-bits of MSR value.\r | |
| 5337 | \r | |
| 5338 | <b>Example usage</b>\r | |
| 5339 | @code\r | |
| 5340 | UINT64 Msr;\r | |
| 5341 | \r | |
| 5342 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r | |
| 5343 | @endcode\r | |
| 7de98828 | 5344 | @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r |
| 04c980a6 MK |
5345 | **/\r |
| 5346 | #define MSR_IA32_X2APIC_VERSION 0x00000803\r | |
| 5347 | \r | |
| 5348 | \r | |
| 5349 | /**\r | |
| 5350 | x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5351 | IA32_APIC_BASE.[10] = 1.\r | |
| 5352 | \r | |
| 5353 | @param ECX MSR_IA32_X2APIC_TPR (0x00000808)\r | |
| 5354 | @param EAX Lower 32-bits of MSR value.\r | |
| 5355 | @param EDX Upper 32-bits of MSR value.\r | |
| 5356 | \r | |
| 5357 | <b>Example usage</b>\r | |
| 5358 | @code\r | |
| 5359 | UINT64 Msr;\r | |
| 5360 | \r | |
| 5361 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r | |
| 5362 | AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r | |
| 5363 | @endcode\r | |
| 7de98828 | 5364 | @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r |
| 04c980a6 MK |
5365 | **/\r |
| 5366 | #define MSR_IA32_X2APIC_TPR 0x00000808\r | |
| 5367 | \r | |
| 5368 | \r | |
| 5369 | /**\r | |
| 5370 | x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5371 | IA32_APIC_BASE.[10] = 1.\r | |
| 5372 | \r | |
| 5373 | @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)\r | |
| 5374 | @param EAX Lower 32-bits of MSR value.\r | |
| 5375 | @param EDX Upper 32-bits of MSR value.\r | |
| 5376 | \r | |
| 5377 | <b>Example usage</b>\r | |
| 5378 | @code\r | |
| 5379 | UINT64 Msr;\r | |
| 5380 | \r | |
| 5381 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r | |
| 5382 | @endcode\r | |
| 7de98828 | 5383 | @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r |
| 04c980a6 MK |
5384 | **/\r |
| 5385 | #define MSR_IA32_X2APIC_PPR 0x0000080A\r | |
| 5386 | \r | |
| 5387 | \r | |
| 5388 | /**\r | |
| 5389 | x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r | |
| 5390 | = 1.\r | |
| 5391 | \r | |
| 5392 | @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)\r | |
| 5393 | @param EAX Lower 32-bits of MSR value.\r | |
| 5394 | @param EDX Upper 32-bits of MSR value.\r | |
| 5395 | \r | |
| 5396 | <b>Example usage</b>\r | |
| 5397 | @code\r | |
| 5398 | UINT64 Msr;\r | |
| 5399 | \r | |
| 5400 | Msr = 0;\r | |
| 5401 | AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r | |
| 5402 | @endcode\r | |
| 7de98828 | 5403 | @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r |
| 04c980a6 MK |
5404 | **/\r |
| 5405 | #define MSR_IA32_X2APIC_EOI 0x0000080B\r | |
| 5406 | \r | |
| 5407 | \r | |
| 5408 | /**\r | |
| 5409 | x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5410 | IA32_APIC_BASE.[10] = 1.\r | |
| 5411 | \r | |
| 5412 | @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)\r | |
| 5413 | @param EAX Lower 32-bits of MSR value.\r | |
| 5414 | @param EDX Upper 32-bits of MSR value.\r | |
| 5415 | \r | |
| 5416 | <b>Example usage</b>\r | |
| 5417 | @code\r | |
| 5418 | UINT64 Msr;\r | |
| 5419 | \r | |
| 5420 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r | |
| 5421 | @endcode\r | |
| 7de98828 | 5422 | @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r |
| 04c980a6 MK |
5423 | **/\r |
| 5424 | #define MSR_IA32_X2APIC_LDR 0x0000080D\r | |
| 5425 | \r | |
| 5426 | \r | |
| 5427 | /**\r | |
| 5428 | x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r | |
| 5429 | && IA32_APIC_BASE.[10] = 1.\r | |
| 5430 | \r | |
| 5431 | @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)\r | |
| 5432 | @param EAX Lower 32-bits of MSR value.\r | |
| 5433 | @param EDX Upper 32-bits of MSR value.\r | |
| 5434 | \r | |
| 5435 | <b>Example usage</b>\r | |
| 5436 | @code\r | |
| 5437 | UINT64 Msr;\r | |
| 5438 | \r | |
| 5439 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r | |
| 5440 | AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r | |
| 5441 | @endcode\r | |
| 7de98828 | 5442 | @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r |
| 04c980a6 MK |
5443 | **/\r |
| 5444 | #define MSR_IA32_X2APIC_SIVR 0x0000080F\r | |
| 5445 | \r | |
| 5446 | \r | |
| 5447 | /**\r | |
| 5448 | x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r | |
| 5449 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5450 | \r | |
| 5451 | @param ECX MSR_IA32_X2APIC_ISRn\r | |
| 5452 | @param EAX Lower 32-bits of MSR value.\r | |
| 5453 | @param EDX Upper 32-bits of MSR value.\r | |
| 5454 | \r | |
| 5455 | <b>Example usage</b>\r | |
| 5456 | @code\r | |
| 5457 | UINT64 Msr;\r | |
| 5458 | \r | |
| 5459 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r | |
| 5460 | @endcode\r | |
| 7de98828 JF |
5461 | @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r |
| 5462 | MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r | |
| 5463 | MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r | |
| 5464 | MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r | |
| 5465 | MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r | |
| 5466 | MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r | |
| 5467 | MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r | |
| 5468 | MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r | |
| 04c980a6 MK |
5469 | @{\r |
| 5470 | **/\r | |
| 5471 | #define MSR_IA32_X2APIC_ISR0 0x00000810\r | |
| 5472 | #define MSR_IA32_X2APIC_ISR1 0x00000811\r | |
| 5473 | #define MSR_IA32_X2APIC_ISR2 0x00000812\r | |
| 5474 | #define MSR_IA32_X2APIC_ISR3 0x00000813\r | |
| 5475 | #define MSR_IA32_X2APIC_ISR4 0x00000814\r | |
| 5476 | #define MSR_IA32_X2APIC_ISR5 0x00000815\r | |
| 5477 | #define MSR_IA32_X2APIC_ISR6 0x00000816\r | |
| 5478 | #define MSR_IA32_X2APIC_ISR7 0x00000817\r | |
| 5479 | /// @}\r | |
| 5480 | \r | |
| 5481 | \r | |
| 5482 | /**\r | |
| 5483 | x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r | |
| 5484 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5485 | \r | |
| 5486 | @param ECX MSR_IA32_X2APIC_TMRn\r | |
| 5487 | @param EAX Lower 32-bits of MSR value.\r | |
| 5488 | @param EDX Upper 32-bits of MSR value.\r | |
| 5489 | \r | |
| 5490 | <b>Example usage</b>\r | |
| 5491 | @code\r | |
| 5492 | UINT64 Msr;\r | |
| 5493 | \r | |
| 5494 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r | |
| 5495 | @endcode\r | |
| 7de98828 JF |
5496 | @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r |
| 5497 | MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r | |
| 5498 | MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r | |
| 5499 | MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r | |
| 5500 | MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r | |
| 5501 | MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r | |
| 5502 | MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r | |
| 5503 | MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r | |
| 04c980a6 MK |
5504 | @{\r |
| 5505 | **/\r | |
| 5506 | #define MSR_IA32_X2APIC_TMR0 0x00000818\r | |
| 5507 | #define MSR_IA32_X2APIC_TMR1 0x00000819\r | |
| 5508 | #define MSR_IA32_X2APIC_TMR2 0x0000081A\r | |
| 5509 | #define MSR_IA32_X2APIC_TMR3 0x0000081B\r | |
| 5510 | #define MSR_IA32_X2APIC_TMR4 0x0000081C\r | |
| 5511 | #define MSR_IA32_X2APIC_TMR5 0x0000081D\r | |
| 5512 | #define MSR_IA32_X2APIC_TMR6 0x0000081E\r | |
| 5513 | #define MSR_IA32_X2APIC_TMR7 0x0000081F\r | |
| 5514 | /// @}\r | |
| 5515 | \r | |
| 5516 | \r | |
| 5517 | /**\r | |
| 5518 | x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r | |
| 5519 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5520 | \r | |
| 5521 | @param ECX MSR_IA32_X2APIC_IRRn\r | |
| 5522 | @param EAX Lower 32-bits of MSR value.\r | |
| 5523 | @param EDX Upper 32-bits of MSR value.\r | |
| 5524 | \r | |
| 5525 | <b>Example usage</b>\r | |
| 5526 | @code\r | |
| 5527 | UINT64 Msr;\r | |
| 5528 | \r | |
| 5529 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r | |
| 5530 | @endcode\r | |
| 7de98828 JF |
5531 | @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r |
| 5532 | MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r | |
| 5533 | MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r | |
| 5534 | MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r | |
| 5535 | MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r | |
| 5536 | MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r | |
| 5537 | MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r | |
| 5538 | MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r | |
| 04c980a6 MK |
5539 | @{\r |
| 5540 | **/\r | |
| 5541 | #define MSR_IA32_X2APIC_IRR0 0x00000820\r | |
| 5542 | #define MSR_IA32_X2APIC_IRR1 0x00000821\r | |
| 5543 | #define MSR_IA32_X2APIC_IRR2 0x00000822\r | |
| 5544 | #define MSR_IA32_X2APIC_IRR3 0x00000823\r | |
| 5545 | #define MSR_IA32_X2APIC_IRR4 0x00000824\r | |
| 5546 | #define MSR_IA32_X2APIC_IRR5 0x00000825\r | |
| 5547 | #define MSR_IA32_X2APIC_IRR6 0x00000826\r | |
| 5548 | #define MSR_IA32_X2APIC_IRR7 0x00000827\r | |
| 5549 | /// @}\r | |
| 5550 | \r | |
| 5551 | \r | |
| 5552 | /**\r | |
| 5553 | x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5554 | IA32_APIC_BASE.[10] = 1.\r | |
| 5555 | \r | |
| 5556 | @param ECX MSR_IA32_X2APIC_ESR (0x00000828)\r | |
| 5557 | @param EAX Lower 32-bits of MSR value.\r | |
| 5558 | @param EDX Upper 32-bits of MSR value.\r | |
| 5559 | \r | |
| 5560 | <b>Example usage</b>\r | |
| 5561 | @code\r | |
| 5562 | UINT64 Msr;\r | |
| 5563 | \r | |
| 5564 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r | |
| 5565 | AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r | |
| 5566 | @endcode\r | |
| 7de98828 | 5567 | @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r |
| 04c980a6 MK |
5568 | **/\r |
| 5569 | #define MSR_IA32_X2APIC_ESR 0x00000828\r | |
| 5570 | \r | |
| 5571 | \r | |
| 5572 | /**\r | |
| 5573 | x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r | |
| 5574 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5575 | \r | |
| 5576 | @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r | |
| 5577 | @param EAX Lower 32-bits of MSR value.\r | |
| 5578 | @param EDX Upper 32-bits of MSR value.\r | |
| 5579 | \r | |
| 5580 | <b>Example usage</b>\r | |
| 5581 | @code\r | |
| 5582 | UINT64 Msr;\r | |
| 5583 | \r | |
| 5584 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r | |
| 5585 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r | |
| 5586 | @endcode\r | |
| 7de98828 | 5587 | @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r |
| 04c980a6 MK |
5588 | **/\r |
| 5589 | #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r | |
| 5590 | \r | |
| 5591 | \r | |
| 5592 | /**\r | |
| 5593 | x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5594 | IA32_APIC_BASE.[10] = 1.\r | |
| 5595 | \r | |
| 5596 | @param ECX MSR_IA32_X2APIC_ICR (0x00000830)\r | |
| 5597 | @param EAX Lower 32-bits of MSR value.\r | |
| 5598 | @param EDX Upper 32-bits of MSR value.\r | |
| 5599 | \r | |
| 5600 | <b>Example usage</b>\r | |
| 5601 | @code\r | |
| 5602 | UINT64 Msr;\r | |
| 5603 | \r | |
| 5604 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r | |
| 5605 | AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r | |
| 5606 | @endcode\r | |
| 7de98828 | 5607 | @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r |
| 04c980a6 MK |
5608 | **/\r |
| 5609 | #define MSR_IA32_X2APIC_ICR 0x00000830\r | |
| 5610 | \r | |
| 5611 | \r | |
| 5612 | /**\r | |
| 5613 | x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5614 | IA32_APIC_BASE.[10] = 1.\r | |
| 5615 | \r | |
| 5616 | @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r | |
| 5617 | @param EAX Lower 32-bits of MSR value.\r | |
| 5618 | @param EDX Upper 32-bits of MSR value.\r | |
| 5619 | \r | |
| 5620 | <b>Example usage</b>\r | |
| 5621 | @code\r | |
| 5622 | UINT64 Msr;\r | |
| 5623 | \r | |
| 5624 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r | |
| 5625 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r | |
| 5626 | @endcode\r | |
| 7de98828 | 5627 | @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r |
| 04c980a6 MK |
5628 | **/\r |
| 5629 | #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r | |
| 5630 | \r | |
| 5631 | \r | |
| 5632 | /**\r | |
| 5633 | x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r | |
| 5634 | 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5635 | \r | |
| 5636 | @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r | |
| 5637 | @param EAX Lower 32-bits of MSR value.\r | |
| 5638 | @param EDX Upper 32-bits of MSR value.\r | |
| 5639 | \r | |
| 5640 | <b>Example usage</b>\r | |
| 5641 | @code\r | |
| 5642 | UINT64 Msr;\r | |
| 5643 | \r | |
| 5644 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r | |
| 5645 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r | |
| 5646 | @endcode\r | |
| 7de98828 | 5647 | @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r |
| 04c980a6 MK |
5648 | **/\r |
| 5649 | #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r | |
| 5650 | \r | |
| 5651 | \r | |
| 5652 | /**\r | |
| 5653 | x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r | |
| 5654 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5655 | \r | |
| 5656 | @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r | |
| 5657 | @param EAX Lower 32-bits of MSR value.\r | |
| 5658 | @param EDX Upper 32-bits of MSR value.\r | |
| 5659 | \r | |
| 5660 | <b>Example usage</b>\r | |
| 5661 | @code\r | |
| 5662 | UINT64 Msr;\r | |
| 5663 | \r | |
| 5664 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r | |
| 5665 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r | |
| 5666 | @endcode\r | |
| 7de98828 | 5667 | @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r |
| 04c980a6 MK |
5668 | **/\r |
| 5669 | #define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r | |
| 5670 | \r | |
| 5671 | \r | |
| 5672 | /**\r | |
| 5673 | x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5674 | IA32_APIC_BASE.[10] = 1.\r | |
| 5675 | \r | |
| 5676 | @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r | |
| 5677 | @param EAX Lower 32-bits of MSR value.\r | |
| 5678 | @param EDX Upper 32-bits of MSR value.\r | |
| 5679 | \r | |
| 5680 | <b>Example usage</b>\r | |
| 5681 | @code\r | |
| 5682 | UINT64 Msr;\r | |
| 5683 | \r | |
| 5684 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r | |
| 5685 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r | |
| 5686 | @endcode\r | |
| 7de98828 | 5687 | @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r |
| 04c980a6 MK |
5688 | **/\r |
| 5689 | #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r | |
| 5690 | \r | |
| 5691 | \r | |
| 5692 | /**\r | |
| 5693 | x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5694 | IA32_APIC_BASE.[10] = 1.\r | |
| 5695 | \r | |
| 5696 | @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r | |
| 5697 | @param EAX Lower 32-bits of MSR value.\r | |
| 5698 | @param EDX Upper 32-bits of MSR value.\r | |
| 5699 | \r | |
| 5700 | <b>Example usage</b>\r | |
| 5701 | @code\r | |
| 5702 | UINT64 Msr;\r | |
| 5703 | \r | |
| 5704 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r | |
| 5705 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r | |
| 5706 | @endcode\r | |
| 7de98828 | 5707 | @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r |
| 04c980a6 MK |
5708 | **/\r |
| 5709 | #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r | |
| 5710 | \r | |
| 5711 | \r | |
| 5712 | /**\r | |
| 5713 | x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5714 | IA32_APIC_BASE.[10] = 1.\r | |
| 5715 | \r | |
| 5716 | @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r | |
| 5717 | @param EAX Lower 32-bits of MSR value.\r | |
| 5718 | @param EDX Upper 32-bits of MSR value.\r | |
| 5719 | \r | |
| 5720 | <b>Example usage</b>\r | |
| 5721 | @code\r | |
| 5722 | UINT64 Msr;\r | |
| 5723 | \r | |
| 5724 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r | |
| 5725 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r | |
| 5726 | @endcode\r | |
| 7de98828 | 5727 | @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r |
| 04c980a6 MK |
5728 | **/\r |
| 5729 | #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r | |
| 5730 | \r | |
| 5731 | \r | |
| 5732 | /**\r | |
| 5733 | x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5734 | IA32_APIC_BASE.[10] = 1.\r | |
| 5735 | \r | |
| 5736 | @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r | |
| 5737 | @param EAX Lower 32-bits of MSR value.\r | |
| 5738 | @param EDX Upper 32-bits of MSR value.\r | |
| 5739 | \r | |
| 5740 | <b>Example usage</b>\r | |
| 5741 | @code\r | |
| 5742 | UINT64 Msr;\r | |
| 5743 | \r | |
| 5744 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r | |
| 5745 | AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r | |
| 5746 | @endcode\r | |
| 7de98828 | 5747 | @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r |
| 04c980a6 MK |
5748 | **/\r |
| 5749 | #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r | |
| 5750 | \r | |
| 5751 | \r | |
| 5752 | /**\r | |
| 5753 | x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5754 | IA32_APIC_BASE.[10] = 1.\r | |
| 5755 | \r | |
| 5756 | @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r | |
| 5757 | @param EAX Lower 32-bits of MSR value.\r | |
| 5758 | @param EDX Upper 32-bits of MSR value.\r | |
| 5759 | \r | |
| 5760 | <b>Example usage</b>\r | |
| 5761 | @code\r | |
| 5762 | UINT64 Msr;\r | |
| 5763 | \r | |
| 5764 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r | |
| 5765 | @endcode\r | |
| 7de98828 | 5766 | @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r |
| 04c980a6 MK |
5767 | **/\r |
| 5768 | #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r | |
| 5769 | \r | |
| 5770 | \r | |
| 5771 | /**\r | |
| 5772 | x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5773 | IA32_APIC_BASE.[10] = 1.\r | |
| 5774 | \r | |
| 5775 | @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r | |
| 5776 | @param EAX Lower 32-bits of MSR value.\r | |
| 5777 | @param EDX Upper 32-bits of MSR value.\r | |
| 5778 | \r | |
| 5779 | <b>Example usage</b>\r | |
| 5780 | @code\r | |
| 5781 | UINT64 Msr;\r | |
| 5782 | \r | |
| 5783 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r | |
| 5784 | AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r | |
| 5785 | @endcode\r | |
| 7de98828 | 5786 | @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r |
| 04c980a6 MK |
5787 | **/\r |
| 5788 | #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r | |
| 5789 | \r | |
| 5790 | \r | |
| 5791 | /**\r | |
| 5792 | x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5793 | IA32_APIC_BASE.[10] = 1.\r | |
| 5794 | \r | |
| 5795 | @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r | |
| 5796 | @param EAX Lower 32-bits of MSR value.\r | |
| 5797 | @param EDX Upper 32-bits of MSR value.\r | |
| 5798 | \r | |
| 5799 | <b>Example usage</b>\r | |
| 5800 | @code\r | |
| 5801 | UINT64 Msr;\r | |
| 5802 | \r | |
| 5803 | Msr = 0;\r | |
| 5804 | AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r | |
| 5805 | @endcode\r | |
| 7de98828 | 5806 | @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r |
| 04c980a6 MK |
5807 | **/\r |
| 5808 | #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r | |
| 5809 | \r | |
| 5810 | \r | |
| 5811 | /**\r | |
| 5812 | Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r | |
| 5813 | \r | |
| 5814 | @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r | |
| 5815 | @param EAX Lower 32-bits of MSR value.\r | |
| 5816 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
| 5817 | @param EDX Upper 32-bits of MSR value.\r | |
| 5818 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
| 5819 | \r | |
| 5820 | <b>Example usage</b>\r | |
| 5821 | @code\r | |
| 5822 | MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;\r | |
| 5823 | \r | |
| 5824 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r | |
| 5825 | AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r | |
| 5826 | @endcode\r | |
| 7de98828 | 5827 | @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r |
| 04c980a6 MK |
5828 | **/\r |
| 5829 | #define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r | |
| 5830 | \r | |
| 5831 | /**\r | |
| 5832 | MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r | |
| 5833 | **/\r | |
| 5834 | typedef union {\r | |
| 5835 | ///\r | |
| 5836 | /// Individual bit fields\r | |
| 5837 | ///\r | |
| 5838 | struct {\r | |
| 5839 | ///\r | |
| 5840 | /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r | |
| 5841 | /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5842 | ///\r | |
| 5843 | UINT32 Enable:1;\r | |
| 5844 | UINT32 Reserved1:29;\r | |
| 5845 | ///\r | |
| 5846 | /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r | |
| 5847 | /// lock bit is set automatically on the first SMI assertion even if not\r | |
| 5848 | /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5849 | ///\r | |
| 5850 | UINT32 Lock:1;\r | |
| 5851 | ///\r | |
| 5852 | /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r | |
| 5853 | /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5854 | ///\r | |
| 5855 | UINT32 DebugOccurred:1;\r | |
| 5856 | UINT32 Reserved2:32;\r | |
| 5857 | } Bits;\r | |
| 5858 | ///\r | |
| 5859 | /// All bit fields as a 32-bit value\r | |
| 5860 | ///\r | |
| 5861 | UINT32 Uint32;\r | |
| 5862 | ///\r | |
| 5863 | /// All bit fields as a 64-bit value\r | |
| 5864 | ///\r | |
| 5865 | UINT64 Uint64;\r | |
| 5866 | } MSR_IA32_DEBUG_INTERFACE_REGISTER;\r | |
| 5867 | \r | |
| 5868 | \r | |
| 5869 | /**\r | |
| 5870 | L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r | |
| 5871 | \r | |
| 5872 | @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)\r | |
| 5873 | @param EAX Lower 32-bits of MSR value.\r | |
| 5874 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
| 5875 | @param EDX Upper 32-bits of MSR value.\r | |
| 5876 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
| 5877 | \r | |
| 5878 | <b>Example usage</b>\r | |
| 5879 | @code\r | |
| 5880 | MSR_IA32_L3_QOS_CFG_REGISTER Msr;\r | |
| 5881 | \r | |
| 5882 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r | |
| 5883 | AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r | |
| 5884 | @endcode\r | |
| 7de98828 | 5885 | @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r |
| 04c980a6 MK |
5886 | **/\r |
| 5887 | #define MSR_IA32_L3_QOS_CFG 0x00000C81\r | |
| 5888 | \r | |
| 5889 | /**\r | |
| 5890 | MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r | |
| 5891 | **/\r | |
| 5892 | typedef union {\r | |
| 5893 | ///\r | |
| 5894 | /// Individual bit fields\r | |
| 5895 | ///\r | |
| 5896 | struct {\r | |
| 5897 | ///\r | |
| 5898 | /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r | |
| 5899 | /// in Code and Data Prioritization (CDP) mode.\r | |
| 5900 | ///\r | |
| 5901 | UINT32 Enable:1;\r | |
| 5902 | UINT32 Reserved1:31;\r | |
| 5903 | UINT32 Reserved2:32;\r | |
| 5904 | } Bits;\r | |
| 5905 | ///\r | |
| 5906 | /// All bit fields as a 32-bit value\r | |
| 5907 | ///\r | |
| 5908 | UINT32 Uint32;\r | |
| 5909 | ///\r | |
| 5910 | /// All bit fields as a 64-bit value\r | |
| 5911 | ///\r | |
| 5912 | UINT64 Uint64;\r | |
| 5913 | } MSR_IA32_L3_QOS_CFG_REGISTER;\r | |
| 5914 | \r | |
| d05b288a ED |
5915 | /**\r |
| 5916 | L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).\r | |
| 5917 | \r | |
| 5918 | @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)\r | |
| 5919 | @param EAX Lower 32-bits of MSR value.\r | |
| 5920 | Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r | |
| 5921 | @param EDX Upper 32-bits of MSR value.\r | |
| 5922 | Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r | |
| 5923 | \r | |
| 5924 | <b>Example usage</b>\r | |
| 5925 | @code\r | |
| 5926 | MSR_IA32_L2_QOS_CFG_REGISTER Msr;\r | |
| 5927 | \r | |
| 5928 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);\r | |
| 5929 | AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);\r | |
| 5930 | @endcode\r | |
| 5931 | @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.\r | |
| 5932 | **/\r | |
| 5933 | #define MSR_IA32_L2_QOS_CFG 0x00000C82\r | |
| 5934 | \r | |
| 5935 | /**\r | |
| 5936 | MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG\r | |
| 5937 | **/\r | |
| 5938 | typedef union {\r | |
| 5939 | ///\r | |
| 5940 | /// Individual bit fields\r | |
| 5941 | ///\r | |
| 5942 | struct {\r | |
| 5943 | ///\r | |
| 5944 | /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate\r | |
| 5945 | /// in Code and Data Prioritization (CDP) mode.\r | |
| 5946 | ///\r | |
| 5947 | UINT32 Enable:1;\r | |
| 5948 | UINT32 Reserved1:31;\r | |
| 5949 | UINT32 Reserved2:32;\r | |
| 5950 | } Bits;\r | |
| 5951 | ///\r | |
| 5952 | /// All bit fields as a 32-bit value\r | |
| 5953 | ///\r | |
| 5954 | UINT32 Uint32;\r | |
| 5955 | ///\r | |
| 5956 | /// All bit fields as a 64-bit value\r | |
| 5957 | ///\r | |
| 5958 | UINT64 Uint64;\r | |
| 5959 | } MSR_IA32_L2_QOS_CFG_REGISTER;\r | |
| 04c980a6 MK |
5960 | \r |
| 5961 | /**\r | |
| 5962 | Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r | |
| 5963 | = 1 ).\r | |
| 5964 | \r | |
| 5965 | @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)\r | |
| 5966 | @param EAX Lower 32-bits of MSR value.\r | |
| 5967 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
| 5968 | @param EDX Upper 32-bits of MSR value.\r | |
| 5969 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
| 5970 | \r | |
| 5971 | <b>Example usage</b>\r | |
| 5972 | @code\r | |
| 5973 | MSR_IA32_QM_EVTSEL_REGISTER Msr;\r | |
| 5974 | \r | |
| 5975 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r | |
| 5976 | AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r | |
| 5977 | @endcode\r | |
| 7de98828 | 5978 | @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r |
| 04c980a6 MK |
5979 | **/\r |
| 5980 | #define MSR_IA32_QM_EVTSEL 0x00000C8D\r | |
| 5981 | \r | |
| 5982 | /**\r | |
| 5983 | MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r | |
| 5984 | **/\r | |
| 5985 | typedef union {\r | |
| 5986 | ///\r | |
| 5987 | /// Individual bit fields\r | |
| 5988 | ///\r | |
| 5989 | struct {\r | |
| 5990 | ///\r | |
| 5991 | /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r | |
| 5992 | /// IA32_QM_CTR.\r | |
| 5993 | ///\r | |
| 5994 | UINT32 EventID:8;\r | |
| 5995 | UINT32 Reserved:24;\r | |
| 5996 | ///\r | |
| 5997 | /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r | |
| 5998 | /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r | |
| 5999 | /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
| 6000 | ///\r | |
| 6001 | UINT32 ResourceMonitoringID:32;\r | |
| 6002 | } Bits;\r | |
| 6003 | ///\r | |
| 6004 | /// All bit fields as a 64-bit value\r | |
| 6005 | ///\r | |
| 6006 | UINT64 Uint64;\r | |
| 6007 | } MSR_IA32_QM_EVTSEL_REGISTER;\r | |
| 6008 | \r | |
| 6009 | \r | |
| 6010 | /**\r | |
| 6011 | Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r | |
| 6012 | ).\r | |
| 6013 | \r | |
| 6014 | @param ECX MSR_IA32_QM_CTR (0x00000C8E)\r | |
| 6015 | @param EAX Lower 32-bits of MSR value.\r | |
| 6016 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
| 6017 | @param EDX Upper 32-bits of MSR value.\r | |
| 6018 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
| 6019 | \r | |
| 6020 | <b>Example usage</b>\r | |
| 6021 | @code\r | |
| 6022 | MSR_IA32_QM_CTR_REGISTER Msr;\r | |
| 6023 | \r | |
| 6024 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r | |
| 6025 | @endcode\r | |
| 7de98828 | 6026 | @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r |
| 04c980a6 MK |
6027 | **/\r |
| 6028 | #define MSR_IA32_QM_CTR 0x00000C8E\r | |
| 6029 | \r | |
| 6030 | /**\r | |
| 6031 | MSR information returned for MSR index #MSR_IA32_QM_CTR\r | |
| 6032 | **/\r | |
| 6033 | typedef union {\r | |
| 6034 | ///\r | |
| 6035 | /// Individual bit fields\r | |
| 6036 | ///\r | |
| 6037 | struct {\r | |
| 6038 | ///\r | |
| 6039 | /// [Bits 31:0] Resource Monitored Data.\r | |
| 6040 | ///\r | |
| 6041 | UINT32 ResourceMonitoredData:32;\r | |
| 6042 | ///\r | |
| 6043 | /// [Bits 61:32] Resource Monitored Data.\r | |
| 6044 | ///\r | |
| 6045 | UINT32 ResourceMonitoredDataHi:30;\r | |
| 6046 | ///\r | |
| 6047 | /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r | |
| 6048 | /// available or not monitored for this resource or RMID.\r | |
| 6049 | ///\r | |
| 6050 | UINT32 Unavailable:1;\r | |
| 6051 | ///\r | |
| 6052 | /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r | |
| 6053 | /// written to IA32_PQR_QM_EVTSEL.\r | |
| 6054 | ///\r | |
| 6055 | UINT32 Error:1;\r | |
| 6056 | } Bits;\r | |
| 6057 | ///\r | |
| 6058 | /// All bit fields as a 64-bit value\r | |
| 6059 | ///\r | |
| 6060 | UINT64 Uint64;\r | |
| 6061 | } MSR_IA32_QM_CTR_REGISTER;\r | |
| 6062 | \r | |
| 6063 | \r | |
| 6064 | /**\r | |
| 0f16be6d HW |
6065 | Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r |
| 6066 | =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r | |
| 04c980a6 MK |
6067 | \r |
| 6068 | @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r | |
| 6069 | @param EAX Lower 32-bits of MSR value.\r | |
| 6070 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
| 6071 | @param EDX Upper 32-bits of MSR value.\r | |
| 6072 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
| 6073 | \r | |
| 6074 | <b>Example usage</b>\r | |
| 6075 | @code\r | |
| 6076 | MSR_IA32_PQR_ASSOC_REGISTER Msr;\r | |
| 6077 | \r | |
| 6078 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r | |
| 6079 | AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r | |
| 6080 | @endcode\r | |
| 7de98828 | 6081 | @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r |
| 04c980a6 MK |
6082 | **/\r |
| 6083 | #define MSR_IA32_PQR_ASSOC 0x00000C8F\r | |
| 6084 | \r | |
| 6085 | /**\r | |
| 6086 | MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r | |
| 6087 | **/\r | |
| 6088 | typedef union {\r | |
| 6089 | ///\r | |
| 6090 | /// Individual bit fields\r | |
| 6091 | ///\r | |
| 6092 | struct {\r | |
| 6093 | ///\r | |
| 6094 | /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r | |
| 6095 | /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r | |
| 6096 | /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
| 6097 | ///\r | |
| 6098 | UINT32 ResourceMonitoringID:32;\r | |
| 6099 | ///\r | |
| 6100 | /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r | |
| 6101 | /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r | |
| 6102 | /// ECX=0):EBX.[15] = 1 ).\r | |
| 6103 | ///\r | |
| 6104 | UINT32 COS:32;\r | |
| 6105 | } Bits;\r | |
| 6106 | ///\r | |
| 6107 | /// All bit fields as a 64-bit value\r | |
| 6108 | ///\r | |
| 6109 | UINT64 Uint64;\r | |
| 6110 | } MSR_IA32_PQR_ASSOC_REGISTER;\r | |
| 6111 | \r | |
| 6112 | \r | |
| 6113 | /**\r | |
| 6114 | Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r | |
| 6115 | ECX=0H):EBX[14] = 1).\r | |
| 6116 | \r | |
| 6117 | @param ECX MSR_IA32_BNDCFGS (0x00000D90)\r | |
| 6118 | @param EAX Lower 32-bits of MSR value.\r | |
| 6119 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
| 6120 | @param EDX Upper 32-bits of MSR value.\r | |
| 6121 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
| 6122 | \r | |
| 6123 | <b>Example usage</b>\r | |
| 6124 | @code\r | |
| 6125 | MSR_IA32_BNDCFGS_REGISTER Msr;\r | |
| 6126 | \r | |
| 6127 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r | |
| 6128 | AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r | |
| 6129 | @endcode\r | |
| 7de98828 | 6130 | @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r |
| 04c980a6 MK |
6131 | **/\r |
| 6132 | #define MSR_IA32_BNDCFGS 0x00000D90\r | |
| 6133 | \r | |
| 6134 | /**\r | |
| 6135 | MSR information returned for MSR index #MSR_IA32_BNDCFGS\r | |
| 6136 | **/\r | |
| 6137 | typedef union {\r | |
| 6138 | ///\r | |
| 6139 | /// Individual bit fields\r | |
| 6140 | ///\r | |
| 6141 | struct {\r | |
| 6142 | ///\r | |
| 6143 | /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r | |
| 6144 | ///\r | |
| 6145 | UINT32 EN:1;\r | |
| 6146 | ///\r | |
| 6147 | /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r | |
| 6148 | /// instructions in the absence of the BND prefix.\r | |
| 6149 | ///\r | |
| 6150 | UINT32 BNDPRESERVE:1;\r | |
| 6151 | UINT32 Reserved:10;\r | |
| 6152 | ///\r | |
| 6153 | /// [Bits 31:12] Base Address of Bound Directory.\r | |
| 6154 | ///\r | |
| 6155 | UINT32 Base:20;\r | |
| 6156 | ///\r | |
| 6157 | /// [Bits 63:32] Base Address of Bound Directory.\r | |
| 6158 | ///\r | |
| 6159 | UINT32 BaseHi:32;\r | |
| 6160 | } Bits;\r | |
| 6161 | ///\r | |
| 6162 | /// All bit fields as a 64-bit value\r | |
| 6163 | ///\r | |
| 6164 | UINT64 Uint64;\r | |
| 6165 | } MSR_IA32_BNDCFGS_REGISTER;\r | |
| 6166 | \r | |
| 6167 | \r | |
| 6168 | /**\r | |
| 6169 | Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r | |
| 6170 | \r | |
| 6171 | @param ECX MSR_IA32_XSS (0x00000DA0)\r | |
| 6172 | @param EAX Lower 32-bits of MSR value.\r | |
| 6173 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
| 6174 | @param EDX Upper 32-bits of MSR value.\r | |
| 6175 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
| 6176 | \r | |
| 6177 | <b>Example usage</b>\r | |
| 6178 | @code\r | |
| 6179 | MSR_IA32_XSS_REGISTER Msr;\r | |
| 6180 | \r | |
| 6181 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r | |
| 6182 | AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r | |
| 6183 | @endcode\r | |
| 7de98828 | 6184 | @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r |
| 04c980a6 MK |
6185 | **/\r |
| 6186 | #define MSR_IA32_XSS 0x00000DA0\r | |
| 6187 | \r | |
| 6188 | /**\r | |
| 6189 | MSR information returned for MSR index #MSR_IA32_XSS\r | |
| 6190 | **/\r | |
| 6191 | typedef union {\r | |
| 6192 | ///\r | |
| 6193 | /// Individual bit fields\r | |
| 6194 | ///\r | |
| 6195 | struct {\r | |
| 6196 | UINT32 Reserved1:8;\r | |
| 6197 | ///\r | |
| 6198 | /// [Bit 8] Trace Packet Configuration State (R/W).\r | |
| 6199 | ///\r | |
| 6200 | UINT32 TracePacketConfigurationState:1;\r | |
| 6201 | UINT32 Reserved2:23;\r | |
| 6202 | UINT32 Reserved3:32;\r | |
| 6203 | } Bits;\r | |
| 6204 | ///\r | |
| 6205 | /// All bit fields as a 32-bit value\r | |
| 6206 | ///\r | |
| 6207 | UINT32 Uint32;\r | |
| 6208 | ///\r | |
| 6209 | /// All bit fields as a 64-bit value\r | |
| 6210 | ///\r | |
| 6211 | UINT64 Uint64;\r | |
| 6212 | } MSR_IA32_XSS_REGISTER;\r | |
| 6213 | \r | |
| 6214 | \r | |
| 6215 | /**\r | |
| 6216 | Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
| 6217 | \r | |
| 6218 | @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r | |
| 6219 | @param EAX Lower 32-bits of MSR value.\r | |
| 6220 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
| 6221 | @param EDX Upper 32-bits of MSR value.\r | |
| 6222 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
| 6223 | \r | |
| 6224 | <b>Example usage</b>\r | |
| 6225 | @code\r | |
| 6226 | MSR_IA32_PKG_HDC_CTL_REGISTER Msr;\r | |
| 6227 | \r | |
| 6228 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r | |
| 6229 | AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r | |
| 6230 | @endcode\r | |
| 7de98828 | 6231 | @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r |
| 04c980a6 MK |
6232 | **/\r |
| 6233 | #define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r | |
| 6234 | \r | |
| 6235 | /**\r | |
| 6236 | MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r | |
| 6237 | **/\r | |
| 6238 | typedef union {\r | |
| 6239 | ///\r | |
| 6240 | /// Individual bit fields\r | |
| 6241 | ///\r | |
| 6242 | struct {\r | |
| 6243 | ///\r | |
| 6244 | /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r | |
| 6245 | /// logical processors in the package. See Section 14.5.2, "Package level\r | |
| 6246 | /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r | |
| 6247 | ///\r | |
| 6248 | UINT32 HDC_Pkg_Enable:1;\r | |
| 6249 | UINT32 Reserved1:31;\r | |
| 6250 | UINT32 Reserved2:32;\r | |
| 6251 | } Bits;\r | |
| 6252 | ///\r | |
| 6253 | /// All bit fields as a 32-bit value\r | |
| 6254 | ///\r | |
| 6255 | UINT32 Uint32;\r | |
| 6256 | ///\r | |
| 6257 | /// All bit fields as a 64-bit value\r | |
| 6258 | ///\r | |
| 6259 | UINT64 Uint64;\r | |
| 6260 | } MSR_IA32_PKG_HDC_CTL_REGISTER;\r | |
| 6261 | \r | |
| 6262 | \r | |
| 6263 | /**\r | |
| 6264 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
| 6265 | \r | |
| 6266 | @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)\r | |
| 6267 | @param EAX Lower 32-bits of MSR value.\r | |
| 6268 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
| 6269 | @param EDX Upper 32-bits of MSR value.\r | |
| 6270 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
| 6271 | \r | |
| 6272 | <b>Example usage</b>\r | |
| 6273 | @code\r | |
| 6274 | MSR_IA32_PM_CTL1_REGISTER Msr;\r | |
| 6275 | \r | |
| 6276 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r | |
| 6277 | AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r | |
| 6278 | @endcode\r | |
| 7de98828 | 6279 | @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r |
| 04c980a6 MK |
6280 | **/\r |
| 6281 | #define MSR_IA32_PM_CTL1 0x00000DB1\r | |
| 6282 | \r | |
| 6283 | /**\r | |
| 6284 | MSR information returned for MSR index #MSR_IA32_PM_CTL1\r | |
| 6285 | **/\r | |
| 6286 | typedef union {\r | |
| 6287 | ///\r | |
| 6288 | /// Individual bit fields\r | |
| 6289 | ///\r | |
| 6290 | struct {\r | |
| 6291 | ///\r | |
| 6292 | /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r | |
| 6293 | /// package level HDC control. See Section 14.5.3.\r | |
| 6294 | /// If CPUID.06H:EAX.[13] = 1.\r | |
| 6295 | ///\r | |
| 6296 | UINT32 HDC_Allow_Block:1;\r | |
| 6297 | UINT32 Reserved1:31;\r | |
| 6298 | UINT32 Reserved2:32;\r | |
| 6299 | } Bits;\r | |
| 6300 | ///\r | |
| 6301 | /// All bit fields as a 32-bit value\r | |
| 6302 | ///\r | |
| 6303 | UINT32 Uint32;\r | |
| 6304 | ///\r | |
| 6305 | /// All bit fields as a 64-bit value\r | |
| 6306 | ///\r | |
| 6307 | UINT64 Uint64;\r | |
| 6308 | } MSR_IA32_PM_CTL1_REGISTER;\r | |
| 6309 | \r | |
| 6310 | \r | |
| 6311 | /**\r | |
| 6312 | Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r | |
| 6313 | Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r | |
| 6314 | processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r | |
| 6315 | \r | |
| 6316 | @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)\r | |
| 6317 | @param EAX Lower 32-bits of MSR value.\r | |
| 6318 | @param EDX Upper 32-bits of MSR value.\r | |
| 6319 | \r | |
| 6320 | <b>Example usage</b>\r | |
| 6321 | @code\r | |
| 6322 | UINT64 Msr;\r | |
| 6323 | \r | |
| 6324 | Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r | |
| 6325 | @endcode\r | |
| 7de98828 | 6326 | @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r |
| 04c980a6 MK |
6327 | **/\r |
| 6328 | #define MSR_IA32_THREAD_STALL 0x00000DB2\r | |
| 6329 | \r | |
| 6330 | \r | |
| 6331 | /**\r | |
| 6332 | Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r | |
| 6333 | CPUID.80000001H:EDX.[2 9]).\r | |
| 6334 | \r | |
| 6335 | @param ECX MSR_IA32_EFER (0xC0000080)\r | |
| 6336 | @param EAX Lower 32-bits of MSR value.\r | |
| 6337 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
| 6338 | @param EDX Upper 32-bits of MSR value.\r | |
| 6339 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
| 6340 | \r | |
| 6341 | <b>Example usage</b>\r | |
| 6342 | @code\r | |
| 6343 | MSR_IA32_EFER_REGISTER Msr;\r | |
| 6344 | \r | |
| 6345 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r | |
| 6346 | AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r | |
| 6347 | @endcode\r | |
| 7de98828 | 6348 | @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r |
| 04c980a6 MK |
6349 | **/\r |
| 6350 | #define MSR_IA32_EFER 0xC0000080\r | |
| 6351 | \r | |
| 6352 | /**\r | |
| 6353 | MSR information returned for MSR index #MSR_IA32_EFER\r | |
| 6354 | **/\r | |
| 6355 | typedef union {\r | |
| 6356 | ///\r | |
| 6357 | /// Individual bit fields\r | |
| 6358 | ///\r | |
| 6359 | struct {\r | |
| 6360 | ///\r | |
| 6361 | /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r | |
| 6362 | /// instructions in 64-bit mode.\r | |
| 6363 | ///\r | |
| 6364 | UINT32 SCE:1;\r | |
| 6365 | UINT32 Reserved1:7;\r | |
| 6366 | ///\r | |
| 6367 | /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r | |
| 6368 | /// operation.\r | |
| 6369 | ///\r | |
| 6370 | UINT32 LME:1;\r | |
| 6371 | UINT32 Reserved2:1;\r | |
| 6372 | ///\r | |
| 6373 | /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r | |
| 6374 | /// is active when set.\r | |
| 6375 | ///\r | |
| 6376 | UINT32 LMA:1;\r | |
| 6377 | ///\r | |
| 6378 | /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r | |
| 6379 | ///\r | |
| 6380 | UINT32 NXE:1;\r | |
| 6381 | UINT32 Reserved3:20;\r | |
| 6382 | UINT32 Reserved4:32;\r | |
| 6383 | } Bits;\r | |
| 6384 | ///\r | |
| 6385 | /// All bit fields as a 32-bit value\r | |
| 6386 | ///\r | |
| 6387 | UINT32 Uint32;\r | |
| 6388 | ///\r | |
| 6389 | /// All bit fields as a 64-bit value\r | |
| 6390 | ///\r | |
| 6391 | UINT64 Uint64;\r | |
| 6392 | } MSR_IA32_EFER_REGISTER;\r | |
| 6393 | \r | |
| 6394 | \r | |
| 6395 | /**\r | |
| 6396 | System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6397 | \r | |
| 6398 | @param ECX MSR_IA32_STAR (0xC0000081)\r | |
| 6399 | @param EAX Lower 32-bits of MSR value.\r | |
| 6400 | @param EDX Upper 32-bits of MSR value.\r | |
| 6401 | \r | |
| 6402 | <b>Example usage</b>\r | |
| 6403 | @code\r | |
| 6404 | UINT64 Msr;\r | |
| 6405 | \r | |
| 6406 | Msr = AsmReadMsr64 (MSR_IA32_STAR);\r | |
| 6407 | AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r | |
| 6408 | @endcode\r | |
| 7de98828 | 6409 | @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r |
| 04c980a6 MK |
6410 | **/\r |
| 6411 | #define MSR_IA32_STAR 0xC0000081\r | |
| 6412 | \r | |
| 6413 | \r | |
| 6414 | /**\r | |
| 6415 | IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6416 | \r | |
| 6417 | @param ECX MSR_IA32_LSTAR (0xC0000082)\r | |
| 6418 | @param EAX Lower 32-bits of MSR value.\r | |
| 6419 | @param EDX Upper 32-bits of MSR value.\r | |
| 6420 | \r | |
| 6421 | <b>Example usage</b>\r | |
| 6422 | @code\r | |
| 6423 | UINT64 Msr;\r | |
| 6424 | \r | |
| 6425 | Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r | |
| 6426 | AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r | |
| 6427 | @endcode\r | |
| 7de98828 | 6428 | @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r |
| 04c980a6 MK |
6429 | **/\r |
| 6430 | #define MSR_IA32_LSTAR 0xC0000082\r | |
| 6431 | \r | |
| d05b288a ED |
6432 | /**\r |
| 6433 | IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL\r | |
| 6434 | instruction is not recognized in compatibility mode. If\r | |
| 6435 | CPUID.80000001:EDX.[29] = 1.\r | |
| 6436 | \r | |
| 6437 | @param ECX MSR_IA32_CSTAR (0xC0000083)\r | |
| 6438 | @param EAX Lower 32-bits of MSR value.\r | |
| 6439 | @param EDX Upper 32-bits of MSR value.\r | |
| 6440 | \r | |
| 6441 | <b>Example usage</b>\r | |
| 6442 | @code\r | |
| 6443 | UINT64 Msr;\r | |
| 6444 | \r | |
| 6445 | Msr = AsmReadMsr64 (MSR_IA32_CSTAR);\r | |
| 6446 | AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);\r | |
| 6447 | @endcode\r | |
| 6448 | @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.\r | |
| 6449 | **/\r | |
| 6450 | #define MSR_IA32_CSTAR 0xC0000083\r | |
| 04c980a6 MK |
6451 | \r |
| 6452 | /**\r | |
| 6453 | System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6454 | \r | |
| 6455 | @param ECX MSR_IA32_FMASK (0xC0000084)\r | |
| 6456 | @param EAX Lower 32-bits of MSR value.\r | |
| 6457 | @param EDX Upper 32-bits of MSR value.\r | |
| 6458 | \r | |
| 6459 | <b>Example usage</b>\r | |
| 6460 | @code\r | |
| 6461 | UINT64 Msr;\r | |
| 6462 | \r | |
| 6463 | Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r | |
| 6464 | AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r | |
| 6465 | @endcode\r | |
| 7de98828 | 6466 | @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r |
| 04c980a6 MK |
6467 | **/\r |
| 6468 | #define MSR_IA32_FMASK 0xC0000084\r | |
| 6469 | \r | |
| 6470 | \r | |
| 6471 | /**\r | |
| 6472 | Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6473 | \r | |
| 6474 | @param ECX MSR_IA32_FS_BASE (0xC0000100)\r | |
| 6475 | @param EAX Lower 32-bits of MSR value.\r | |
| 6476 | @param EDX Upper 32-bits of MSR value.\r | |
| 6477 | \r | |
| 6478 | <b>Example usage</b>\r | |
| 6479 | @code\r | |
| 6480 | UINT64 Msr;\r | |
| 6481 | \r | |
| 6482 | Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r | |
| 6483 | AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r | |
| 6484 | @endcode\r | |
| 7de98828 | 6485 | @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r |
| 04c980a6 MK |
6486 | **/\r |
| 6487 | #define MSR_IA32_FS_BASE 0xC0000100\r | |
| 6488 | \r | |
| 6489 | \r | |
| 6490 | /**\r | |
| 6491 | Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6492 | \r | |
| 6493 | @param ECX MSR_IA32_GS_BASE (0xC0000101)\r | |
| 6494 | @param EAX Lower 32-bits of MSR value.\r | |
| 6495 | @param EDX Upper 32-bits of MSR value.\r | |
| 6496 | \r | |
| 6497 | <b>Example usage</b>\r | |
| 6498 | @code\r | |
| 6499 | UINT64 Msr;\r | |
| 6500 | \r | |
| 6501 | Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r | |
| 6502 | AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r | |
| 6503 | @endcode\r | |
| 7de98828 | 6504 | @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r |
| 04c980a6 MK |
6505 | **/\r |
| 6506 | #define MSR_IA32_GS_BASE 0xC0000101\r | |
| 6507 | \r | |
| 6508 | \r | |
| 6509 | /**\r | |
| 6510 | Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6511 | \r | |
| 6512 | @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r | |
| 6513 | @param EAX Lower 32-bits of MSR value.\r | |
| 6514 | @param EDX Upper 32-bits of MSR value.\r | |
| 6515 | \r | |
| 6516 | <b>Example usage</b>\r | |
| 6517 | @code\r | |
| 6518 | UINT64 Msr;\r | |
| 6519 | \r | |
| 6520 | Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r | |
| 6521 | AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r | |
| 6522 | @endcode\r | |
| 7de98828 | 6523 | @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r |
| 04c980a6 MK |
6524 | **/\r |
| 6525 | #define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r | |
| 6526 | \r | |
| 6527 | \r | |
| 6528 | /**\r | |
| 6529 | Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r | |
| 6530 | \r | |
| 6531 | @param ECX MSR_IA32_TSC_AUX (0xC0000103)\r | |
| 6532 | @param EAX Lower 32-bits of MSR value.\r | |
| 6533 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
| 6534 | @param EDX Upper 32-bits of MSR value.\r | |
| 6535 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
| 6536 | \r | |
| 6537 | <b>Example usage</b>\r | |
| 6538 | @code\r | |
| 6539 | MSR_IA32_TSC_AUX_REGISTER Msr;\r | |
| 6540 | \r | |
| 6541 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r | |
| 6542 | AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r | |
| 6543 | @endcode\r | |
| 7de98828 | 6544 | @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r |
| 04c980a6 MK |
6545 | **/\r |
| 6546 | #define MSR_IA32_TSC_AUX 0xC0000103\r | |
| 6547 | \r | |
| 6548 | /**\r | |
| 6549 | MSR information returned for MSR index #MSR_IA32_TSC_AUX\r | |
| 6550 | **/\r | |
| 6551 | typedef union {\r | |
| 6552 | ///\r | |
| 6553 | /// Individual bit fields\r | |
| 6554 | ///\r | |
| 6555 | struct {\r | |
| 6556 | ///\r | |
| 6557 | /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r | |
| 6558 | ///\r | |
| 6559 | UINT32 AUX:32;\r | |
| 6560 | UINT32 Reserved:32;\r | |
| 6561 | } Bits;\r | |
| 6562 | ///\r | |
| 6563 | /// All bit fields as a 32-bit value\r | |
| 6564 | ///\r | |
| 6565 | UINT32 Uint32;\r | |
| 6566 | ///\r | |
| 6567 | /// All bit fields as a 64-bit value\r | |
| 6568 | ///\r | |
| 6569 | UINT64 Uint64;\r | |
| 6570 | } MSR_IA32_TSC_AUX_REGISTER;\r | |
| 6571 | \r | |
| 6572 | #endif\r |