projects / mirror_edk2.git / blame
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1 | /** @file\r |
| 2 | Architectural MSR Definitions.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 10 | This program and the accompanying materials\r | |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r | |
| 21 | \r | |
| 831d287a MK |
22 | @par Specification Reference:\r |
| 23 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 24 | December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.\r | |
| 25 | \r | |
| 26 | @par Specification Reference:\r | |
| 27 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 28 | December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.\r | |
| 29 | \r | |
| 04c980a6 MK |
30 | **/\r |
| 31 | \r | |
| 32 | #ifndef __ARCHITECTURAL_MSR_H__\r | |
| 33 | #define __ARCHITECTURAL_MSR_H__\r | |
| 34 | \r | |
| 35 | /**\r | |
| 36 | See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r | |
| 37 | \r | |
| 38 | @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r | |
| 39 | @param EAX Lower 32-bits of MSR value.\r | |
| 40 | @param EDX Upper 32-bits of MSR value.\r | |
| 41 | \r | |
| 42 | <b>Example usage</b>\r | |
| 43 | @code\r | |
| 44 | UINT64 Msr;\r | |
| 45 | \r | |
| 46 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r | |
| 47 | AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r | |
| 48 | @endcode\r | |
| 7de98828 | 49 | @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r |
| 04c980a6 MK |
50 | **/\r |
| 51 | #define MSR_IA32_P5_MC_ADDR 0x00000000\r | |
| 52 | \r | |
| 53 | \r | |
| 54 | /**\r | |
| 55 | See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r | |
| 56 | \r | |
| 57 | @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r | |
| 58 | @param EAX Lower 32-bits of MSR value.\r | |
| 59 | @param EDX Upper 32-bits of MSR value.\r | |
| 60 | \r | |
| 61 | <b>Example usage</b>\r | |
| 62 | @code\r | |
| 63 | UINT64 Msr;\r | |
| 64 | \r | |
| 65 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r | |
| 66 | AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r | |
| 67 | @endcode\r | |
| 7de98828 | 68 | @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r |
| 04c980a6 MK |
69 | **/\r |
| 70 | #define MSR_IA32_P5_MC_TYPE 0x00000001\r | |
| 71 | \r | |
| 72 | \r | |
| 73 | /**\r | |
| 74 | See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r | |
| 75 | at Display Family / Display Model 0F_03H.\r | |
| 76 | \r | |
| 77 | @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r | |
| 78 | @param EAX Lower 32-bits of MSR value.\r | |
| 79 | @param EDX Upper 32-bits of MSR value.\r | |
| 80 | \r | |
| 81 | <b>Example usage</b>\r | |
| 82 | @code\r | |
| 83 | UINT64 Msr;\r | |
| 84 | \r | |
| 85 | Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r | |
| 86 | AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r | |
| 87 | @endcode\r | |
| 7de98828 | 88 | @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r |
| 04c980a6 MK |
89 | **/\r |
| 90 | #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r | |
| 91 | \r | |
| 92 | \r | |
| 93 | /**\r | |
| 94 | See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /\r | |
| 95 | Display Model 05_01H.\r | |
| 96 | \r | |
| 97 | @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r | |
| 98 | @param EAX Lower 32-bits of MSR value.\r | |
| 99 | @param EDX Upper 32-bits of MSR value.\r | |
| 100 | \r | |
| 101 | <b>Example usage</b>\r | |
| 102 | @code\r | |
| 103 | UINT64 Msr;\r | |
| 104 | \r | |
| 105 | Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r | |
| 106 | AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r | |
| 107 | @endcode\r | |
| 7de98828 | 108 | @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r |
| 04c980a6 MK |
109 | **/\r |
| 110 | #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r | |
| 111 | \r | |
| 112 | \r | |
| 113 | /**\r | |
| 114 | Platform ID (RO) The operating system can use this MSR to determine "slot"\r | |
| 115 | information for the processor and the proper microcode update to load.\r | |
| 116 | Introduced at Display Family / Display Model 06_01H.\r | |
| 117 | \r | |
| 118 | @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r | |
| 119 | @param EAX Lower 32-bits of MSR value.\r | |
| 120 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 121 | @param EDX Upper 32-bits of MSR value.\r | |
| 122 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 123 | \r | |
| 124 | <b>Example usage</b>\r | |
| 125 | @code\r | |
| 126 | MSR_IA32_PLATFORM_ID_REGISTER Msr;\r | |
| 127 | \r | |
| 128 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r | |
| 129 | @endcode\r | |
| 7de98828 | 130 | @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r |
| 04c980a6 MK |
131 | **/\r |
| 132 | #define MSR_IA32_PLATFORM_ID 0x00000017\r | |
| 133 | \r | |
| 134 | /**\r | |
| 135 | MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r | |
| 136 | **/\r | |
| 137 | typedef union {\r | |
| 138 | ///\r | |
| 139 | /// Individual bit fields\r | |
| 140 | ///\r | |
| 141 | struct {\r | |
| 142 | UINT32 Reserved1:32;\r | |
| 143 | UINT32 Reserved2:18;\r | |
| 144 | ///\r | |
| 145 | /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r | |
| 146 | /// intended platform for the processor.\r | |
| 147 | /// 52 51 50\r | |
| 148 | /// -- -- --\r | |
| 149 | /// 0 0 0 Processor Flag 0.\r | |
| 150 | /// 0 0 1 Processor Flag 1\r | |
| 151 | /// 0 1 0 Processor Flag 2\r | |
| 152 | /// 0 1 1 Processor Flag 3\r | |
| 153 | /// 1 0 0 Processor Flag 4\r | |
| 154 | /// 1 0 1 Processor Flag 5\r | |
| 155 | /// 1 1 0 Processor Flag 6\r | |
| 156 | /// 1 1 1 Processor Flag 7\r | |
| 157 | ///\r | |
| 158 | UINT32 PlatformId:3;\r | |
| 159 | UINT32 Reserved3:11;\r | |
| 160 | } Bits;\r | |
| 161 | ///\r | |
| 162 | /// All bit fields as a 64-bit value\r | |
| 163 | ///\r | |
| 164 | UINT64 Uint64;\r | |
| 165 | } MSR_IA32_PLATFORM_ID_REGISTER;\r | |
| 166 | \r | |
| 167 | \r | |
| 168 | /**\r | |
| 169 | 06_01H.\r | |
| 170 | \r | |
| 171 | @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r | |
| 172 | @param EAX Lower 32-bits of MSR value.\r | |
| 173 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 174 | @param EDX Upper 32-bits of MSR value.\r | |
| 175 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 176 | \r | |
| 177 | <b>Example usage</b>\r | |
| 178 | @code\r | |
| 179 | MSR_IA32_APIC_BASE_REGISTER Msr;\r | |
| 180 | \r | |
| 181 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
| 182 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r | |
| 183 | @endcode\r | |
| 7de98828 | 184 | @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r |
| 04c980a6 MK |
185 | **/\r |
| 186 | #define MSR_IA32_APIC_BASE 0x0000001B\r | |
| 187 | \r | |
| 188 | /**\r | |
| 189 | MSR information returned for MSR index #MSR_IA32_APIC_BASE\r | |
| 190 | **/\r | |
| 191 | typedef union {\r | |
| 192 | ///\r | |
| 193 | /// Individual bit fields\r | |
| 194 | ///\r | |
| 195 | struct {\r | |
| 196 | UINT32 Reserved1:8;\r | |
| 197 | ///\r | |
| 198 | /// [Bit 8] BSP flag (R/W).\r | |
| 199 | ///\r | |
| 200 | UINT32 BSP:1;\r | |
| 201 | UINT32 Reserved2:1;\r | |
| 202 | ///\r | |
| 203 | /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r | |
| 204 | /// Model 06_1AH.\r | |
| 205 | ///\r | |
| 206 | UINT32 EXTD:1;\r | |
| 207 | ///\r | |
| 208 | /// [Bit 11] APIC Global Enable (R/W).\r | |
| 209 | ///\r | |
| 210 | UINT32 EN:1;\r | |
| 211 | ///\r | |
| 212 | /// [Bits 31:12] APIC Base (R/W).\r | |
| 213 | ///\r | |
| 214 | UINT32 ApicBase:20;\r | |
| 215 | ///\r | |
| 216 | /// [Bits 63:32] APIC Base (R/W).\r | |
| 217 | ///\r | |
| 218 | UINT32 ApicBaseHi:32;\r | |
| 219 | } Bits;\r | |
| 220 | ///\r | |
| 221 | /// All bit fields as a 64-bit value\r | |
| 222 | ///\r | |
| 223 | UINT64 Uint64;\r | |
| 224 | } MSR_IA32_APIC_BASE_REGISTER;\r | |
| 225 | \r | |
| 226 | \r | |
| 227 | /**\r | |
| 228 | Control Features in Intel 64 Processor (R/W). If any one enumeration\r | |
| 229 | condition for defined bit field holds.\r | |
| 230 | \r | |
| 231 | @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r | |
| 232 | @param EAX Lower 32-bits of MSR value.\r | |
| 233 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 234 | @param EDX Upper 32-bits of MSR value.\r | |
| 235 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 236 | \r | |
| 237 | <b>Example usage</b>\r | |
| 238 | @code\r | |
| 239 | MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r | |
| 240 | \r | |
| 241 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r | |
| 242 | AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r | |
| 243 | @endcode\r | |
| 7de98828 | 244 | @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r |
| 04c980a6 MK |
245 | **/\r |
| 246 | #define MSR_IA32_FEATURE_CONTROL 0x0000003A\r | |
| 247 | \r | |
| 248 | /**\r | |
| 249 | MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r | |
| 250 | **/\r | |
| 251 | typedef union {\r | |
| 252 | ///\r | |
| 253 | /// Individual bit fields\r | |
| 254 | ///\r | |
| 255 | struct {\r | |
| 256 | ///\r | |
| 257 | /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r | |
| 258 | /// being written, writes to this bit will result in GP(0). Note: Once the\r | |
| 259 | /// Lock bit is set, the contents of this register cannot be modified.\r | |
| 260 | /// Therefore the lock bit must be set after configuring support for Intel\r | |
| 261 | /// Virtualization Technology and prior to transferring control to an\r | |
| 262 | /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r | |
| 263 | /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r | |
| 264 | /// is not deasserted. If any one enumeration condition for defined bit\r | |
| 265 | /// field position greater than bit 0 holds.\r | |
| 266 | ///\r | |
| 267 | UINT32 Lock:1;\r | |
| 268 | ///\r | |
| 269 | /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r | |
| 270 | /// system executive to use VMX in conjunction with SMX to support\r | |
| 271 | /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r | |
| 272 | /// when the CPUID function 1 returns VMX feature flag and SMX feature\r | |
| 273 | /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r | |
| 274 | /// CPUID.01H:ECX[6] = 1.\r | |
| 275 | ///\r | |
| 276 | UINT32 EnableVmxInsideSmx:1;\r | |
| 277 | ///\r | |
| 278 | /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r | |
| 279 | /// for system executive that do not require SMX. BIOS must set this bit\r | |
| 280 | /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r | |
| 281 | /// 5). If CPUID.01H:ECX[5] = 1.\r | |
| 282 | ///\r | |
| 283 | UINT32 EnableVmxOutsideSmx:1;\r | |
| 284 | UINT32 Reserved1:5;\r | |
| 285 | ///\r | |
| 286 | /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r | |
| 287 | /// in the field represents an enable control for a corresponding SENTER\r | |
| 288 | /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r | |
| 289 | /// CPUID.01H:ECX[6] = 1.\r | |
| 290 | ///\r | |
| 291 | UINT32 SenterLocalFunctionEnables:7;\r | |
| 292 | ///\r | |
| 293 | /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r | |
| 294 | /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r | |
| 295 | /// 6] is set. If CPUID.01H:ECX[6] = 1.\r | |
| 296 | ///\r | |
| 297 | UINT32 SenterGlobalEnable:1;\r | |
| 298 | UINT32 Reserved2:2;\r | |
| 299 | ///\r | |
| 300 | /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r | |
| 301 | /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is\r | |
| 302 | /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r | |
| 303 | ///\r | |
| 304 | UINT32 SgxEnable:1;\r | |
| 305 | UINT32 Reserved3:1;\r | |
| 306 | ///\r | |
| 307 | /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r | |
| 308 | /// MSRs associated with LMCE to configure delivery of some machine check\r | |
| 309 | /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r | |
| 310 | ///\r | |
| 311 | UINT32 LmceOn:1;\r | |
| 312 | UINT32 Reserved4:11;\r | |
| 313 | UINT32 Reserved5:32;\r | |
| 314 | } Bits;\r | |
| 315 | ///\r | |
| 316 | /// All bit fields as a 32-bit value\r | |
| 317 | ///\r | |
| 318 | UINT32 Uint32;\r | |
| 319 | ///\r | |
| 320 | /// All bit fields as a 64-bit value\r | |
| 321 | ///\r | |
| 322 | UINT64 Uint64;\r | |
| 323 | } MSR_IA32_FEATURE_CONTROL_REGISTER;\r | |
| 324 | \r | |
| 325 | \r | |
| 326 | /**\r | |
| 327 | Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r | |
| 328 | ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r | |
| 329 | a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r | |
| 330 | the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r | |
| 331 | not affect the internal invariant TSC hardware.\r | |
| 332 | \r | |
| 333 | @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r | |
| 334 | @param EAX Lower 32-bits of MSR value.\r | |
| 335 | @param EDX Upper 32-bits of MSR value.\r | |
| 336 | \r | |
| 337 | <b>Example usage</b>\r | |
| 338 | @code\r | |
| 339 | UINT64 Msr;\r | |
| 340 | \r | |
| 341 | Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r | |
| 342 | AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r | |
| 343 | @endcode\r | |
| 7de98828 | 344 | @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r |
| 04c980a6 MK |
345 | **/\r |
| 346 | #define MSR_IA32_TSC_ADJUST 0x0000003B\r | |
| 347 | \r | |
| 348 | \r | |
| 349 | /**\r | |
| 350 | BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r | |
| 351 | microcode update to be loaded into the processor. See Section 9.11.6,\r | |
| 352 | "Microcode Update Loader." A processor may prevent writing to this MSR when\r | |
| 353 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 354 | Introduced at Display Family / Display Model 06_01H.\r | |
| 355 | \r | |
| 356 | @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r | |
| 357 | @param EAX Lower 32-bits of MSR value.\r | |
| 358 | @param EDX Upper 32-bits of MSR value.\r | |
| 359 | \r | |
| 360 | <b>Example usage</b>\r | |
| 361 | @code\r | |
| 362 | UINT64 Msr;\r | |
| 363 | \r | |
| 364 | Msr = 0;\r | |
| 365 | AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r | |
| 366 | @endcode\r | |
| 7de98828 | 367 | @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r |
| 04c980a6 MK |
368 | **/\r |
| 369 | #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r | |
| 370 | \r | |
| 371 | \r | |
| 372 | /**\r | |
| 373 | BIOS Update Signature (RO) Returns the microcode update signature following\r | |
| 374 | the execution of CPUID.01H. A processor may prevent writing to this MSR when\r | |
| 375 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 376 | Introduced at Display Family / Display Model 06_01H.\r | |
| 377 | \r | |
| 378 | @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r | |
| 379 | @param EAX Lower 32-bits of MSR value.\r | |
| 380 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 381 | @param EDX Upper 32-bits of MSR value.\r | |
| 382 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 383 | \r | |
| 384 | <b>Example usage</b>\r | |
| 385 | @code\r | |
| 386 | MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r | |
| 387 | \r | |
| 388 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r | |
| 389 | @endcode\r | |
| 7de98828 | 390 | @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r |
| 04c980a6 MK |
391 | **/\r |
| 392 | #define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r | |
| 393 | \r | |
| 394 | /**\r | |
| 395 | MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r | |
| 396 | **/\r | |
| 397 | typedef union {\r | |
| 398 | ///\r | |
| 399 | /// Individual bit fields\r | |
| 400 | ///\r | |
| 401 | struct {\r | |
| 402 | UINT32 Reserved:32;\r | |
| 403 | ///\r | |
| 404 | /// [Bits 63:32] Microcode update signature. This field contains the\r | |
| 405 | /// signature of the currently loaded microcode update when read following\r | |
| 406 | /// the execution of the CPUID instruction, function 1. It is required\r | |
| 407 | /// that this register field be pre-loaded with zero prior to executing\r | |
| 408 | /// the CPUID, function 1. If the field remains equal to zero, then there\r | |
| 409 | /// is no microcode update loaded. Another nonzero value will be the\r | |
| 410 | /// signature.\r | |
| 411 | ///\r | |
| 412 | UINT32 MicrocodeUpdateSignature:32;\r | |
| 413 | } Bits;\r | |
| 414 | ///\r | |
| 415 | /// All bit fields as a 64-bit value\r | |
| 416 | ///\r | |
| 417 | UINT64 Uint64;\r | |
| 418 | } MSR_IA32_BIOS_SIGN_ID_REGISTER;\r | |
| 419 | \r | |
| 420 | \r | |
| 421 | /**\r | |
| 831d287a | 422 | SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r |
| 04c980a6 MK |
423 | 1.\r |
| 424 | \r | |
| 425 | @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r | |
| 426 | @param EAX Lower 32-bits of MSR value.\r | |
| 427 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 428 | @param EDX Upper 32-bits of MSR value.\r | |
| 429 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 430 | \r | |
| 431 | <b>Example usage</b>\r | |
| 432 | @code\r | |
| 433 | MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r | |
| 434 | \r | |
| 435 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r | |
| 436 | AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r | |
| 437 | @endcode\r | |
| 7de98828 | 438 | @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r |
| 04c980a6 MK |
439 | **/\r |
| 440 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r | |
| 441 | \r | |
| 442 | /**\r | |
| 443 | MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r | |
| 444 | **/\r | |
| 445 | typedef union {\r | |
| 446 | ///\r | |
| 447 | /// Individual bit fields\r | |
| 448 | ///\r | |
| 449 | struct {\r | |
| 450 | ///\r | |
| 451 | /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r | |
| 452 | /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r | |
| 453 | /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r | |
| 454 | /// if the bit is 0. This bit is cleared when the logical processor is\r | |
| 455 | /// reset.\r | |
| 456 | ///\r | |
| 457 | UINT32 Valid:1;\r | |
| 458 | UINT32 Reserved1:1;\r | |
| 459 | ///\r | |
| 460 | /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the\r | |
| 461 | /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs\r | |
| 462 | /// unless bit 2 is 1 (the value of bit 0 is irrelevant).\r | |
| 463 | ///\r | |
| 464 | UINT32 BlockSmi:1;\r | |
| 465 | UINT32 Reserved2:9;\r | |
| 466 | ///\r | |
| 467 | /// [Bits 31:12] MSEG Base (R/W).\r | |
| 468 | ///\r | |
| 469 | UINT32 MsegBase:20;\r | |
| 470 | UINT32 Reserved3:32;\r | |
| 471 | } Bits;\r | |
| 472 | ///\r | |
| 473 | /// All bit fields as a 32-bit value\r | |
| 474 | ///\r | |
| 475 | UINT32 Uint32;\r | |
| 476 | ///\r | |
| 477 | /// All bit fields as a 64-bit value\r | |
| 478 | ///\r | |
| 479 | UINT64 Uint64;\r | |
| 480 | } MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r | |
| 481 | \r | |
| 831d287a MK |
482 | /**\r |
| 483 | MSEG header that is located at the physical address specified by the MsegBase\r | |
| 484 | field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 485 | **/\r | |
| 486 | typedef struct {\r | |
| 487 | UINT32 MsegHeaderRevision;\r | |
| 488 | UINT32 MonitorFeatures;\r | |
| 489 | UINT32 GdtrLimit;\r | |
| 490 | UINT32 GdtrBaseOffset;\r | |
| 491 | UINT32 CsSelector;\r | |
| 492 | UINT32 EipOffset;\r | |
| 493 | UINT32 EspOffset;\r | |
| 494 | UINT32 Cr3Offset;\r | |
| 495 | //\r | |
| 496 | // Pad header so total size is 2KB\r | |
| 497 | //\r | |
| 498 | UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r | |
| 499 | } MSEG_HEADER;\r | |
| 500 | \r | |
| 04c980a6 MK |
501 | \r |
| 502 | /**\r | |
| 503 | Base address of the logical processor's SMRAM image (RO, SMM only). If\r | |
| 504 | IA32_VMX_MISC[15].\r | |
| 505 | \r | |
| 506 | @param ECX MSR_IA32_SMBASE (0x0000009E)\r | |
| 507 | @param EAX Lower 32-bits of MSR value.\r | |
| 508 | @param EDX Upper 32-bits of MSR value.\r | |
| 509 | \r | |
| 510 | <b>Example usage</b>\r | |
| 511 | @code\r | |
| 512 | UINT64 Msr;\r | |
| 513 | \r | |
| 514 | Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r | |
| 515 | @endcode\r | |
| 7de98828 | 516 | @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r |
| 04c980a6 MK |
517 | **/\r |
| 518 | #define MSR_IA32_SMBASE 0x0000009E\r | |
| 519 | \r | |
| 520 | \r | |
| 521 | /**\r | |
| 522 | General Performance Counters (R/W).\r | |
| 523 | MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r | |
| 524 | \r | |
| 525 | @param ECX MSR_IA32_PMCn\r | |
| 526 | @param EAX Lower 32-bits of MSR value.\r | |
| 527 | @param EDX Upper 32-bits of MSR value.\r | |
| 528 | \r | |
| 529 | <b>Example usage</b>\r | |
| 530 | @code\r | |
| 531 | UINT64 Msr;\r | |
| 532 | \r | |
| 533 | Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r | |
| 534 | AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r | |
| 535 | @endcode\r | |
| 7de98828 JF |
536 | @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r |
| 537 | MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r | |
| 538 | MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r | |
| 539 | MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r | |
| 540 | MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r | |
| 541 | MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r | |
| 542 | MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r | |
| 543 | MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r | |
| 04c980a6 MK |
544 | @{\r |
| 545 | **/\r | |
| 546 | #define MSR_IA32_PMC0 0x000000C1\r | |
| 547 | #define MSR_IA32_PMC1 0x000000C2\r | |
| 548 | #define MSR_IA32_PMC2 0x000000C3\r | |
| 549 | #define MSR_IA32_PMC3 0x000000C4\r | |
| 550 | #define MSR_IA32_PMC4 0x000000C5\r | |
| 551 | #define MSR_IA32_PMC5 0x000000C6\r | |
| 552 | #define MSR_IA32_PMC6 0x000000C7\r | |
| 553 | #define MSR_IA32_PMC7 0x000000C8\r | |
| 554 | /// @}\r | |
| 555 | \r | |
| 556 | \r | |
| 557 | /**\r | |
| 558 | TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r | |
| 559 | C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r | |
| 560 | to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r | |
| 561 | wrap-around of IA32_APERF.\r | |
| 562 | \r | |
| 563 | @param ECX MSR_IA32_MPERF (0x000000E7)\r | |
| 564 | @param EAX Lower 32-bits of MSR value.\r | |
| 565 | @param EDX Upper 32-bits of MSR value.\r | |
| 566 | \r | |
| 567 | <b>Example usage</b>\r | |
| 568 | @code\r | |
| 569 | UINT64 Msr;\r | |
| 570 | \r | |
| 571 | Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r | |
| 572 | AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r | |
| 573 | @endcode\r | |
| 7de98828 | 574 | @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r |
| 04c980a6 MK |
575 | **/\r |
| 576 | #define MSR_IA32_MPERF 0x000000E7\r | |
| 577 | \r | |
| 578 | \r | |
| 579 | /**\r | |
| 580 | Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r | |
| 581 | 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r | |
| 582 | the coordinated clock frequency, when the logical processor is in C0.\r | |
| 583 | Cleared upon overflow / wrap-around of IA32_MPERF.\r | |
| 584 | \r | |
| 585 | @param ECX MSR_IA32_APERF (0x000000E8)\r | |
| 586 | @param EAX Lower 32-bits of MSR value.\r | |
| 587 | @param EDX Upper 32-bits of MSR value.\r | |
| 588 | \r | |
| 589 | <b>Example usage</b>\r | |
| 590 | @code\r | |
| 591 | UINT64 Msr;\r | |
| 592 | \r | |
| 593 | Msr = AsmReadMsr64 (MSR_IA32_APERF);\r | |
| 594 | AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r | |
| 595 | @endcode\r | |
| 7de98828 | 596 | @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r |
| 04c980a6 MK |
597 | **/\r |
| 598 | #define MSR_IA32_APERF 0x000000E8\r | |
| 599 | \r | |
| 600 | \r | |
| 601 | /**\r | |
| 602 | MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r | |
| 603 | Introduced at Display Family / Display Model 06_01H.\r | |
| 604 | \r | |
| 605 | @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r | |
| 606 | @param EAX Lower 32-bits of MSR value.\r | |
| 607 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 608 | @param EDX Upper 32-bits of MSR value.\r | |
| 609 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 610 | \r | |
| 611 | <b>Example usage</b>\r | |
| 612 | @code\r | |
| 613 | MSR_IA32_MTRRCAP_REGISTER Msr;\r | |
| 614 | \r | |
| 615 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r | |
| 616 | @endcode\r | |
| 7de98828 | 617 | @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r |
| 04c980a6 MK |
618 | **/\r |
| 619 | #define MSR_IA32_MTRRCAP 0x000000FE\r | |
| 620 | \r | |
| 621 | /**\r | |
| 622 | MSR information returned for MSR index #MSR_IA32_MTRRCAP\r | |
| 623 | **/\r | |
| 624 | typedef union {\r | |
| 625 | ///\r | |
| 626 | /// Individual bit fields\r | |
| 627 | ///\r | |
| 628 | struct {\r | |
| 629 | ///\r | |
| 630 | /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r | |
| 631 | /// processor.\r | |
| 632 | ///\r | |
| 633 | UINT32 VCNT:8;\r | |
| 634 | ///\r | |
| 635 | /// [Bit 8] Fixed range MTRRs are supported when set.\r | |
| 636 | ///\r | |
| 637 | UINT32 FIX:1;\r | |
| 638 | UINT32 Reserved1:1;\r | |
| 639 | ///\r | |
| 640 | /// [Bit 10] WC Supported when set.\r | |
| 641 | ///\r | |
| 642 | UINT32 WC:1;\r | |
| 643 | ///\r | |
| 644 | /// [Bit 11] SMRR Supported when set.\r | |
| 645 | ///\r | |
| 646 | UINT32 SMRR:1;\r | |
| 647 | UINT32 Reserved2:20;\r | |
| 648 | UINT32 Reserved3:32;\r | |
| 649 | } Bits;\r | |
| 650 | ///\r | |
| 651 | /// All bit fields as a 32-bit value\r | |
| 652 | ///\r | |
| 653 | UINT32 Uint32;\r | |
| 654 | ///\r | |
| 655 | /// All bit fields as a 64-bit value\r | |
| 656 | ///\r | |
| 657 | UINT64 Uint64;\r | |
| 658 | } MSR_IA32_MTRRCAP_REGISTER;\r | |
| 659 | \r | |
| 660 | \r | |
| 661 | /**\r | |
| 662 | SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 663 | \r | |
| 664 | @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r | |
| 665 | @param EAX Lower 32-bits of MSR value.\r | |
| 666 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 667 | @param EDX Upper 32-bits of MSR value.\r | |
| 668 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 669 | \r | |
| 670 | <b>Example usage</b>\r | |
| 671 | @code\r | |
| 672 | MSR_IA32_SYSENTER_CS_REGISTER Msr;\r | |
| 673 | \r | |
| 674 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r | |
| 675 | AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r | |
| 676 | @endcode\r | |
| 7de98828 | 677 | @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r |
| 04c980a6 MK |
678 | **/\r |
| 679 | #define MSR_IA32_SYSENTER_CS 0x00000174\r | |
| 680 | \r | |
| 681 | /**\r | |
| 682 | MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r | |
| 683 | **/\r | |
| 684 | typedef union {\r | |
| 685 | ///\r | |
| 686 | /// Individual bit fields\r | |
| 687 | ///\r | |
| 688 | struct {\r | |
| 689 | ///\r | |
| 690 | /// [Bits 15:0] CS Selector.\r | |
| 691 | ///\r | |
| 692 | UINT32 CS:16;\r | |
| 693 | UINT32 Reserved1:16;\r | |
| 694 | UINT32 Reserved2:32;\r | |
| 695 | } Bits;\r | |
| 696 | ///\r | |
| 697 | /// All bit fields as a 32-bit value\r | |
| 698 | ///\r | |
| 699 | UINT32 Uint32;\r | |
| 700 | ///\r | |
| 701 | /// All bit fields as a 64-bit value\r | |
| 702 | ///\r | |
| 703 | UINT64 Uint64;\r | |
| 704 | } MSR_IA32_SYSENTER_CS_REGISTER;\r | |
| 705 | \r | |
| 706 | \r | |
| 707 | /**\r | |
| 708 | SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 709 | \r | |
| 710 | @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r | |
| 711 | @param EAX Lower 32-bits of MSR value.\r | |
| 712 | @param EDX Upper 32-bits of MSR value.\r | |
| 713 | \r | |
| 714 | <b>Example usage</b>\r | |
| 715 | @code\r | |
| 716 | UINT64 Msr;\r | |
| 717 | \r | |
| 718 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r | |
| 719 | AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r | |
| 720 | @endcode\r | |
| 7de98828 | 721 | @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r |
| 04c980a6 MK |
722 | **/\r |
| 723 | #define MSR_IA32_SYSENTER_ESP 0x00000175\r | |
| 724 | \r | |
| 725 | \r | |
| 726 | /**\r | |
| 727 | SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 728 | \r | |
| 729 | @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r | |
| 730 | @param EAX Lower 32-bits of MSR value.\r | |
| 731 | @param EDX Upper 32-bits of MSR value.\r | |
| 732 | \r | |
| 733 | <b>Example usage</b>\r | |
| 734 | @code\r | |
| 735 | UINT64 Msr;\r | |
| 736 | \r | |
| 737 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r | |
| 738 | AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r | |
| 739 | @endcode\r | |
| 7de98828 | 740 | @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r |
| 04c980a6 MK |
741 | **/\r |
| 742 | #define MSR_IA32_SYSENTER_EIP 0x00000176\r | |
| 743 | \r | |
| 744 | \r | |
| 745 | /**\r | |
| 746 | Global Machine Check Capability (RO). Introduced at Display Family / Display\r | |
| 747 | Model 06_01H.\r | |
| 748 | \r | |
| 749 | @param ECX MSR_IA32_MCG_CAP (0x00000179)\r | |
| 750 | @param EAX Lower 32-bits of MSR value.\r | |
| 751 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 752 | @param EDX Upper 32-bits of MSR value.\r | |
| 753 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 754 | \r | |
| 755 | <b>Example usage</b>\r | |
| 756 | @code\r | |
| 757 | MSR_IA32_MCG_CAP_REGISTER Msr;\r | |
| 758 | \r | |
| 759 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
| 760 | @endcode\r | |
| 7de98828 | 761 | @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r |
| 04c980a6 MK |
762 | **/\r |
| 763 | #define MSR_IA32_MCG_CAP 0x00000179\r | |
| 764 | \r | |
| 765 | /**\r | |
| 766 | MSR information returned for MSR index #MSR_IA32_MCG_CAP\r | |
| 767 | **/\r | |
| 768 | typedef union {\r | |
| 769 | ///\r | |
| 770 | /// Individual bit fields\r | |
| 771 | ///\r | |
| 772 | struct {\r | |
| 773 | ///\r | |
| 774 | /// [Bits 7:0] Count: Number of reporting banks.\r | |
| 775 | ///\r | |
| 776 | UINT32 Count:8;\r | |
| 777 | ///\r | |
| 778 | /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r | |
| 779 | ///\r | |
| 780 | UINT32 MCG_CTL_P:1;\r | |
| 781 | ///\r | |
| 782 | /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r | |
| 783 | /// if this bit is set.\r | |
| 784 | ///\r | |
| 785 | UINT32 MCG_EXT_P:1;\r | |
| 786 | ///\r | |
| 787 | /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r | |
| 788 | /// Introduced at Display Family / Display Model 06_01H.\r | |
| 789 | ///\r | |
| 790 | UINT32 MCP_CMCI_P:1;\r | |
| 791 | ///\r | |
| 792 | /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r | |
| 793 | /// if this bit is set.\r | |
| 794 | ///\r | |
| 795 | UINT32 MCG_TES_P:1;\r | |
| 796 | UINT32 Reserved1:4;\r | |
| 797 | ///\r | |
| 798 | /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r | |
| 799 | /// registers present.\r | |
| 800 | ///\r | |
| 801 | UINT32 MCG_EXT_CNT:8;\r | |
| 802 | ///\r | |
| 803 | /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r | |
| 804 | /// this bit is set.\r | |
| 805 | ///\r | |
| 806 | UINT32 MCG_SER_P:1;\r | |
| 807 | UINT32 Reserved2:1;\r | |
| 808 | ///\r | |
| 809 | /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r | |
| 810 | /// firmware to be invoked when an error is detected so that it may\r | |
| 811 | /// provide additional platform specific information in an ACPI format\r | |
| 812 | /// "Generic Error Data Entry" that augments the data included in machine\r | |
| 813 | /// check bank registers. Introduced at Display Family / Display Model\r | |
| 814 | /// 06_3EH.\r | |
| 815 | ///\r | |
| 816 | UINT32 MCG_ELOG_P:1;\r | |
| 817 | ///\r | |
| 818 | /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r | |
| 819 | /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r | |
| 820 | /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r | |
| 821 | /// Display Model 06_3EH.\r | |
| 822 | ///\r | |
| 823 | UINT32 MCG_LMCE_P:1;\r | |
| 824 | UINT32 Reserved3:4;\r | |
| 825 | UINT32 Reserved4:32;\r | |
| 826 | } Bits;\r | |
| 827 | ///\r | |
| 828 | /// All bit fields as a 32-bit value\r | |
| 829 | ///\r | |
| 830 | UINT32 Uint32;\r | |
| 831 | ///\r | |
| 832 | /// All bit fields as a 64-bit value\r | |
| 833 | ///\r | |
| 834 | UINT64 Uint64;\r | |
| 835 | } MSR_IA32_MCG_CAP_REGISTER;\r | |
| 836 | \r | |
| 837 | \r | |
| 838 | /**\r | |
| 839 | Global Machine Check Status (R/W0). Introduced at Display Family / Display\r | |
| 840 | Model 06_01H.\r | |
| 841 | \r | |
| 842 | @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r | |
| 843 | @param EAX Lower 32-bits of MSR value.\r | |
| 844 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 845 | @param EDX Upper 32-bits of MSR value.\r | |
| 846 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 847 | \r | |
| 848 | <b>Example usage</b>\r | |
| 849 | @code\r | |
| 850 | MSR_IA32_MCG_STATUS_REGISTER Msr;\r | |
| 851 | \r | |
| 852 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r | |
| 853 | AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r | |
| 854 | @endcode\r | |
| 7de98828 | 855 | @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r |
| 04c980a6 MK |
856 | **/\r |
| 857 | #define MSR_IA32_MCG_STATUS 0x0000017A\r | |
| 858 | \r | |
| 859 | /**\r | |
| 860 | MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r | |
| 861 | **/\r | |
| 862 | typedef union {\r | |
| 863 | ///\r | |
| 864 | /// Individual bit fields\r | |
| 865 | ///\r | |
| 866 | struct {\r | |
| 867 | ///\r | |
| 868 | /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r | |
| 869 | /// Model 06_01H.\r | |
| 870 | ///\r | |
| 871 | UINT32 RIPV:1;\r | |
| 872 | ///\r | |
| 873 | /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r | |
| 874 | /// Model 06_01H.\r | |
| 875 | ///\r | |
| 876 | UINT32 EIPV:1;\r | |
| 877 | ///\r | |
| 878 | /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r | |
| 879 | /// / Display Model 06_01H.\r | |
| 880 | ///\r | |
| 881 | UINT32 MCIP:1;\r | |
| 882 | ///\r | |
| 883 | /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r | |
| 884 | ///\r | |
| 885 | UINT32 LMCE_S:1;\r | |
| 886 | UINT32 Reserved1:28;\r | |
| 887 | UINT32 Reserved2:32;\r | |
| 888 | } Bits;\r | |
| 889 | ///\r | |
| 890 | /// All bit fields as a 32-bit value\r | |
| 891 | ///\r | |
| 892 | UINT32 Uint32;\r | |
| 893 | ///\r | |
| 894 | /// All bit fields as a 64-bit value\r | |
| 895 | ///\r | |
| 896 | UINT64 Uint64;\r | |
| 897 | } MSR_IA32_MCG_STATUS_REGISTER;\r | |
| 898 | \r | |
| 899 | \r | |
| 900 | /**\r | |
| 901 | Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r | |
| 902 | \r | |
| 903 | @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r | |
| 904 | @param EAX Lower 32-bits of MSR value.\r | |
| 905 | @param EDX Upper 32-bits of MSR value.\r | |
| 906 | \r | |
| 907 | <b>Example usage</b>\r | |
| 908 | @code\r | |
| 909 | UINT64 Msr;\r | |
| 910 | \r | |
| 911 | Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r | |
| 912 | AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r | |
| 913 | @endcode\r | |
| 7de98828 | 914 | @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r |
| 04c980a6 MK |
915 | **/\r |
| 916 | #define MSR_IA32_MCG_CTL 0x0000017B\r | |
| 917 | \r | |
| 918 | \r | |
| 919 | /**\r | |
| 920 | Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r | |
| 921 | \r | |
| 922 | @param ECX MSR_IA32_PERFEVTSELn\r | |
| 923 | @param EAX Lower 32-bits of MSR value.\r | |
| 924 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 925 | @param EDX Upper 32-bits of MSR value.\r | |
| 926 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 927 | \r | |
| 928 | <b>Example usage</b>\r | |
| 929 | @code\r | |
| 930 | MSR_IA32_PERFEVTSEL_REGISTER Msr;\r | |
| 931 | \r | |
| 932 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r | |
| 933 | AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r | |
| 934 | @endcode\r | |
| 7de98828 JF |
935 | @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r |
| 936 | MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r | |
| 937 | MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r | |
| 938 | MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r | |
| 04c980a6 MK |
939 | @{\r |
| 940 | **/\r | |
| 941 | #define MSR_IA32_PERFEVTSEL0 0x00000186\r | |
| 942 | #define MSR_IA32_PERFEVTSEL1 0x00000187\r | |
| 943 | #define MSR_IA32_PERFEVTSEL2 0x00000188\r | |
| 944 | #define MSR_IA32_PERFEVTSEL3 0x00000189\r | |
| 945 | /// @}\r | |
| 946 | \r | |
| 947 | /**\r | |
| 948 | MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r | |
| 949 | #MSR_IA32_PERFEVTSEL3\r | |
| 950 | **/\r | |
| 951 | typedef union {\r | |
| 952 | ///\r | |
| 953 | /// Individual bit fields\r | |
| 954 | ///\r | |
| 955 | struct {\r | |
| 956 | ///\r | |
| 957 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 958 | ///\r | |
| 959 | UINT32 EventSelect:8;\r | |
| 960 | ///\r | |
| 961 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 962 | /// detect on the selected event logic.\r | |
| 963 | ///\r | |
| 964 | UINT32 UMASK:8;\r | |
| 965 | ///\r | |
| 966 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 967 | ///\r | |
| 968 | UINT32 USR:1;\r | |
| 969 | ///\r | |
| 970 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 971 | ///\r | |
| 972 | UINT32 OS:1;\r | |
| 973 | ///\r | |
| 974 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 975 | ///\r | |
| 976 | UINT32 E:1;\r | |
| 977 | ///\r | |
| 978 | /// [Bit 19] PC: enables pin control.\r | |
| 979 | ///\r | |
| 980 | UINT32 PC:1;\r | |
| 981 | ///\r | |
| 982 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 983 | ///\r | |
| 984 | UINT32 INT:1;\r | |
| 985 | ///\r | |
| 986 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 987 | /// event conditions occurring across all logical processors sharing a\r | |
| 988 | /// processor core. When set to 0, the counter only increments the\r | |
| 989 | /// associated event conditions occurring in the logical processor which\r | |
| 990 | /// programmed the MSR.\r | |
| 991 | ///\r | |
| 992 | UINT32 ANY:1;\r | |
| 993 | ///\r | |
| 994 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 995 | /// counting when this bit is set.\r | |
| 996 | ///\r | |
| 997 | UINT32 EN:1;\r | |
| 998 | ///\r | |
| 999 | /// [Bit 23] INV: invert the CMASK.\r | |
| 1000 | ///\r | |
| 1001 | UINT32 INV:1;\r | |
| 1002 | ///\r | |
| 1003 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 1004 | /// performance counter increments each cycle if the event count is\r | |
| 1005 | /// greater than or equal to the CMASK.\r | |
| 1006 | ///\r | |
| 1007 | UINT32 CMASK:8;\r | |
| 1008 | UINT32 Reserved:32;\r | |
| 1009 | } Bits;\r | |
| 1010 | ///\r | |
| 1011 | /// All bit fields as a 32-bit value\r | |
| 1012 | ///\r | |
| 1013 | UINT32 Uint32;\r | |
| 1014 | ///\r | |
| 1015 | /// All bit fields as a 64-bit value\r | |
| 1016 | ///\r | |
| 1017 | UINT64 Uint64;\r | |
| 1018 | } MSR_IA32_PERFEVTSEL_REGISTER;\r | |
| 1019 | \r | |
| 1020 | \r | |
| 1021 | /**\r | |
| 1022 | Current performance state(P-State) operating point (RO). Introduced at\r | |
| 1023 | Display Family / Display Model 0F_03H.\r | |
| 1024 | \r | |
| 1025 | @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r | |
| 1026 | @param EAX Lower 32-bits of MSR value.\r | |
| 1027 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1028 | @param EDX Upper 32-bits of MSR value.\r | |
| 1029 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1030 | \r | |
| 1031 | <b>Example usage</b>\r | |
| 1032 | @code\r | |
| 1033 | MSR_IA32_PERF_STATUS_REGISTER Msr;\r | |
| 1034 | \r | |
| 1035 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r | |
| 1036 | @endcode\r | |
| 7de98828 | 1037 | @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r |
| 04c980a6 MK |
1038 | **/\r |
| 1039 | #define MSR_IA32_PERF_STATUS 0x00000198\r | |
| 1040 | \r | |
| 1041 | /**\r | |
| 1042 | MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r | |
| 1043 | **/\r | |
| 1044 | typedef union {\r | |
| 1045 | ///\r | |
| 1046 | /// Individual bit fields\r | |
| 1047 | ///\r | |
| 1048 | struct {\r | |
| 1049 | ///\r | |
| 1050 | /// [Bits 15:0] Current performance State Value.\r | |
| 1051 | ///\r | |
| 1052 | UINT32 State:16;\r | |
| 1053 | UINT32 Reserved1:16;\r | |
| 1054 | UINT32 Reserved2:32;\r | |
| 1055 | } Bits;\r | |
| 1056 | ///\r | |
| 1057 | /// All bit fields as a 32-bit value\r | |
| 1058 | ///\r | |
| 1059 | UINT32 Uint32;\r | |
| 1060 | ///\r | |
| 1061 | /// All bit fields as a 64-bit value\r | |
| 1062 | ///\r | |
| 1063 | UINT64 Uint64;\r | |
| 1064 | } MSR_IA32_PERF_STATUS_REGISTER;\r | |
| 1065 | \r | |
| 1066 | \r | |
| 1067 | /**\r | |
| 1068 | (R/W). Introduced at Display Family / Display Model 0F_03H.\r | |
| 1069 | \r | |
| 1070 | @param ECX MSR_IA32_PERF_CTL (0x00000199)\r | |
| 1071 | @param EAX Lower 32-bits of MSR value.\r | |
| 1072 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1073 | @param EDX Upper 32-bits of MSR value.\r | |
| 1074 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1075 | \r | |
| 1076 | <b>Example usage</b>\r | |
| 1077 | @code\r | |
| 1078 | MSR_IA32_PERF_CTL_REGISTER Msr;\r | |
| 1079 | \r | |
| 1080 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r | |
| 1081 | AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r | |
| 1082 | @endcode\r | |
| 7de98828 | 1083 | @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r |
| 04c980a6 MK |
1084 | **/\r |
| 1085 | #define MSR_IA32_PERF_CTL 0x00000199\r | |
| 1086 | \r | |
| 1087 | /**\r | |
| 1088 | MSR information returned for MSR index #MSR_IA32_PERF_CTL\r | |
| 1089 | **/\r | |
| 1090 | typedef union {\r | |
| 1091 | ///\r | |
| 1092 | /// Individual bit fields\r | |
| 1093 | ///\r | |
| 1094 | struct {\r | |
| 1095 | ///\r | |
| 1096 | /// [Bits 15:0] Target performance State Value.\r | |
| 1097 | ///\r | |
| 1098 | UINT32 TargetState:16;\r | |
| 1099 | UINT32 Reserved1:16;\r | |
| 1100 | ///\r | |
| 1101 | /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r | |
| 1102 | /// (Mobile only).\r | |
| 1103 | ///\r | |
| 1104 | UINT32 IDA:1;\r | |
| 1105 | UINT32 Reserved2:31;\r | |
| 1106 | } Bits;\r | |
| 1107 | ///\r | |
| 1108 | /// All bit fields as a 64-bit value\r | |
| 1109 | ///\r | |
| 1110 | UINT64 Uint64;\r | |
| 1111 | } MSR_IA32_PERF_CTL_REGISTER;\r | |
| 1112 | \r | |
| 1113 | \r | |
| 1114 | /**\r | |
| 1115 | Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r | |
| 1116 | Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.\r | |
| 1117 | \r | |
| 1118 | @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r | |
| 1119 | @param EAX Lower 32-bits of MSR value.\r | |
| 1120 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1121 | @param EDX Upper 32-bits of MSR value.\r | |
| 1122 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1123 | \r | |
| 1124 | <b>Example usage</b>\r | |
| 1125 | @code\r | |
| 1126 | MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r | |
| 1127 | \r | |
| 1128 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r | |
| 1129 | AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r | |
| 1130 | @endcode\r | |
| 7de98828 | 1131 | @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r |
| 04c980a6 MK |
1132 | **/\r |
| 1133 | #define MSR_IA32_CLOCK_MODULATION 0x0000019A\r | |
| 1134 | \r | |
| 1135 | /**\r | |
| 1136 | MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r | |
| 1137 | **/\r | |
| 1138 | typedef union {\r | |
| 1139 | ///\r | |
| 1140 | /// Individual bit fields\r | |
| 1141 | ///\r | |
| 1142 | struct {\r | |
| 1143 | ///\r | |
| 1144 | /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r | |
| 1145 | /// CPUID.06H:EAX[5] = 1.\r | |
| 1146 | ///\r | |
| 1147 | UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r | |
| 1148 | ///\r | |
| 1149 | /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r | |
| 1150 | /// values for target duty cycle modulation.\r | |
| 1151 | ///\r | |
| 1152 | UINT32 OnDemandClockModulationDutyCycle:3;\r | |
| 1153 | ///\r | |
| 1154 | /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r | |
| 1155 | ///\r | |
| 1156 | UINT32 OnDemandClockModulationEnable:1;\r | |
| 1157 | UINT32 Reserved1:27;\r | |
| 1158 | UINT32 Reserved2:32;\r | |
| 1159 | } Bits;\r | |
| 1160 | ///\r | |
| 1161 | /// All bit fields as a 32-bit value\r | |
| 1162 | ///\r | |
| 1163 | UINT32 Uint32;\r | |
| 1164 | ///\r | |
| 1165 | /// All bit fields as a 64-bit value\r | |
| 1166 | ///\r | |
| 1167 | UINT64 Uint64;\r | |
| 1168 | } MSR_IA32_CLOCK_MODULATION_REGISTER;\r | |
| 1169 | \r | |
| 1170 | \r | |
| 1171 | /**\r | |
| 1172 | Thermal Interrupt Control (R/W) Enables and disables the generation of an\r | |
| 1173 | interrupt on temperature transitions detected with the processor's thermal\r | |
| 1174 | sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r | |
| 1175 | Introduced at Display Family / Display Model 0F_0H.\r | |
| 1176 | \r | |
| 1177 | @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r | |
| 1178 | @param EAX Lower 32-bits of MSR value.\r | |
| 1179 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1180 | @param EDX Upper 32-bits of MSR value.\r | |
| 1181 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1182 | \r | |
| 1183 | <b>Example usage</b>\r | |
| 1184 | @code\r | |
| 1185 | MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1186 | \r | |
| 1187 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r | |
| 1188 | AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1189 | @endcode\r | |
| 7de98828 | 1190 | @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1191 | **/\r |
| 1192 | #define MSR_IA32_THERM_INTERRUPT 0x0000019B\r | |
| 1193 | \r | |
| 1194 | /**\r | |
| 1195 | MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r | |
| 1196 | **/\r | |
| 1197 | typedef union {\r | |
| 1198 | ///\r | |
| 1199 | /// Individual bit fields\r | |
| 1200 | ///\r | |
| 1201 | struct {\r | |
| 1202 | ///\r | |
| 1203 | /// [Bit 0] High-Temperature Interrupt Enable.\r | |
| 1204 | ///\r | |
| 1205 | UINT32 HighTempEnable:1;\r | |
| 1206 | ///\r | |
| 1207 | /// [Bit 1] Low-Temperature Interrupt Enable.\r | |
| 1208 | ///\r | |
| 1209 | UINT32 LowTempEnable:1;\r | |
| 1210 | ///\r | |
| 1211 | /// [Bit 2] PROCHOT# Interrupt Enable.\r | |
| 1212 | ///\r | |
| 1213 | UINT32 PROCHOT_Enable:1;\r | |
| 1214 | ///\r | |
| 1215 | /// [Bit 3] FORCEPR# Interrupt Enable.\r | |
| 1216 | ///\r | |
| 1217 | UINT32 FORCEPR_Enable:1;\r | |
| 1218 | ///\r | |
| 1219 | /// [Bit 4] Critical Temperature Interrupt Enable.\r | |
| 1220 | ///\r | |
| 1221 | UINT32 CriticalTempEnable:1;\r | |
| 1222 | UINT32 Reserved1:3;\r | |
| 1223 | ///\r | |
| 1224 | /// [Bits 14:8] Threshold #1 Value.\r | |
| 1225 | ///\r | |
| 1226 | UINT32 Threshold1:7;\r | |
| 1227 | ///\r | |
| 1228 | /// [Bit 15] Threshold #1 Interrupt Enable.\r | |
| 1229 | ///\r | |
| 1230 | UINT32 Threshold1Enable:1;\r | |
| 1231 | ///\r | |
| 1232 | /// [Bits 22:16] Threshold #2 Value.\r | |
| 1233 | ///\r | |
| 1234 | UINT32 Threshold2:7;\r | |
| 1235 | ///\r | |
| 1236 | /// [Bit 23] Threshold #2 Interrupt Enable.\r | |
| 1237 | ///\r | |
| 1238 | UINT32 Threshold2Enable:1;\r | |
| 1239 | ///\r | |
| 1240 | /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r | |
| 1241 | ///\r | |
| 1242 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1243 | UINT32 Reserved2:7;\r | |
| 1244 | UINT32 Reserved3:32;\r | |
| 1245 | } Bits;\r | |
| 1246 | ///\r | |
| 1247 | /// All bit fields as a 32-bit value\r | |
| 1248 | ///\r | |
| 1249 | UINT32 Uint32;\r | |
| 1250 | ///\r | |
| 1251 | /// All bit fields as a 64-bit value\r | |
| 1252 | ///\r | |
| 1253 | UINT64 Uint64;\r | |
| 1254 | } MSR_IA32_THERM_INTERRUPT_REGISTER;\r | |
| 1255 | \r | |
| 1256 | \r | |
| 1257 | /**\r | |
| 1258 | Thermal Status Information (RO) Contains status information about the\r | |
| 1259 | processor's thermal sensor and automatic thermal monitoring facilities. See\r | |
| 1260 | Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display\r | |
| 1261 | Model 0F_0H.\r | |
| 1262 | \r | |
| 1263 | @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r | |
| 1264 | @param EAX Lower 32-bits of MSR value.\r | |
| 1265 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1266 | @param EDX Upper 32-bits of MSR value.\r | |
| 1267 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1268 | \r | |
| 1269 | <b>Example usage</b>\r | |
| 1270 | @code\r | |
| 1271 | MSR_IA32_THERM_STATUS_REGISTER Msr;\r | |
| 1272 | \r | |
| 1273 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r | |
| 1274 | @endcode\r | |
| 7de98828 | 1275 | @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1276 | **/\r |
| 1277 | #define MSR_IA32_THERM_STATUS 0x0000019C\r | |
| 1278 | \r | |
| 1279 | /**\r | |
| 1280 | MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r | |
| 1281 | **/\r | |
| 1282 | typedef union {\r | |
| 1283 | ///\r | |
| 1284 | /// Individual bit fields\r | |
| 1285 | ///\r | |
| 1286 | struct {\r | |
| 1287 | ///\r | |
| 1288 | /// [Bit 0] Thermal Status (RO):.\r | |
| 1289 | ///\r | |
| 1290 | UINT32 ThermalStatus:1;\r | |
| 1291 | ///\r | |
| 1292 | /// [Bit 1] Thermal Status Log (R/W):.\r | |
| 1293 | ///\r | |
| 1294 | UINT32 ThermalStatusLog:1;\r | |
| 1295 | ///\r | |
| 1296 | /// [Bit 2] PROCHOT # or FORCEPR# event (RO).\r | |
| 1297 | ///\r | |
| 1298 | UINT32 PROCHOT_FORCEPR_Event:1;\r | |
| 1299 | ///\r | |
| 1300 | /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).\r | |
| 1301 | ///\r | |
| 1302 | UINT32 PROCHOT_FORCEPR_Log:1;\r | |
| 1303 | ///\r | |
| 1304 | /// [Bit 4] Critical Temperature Status (RO).\r | |
| 1305 | ///\r | |
| 1306 | UINT32 CriticalTempStatus:1;\r | |
| 1307 | ///\r | |
| 1308 | /// [Bit 5] Critical Temperature Status log (R/WC0).\r | |
| 1309 | ///\r | |
| 1310 | UINT32 CriticalTempStatusLog:1;\r | |
| 1311 | ///\r | |
| 1312 | /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1313 | ///\r | |
| 1314 | UINT32 ThermalThreshold1Status:1;\r | |
| 1315 | ///\r | |
| 1316 | /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1317 | ///\r | |
| 1318 | UINT32 ThermalThreshold1Log:1;\r | |
| 1319 | ///\r | |
| 1320 | /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1321 | ///\r | |
| 1322 | UINT32 ThermalThreshold2Status:1;\r | |
| 1323 | ///\r | |
| 1324 | /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1325 | ///\r | |
| 1326 | UINT32 ThermalThreshold2Log:1;\r | |
| 1327 | ///\r | |
| 1328 | /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r | |
| 1329 | ///\r | |
| 1330 | UINT32 PowerLimitStatus:1;\r | |
| 1331 | ///\r | |
| 1332 | /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r | |
| 1333 | ///\r | |
| 1334 | UINT32 PowerLimitLog:1;\r | |
| 1335 | ///\r | |
| 1336 | /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1337 | ///\r | |
| 1338 | UINT32 CurrentLimitStatus:1;\r | |
| 1339 | ///\r | |
| 1340 | /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1341 | ///\r | |
| 1342 | UINT32 CurrentLimitLog:1;\r | |
| 1343 | ///\r | |
| 1344 | /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1345 | ///\r | |
| 1346 | UINT32 CrossDomainLimitStatus:1;\r | |
| 1347 | ///\r | |
| 1348 | /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1349 | ///\r | |
| 1350 | UINT32 CrossDomainLimitLog:1;\r | |
| 1351 | ///\r | |
| 1352 | /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1353 | ///\r | |
| 1354 | UINT32 DigitalReadout:7;\r | |
| 1355 | UINT32 Reserved1:4;\r | |
| 1356 | ///\r | |
| 1357 | /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r | |
| 1358 | /// 1.\r | |
| 1359 | ///\r | |
| 1360 | UINT32 ResolutionInDegreesCelsius:4;\r | |
| 1361 | ///\r | |
| 1362 | /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1363 | ///\r | |
| 1364 | UINT32 ReadingValid:1;\r | |
| 1365 | UINT32 Reserved2:32;\r | |
| 1366 | } Bits;\r | |
| 1367 | ///\r | |
| 1368 | /// All bit fields as a 32-bit value\r | |
| 1369 | ///\r | |
| 1370 | UINT32 Uint32;\r | |
| 1371 | ///\r | |
| 1372 | /// All bit fields as a 64-bit value\r | |
| 1373 | ///\r | |
| 1374 | UINT64 Uint64;\r | |
| 1375 | } MSR_IA32_THERM_STATUS_REGISTER;\r | |
| 1376 | \r | |
| 1377 | \r | |
| 1378 | /**\r | |
| 1379 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
| 1380 | functions to be enabled and disabled.\r | |
| 1381 | \r | |
| 1382 | @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r | |
| 1383 | @param EAX Lower 32-bits of MSR value.\r | |
| 1384 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1385 | @param EDX Upper 32-bits of MSR value.\r | |
| 1386 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1387 | \r | |
| 1388 | <b>Example usage</b>\r | |
| 1389 | @code\r | |
| 1390 | MSR_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 1391 | \r | |
| 1392 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r | |
| 1393 | AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 1394 | @endcode\r | |
| 7de98828 | 1395 | @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
| 04c980a6 MK |
1396 | **/\r |
| 1397 | #define MSR_IA32_MISC_ENABLE 0x000001A0\r | |
| 1398 | \r | |
| 1399 | /**\r | |
| 1400 | MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r | |
| 1401 | **/\r | |
| 1402 | typedef union {\r | |
| 1403 | ///\r | |
| 1404 | /// Individual bit fields\r | |
| 1405 | ///\r | |
| 1406 | struct {\r | |
| 1407 | ///\r | |
| 1408 | /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r | |
| 1409 | /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r | |
| 1410 | /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r | |
| 1411 | ///\r | |
| 1412 | UINT32 FastStrings:1;\r | |
| 1413 | UINT32 Reserved1:2;\r | |
| 1414 | ///\r | |
| 1415 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r | |
| 1416 | /// this bit enables the thermal control circuit (TCC) portion of the\r | |
| 1417 | /// Intel Thermal Monitor feature. This allows the processor to\r | |
| 1418 | /// automatically reduce power consumption in response to TCC activation.\r | |
| 1419 | /// 0 = Disabled. Note: In some products clearing this bit might be\r | |
| 1420 | /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r | |
| 1421 | /// thermal throttling will still be activated. Introduced at Display\r | |
| 1422 | /// Family / Display Model 0F_0H.\r | |
| 1423 | ///\r | |
| 1424 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 1425 | UINT32 Reserved2:3;\r | |
| 1426 | ///\r | |
| 1427 | /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r | |
| 1428 | /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r | |
| 1429 | /// Display Family / Display Model 0F_0H.\r | |
| 1430 | ///\r | |
| 1431 | UINT32 PerformanceMonitoring:1;\r | |
| 1432 | UINT32 Reserved3:3;\r | |
| 1433 | ///\r | |
| 1434 | /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r | |
| 1435 | /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r | |
| 1436 | /// Display Family / Display Model 0F_0H.\r | |
| 1437 | ///\r | |
| 1438 | UINT32 BTS:1;\r | |
| 1439 | ///\r | |
| 1440 | /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =\r | |
| 1441 | /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r | |
| 1442 | /// Family / Display Model 06_0FH.\r | |
| 1443 | ///\r | |
| 1444 | UINT32 PEBS:1;\r | |
| 1445 | UINT32 Reserved4:3;\r | |
| 1446 | ///\r | |
| 1447 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r | |
| 1448 | /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r | |
| 1449 | /// Technology enabled. If CPUID.01H: ECX[7] =1.\r | |
| 1450 | ///\r | |
| 1451 | UINT32 EIST:1;\r | |
| 1452 | UINT32 Reserved5:1;\r | |
| 1453 | ///\r | |
| 1454 | /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r | |
| 1455 | /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r | |
| 1456 | /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r | |
| 1457 | /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r | |
| 1458 | /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r | |
| 1459 | /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r | |
| 1460 | /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r | |
| 1461 | /// in the default state. Writing this bit when the SSE3 feature flag is\r | |
| 1462 | /// set to 0 may generate a #GP exception. Introduced at Display Family /\r | |
| 1463 | /// Display Model 0F_03H.\r | |
| 1464 | ///\r | |
| 1465 | UINT32 MONITOR:1;\r | |
| 1466 | UINT32 Reserved6:3;\r | |
| 1467 | ///\r | |
| 1468 | /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r | |
| 1469 | /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup\r | |
| 1470 | /// question that allows users to specify when the installed OS does not\r | |
| 1471 | /// support CPUID functions greater than 3. Before setting this bit, BIOS\r | |
| 1472 | /// must execute the CPUID.0H and examine the maximum value returned in\r | |
| 1473 | /// EAX[7:0]. If the maximum value is greater than 3, the bit is\r | |
| 1474 | /// supported. Otherwise, the bit is not supported. Writing to this bit\r | |
| 1475 | /// when the maximum value is greater than 3 may generate a #GP exception.\r | |
| 1476 | /// Setting this bit may cause unexpected behavior in software that\r | |
| 1477 | /// depends on the availability of CPUID leaves greater than 3. Introduced\r | |
| 1478 | /// at Display Family / Display Model 0F_03H.\r | |
| 1479 | ///\r | |
| 1480 | UINT32 LimitCpuidMaxval:1;\r | |
| 1481 | ///\r | |
| 1482 | /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r | |
| 1483 | /// disabled. xTPR messages are optional messages that allow the processor\r | |
| 1484 | /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r | |
| 1485 | ///\r | |
| 1486 | UINT32 xTPR_Message_Disable:1;\r | |
| 1487 | UINT32 Reserved7:8;\r | |
| 1488 | UINT32 Reserved8:2;\r | |
| 1489 | ///\r | |
| 1490 | /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r | |
| 1491 | /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r | |
| 1492 | /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r | |
| 1493 | /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r | |
| 1494 | /// paging and take advantage of data only pages. BIOS must not alter the\r | |
| 1495 | /// contents of this bit location, if XD bit is not supported. Writing\r | |
| 1496 | /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r | |
| 1497 | /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r | |
| 1498 | ///\r | |
| 1499 | UINT32 XD:1;\r | |
| 1500 | UINT32 Reserved9:29;\r | |
| 1501 | } Bits;\r | |
| 1502 | ///\r | |
| 1503 | /// All bit fields as a 64-bit value\r | |
| 1504 | ///\r | |
| 1505 | UINT64 Uint64;\r | |
| 1506 | } MSR_IA32_MISC_ENABLE_REGISTER;\r | |
| 1507 | \r | |
| 1508 | \r | |
| 1509 | /**\r | |
| 1510 | Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r | |
| 1511 | \r | |
| 1512 | @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r | |
| 1513 | @param EAX Lower 32-bits of MSR value.\r | |
| 1514 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1515 | @param EDX Upper 32-bits of MSR value.\r | |
| 1516 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1517 | \r | |
| 1518 | <b>Example usage</b>\r | |
| 1519 | @code\r | |
| 1520 | MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r | |
| 1521 | \r | |
| 1522 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r | |
| 1523 | AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r | |
| 1524 | @endcode\r | |
| 7de98828 | 1525 | @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r |
| 04c980a6 MK |
1526 | **/\r |
| 1527 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r | |
| 1528 | \r | |
| 1529 | /**\r | |
| 1530 | MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r | |
| 1531 | **/\r | |
| 1532 | typedef union {\r | |
| 1533 | ///\r | |
| 1534 | /// Individual bit fields\r | |
| 1535 | ///\r | |
| 1536 | struct {\r | |
| 1537 | ///\r | |
| 1538 | /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r | |
| 1539 | /// performance. 15 indicates preference to maximize energy saving.\r | |
| 1540 | ///\r | |
| 1541 | UINT32 PowerPolicyPreference:4;\r | |
| 1542 | UINT32 Reserved1:28;\r | |
| 1543 | UINT32 Reserved2:32;\r | |
| 1544 | } Bits;\r | |
| 1545 | ///\r | |
| 1546 | /// All bit fields as a 32-bit value\r | |
| 1547 | ///\r | |
| 1548 | UINT32 Uint32;\r | |
| 1549 | ///\r | |
| 1550 | /// All bit fields as a 64-bit value\r | |
| 1551 | ///\r | |
| 1552 | UINT64 Uint64;\r | |
| 1553 | } MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r | |
| 1554 | \r | |
| 1555 | \r | |
| 1556 | /**\r | |
| 1557 | Package Thermal Status Information (RO) Contains status information about\r | |
| 1558 | the package's thermal sensor. See Section 14.8, "Package Level Thermal\r | |
| 1559 | Management.". If CPUID.06H: EAX[6] = 1.\r | |
| 1560 | \r | |
| 1561 | @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r | |
| 1562 | @param EAX Lower 32-bits of MSR value.\r | |
| 1563 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1564 | @param EDX Upper 32-bits of MSR value.\r | |
| 1565 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1566 | \r | |
| 1567 | <b>Example usage</b>\r | |
| 1568 | @code\r | |
| 1569 | MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r | |
| 1570 | \r | |
| 1571 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r | |
| 1572 | @endcode\r | |
| 7de98828 | 1573 | @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1574 | **/\r |
| 1575 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r | |
| 1576 | \r | |
| 1577 | /**\r | |
| 1578 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r | |
| 1579 | **/\r | |
| 1580 | typedef union {\r | |
| 1581 | ///\r | |
| 1582 | /// Individual bit fields\r | |
| 1583 | ///\r | |
| 1584 | struct {\r | |
| 1585 | ///\r | |
| 1586 | /// [Bit 0] Pkg Thermal Status (RO):.\r | |
| 1587 | ///\r | |
| 1588 | UINT32 ThermalStatus:1;\r | |
| 1589 | ///\r | |
| 1590 | /// [Bit 1] Pkg Thermal Status Log (R/W):.\r | |
| 1591 | ///\r | |
| 1592 | UINT32 ThermalStatusLog:1;\r | |
| 1593 | ///\r | |
| 1594 | /// [Bit 2] Pkg PROCHOT # event (RO).\r | |
| 1595 | ///\r | |
| 1596 | UINT32 PROCHOT_Event:1;\r | |
| 1597 | ///\r | |
| 1598 | /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r | |
| 1599 | ///\r | |
| 1600 | UINT32 PROCHOT_Log:1;\r | |
| 1601 | ///\r | |
| 1602 | /// [Bit 4] Pkg Critical Temperature Status (RO).\r | |
| 1603 | ///\r | |
| 1604 | UINT32 CriticalTempStatus:1;\r | |
| 1605 | ///\r | |
| 1606 | /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r | |
| 1607 | ///\r | |
| 1608 | UINT32 CriticalTempStatusLog:1;\r | |
| 1609 | ///\r | |
| 1610 | /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r | |
| 1611 | ///\r | |
| 1612 | UINT32 ThermalThreshold1Status:1;\r | |
| 1613 | ///\r | |
| 1614 | /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1615 | ///\r | |
| 1616 | UINT32 ThermalThreshold1Log:1;\r | |
| 1617 | ///\r | |
| 1618 | /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r | |
| 1619 | ///\r | |
| 1620 | UINT32 ThermalThreshold2Status:1;\r | |
| 1621 | ///\r | |
| 1622 | /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1623 | ///\r | |
| 1624 | UINT32 ThermalThreshold2Log:1;\r | |
| 1625 | ///\r | |
| 1626 | /// [Bit 10] Pkg Power Limitation Status (RO).\r | |
| 1627 | ///\r | |
| 1628 | UINT32 PowerLimitStatus:1;\r | |
| 1629 | ///\r | |
| 1630 | /// [Bit 11] Pkg Power Limitation log (R/WC0).\r | |
| 1631 | ///\r | |
| 1632 | UINT32 PowerLimitLog:1;\r | |
| 1633 | UINT32 Reserved1:4;\r | |
| 1634 | ///\r | |
| 1635 | /// [Bits 22:16] Pkg Digital Readout (RO).\r | |
| 1636 | ///\r | |
| 1637 | UINT32 DigitalReadout:7;\r | |
| 1638 | UINT32 Reserved2:9;\r | |
| 1639 | UINT32 Reserved3:32;\r | |
| 1640 | } Bits;\r | |
| 1641 | ///\r | |
| 1642 | /// All bit fields as a 32-bit value\r | |
| 1643 | ///\r | |
| 1644 | UINT32 Uint32;\r | |
| 1645 | ///\r | |
| 1646 | /// All bit fields as a 64-bit value\r | |
| 1647 | ///\r | |
| 1648 | UINT64 Uint64;\r | |
| 1649 | } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r | |
| 1650 | \r | |
| 1651 | \r | |
| 1652 | /**\r | |
| 1653 | Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r | |
| 1654 | an interrupt on temperature transitions detected with the package's thermal\r | |
| 1655 | sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r | |
| 1656 | EAX[6] = 1.\r | |
| 1657 | \r | |
| 1658 | @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r | |
| 1659 | @param EAX Lower 32-bits of MSR value.\r | |
| 1660 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1661 | @param EDX Upper 32-bits of MSR value.\r | |
| 1662 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1663 | \r | |
| 1664 | <b>Example usage</b>\r | |
| 1665 | @code\r | |
| 1666 | MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1667 | \r | |
| 1668 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r | |
| 1669 | AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1670 | @endcode\r | |
| 7de98828 | 1671 | @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1672 | **/\r |
| 1673 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r | |
| 1674 | \r | |
| 1675 | /**\r | |
| 1676 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r | |
| 1677 | **/\r | |
| 1678 | typedef union {\r | |
| 1679 | ///\r | |
| 1680 | /// Individual bit fields\r | |
| 1681 | ///\r | |
| 1682 | struct {\r | |
| 1683 | ///\r | |
| 1684 | /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r | |
| 1685 | ///\r | |
| 1686 | UINT32 HighTempEnable:1;\r | |
| 1687 | ///\r | |
| 1688 | /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r | |
| 1689 | ///\r | |
| 1690 | UINT32 LowTempEnable:1;\r | |
| 1691 | ///\r | |
| 1692 | /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r | |
| 1693 | ///\r | |
| 1694 | UINT32 PROCHOT_Enable:1;\r | |
| 1695 | UINT32 Reserved1:1;\r | |
| 1696 | ///\r | |
| 1697 | /// [Bit 4] Pkg Overheat Interrupt Enable.\r | |
| 1698 | ///\r | |
| 1699 | UINT32 OverheatEnable:1;\r | |
| 1700 | UINT32 Reserved2:3;\r | |
| 1701 | ///\r | |
| 1702 | /// [Bits 14:8] Pkg Threshold #1 Value.\r | |
| 1703 | ///\r | |
| 1704 | UINT32 Threshold1:7;\r | |
| 1705 | ///\r | |
| 1706 | /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r | |
| 1707 | ///\r | |
| 1708 | UINT32 Threshold1Enable:1;\r | |
| 1709 | ///\r | |
| 1710 | /// [Bits 22:16] Pkg Threshold #2 Value.\r | |
| 1711 | ///\r | |
| 1712 | UINT32 Threshold2:7;\r | |
| 1713 | ///\r | |
| 1714 | /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r | |
| 1715 | ///\r | |
| 1716 | UINT32 Threshold2Enable:1;\r | |
| 1717 | ///\r | |
| 1718 | /// [Bit 24] Pkg Power Limit Notification Enable.\r | |
| 1719 | ///\r | |
| 1720 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1721 | UINT32 Reserved3:7;\r | |
| 1722 | UINT32 Reserved4:32;\r | |
| 1723 | } Bits;\r | |
| 1724 | ///\r | |
| 1725 | /// All bit fields as a 32-bit value\r | |
| 1726 | ///\r | |
| 1727 | UINT32 Uint32;\r | |
| 1728 | ///\r | |
| 1729 | /// All bit fields as a 64-bit value\r | |
| 1730 | ///\r | |
| 1731 | UINT64 Uint64;\r | |
| 1732 | } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r | |
| 1733 | \r | |
| 1734 | \r | |
| 1735 | /**\r | |
| 1736 | Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r | |
| 1737 | Model 06_0EH.\r | |
| 1738 | \r | |
| 1739 | @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r | |
| 1740 | @param EAX Lower 32-bits of MSR value.\r | |
| 1741 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1742 | @param EDX Upper 32-bits of MSR value.\r | |
| 1743 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1744 | \r | |
| 1745 | <b>Example usage</b>\r | |
| 1746 | @code\r | |
| 1747 | MSR_IA32_DEBUGCTL_REGISTER Msr;\r | |
| 1748 | \r | |
| 1749 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r | |
| 1750 | AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r | |
| 1751 | @endcode\r | |
| 7de98828 | 1752 | @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r |
| 04c980a6 MK |
1753 | **/\r |
| 1754 | #define MSR_IA32_DEBUGCTL 0x000001D9\r | |
| 1755 | \r | |
| 1756 | /**\r | |
| 1757 | MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r | |
| 1758 | **/\r | |
| 1759 | typedef union {\r | |
| 1760 | ///\r | |
| 1761 | /// Individual bit fields\r | |
| 1762 | ///\r | |
| 1763 | struct {\r | |
| 1764 | ///\r | |
| 1765 | /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r | |
| 1766 | /// running trace of the most recent branches taken by the processor in\r | |
| 1767 | /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r | |
| 1768 | ///\r | |
| 1769 | UINT32 LBR:1;\r | |
| 1770 | ///\r | |
| 1771 | /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r | |
| 1772 | /// EFLAGS.TF as single-step on branches instead of single-step on\r | |
| 1773 | /// instructions. Introduced at Display Family / Display Model 06_01H.\r | |
| 1774 | ///\r | |
| 1775 | UINT32 BTF:1;\r | |
| 1776 | UINT32 Reserved1:4;\r | |
| 1777 | ///\r | |
| 1778 | /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r | |
| 1779 | /// sent. Introduced at Display Family / Display Model 06_0EH.\r | |
| 1780 | ///\r | |
| 1781 | UINT32 TR:1;\r | |
| 1782 | ///\r | |
| 1783 | /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r | |
| 1784 | /// be logged in a BTS buffer. Introduced at Display Family / Display\r | |
| 1785 | /// Model 06_0EH.\r | |
| 1786 | ///\r | |
| 1787 | UINT32 BTS:1;\r | |
| 1788 | ///\r | |
| 1789 | /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r | |
| 1790 | /// fashion. When this bit is set, an interrupt is generated by the BTS\r | |
| 1791 | /// facility when the BTS buffer is full. Introduced at Display Family /\r | |
| 1792 | /// Display Model 06_0EH.\r | |
| 1793 | ///\r | |
| 1794 | UINT32 BTINT:1;\r | |
| 1795 | ///\r | |
| 1796 | /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r | |
| 1797 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1798 | ///\r | |
| 1799 | UINT32 BTS_OFF_OS:1;\r | |
| 1800 | ///\r | |
| 1801 | /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r | |
| 1802 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1803 | ///\r | |
| 1804 | UINT32 BTS_OFF_USR:1;\r | |
| 1805 | ///\r | |
| 1806 | /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r | |
| 1807 | /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1808 | ///\r | |
| 1809 | UINT32 FREEZE_LBRS_ON_PMI:1;\r | |
| 1810 | ///\r | |
| 1811 | /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r | |
| 1812 | /// global counter control MSR are frozen (address 38FH) on a PMI request.\r | |
| 1813 | /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1814 | ///\r | |
| 1815 | UINT32 FREEZE_PERFMON_ON_PMI:1;\r | |
| 1816 | ///\r | |
| 1817 | /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r | |
| 1818 | /// receive and generate PMI on behalf of the uncore. Introduced at\r | |
| 1819 | /// Display Family / Display Model 06_1AH.\r | |
| 1820 | ///\r | |
| 1821 | UINT32 ENABLE_UNCORE_PMI:1;\r | |
| 1822 | ///\r | |
| 1823 | /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r | |
| 1824 | /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r | |
| 1825 | ///\r | |
| 1826 | UINT32 FREEZE_WHILE_SMM:1;\r | |
| 1827 | ///\r | |
| 1828 | /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r | |
| 1829 | /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r | |
| 1830 | ///\r | |
| 1831 | UINT32 RTM_DEBUG:1;\r | |
| 1832 | UINT32 Reserved2:16;\r | |
| 1833 | UINT32 Reserved3:32;\r | |
| 1834 | } Bits;\r | |
| 1835 | ///\r | |
| 1836 | /// All bit fields as a 32-bit value\r | |
| 1837 | ///\r | |
| 1838 | UINT32 Uint32;\r | |
| 1839 | ///\r | |
| 1840 | /// All bit fields as a 64-bit value\r | |
| 1841 | ///\r | |
| 1842 | UINT64 Uint64;\r | |
| 1843 | } MSR_IA32_DEBUGCTL_REGISTER;\r | |
| 1844 | \r | |
| 1845 | \r | |
| 1846 | /**\r | |
| 1847 | SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r | |
| 1848 | If IA32_MTRRCAP.SMRR[11] = 1.\r | |
| 1849 | \r | |
| 1850 | @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r | |
| 1851 | @param EAX Lower 32-bits of MSR value.\r | |
| 1852 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1853 | @param EDX Upper 32-bits of MSR value.\r | |
| 1854 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1855 | \r | |
| 1856 | <b>Example usage</b>\r | |
| 1857 | @code\r | |
| 1858 | MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r | |
| 1859 | \r | |
| 1860 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r | |
| 1861 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r | |
| 1862 | @endcode\r | |
| 7de98828 | 1863 | @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r |
| 04c980a6 MK |
1864 | **/\r |
| 1865 | #define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r | |
| 1866 | \r | |
| 1867 | /**\r | |
| 1868 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r | |
| 1869 | **/\r | |
| 1870 | typedef union {\r | |
| 1871 | ///\r | |
| 1872 | /// Individual bit fields\r | |
| 1873 | ///\r | |
| 1874 | struct {\r | |
| 1875 | ///\r | |
| 1876 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 1877 | ///\r | |
| 1878 | UINT32 Type:8;\r | |
| 1879 | UINT32 Reserved1:4;\r | |
| 1880 | ///\r | |
| 1881 | /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r | |
| 1882 | ///\r | |
| 1883 | UINT32 PhysBase:20;\r | |
| 1884 | UINT32 Reserved2:32;\r | |
| 1885 | } Bits;\r | |
| 1886 | ///\r | |
| 1887 | /// All bit fields as a 32-bit value\r | |
| 1888 | ///\r | |
| 1889 | UINT32 Uint32;\r | |
| 1890 | ///\r | |
| 1891 | /// All bit fields as a 64-bit value\r | |
| 1892 | ///\r | |
| 1893 | UINT64 Uint64;\r | |
| 1894 | } MSR_IA32_SMRR_PHYSBASE_REGISTER;\r | |
| 1895 | \r | |
| 1896 | \r | |
| 1897 | /**\r | |
| 1898 | SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If\r | |
| 1899 | IA32_MTRRCAP[SMRR] = 1.\r | |
| 1900 | \r | |
| 1901 | @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r | |
| 1902 | @param EAX Lower 32-bits of MSR value.\r | |
| 1903 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1904 | @param EDX Upper 32-bits of MSR value.\r | |
| 1905 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1906 | \r | |
| 1907 | <b>Example usage</b>\r | |
| 1908 | @code\r | |
| 1909 | MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r | |
| 1910 | \r | |
| 1911 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r | |
| 1912 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r | |
| 1913 | @endcode\r | |
| 7de98828 | 1914 | @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r |
| 04c980a6 MK |
1915 | **/\r |
| 1916 | #define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r | |
| 1917 | \r | |
| 1918 | /**\r | |
| 1919 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r | |
| 1920 | **/\r | |
| 1921 | typedef union {\r | |
| 1922 | ///\r | |
| 1923 | /// Individual bit fields\r | |
| 1924 | ///\r | |
| 1925 | struct {\r | |
| 1926 | UINT32 Reserved1:11;\r | |
| 1927 | ///\r | |
| 1928 | /// [Bit 11] Valid Enable range mask.\r | |
| 1929 | ///\r | |
| 1930 | UINT32 Valid:1;\r | |
| 1931 | ///\r | |
| 1932 | /// [Bits 31:12] PhysMask SMRR address range mask.\r | |
| 1933 | ///\r | |
| 1934 | UINT32 PhysMask:20;\r | |
| 1935 | UINT32 Reserved2:32;\r | |
| 1936 | } Bits;\r | |
| 1937 | ///\r | |
| 1938 | /// All bit fields as a 32-bit value\r | |
| 1939 | ///\r | |
| 1940 | UINT32 Uint32;\r | |
| 1941 | ///\r | |
| 1942 | /// All bit fields as a 64-bit value\r | |
| 1943 | ///\r | |
| 1944 | UINT64 Uint64;\r | |
| 1945 | } MSR_IA32_SMRR_PHYSMASK_REGISTER;\r | |
| 1946 | \r | |
| 1947 | \r | |
| 1948 | /**\r | |
| 1949 | DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r | |
| 1950 | \r | |
| 1951 | @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r | |
| 1952 | @param EAX Lower 32-bits of MSR value.\r | |
| 1953 | @param EDX Upper 32-bits of MSR value.\r | |
| 1954 | \r | |
| 1955 | <b>Example usage</b>\r | |
| 1956 | @code\r | |
| 1957 | UINT64 Msr;\r | |
| 1958 | \r | |
| 1959 | Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r | |
| 1960 | @endcode\r | |
| 7de98828 | 1961 | @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r |
| 04c980a6 MK |
1962 | **/\r |
| 1963 | #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r | |
| 1964 | \r | |
| 1965 | \r | |
| 1966 | /**\r | |
| 1967 | If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r | |
| 1968 | \r | |
| 1969 | @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r | |
| 1970 | @param EAX Lower 32-bits of MSR value.\r | |
| 1971 | @param EDX Upper 32-bits of MSR value.\r | |
| 1972 | \r | |
| 1973 | <b>Example usage</b>\r | |
| 1974 | @code\r | |
| 1975 | UINT64 Msr;\r | |
| 1976 | \r | |
| 1977 | Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r | |
| 1978 | AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r | |
| 1979 | @endcode\r | |
| 7de98828 | 1980 | @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r |
| 04c980a6 MK |
1981 | **/\r |
| 1982 | #define MSR_IA32_CPU_DCA_CAP 0x000001F9\r | |
| 1983 | \r | |
| 1984 | \r | |
| 1985 | /**\r | |
| 1986 | DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r | |
| 1987 | \r | |
| 1988 | @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r | |
| 1989 | @param EAX Lower 32-bits of MSR value.\r | |
| 1990 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 1991 | @param EDX Upper 32-bits of MSR value.\r | |
| 1992 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 1993 | \r | |
| 1994 | <b>Example usage</b>\r | |
| 1995 | @code\r | |
| 1996 | MSR_IA32_DCA_0_CAP_REGISTER Msr;\r | |
| 1997 | \r | |
| 1998 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r | |
| 1999 | AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r | |
| 2000 | @endcode\r | |
| 7de98828 | 2001 | @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r |
| 04c980a6 MK |
2002 | **/\r |
| 2003 | #define MSR_IA32_DCA_0_CAP 0x000001FA\r | |
| 2004 | \r | |
| 2005 | /**\r | |
| 2006 | MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r | |
| 2007 | **/\r | |
| 2008 | typedef union {\r | |
| 2009 | ///\r | |
| 2010 | /// Individual bit fields\r | |
| 2011 | ///\r | |
| 2012 | struct {\r | |
| 2013 | ///\r | |
| 2014 | /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r | |
| 2015 | /// defeatures are set.\r | |
| 2016 | ///\r | |
| 2017 | UINT32 DCA_ACTIVE:1;\r | |
| 2018 | ///\r | |
| 2019 | /// [Bits 2:1] TRANSACTION.\r | |
| 2020 | ///\r | |
| 2021 | UINT32 TRANSACTION:2;\r | |
| 2022 | ///\r | |
| 2023 | /// [Bits 6:3] DCA_TYPE.\r | |
| 2024 | ///\r | |
| 2025 | UINT32 DCA_TYPE:4;\r | |
| 2026 | ///\r | |
| 2027 | /// [Bits 10:7] DCA_QUEUE_SIZE.\r | |
| 2028 | ///\r | |
| 2029 | UINT32 DCA_QUEUE_SIZE:4;\r | |
| 2030 | UINT32 Reserved1:2;\r | |
| 2031 | ///\r | |
| 2032 | /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r | |
| 2033 | /// side-effect.\r | |
| 2034 | ///\r | |
| 2035 | UINT32 DCA_DELAY:4;\r | |
| 2036 | UINT32 Reserved2:7;\r | |
| 2037 | ///\r | |
| 2038 | /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r | |
| 2039 | ///\r | |
| 2040 | UINT32 SW_BLOCK:1;\r | |
| 2041 | UINT32 Reserved3:1;\r | |
| 2042 | ///\r | |
| 2043 | /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r | |
| 2044 | ///\r | |
| 2045 | UINT32 HW_BLOCK:1;\r | |
| 2046 | UINT32 Reserved4:5;\r | |
| 2047 | UINT32 Reserved5:32;\r | |
| 2048 | } Bits;\r | |
| 2049 | ///\r | |
| 2050 | /// All bit fields as a 32-bit value\r | |
| 2051 | ///\r | |
| 2052 | UINT32 Uint32;\r | |
| 2053 | ///\r | |
| 2054 | /// All bit fields as a 64-bit value\r | |
| 2055 | ///\r | |
| 2056 | UINT64 Uint64;\r | |
| 2057 | } MSR_IA32_DCA_0_CAP_REGISTER;\r | |
| 2058 | \r | |
| 2059 | \r | |
| 2060 | /**\r | |
| 2061 | MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2062 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2063 | \r | |
| 2064 | @param ECX MSR_IA32_MTRR_PHYSBASEn\r | |
| 2065 | @param EAX Lower 32-bits of MSR value.\r | |
| 2066 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2067 | @param EDX Upper 32-bits of MSR value.\r | |
| 2068 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2069 | \r | |
| 2070 | <b>Example usage</b>\r | |
| 2071 | @code\r | |
| 2072 | MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r | |
| 2073 | \r | |
| 2074 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r | |
| 2075 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r | |
| 2076 | @endcode\r | |
| 7de98828 JF |
2077 | @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r |
| 2078 | MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r | |
| 2079 | MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r | |
| 2080 | MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r | |
| 2081 | MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r | |
| 2082 | MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r | |
| 2083 | MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r | |
| 2084 | MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r | |
| 2085 | MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r | |
| 2086 | MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r | |
| 04c980a6 MK |
2087 | @{\r |
| 2088 | **/\r | |
| 2089 | #define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r | |
| 2090 | #define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r | |
| 2091 | #define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r | |
| 2092 | #define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r | |
| 2093 | #define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r | |
| 2094 | #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r | |
| 2095 | #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r | |
| 2096 | #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r | |
| 2097 | #define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r | |
| 2098 | #define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r | |
| 2099 | /// @}\r | |
| 2100 | \r | |
| 2101 | /**\r | |
| 2102 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r | |
| 2103 | #MSR_IA32_MTRR_PHYSBASE9\r | |
| 2104 | **/\r | |
| 2105 | typedef union {\r | |
| 2106 | ///\r | |
| 2107 | /// Individual bit fields\r | |
| 2108 | ///\r | |
| 2109 | struct {\r | |
| 2110 | ///\r | |
| 2111 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 2112 | ///\r | |
| 2113 | UINT32 Type:8;\r | |
| 2114 | UINT32 Reserved1:4;\r | |
| 2115 | ///\r | |
| 2116 | /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r | |
| 2117 | ///\r | |
| 2118 | UINT32 PhysBase:20;\r | |
| 2119 | ///\r | |
| 2120 | /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r | |
| 2121 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2122 | /// maximum physical address range supported by the processor. It is\r | |
| 2123 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2124 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2125 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2126 | ///\r | |
| 2127 | UINT32 PhysBaseHi:32;\r | |
| 2128 | } Bits;\r | |
| 2129 | ///\r | |
| 2130 | /// All bit fields as a 64-bit value\r | |
| 2131 | ///\r | |
| 2132 | UINT64 Uint64;\r | |
| 2133 | } MSR_IA32_MTRR_PHYSBASE_REGISTER;\r | |
| 2134 | \r | |
| 2135 | \r | |
| 2136 | /**\r | |
| 2137 | MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2138 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2139 | \r | |
| 2140 | @param ECX MSR_IA32_MTRR_PHYSMASKn\r | |
| 2141 | @param EAX Lower 32-bits of MSR value.\r | |
| 2142 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2143 | @param EDX Upper 32-bits of MSR value.\r | |
| 2144 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2145 | \r | |
| 2146 | <b>Example usage</b>\r | |
| 2147 | @code\r | |
| 2148 | MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r | |
| 2149 | \r | |
| 2150 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r | |
| 2151 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r | |
| 2152 | @endcode\r | |
| 7de98828 JF |
2153 | @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r |
| 2154 | MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r | |
| 2155 | MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r | |
| 2156 | MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r | |
| 2157 | MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r | |
| 2158 | MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r | |
| 2159 | MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r | |
| 2160 | MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r | |
| 2161 | MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r | |
| 2162 | MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r | |
| 04c980a6 MK |
2163 | @{\r |
| 2164 | **/\r | |
| 2165 | #define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r | |
| 2166 | #define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r | |
| 2167 | #define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r | |
| 2168 | #define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r | |
| 2169 | #define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r | |
| 2170 | #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r | |
| 2171 | #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r | |
| 2172 | #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r | |
| 2173 | #define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r | |
| 2174 | #define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r | |
| 2175 | /// @}\r | |
| 2176 | \r | |
| 2177 | /**\r | |
| 2178 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r | |
| 2179 | #MSR_IA32_MTRR_PHYSMASK9\r | |
| 2180 | **/\r | |
| 2181 | typedef union {\r | |
| 2182 | ///\r | |
| 2183 | /// Individual bit fields\r | |
| 2184 | ///\r | |
| 2185 | struct {\r | |
| 2186 | UINT32 Reserved1:11;\r | |
| 2187 | ///\r | |
| 2188 | /// [Bit 11] Valid Enable range mask.\r | |
| 2189 | ///\r | |
| 490b048b | 2190 | UINT32 V:1;\r |
| 04c980a6 MK |
2191 | ///\r |
| 2192 | /// [Bits 31:12] PhysMask. MTRR address range mask.\r | |
| 2193 | ///\r | |
| 2194 | UINT32 PhysMask:20;\r | |
| 2195 | ///\r | |
| 2196 | /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r | |
| 2197 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2198 | /// maximum physical address range supported by the processor. It is\r | |
| 2199 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2200 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2201 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2202 | ///\r | |
| 2203 | UINT32 PhysMaskHi:32;\r | |
| 2204 | } Bits;\r | |
| 2205 | ///\r | |
| 2206 | /// All bit fields as a 64-bit value\r | |
| 2207 | ///\r | |
| 2208 | UINT64 Uint64;\r | |
| 2209 | } MSR_IA32_MTRR_PHYSMASK_REGISTER;\r | |
| 2210 | \r | |
| 2211 | \r | |
| 2212 | /**\r | |
| 2213 | MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2214 | \r | |
| 2215 | @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r | |
| 2216 | @param EAX Lower 32-bits of MSR value.\r | |
| 2217 | @param EDX Upper 32-bits of MSR value.\r | |
| 2218 | \r | |
| 2219 | <b>Example usage</b>\r | |
| 2220 | @code\r | |
| 2221 | UINT64 Msr;\r | |
| 2222 | \r | |
| 2223 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r | |
| 2224 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r | |
| 2225 | @endcode\r | |
| 7de98828 | 2226 | @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r |
| 04c980a6 MK |
2227 | **/\r |
| 2228 | #define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r | |
| 2229 | \r | |
| 2230 | \r | |
| 2231 | /**\r | |
| 2232 | MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2233 | \r | |
| 2234 | @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r | |
| 2235 | @param EAX Lower 32-bits of MSR value.\r | |
| 2236 | @param EDX Upper 32-bits of MSR value.\r | |
| 2237 | \r | |
| 2238 | <b>Example usage</b>\r | |
| 2239 | @code\r | |
| 2240 | UINT64 Msr;\r | |
| 2241 | \r | |
| 2242 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r | |
| 2243 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r | |
| 2244 | @endcode\r | |
| 7de98828 | 2245 | @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r |
| 04c980a6 MK |
2246 | **/\r |
| 2247 | #define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r | |
| 2248 | \r | |
| 2249 | \r | |
| 2250 | /**\r | |
| 2251 | MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2252 | \r | |
| 2253 | @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r | |
| 2254 | @param EAX Lower 32-bits of MSR value.\r | |
| 2255 | @param EDX Upper 32-bits of MSR value.\r | |
| 2256 | \r | |
| 2257 | <b>Example usage</b>\r | |
| 2258 | @code\r | |
| 2259 | UINT64 Msr;\r | |
| 2260 | \r | |
| 2261 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r | |
| 2262 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r | |
| 2263 | @endcode\r | |
| 7de98828 | 2264 | @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r |
| 04c980a6 MK |
2265 | **/\r |
| 2266 | #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r | |
| 2267 | \r | |
| 2268 | \r | |
| 2269 | /**\r | |
| 2270 | See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2271 | \r | |
| 2272 | @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r | |
| 2273 | @param EAX Lower 32-bits of MSR value.\r | |
| 2274 | @param EDX Upper 32-bits of MSR value.\r | |
| 2275 | \r | |
| 2276 | <b>Example usage</b>\r | |
| 2277 | @code\r | |
| 2278 | UINT64 Msr;\r | |
| 2279 | \r | |
| 2280 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r | |
| 2281 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r | |
| 2282 | @endcode\r | |
| 7de98828 | 2283 | @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r |
| 04c980a6 MK |
2284 | **/\r |
| 2285 | #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r | |
| 2286 | \r | |
| 2287 | \r | |
| 2288 | /**\r | |
| 2289 | MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2290 | \r | |
| 2291 | @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r | |
| 2292 | @param EAX Lower 32-bits of MSR value.\r | |
| 2293 | @param EDX Upper 32-bits of MSR value.\r | |
| 2294 | \r | |
| 2295 | <b>Example usage</b>\r | |
| 2296 | @code\r | |
| 2297 | UINT64 Msr;\r | |
| 2298 | \r | |
| 2299 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r | |
| 2300 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r | |
| 2301 | @endcode\r | |
| 7de98828 | 2302 | @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r |
| 04c980a6 MK |
2303 | **/\r |
| 2304 | #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r | |
| 2305 | \r | |
| 2306 | \r | |
| 2307 | /**\r | |
| 2308 | MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2309 | \r | |
| 2310 | @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r | |
| 2311 | @param EAX Lower 32-bits of MSR value.\r | |
| 2312 | @param EDX Upper 32-bits of MSR value.\r | |
| 2313 | \r | |
| 2314 | <b>Example usage</b>\r | |
| 2315 | @code\r | |
| 2316 | UINT64 Msr;\r | |
| 2317 | \r | |
| 2318 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r | |
| 2319 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r | |
| 2320 | @endcode\r | |
| 7de98828 | 2321 | @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r |
| 04c980a6 MK |
2322 | **/\r |
| 2323 | #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r | |
| 2324 | \r | |
| 2325 | \r | |
| 2326 | /**\r | |
| 2327 | MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2328 | \r | |
| 2329 | @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r | |
| 2330 | @param EAX Lower 32-bits of MSR value.\r | |
| 2331 | @param EDX Upper 32-bits of MSR value.\r | |
| 2332 | \r | |
| 2333 | <b>Example usage</b>\r | |
| 2334 | @code\r | |
| 2335 | UINT64 Msr;\r | |
| 2336 | \r | |
| 2337 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r | |
| 2338 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r | |
| 2339 | @endcode\r | |
| 7de98828 | 2340 | @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r |
| 04c980a6 MK |
2341 | **/\r |
| 2342 | #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r | |
| 2343 | \r | |
| 2344 | \r | |
| 2345 | /**\r | |
| 2346 | MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2347 | \r | |
| 2348 | @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r | |
| 2349 | @param EAX Lower 32-bits of MSR value.\r | |
| 2350 | @param EDX Upper 32-bits of MSR value.\r | |
| 2351 | \r | |
| 2352 | <b>Example usage</b>\r | |
| 2353 | @code\r | |
| 2354 | UINT64 Msr;\r | |
| 2355 | \r | |
| 2356 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r | |
| 2357 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r | |
| 2358 | @endcode\r | |
| 7de98828 | 2359 | @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r |
| 04c980a6 MK |
2360 | **/\r |
| 2361 | #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r | |
| 2362 | \r | |
| 2363 | \r | |
| 2364 | /**\r | |
| 2365 | MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2366 | \r | |
| 2367 | @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r | |
| 2368 | @param EAX Lower 32-bits of MSR value.\r | |
| 2369 | @param EDX Upper 32-bits of MSR value.\r | |
| 2370 | \r | |
| 2371 | <b>Example usage</b>\r | |
| 2372 | @code\r | |
| 2373 | UINT64 Msr;\r | |
| 2374 | \r | |
| 2375 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r | |
| 2376 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r | |
| 2377 | @endcode\r | |
| 7de98828 | 2378 | @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r |
| 04c980a6 MK |
2379 | **/\r |
| 2380 | #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r | |
| 2381 | \r | |
| 2382 | \r | |
| 2383 | /**\r | |
| 2384 | MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2385 | \r | |
| 2386 | @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r | |
| 2387 | @param EAX Lower 32-bits of MSR value.\r | |
| 2388 | @param EDX Upper 32-bits of MSR value.\r | |
| 2389 | \r | |
| 2390 | <b>Example usage</b>\r | |
| 2391 | @code\r | |
| 2392 | UINT64 Msr;\r | |
| 2393 | \r | |
| 2394 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r | |
| 2395 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r | |
| 2396 | @endcode\r | |
| 7de98828 | 2397 | @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r |
| 04c980a6 MK |
2398 | **/\r |
| 2399 | #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r | |
| 2400 | \r | |
| 2401 | \r | |
| 2402 | /**\r | |
| 2403 | MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2404 | \r | |
| 2405 | @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r | |
| 2406 | @param EAX Lower 32-bits of MSR value.\r | |
| 2407 | @param EDX Upper 32-bits of MSR value.\r | |
| 2408 | \r | |
| 2409 | <b>Example usage</b>\r | |
| 2410 | @code\r | |
| 2411 | UINT64 Msr;\r | |
| 2412 | \r | |
| 2413 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r | |
| 2414 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r | |
| 2415 | @endcode\r | |
| 7de98828 | 2416 | @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r |
| 04c980a6 MK |
2417 | **/\r |
| 2418 | #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r | |
| 2419 | \r | |
| 2420 | \r | |
| 2421 | /**\r | |
| 2422 | IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r | |
| 2423 | \r | |
| 2424 | @param ECX MSR_IA32_PAT (0x00000277)\r | |
| 2425 | @param EAX Lower 32-bits of MSR value.\r | |
| 2426 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2427 | @param EDX Upper 32-bits of MSR value.\r | |
| 2428 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2429 | \r | |
| 2430 | <b>Example usage</b>\r | |
| 2431 | @code\r | |
| 2432 | MSR_IA32_PAT_REGISTER Msr;\r | |
| 2433 | \r | |
| 2434 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r | |
| 2435 | AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r | |
| 2436 | @endcode\r | |
| 7de98828 | 2437 | @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r |
| 04c980a6 MK |
2438 | **/\r |
| 2439 | #define MSR_IA32_PAT 0x00000277\r | |
| 2440 | \r | |
| 2441 | /**\r | |
| 2442 | MSR information returned for MSR index #MSR_IA32_PAT\r | |
| 2443 | **/\r | |
| 2444 | typedef union {\r | |
| 2445 | ///\r | |
| 2446 | /// Individual bit fields\r | |
| 2447 | ///\r | |
| 2448 | struct {\r | |
| 2449 | ///\r | |
| 2450 | /// [Bits 2:0] PA0.\r | |
| 2451 | ///\r | |
| 2452 | UINT32 PA0:3;\r | |
| 2453 | UINT32 Reserved1:5;\r | |
| 2454 | ///\r | |
| 2455 | /// [Bits 10:8] PA1.\r | |
| 2456 | ///\r | |
| 2457 | UINT32 PA1:3;\r | |
| 2458 | UINT32 Reserved2:5;\r | |
| 2459 | ///\r | |
| 2460 | /// [Bits 18:16] PA2.\r | |
| 2461 | ///\r | |
| 2462 | UINT32 PA2:3;\r | |
| 2463 | UINT32 Reserved3:5;\r | |
| 2464 | ///\r | |
| 2465 | /// [Bits 26:24] PA3.\r | |
| 2466 | ///\r | |
| 2467 | UINT32 PA3:3;\r | |
| 2468 | UINT32 Reserved4:5;\r | |
| 2469 | ///\r | |
| 2470 | /// [Bits 34:32] PA4.\r | |
| 2471 | ///\r | |
| 2472 | UINT32 PA4:3;\r | |
| 2473 | UINT32 Reserved5:5;\r | |
| 2474 | ///\r | |
| 2475 | /// [Bits 42:40] PA5.\r | |
| 2476 | ///\r | |
| 2477 | UINT32 PA5:3;\r | |
| 2478 | UINT32 Reserved6:5;\r | |
| 2479 | ///\r | |
| 2480 | /// [Bits 50:48] PA6.\r | |
| 2481 | ///\r | |
| 2482 | UINT32 PA6:3;\r | |
| 2483 | UINT32 Reserved7:5;\r | |
| 2484 | ///\r | |
| 2485 | /// [Bits 58:56] PA7.\r | |
| 2486 | ///\r | |
| 2487 | UINT32 PA7:3;\r | |
| 2488 | UINT32 Reserved8:5;\r | |
| 2489 | } Bits;\r | |
| 2490 | ///\r | |
| 2491 | /// All bit fields as a 64-bit value\r | |
| 2492 | ///\r | |
| 2493 | UINT64 Uint64;\r | |
| 2494 | } MSR_IA32_PAT_REGISTER;\r | |
| 2495 | \r | |
| 2496 | \r | |
| 2497 | /**\r | |
| 2498 | Provides the programming interface to use corrected MC error signaling\r | |
| 2499 | capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r | |
| 2500 | \r | |
| 2501 | @param ECX MSR_IA32_MCn_CTL2\r | |
| 2502 | @param EAX Lower 32-bits of MSR value.\r | |
| 2503 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2504 | @param EDX Upper 32-bits of MSR value.\r | |
| 2505 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2506 | \r | |
| 2507 | <b>Example usage</b>\r | |
| 2508 | @code\r | |
| 2509 | MSR_IA32_MC_CTL2_REGISTER Msr;\r | |
| 2510 | \r | |
| 2511 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r | |
| 2512 | AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r | |
| 2513 | @endcode\r | |
| 7de98828 JF |
2514 | @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r |
| 2515 | MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r | |
| 2516 | MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r | |
| 2517 | MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r | |
| 2518 | MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r | |
| 2519 | MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r | |
| 2520 | MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r | |
| 2521 | MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r | |
| 2522 | MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r | |
| 2523 | MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r | |
| 2524 | MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r | |
| 2525 | MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r | |
| 2526 | MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r | |
| 2527 | MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r | |
| 2528 | MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r | |
| 2529 | MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r | |
| 2530 | MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r | |
| 2531 | MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r | |
| 2532 | MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r | |
| 2533 | MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r | |
| 2534 | MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r | |
| 2535 | MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r | |
| 2536 | MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r | |
| 2537 | MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r | |
| 2538 | MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r | |
| 2539 | MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r | |
| 2540 | MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r | |
| 2541 | MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r | |
| 2542 | MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r | |
| 2543 | MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r | |
| 2544 | MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r | |
| 2545 | MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r | |
| 04c980a6 MK |
2546 | @{\r |
| 2547 | **/\r | |
| 2548 | #define MSR_IA32_MC0_CTL2 0x00000280\r | |
| 2549 | #define MSR_IA32_MC1_CTL2 0x00000281\r | |
| 2550 | #define MSR_IA32_MC2_CTL2 0x00000282\r | |
| 2551 | #define MSR_IA32_MC3_CTL2 0x00000283\r | |
| 2552 | #define MSR_IA32_MC4_CTL2 0x00000284\r | |
| 2553 | #define MSR_IA32_MC5_CTL2 0x00000285\r | |
| 2554 | #define MSR_IA32_MC6_CTL2 0x00000286\r | |
| 2555 | #define MSR_IA32_MC7_CTL2 0x00000287\r | |
| 2556 | #define MSR_IA32_MC8_CTL2 0x00000288\r | |
| 2557 | #define MSR_IA32_MC9_CTL2 0x00000289\r | |
| 2558 | #define MSR_IA32_MC10_CTL2 0x0000028A\r | |
| 2559 | #define MSR_IA32_MC11_CTL2 0x0000028B\r | |
| 2560 | #define MSR_IA32_MC12_CTL2 0x0000028C\r | |
| 2561 | #define MSR_IA32_MC13_CTL2 0x0000028D\r | |
| 2562 | #define MSR_IA32_MC14_CTL2 0x0000028E\r | |
| 2563 | #define MSR_IA32_MC15_CTL2 0x0000028F\r | |
| 2564 | #define MSR_IA32_MC16_CTL2 0x00000290\r | |
| 2565 | #define MSR_IA32_MC17_CTL2 0x00000291\r | |
| 2566 | #define MSR_IA32_MC18_CTL2 0x00000292\r | |
| 2567 | #define MSR_IA32_MC19_CTL2 0x00000293\r | |
| 2568 | #define MSR_IA32_MC20_CTL2 0x00000294\r | |
| 2569 | #define MSR_IA32_MC21_CTL2 0x00000295\r | |
| 2570 | #define MSR_IA32_MC22_CTL2 0x00000296\r | |
| 2571 | #define MSR_IA32_MC23_CTL2 0x00000297\r | |
| 2572 | #define MSR_IA32_MC24_CTL2 0x00000298\r | |
| 2573 | #define MSR_IA32_MC25_CTL2 0x00000299\r | |
| 2574 | #define MSR_IA32_MC26_CTL2 0x0000029A\r | |
| 2575 | #define MSR_IA32_MC27_CTL2 0x0000029B\r | |
| 2576 | #define MSR_IA32_MC28_CTL2 0x0000029C\r | |
| 2577 | #define MSR_IA32_MC29_CTL2 0x0000029D\r | |
| 2578 | #define MSR_IA32_MC30_CTL2 0x0000029E\r | |
| 2579 | #define MSR_IA32_MC31_CTL2 0x0000029F\r | |
| 2580 | /// @}\r | |
| 2581 | \r | |
| 2582 | /**\r | |
| 2583 | MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r | |
| 2584 | to #MSR_IA32_MC31_CTL2\r | |
| 2585 | **/\r | |
| 2586 | typedef union {\r | |
| 2587 | ///\r | |
| 2588 | /// Individual bit fields\r | |
| 2589 | ///\r | |
| 2590 | struct {\r | |
| 2591 | ///\r | |
| 2592 | /// [Bits 14:0] Corrected error count threshold.\r | |
| 2593 | ///\r | |
| 2594 | UINT32 CorrectedErrorCountThreshold:15;\r | |
| 2595 | UINT32 Reserved1:15;\r | |
| 2596 | ///\r | |
| 2597 | /// [Bit 30] CMCI_EN.\r | |
| 2598 | ///\r | |
| 2599 | UINT32 CMCI_EN:1;\r | |
| 2600 | UINT32 Reserved2:1;\r | |
| 2601 | UINT32 Reserved3:32;\r | |
| 2602 | } Bits;\r | |
| 2603 | ///\r | |
| 2604 | /// All bit fields as a 32-bit value\r | |
| 2605 | ///\r | |
| 2606 | UINT32 Uint32;\r | |
| 2607 | ///\r | |
| 2608 | /// All bit fields as a 64-bit value\r | |
| 2609 | ///\r | |
| 2610 | UINT64 Uint64;\r | |
| 2611 | } MSR_IA32_MC_CTL2_REGISTER;\r | |
| 2612 | \r | |
| 2613 | \r | |
| 2614 | /**\r | |
| 2615 | MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2616 | \r | |
| 2617 | @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r | |
| 2618 | @param EAX Lower 32-bits of MSR value.\r | |
| 2619 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2620 | @param EDX Upper 32-bits of MSR value.\r | |
| 2621 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2622 | \r | |
| 2623 | <b>Example usage</b>\r | |
| 2624 | @code\r | |
| 2625 | MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r | |
| 2626 | \r | |
| 2627 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r | |
| 2628 | AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r | |
| 2629 | @endcode\r | |
| 7de98828 | 2630 | @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r |
| 04c980a6 MK |
2631 | **/\r |
| 2632 | #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r | |
| 2633 | \r | |
| 2634 | /**\r | |
| 2635 | MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r | |
| 2636 | **/\r | |
| 2637 | typedef union {\r | |
| 2638 | ///\r | |
| 2639 | /// Individual bit fields\r | |
| 2640 | ///\r | |
| 2641 | struct {\r | |
| 2642 | ///\r | |
| 2643 | /// [Bits 2:0] Default Memory Type.\r | |
| 2644 | ///\r | |
| 2645 | UINT32 Type:3;\r | |
| 2646 | UINT32 Reserved1:7;\r | |
| 2647 | ///\r | |
| 2648 | /// [Bit 10] Fixed Range MTRR Enable.\r | |
| 2649 | ///\r | |
| 2650 | UINT32 FE:1;\r | |
| 2651 | ///\r | |
| 2652 | /// [Bit 11] MTRR Enable.\r | |
| 2653 | ///\r | |
| 2654 | UINT32 E:1;\r | |
| 2655 | UINT32 Reserved2:20;\r | |
| 2656 | UINT32 Reserved3:32;\r | |
| 2657 | } Bits;\r | |
| 2658 | ///\r | |
| 2659 | /// All bit fields as a 32-bit value\r | |
| 2660 | ///\r | |
| 2661 | UINT32 Uint32;\r | |
| 2662 | ///\r | |
| 2663 | /// All bit fields as a 64-bit value\r | |
| 2664 | ///\r | |
| 2665 | UINT64 Uint64;\r | |
| 2666 | } MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r | |
| 2667 | \r | |
| 2668 | \r | |
| 2669 | /**\r | |
| 2670 | Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r | |
| 2671 | CPUID.0AH: EDX[4:0] > 0.\r | |
| 2672 | \r | |
| 2673 | @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r | |
| 2674 | @param EAX Lower 32-bits of MSR value.\r | |
| 2675 | @param EDX Upper 32-bits of MSR value.\r | |
| 2676 | \r | |
| 2677 | <b>Example usage</b>\r | |
| 2678 | @code\r | |
| 2679 | UINT64 Msr;\r | |
| 2680 | \r | |
| 2681 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r | |
| 2682 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r | |
| 2683 | @endcode\r | |
| 7de98828 | 2684 | @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r |
| 04c980a6 MK |
2685 | **/\r |
| 2686 | #define MSR_IA32_FIXED_CTR0 0x00000309\r | |
| 2687 | \r | |
| 2688 | \r | |
| 2689 | /**\r | |
| 2690 | Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.\r | |
| 2691 | If CPUID.0AH: EDX[4:0] > 1.\r | |
| 2692 | \r | |
| 2693 | @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r | |
| 2694 | @param EAX Lower 32-bits of MSR value.\r | |
| 2695 | @param EDX Upper 32-bits of MSR value.\r | |
| 2696 | \r | |
| 2697 | <b>Example usage</b>\r | |
| 2698 | @code\r | |
| 2699 | UINT64 Msr;\r | |
| 2700 | \r | |
| 2701 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r | |
| 2702 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r | |
| 2703 | @endcode\r | |
| 7de98828 | 2704 | @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r |
| 04c980a6 MK |
2705 | **/\r |
| 2706 | #define MSR_IA32_FIXED_CTR1 0x0000030A\r | |
| 2707 | \r | |
| 2708 | \r | |
| 2709 | /**\r | |
| 2710 | Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.\r | |
| 2711 | If CPUID.0AH: EDX[4:0] > 2.\r | |
| 2712 | \r | |
| 2713 | @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r | |
| 2714 | @param EAX Lower 32-bits of MSR value.\r | |
| 2715 | @param EDX Upper 32-bits of MSR value.\r | |
| 2716 | \r | |
| 2717 | <b>Example usage</b>\r | |
| 2718 | @code\r | |
| 2719 | UINT64 Msr;\r | |
| 2720 | \r | |
| 2721 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r | |
| 2722 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r | |
| 2723 | @endcode\r | |
| 7de98828 | 2724 | @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r |
| 04c980a6 MK |
2725 | **/\r |
| 2726 | #define MSR_IA32_FIXED_CTR2 0x0000030B\r | |
| 2727 | \r | |
| 2728 | \r | |
| 2729 | /**\r | |
| 2730 | RO. If CPUID.01H: ECX[15] = 1.\r | |
| 2731 | \r | |
| 2732 | @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r | |
| 2733 | @param EAX Lower 32-bits of MSR value.\r | |
| 2734 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2735 | @param EDX Upper 32-bits of MSR value.\r | |
| 2736 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2737 | \r | |
| 2738 | <b>Example usage</b>\r | |
| 2739 | @code\r | |
| 2740 | MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r | |
| 2741 | \r | |
| 2742 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r | |
| 2743 | AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r | |
| 2744 | @endcode\r | |
| 7de98828 | 2745 | @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r |
| 04c980a6 MK |
2746 | **/\r |
| 2747 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345\r | |
| 2748 | \r | |
| 2749 | /**\r | |
| 2750 | MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r | |
| 2751 | **/\r | |
| 2752 | typedef union {\r | |
| 2753 | ///\r | |
| 2754 | /// Individual bit fields\r | |
| 2755 | ///\r | |
| 2756 | struct {\r | |
| 2757 | ///\r | |
| 2758 | /// [Bits 5:0] LBR format.\r | |
| 2759 | ///\r | |
| 2760 | UINT32 LBR_FMT:6;\r | |
| 2761 | ///\r | |
| 2762 | /// [Bit 6] PEBS Trap.\r | |
| 2763 | ///\r | |
| 2764 | UINT32 PEBS_TRAP:1;\r | |
| 2765 | ///\r | |
| 2766 | /// [Bit 7] PEBSSaveArchRegs.\r | |
| 2767 | ///\r | |
| 2768 | UINT32 PEBS_ARCH_REG:1;\r | |
| 2769 | ///\r | |
| 2770 | /// [Bits 11:8] PEBS Record Format.\r | |
| 2771 | ///\r | |
| 2772 | UINT32 PEBS_REC_FMT:4;\r | |
| 2773 | ///\r | |
| 2774 | /// [Bit 12] 1: Freeze while SMM is supported.\r | |
| 2775 | ///\r | |
| 2776 | UINT32 SMM_FREEZE:1;\r | |
| 2777 | ///\r | |
| 2778 | /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r | |
| 2779 | ///\r | |
| 2780 | UINT32 FW_WRITE:1;\r | |
| 2781 | UINT32 Reserved1:18;\r | |
| 2782 | UINT32 Reserved2:32;\r | |
| 2783 | } Bits;\r | |
| 2784 | ///\r | |
| 2785 | /// All bit fields as a 32-bit value\r | |
| 2786 | ///\r | |
| 2787 | UINT32 Uint32;\r | |
| 2788 | ///\r | |
| 2789 | /// All bit fields as a 64-bit value\r | |
| 2790 | ///\r | |
| 2791 | UINT64 Uint64;\r | |
| 2792 | } MSR_IA32_PERF_CAPABILITIES_REGISTER;\r | |
| 2793 | \r | |
| 2794 | \r | |
| 2795 | /**\r | |
| 2796 | Fixed-Function Performance Counter Control (R/W) Counter increments while\r | |
| 2797 | the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r | |
| 2798 | the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r | |
| 2799 | > 1.\r | |
| 2800 | \r | |
| 2801 | @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r | |
| 2802 | @param EAX Lower 32-bits of MSR value.\r | |
| 2803 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2804 | @param EDX Upper 32-bits of MSR value.\r | |
| 2805 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2806 | \r | |
| 2807 | <b>Example usage</b>\r | |
| 2808 | @code\r | |
| 2809 | MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r | |
| 2810 | \r | |
| 2811 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r | |
| 2812 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r | |
| 2813 | @endcode\r | |
| 7de98828 | 2814 | @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r |
| 04c980a6 MK |
2815 | **/\r |
| 2816 | #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r | |
| 2817 | \r | |
| 2818 | /**\r | |
| 2819 | MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r | |
| 2820 | **/\r | |
| 2821 | typedef union {\r | |
| 2822 | ///\r | |
| 2823 | /// Individual bit fields\r | |
| 2824 | ///\r | |
| 2825 | struct {\r | |
| 2826 | ///\r | |
| 2827 | /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r | |
| 2828 | ///\r | |
| 2829 | UINT32 EN0_OS:1;\r | |
| 2830 | ///\r | |
| 2831 | /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r | |
| 2832 | ///\r | |
| 2833 | UINT32 EN0_Usr:1;\r | |
| 2834 | ///\r | |
| 2835 | /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r | |
| 2836 | /// event conditions occurring across all logical processors sharing a\r | |
| 2837 | /// processor core. When set to 0, the counter only increments the\r | |
| 2838 | /// associated event conditions occurring in the logical processor which\r | |
| 2839 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2840 | ///\r | |
| 2841 | UINT32 AnyThread0:1;\r | |
| 2842 | ///\r | |
| 2843 | /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r | |
| 2844 | ///\r | |
| 2845 | UINT32 EN0_PMI:1;\r | |
| 2846 | ///\r | |
| 2847 | /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r | |
| 2848 | ///\r | |
| 2849 | UINT32 EN1_OS:1;\r | |
| 2850 | ///\r | |
| 2851 | /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r | |
| 2852 | ///\r | |
| 2853 | UINT32 EN1_Usr:1;\r | |
| 2854 | ///\r | |
| 2855 | /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r | |
| 2856 | /// event conditions occurring across all logical processors sharing a\r | |
| 2857 | /// processor core. When set to 0, the counter only increments the\r | |
| 2858 | /// associated event conditions occurring in the logical processor which\r | |
| 2859 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2860 | ///\r | |
| 2861 | UINT32 AnyThread1:1;\r | |
| 2862 | ///\r | |
| 2863 | /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r | |
| 2864 | ///\r | |
| 2865 | UINT32 EN1_PMI:1;\r | |
| 2866 | ///\r | |
| 2867 | /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r | |
| 2868 | ///\r | |
| 2869 | UINT32 EN2_OS:1;\r | |
| 2870 | ///\r | |
| 2871 | /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r | |
| 2872 | ///\r | |
| 2873 | UINT32 EN2_Usr:1;\r | |
| 2874 | ///\r | |
| 2875 | /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r | |
| 2876 | /// event conditions occurring across all logical processors sharing a\r | |
| 2877 | /// processor core. When set to 0, the counter only increments the\r | |
| 2878 | /// associated event conditions occurring in the logical processor which\r | |
| 2879 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2880 | ///\r | |
| 2881 | UINT32 AnyThread2:1;\r | |
| 2882 | ///\r | |
| 2883 | /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r | |
| 2884 | ///\r | |
| 2885 | UINT32 EN2_PMI:1;\r | |
| 2886 | UINT32 Reserved1:20;\r | |
| 2887 | UINT32 Reserved2:32;\r | |
| 2888 | } Bits;\r | |
| 2889 | ///\r | |
| 2890 | /// All bit fields as a 32-bit value\r | |
| 2891 | ///\r | |
| 2892 | UINT32 Uint32;\r | |
| 2893 | ///\r | |
| 2894 | /// All bit fields as a 64-bit value\r | |
| 2895 | ///\r | |
| 2896 | UINT64 Uint64;\r | |
| 2897 | } MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r | |
| 2898 | \r | |
| 2899 | \r | |
| 2900 | /**\r | |
| 2901 | Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r | |
| 2902 | \r | |
| 2903 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r | |
| 2904 | @param EAX Lower 32-bits of MSR value.\r | |
| 2905 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2906 | @param EDX Upper 32-bits of MSR value.\r | |
| 2907 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2908 | \r | |
| 2909 | <b>Example usage</b>\r | |
| 2910 | @code\r | |
| 2911 | MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
| 2912 | \r | |
| 2913 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r | |
| 2914 | @endcode\r | |
| 7de98828 | 2915 | @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r |
| 04c980a6 MK |
2916 | **/\r |
| 2917 | #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r | |
| 2918 | \r | |
| 2919 | /**\r | |
| 2920 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r | |
| 2921 | **/\r | |
| 2922 | typedef union {\r | |
| 2923 | ///\r | |
| 2924 | /// Individual bit fields\r | |
| 2925 | ///\r | |
| 2926 | struct {\r | |
| 2927 | ///\r | |
| 2928 | /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r | |
| 2929 | /// EAX[15:8] > 0.\r | |
| 2930 | ///\r | |
| 2931 | UINT32 Ovf_PMC0:1;\r | |
| 2932 | ///\r | |
| 2933 | /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r | |
| 2934 | /// EAX[15:8] > 1.\r | |
| 2935 | ///\r | |
| 2936 | UINT32 Ovf_PMC1:1;\r | |
| 2937 | ///\r | |
| 2938 | /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r | |
| 2939 | /// EAX[15:8] > 2.\r | |
| 2940 | ///\r | |
| 2941 | UINT32 Ovf_PMC2:1;\r | |
| 2942 | ///\r | |
| 2943 | /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r | |
| 2944 | /// EAX[15:8] > 3.\r | |
| 2945 | ///\r | |
| 2946 | UINT32 Ovf_PMC3:1;\r | |
| 2947 | UINT32 Reserved1:28;\r | |
| 2948 | ///\r | |
| 2949 | /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r | |
| 2950 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2951 | ///\r | |
| 2952 | UINT32 Ovf_FixedCtr0:1;\r | |
| 2953 | ///\r | |
| 2954 | /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r | |
| 2955 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2956 | ///\r | |
| 2957 | UINT32 Ovf_FixedCtr1:1;\r | |
| 2958 | ///\r | |
| 2959 | /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r | |
| 2960 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2961 | ///\r | |
| 2962 | UINT32 Ovf_FixedCtr2:1;\r | |
| 2963 | UINT32 Reserved2:20;\r | |
| 2964 | ///\r | |
| 2965 | /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r | |
| 2966 | /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
| 2967 | /// && IA32_RTIT_CTL.ToPA = 1.\r | |
| 2968 | ///\r | |
| 2969 | UINT32 Trace_ToPA_PMI:1;\r | |
| 2970 | UINT32 Reserved3:2;\r | |
| 2971 | ///\r | |
| 2972 | /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r | |
| 2973 | /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r | |
| 2974 | /// CPUID.0AH: EAX[7:0] > 3.\r | |
| 2975 | ///\r | |
| 2976 | UINT32 LBR_Frz:1;\r | |
| 2977 | ///\r | |
| 2978 | /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r | |
| 2979 | /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r | |
| 2980 | /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 2981 | ///\r | |
| 2982 | UINT32 CTR_Frz:1;\r | |
| 2983 | ///\r | |
| 2984 | /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r | |
| 2985 | /// include contributions from the direct or indirect operation intel SGX\r | |
| 2986 | /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r | |
| 2987 | ///\r | |
| 2988 | UINT32 ASCI:1;\r | |
| 2989 | ///\r | |
| 2990 | /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r | |
| 2991 | /// EAX[7:0] > 2.\r | |
| 2992 | ///\r | |
| 2993 | UINT32 Ovf_Uncore:1;\r | |
| 2994 | ///\r | |
| 2995 | /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r | |
| 2996 | /// EAX[7:0] > 0.\r | |
| 2997 | ///\r | |
| 2998 | UINT32 OvfBuf:1;\r | |
| 2999 | ///\r | |
| 3000 | /// [Bit 63] CondChgd: status bits of this register has changed. If\r | |
| 3001 | /// CPUID.0AH: EAX[7:0] > 0.\r | |
| 3002 | ///\r | |
| 3003 | UINT32 CondChgd:1;\r | |
| 3004 | } Bits;\r | |
| 3005 | ///\r | |
| 3006 | /// All bit fields as a 64-bit value\r | |
| 3007 | ///\r | |
| 3008 | UINT64 Uint64;\r | |
| 3009 | } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r | |
| 3010 | \r | |
| 3011 | \r | |
| 3012 | /**\r | |
| 3013 | Global Performance Counter Control (R/W) Counter increments while the result\r | |
| 3014 | of ANDing respective enable bit in this MSR with the corresponding OS or USR\r | |
| 3015 | bits in the general-purpose or fixed counter control MSR is true. If\r | |
| 3016 | CPUID.0AH: EAX[7:0] > 0.\r | |
| 3017 | \r | |
| 3018 | @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r | |
| 3019 | @param EAX Lower 32-bits of MSR value.\r | |
| 3020 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 3021 | @param EDX Upper 32-bits of MSR value.\r | |
| 3022 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 3023 | \r | |
| 3024 | <b>Example usage</b>\r | |
| 3025 | @code\r | |
| 3026 | MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
| 3027 | \r | |
| 3028 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r | |
| 3029 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
| 3030 | @endcode\r | |
| 7de98828 | 3031 | @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r |
| 04c980a6 MK |
3032 | **/\r |
| 3033 | #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r | |
| 3034 | \r | |
| 3035 | /**\r | |
| 3036 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r | |
| 3037 | **/\r | |
| 3038 | typedef union {\r | |
| 3039 | ///\r | |
| 3040 | /// Individual bit fields\r | |
| 3041 | ///\r | |
| 3042 | struct {\r | |
| 3043 | ///\r | |
| 3044 | /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3045 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3046 | /// Bits n..31 are reserved.\r | |
| 3047 | ///\r | |
| 3048 | UINT32 EN_PMCn:32;\r | |
| 3049 | ///\r | |
| 3050 | /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r | |
| 3051 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3052 | /// Bits 31:n are reserved.\r | |
| 3053 | ///\r | |
| 3054 | UINT32 EN_FIXED_CTRn:32;\r | |
| 3055 | } Bits;\r | |
| 3056 | ///\r | |
| 3057 | /// All bit fields as a 64-bit value\r | |
| 3058 | ///\r | |
| 3059 | UINT64 Uint64;\r | |
| 3060 | } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r | |
| 3061 | \r | |
| 3062 | \r | |
| 3063 | /**\r | |
| 3064 | Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r | |
| 3065 | 0 && CPUID.0AH: EAX[7:0] <= 3.\r | |
| 3066 | \r | |
| 3067 | @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
| 3068 | @param EAX Lower 32-bits of MSR value.\r | |
| 3069 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3070 | @param EDX Upper 32-bits of MSR value.\r | |
| 3071 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3072 | \r | |
| 3073 | <b>Example usage</b>\r | |
| 3074 | @code\r | |
| 3075 | MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r | |
| 3076 | \r | |
| 3077 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r | |
| 3078 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r | |
| 3079 | @endcode\r | |
| 7de98828 | 3080 | @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r |
| 04c980a6 MK |
3081 | **/\r |
| 3082 | #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r | |
| 3083 | \r | |
| 3084 | /**\r | |
| 3085 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r | |
| 3086 | **/\r | |
| 3087 | typedef union {\r | |
| 3088 | ///\r | |
| 3089 | /// Individual bit fields\r | |
| 3090 | ///\r | |
| 3091 | struct {\r | |
| 3092 | ///\r | |
| 3093 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3094 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3095 | /// Bits 31:n are reserved.\r | |
| 3096 | ///\r | |
| 3097 | UINT32 Ovf_PMCn:32;\r | |
| 3098 | ///\r | |
| 3099 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3100 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3101 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3102 | /// Bits 22:n are reserved.\r | |
| 3103 | ///\r | |
| 3104 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3105 | ///\r | |
| 3106 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3107 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r | |
| 3108 | ///\r | |
| 3109 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3110 | UINT32 Reserved2:5;\r | |
| 3111 | ///\r | |
| 3112 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3113 | /// Display Model 06_2EH.\r | |
| 3114 | ///\r | |
| 3115 | UINT32 Ovf_Uncore:1;\r | |
| 3116 | ///\r | |
| 3117 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3118 | ///\r | |
| 3119 | UINT32 OvfBuf:1;\r | |
| 3120 | ///\r | |
| 3121 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3122 | ///\r | |
| 3123 | UINT32 CondChgd:1;\r | |
| 3124 | } Bits;\r | |
| 3125 | ///\r | |
| 3126 | /// All bit fields as a 64-bit value\r | |
| 3127 | ///\r | |
| 3128 | UINT64 Uint64;\r | |
| 3129 | } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r | |
| 3130 | \r | |
| 3131 | \r | |
| 3132 | /**\r | |
| 3133 | Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r | |
| 3134 | EAX[7:0] > 3.\r | |
| 3135 | \r | |
| 3136 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
| 3137 | @param EAX Lower 32-bits of MSR value.\r | |
| 3138 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3139 | @param EDX Upper 32-bits of MSR value.\r | |
| 3140 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3141 | \r | |
| 3142 | <b>Example usage</b>\r | |
| 3143 | @code\r | |
| 3144 | MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
| 3145 | \r | |
| 3146 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
| 3147 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
| 3148 | @endcode\r | |
| 7de98828 | 3149 | @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r |
| 04c980a6 MK |
3150 | **/\r |
| 3151 | #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r | |
| 3152 | \r | |
| 3153 | /**\r | |
| 3154 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r | |
| 3155 | **/\r | |
| 3156 | typedef union {\r | |
| 3157 | ///\r | |
| 3158 | /// Individual bit fields\r | |
| 3159 | ///\r | |
| 3160 | struct {\r | |
| 3161 | ///\r | |
| 3162 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3163 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3164 | /// Bits 31:n are reserved.\r | |
| 3165 | ///\r | |
| 3166 | UINT32 Ovf_PMCn:32;\r | |
| 3167 | ///\r | |
| 3168 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3169 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3170 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3171 | /// Bits 22:n are reserved.\r | |
| 3172 | ///\r | |
| 3173 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3174 | ///\r | |
| 3175 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3176 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r | |
| 3177 | ///\r | |
| 3178 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3179 | UINT32 Reserved2:2;\r | |
| 3180 | ///\r | |
| 3181 | /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3182 | ///\r | |
| 3183 | UINT32 LBR_Frz:1;\r | |
| 3184 | ///\r | |
| 3185 | /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3186 | ///\r | |
| 3187 | UINT32 CTR_Frz:1;\r | |
| 3188 | ///\r | |
| 3189 | /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3190 | ///\r | |
| 3191 | UINT32 ASCI:1;\r | |
| 3192 | ///\r | |
| 3193 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3194 | /// Display Model 06_2EH.\r | |
| 3195 | ///\r | |
| 3196 | UINT32 Ovf_Uncore:1;\r | |
| 3197 | ///\r | |
| 3198 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3199 | ///\r | |
| 3200 | UINT32 OvfBuf:1;\r | |
| 3201 | ///\r | |
| 3202 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3203 | ///\r | |
| 3204 | UINT32 CondChgd:1;\r | |
| 3205 | } Bits;\r | |
| 3206 | ///\r | |
| 3207 | /// All bit fields as a 64-bit value\r | |
| 3208 | ///\r | |
| 3209 | UINT64 Uint64;\r | |
| 3210 | } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r | |
| 3211 | \r | |
| 3212 | \r | |
| 3213 | /**\r | |
| 3214 | Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r | |
| 3215 | EAX[7:0] > 3.\r | |
| 3216 | \r | |
| 3217 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
| 3218 | @param EAX Lower 32-bits of MSR value.\r | |
| 3219 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3220 | @param EDX Upper 32-bits of MSR value.\r | |
| 3221 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3222 | \r | |
| 3223 | <b>Example usage</b>\r | |
| 3224 | @code\r | |
| 3225 | MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
| 3226 | \r | |
| 3227 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r | |
| 3228 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
| 3229 | @endcode\r | |
| 7de98828 | 3230 | @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r |
| 04c980a6 MK |
3231 | **/\r |
| 3232 | #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
| 3233 | \r | |
| 3234 | /**\r | |
| 3235 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r | |
| 3236 | **/\r | |
| 3237 | typedef union {\r | |
| 3238 | ///\r | |
| 3239 | /// Individual bit fields\r | |
| 3240 | ///\r | |
| 3241 | struct {\r | |
| 3242 | ///\r | |
| 3243 | /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3244 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3245 | /// Bits 31:n are reserved.\r | |
| 3246 | ///\r | |
| 3247 | UINT32 Ovf_PMCn:32;\r | |
| 3248 | ///\r | |
| 3249 | /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r | |
| 3250 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3251 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3252 | /// Bits 22:n are reserved.\r | |
| 3253 | ///\r | |
| 3254 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3255 | ///\r | |
| 3256 | /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3257 | ///\r | |
| 3258 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3259 | UINT32 Reserved2:2;\r | |
| 3260 | ///\r | |
| 3261 | /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3262 | ///\r | |
| 3263 | UINT32 LBR_Frz:1;\r | |
| 3264 | ///\r | |
| 3265 | /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3266 | ///\r | |
| 3267 | UINT32 CTR_Frz:1;\r | |
| 3268 | ///\r | |
| 3269 | /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3270 | ///\r | |
| 3271 | UINT32 ASCI:1;\r | |
| 3272 | ///\r | |
| 3273 | /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3274 | ///\r | |
| 3275 | UINT32 Ovf_Uncore:1;\r | |
| 3276 | ///\r | |
| 3277 | /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3278 | ///\r | |
| 3279 | UINT32 OvfBuf:1;\r | |
| 3280 | UINT32 Reserved3:1;\r | |
| 3281 | } Bits;\r | |
| 3282 | ///\r | |
| 3283 | /// All bit fields as a 64-bit value\r | |
| 3284 | ///\r | |
| 3285 | UINT64 Uint64;\r | |
| 3286 | } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r | |
| 3287 | \r | |
| 3288 | \r | |
| 3289 | /**\r | |
| 3290 | Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r | |
| 3291 | 3.\r | |
| 3292 | \r | |
| 3293 | @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r | |
| 3294 | @param EAX Lower 32-bits of MSR value.\r | |
| 3295 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3296 | @param EDX Upper 32-bits of MSR value.\r | |
| 3297 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3298 | \r | |
| 3299 | <b>Example usage</b>\r | |
| 3300 | @code\r | |
| 3301 | MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r | |
| 3302 | \r | |
| 3303 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r | |
| 3304 | @endcode\r | |
| 7de98828 | 3305 | @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r |
| 04c980a6 MK |
3306 | **/\r |
| 3307 | #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r | |
| 3308 | \r | |
| 3309 | /**\r | |
| 3310 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r | |
| 3311 | **/\r | |
| 3312 | typedef union {\r | |
| 3313 | ///\r | |
| 3314 | /// Individual bit fields\r | |
| 3315 | ///\r | |
| 3316 | struct {\r | |
| 3317 | ///\r | |
| 3318 | /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3319 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3320 | /// Bits 31:n are reserved.\r | |
| 3321 | ///\r | |
| 3322 | UINT32 IA32_PERFEVTSELn:32;\r | |
| 3323 | ///\r | |
| 3324 | /// [Bits 62:32] IA32_FIXED_CTRn in use.\r | |
| 3325 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3326 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3327 | /// Bits 30:n are reserved.\r | |
| 3328 | ///\r | |
| 3329 | UINT32 IA32_FIXED_CTRn:31;\r | |
| 3330 | ///\r | |
| 3331 | /// [Bit 63] PMI in use.\r | |
| 3332 | ///\r | |
| 3333 | UINT32 PMI:1;\r | |
| 3334 | } Bits;\r | |
| 3335 | ///\r | |
| 3336 | /// All bit fields as a 64-bit value\r | |
| 3337 | ///\r | |
| 3338 | UINT64 Uint64;\r | |
| 3339 | } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r | |
| 3340 | \r | |
| 3341 | \r | |
| 3342 | /**\r | |
| 3343 | PEBS Control (R/W).\r | |
| 3344 | \r | |
| 3345 | @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r | |
| 3346 | @param EAX Lower 32-bits of MSR value.\r | |
| 3347 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3348 | @param EDX Upper 32-bits of MSR value.\r | |
| 3349 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3350 | \r | |
| 3351 | <b>Example usage</b>\r | |
| 3352 | @code\r | |
| 3353 | MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r | |
| 3354 | \r | |
| 3355 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r | |
| 3356 | AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r | |
| 3357 | @endcode\r | |
| 7de98828 | 3358 | @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r |
| 04c980a6 MK |
3359 | **/\r |
| 3360 | #define MSR_IA32_PEBS_ENABLE 0x000003F1\r | |
| 3361 | \r | |
| 3362 | /**\r | |
| 3363 | MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r | |
| 3364 | **/\r | |
| 3365 | typedef union {\r | |
| 3366 | ///\r | |
| 3367 | /// Individual bit fields\r | |
| 3368 | ///\r | |
| 3369 | struct {\r | |
| 3370 | ///\r | |
| 3371 | /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r | |
| 3372 | /// Display Model 06_0FH.\r | |
| 3373 | ///\r | |
| 3374 | UINT32 Enable:1;\r | |
| 3375 | ///\r | |
| 3376 | /// [Bits 3:1] Reserved or Model specific.\r | |
| 3377 | ///\r | |
| 3378 | UINT32 Reserved1:3;\r | |
| 3379 | UINT32 Reserved2:28;\r | |
| 3380 | ///\r | |
| 3381 | /// [Bits 35:32] Reserved or Model specific.\r | |
| 3382 | ///\r | |
| 3383 | UINT32 Reserved3:4;\r | |
| 3384 | UINT32 Reserved4:28;\r | |
| 3385 | } Bits;\r | |
| 3386 | ///\r | |
| 3387 | /// All bit fields as a 64-bit value\r | |
| 3388 | ///\r | |
| 3389 | UINT64 Uint64;\r | |
| 3390 | } MSR_IA32_PEBS_ENABLE_REGISTER;\r | |
| 3391 | \r | |
| 3392 | \r | |
| 3393 | /**\r | |
| 3394 | MCn_CTL. If IA32_MCG_CAP.CNT > n.\r | |
| 3395 | \r | |
| 3396 | @param ECX MSR_IA32_MCn_CTL\r | |
| 3397 | @param EAX Lower 32-bits of MSR value.\r | |
| 3398 | @param EDX Upper 32-bits of MSR value.\r | |
| 3399 | \r | |
| 3400 | <b>Example usage</b>\r | |
| 3401 | @code\r | |
| 3402 | UINT64 Msr;\r | |
| 3403 | \r | |
| 3404 | Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r | |
| 3405 | AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r | |
| 3406 | @endcode\r | |
| 7de98828 JF |
3407 | @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r |
| 3408 | MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r | |
| 3409 | MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r | |
| 3410 | MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r | |
| 3411 | MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r | |
| 3412 | MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r | |
| 3413 | MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r | |
| 3414 | MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r | |
| 3415 | MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r | |
| 3416 | MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r | |
| 3417 | MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r | |
| 3418 | MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r | |
| 3419 | MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r | |
| 3420 | MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r | |
| 3421 | MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r | |
| 3422 | MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r | |
| 3423 | MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r | |
| 3424 | MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r | |
| 3425 | MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r | |
| 3426 | MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r | |
| 3427 | MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r | |
| 3428 | MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r | |
| 3429 | MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r | |
| 3430 | MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r | |
| 3431 | MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r | |
| 3432 | MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r | |
| 3433 | MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r | |
| 3434 | MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r | |
| 3435 | MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r | |
| 04c980a6 MK |
3436 | @{\r |
| 3437 | **/\r | |
| 3438 | #define MSR_IA32_MC0_CTL 0x00000400\r | |
| 3439 | #define MSR_IA32_MC1_CTL 0x00000404\r | |
| 3440 | #define MSR_IA32_MC2_CTL 0x00000408\r | |
| 3441 | #define MSR_IA32_MC3_CTL 0x0000040C\r | |
| 3442 | #define MSR_IA32_MC4_CTL 0x00000410\r | |
| 3443 | #define MSR_IA32_MC5_CTL 0x00000414\r | |
| 3444 | #define MSR_IA32_MC6_CTL 0x00000418\r | |
| 3445 | #define MSR_IA32_MC7_CTL 0x0000041C\r | |
| 3446 | #define MSR_IA32_MC8_CTL 0x00000420\r | |
| 3447 | #define MSR_IA32_MC9_CTL 0x00000424\r | |
| 3448 | #define MSR_IA32_MC10_CTL 0x00000428\r | |
| 3449 | #define MSR_IA32_MC11_CTL 0x0000042C\r | |
| 3450 | #define MSR_IA32_MC12_CTL 0x00000430\r | |
| 3451 | #define MSR_IA32_MC13_CTL 0x00000434\r | |
| 3452 | #define MSR_IA32_MC14_CTL 0x00000438\r | |
| 3453 | #define MSR_IA32_MC15_CTL 0x0000043C\r | |
| 3454 | #define MSR_IA32_MC16_CTL 0x00000440\r | |
| 3455 | #define MSR_IA32_MC17_CTL 0x00000444\r | |
| 3456 | #define MSR_IA32_MC18_CTL 0x00000448\r | |
| 3457 | #define MSR_IA32_MC19_CTL 0x0000044C\r | |
| 3458 | #define MSR_IA32_MC20_CTL 0x00000450\r | |
| 3459 | #define MSR_IA32_MC21_CTL 0x00000454\r | |
| 3460 | #define MSR_IA32_MC22_CTL 0x00000458\r | |
| 3461 | #define MSR_IA32_MC23_CTL 0x0000045C\r | |
| 3462 | #define MSR_IA32_MC24_CTL 0x00000460\r | |
| 3463 | #define MSR_IA32_MC25_CTL 0x00000464\r | |
| 3464 | #define MSR_IA32_MC26_CTL 0x00000468\r | |
| 3465 | #define MSR_IA32_MC27_CTL 0x0000046C\r | |
| 3466 | #define MSR_IA32_MC28_CTL 0x00000470\r | |
| 3467 | /// @}\r | |
| 3468 | \r | |
| 3469 | \r | |
| 3470 | /**\r | |
| 3471 | MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r | |
| 3472 | \r | |
| 3473 | @param ECX MSR_IA32_MCn_STATUS\r | |
| 3474 | @param EAX Lower 32-bits of MSR value.\r | |
| 3475 | @param EDX Upper 32-bits of MSR value.\r | |
| 3476 | \r | |
| 3477 | <b>Example usage</b>\r | |
| 3478 | @code\r | |
| 3479 | UINT64 Msr;\r | |
| 3480 | \r | |
| 3481 | Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r | |
| 3482 | AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r | |
| 3483 | @endcode\r | |
| 7de98828 JF |
3484 | @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r |
| 3485 | MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r | |
| 3486 | MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r | |
| 3487 | MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r | |
| 3488 | MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r | |
| 3489 | MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r | |
| 3490 | MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r | |
| 3491 | MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r | |
| 3492 | MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r | |
| 3493 | MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r | |
| 3494 | MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r | |
| 3495 | MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r | |
| 3496 | MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r | |
| 3497 | MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r | |
| 3498 | MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r | |
| 3499 | MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r | |
| 3500 | MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r | |
| 3501 | MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r | |
| 3502 | MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r | |
| 3503 | MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r | |
| 3504 | MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r | |
| 3505 | MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r | |
| 3506 | MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r | |
| 3507 | MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r | |
| 3508 | MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r | |
| 3509 | MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r | |
| 3510 | MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r | |
| 3511 | MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r | |
| 3512 | MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r | |
| 04c980a6 MK |
3513 | @{\r |
| 3514 | **/\r | |
| 3515 | #define MSR_IA32_MC0_STATUS 0x00000401\r | |
| 3516 | #define MSR_IA32_MC1_STATUS 0x00000405\r | |
| 3517 | #define MSR_IA32_MC2_STATUS 0x00000409\r | |
| 3518 | #define MSR_IA32_MC3_STATUS 0x0000040D\r | |
| 3519 | #define MSR_IA32_MC4_STATUS 0x00000411\r | |
| 3520 | #define MSR_IA32_MC5_STATUS 0x00000415\r | |
| 3521 | #define MSR_IA32_MC6_STATUS 0x00000419\r | |
| 3522 | #define MSR_IA32_MC7_STATUS 0x0000041D\r | |
| 3523 | #define MSR_IA32_MC8_STATUS 0x00000421\r | |
| 3524 | #define MSR_IA32_MC9_STATUS 0x00000425\r | |
| 3525 | #define MSR_IA32_MC10_STATUS 0x00000429\r | |
| 3526 | #define MSR_IA32_MC11_STATUS 0x0000042D\r | |
| 3527 | #define MSR_IA32_MC12_STATUS 0x00000431\r | |
| 3528 | #define MSR_IA32_MC13_STATUS 0x00000435\r | |
| 3529 | #define MSR_IA32_MC14_STATUS 0x00000439\r | |
| 3530 | #define MSR_IA32_MC15_STATUS 0x0000043D\r | |
| 3531 | #define MSR_IA32_MC16_STATUS 0x00000441\r | |
| 3532 | #define MSR_IA32_MC17_STATUS 0x00000445\r | |
| 3533 | #define MSR_IA32_MC18_STATUS 0x00000449\r | |
| 3534 | #define MSR_IA32_MC19_STATUS 0x0000044D\r | |
| 3535 | #define MSR_IA32_MC20_STATUS 0x00000451\r | |
| 3536 | #define MSR_IA32_MC21_STATUS 0x00000455\r | |
| 3537 | #define MSR_IA32_MC22_STATUS 0x00000459\r | |
| 3538 | #define MSR_IA32_MC23_STATUS 0x0000045D\r | |
| 3539 | #define MSR_IA32_MC24_STATUS 0x00000461\r | |
| 3540 | #define MSR_IA32_MC25_STATUS 0x00000465\r | |
| 3541 | #define MSR_IA32_MC26_STATUS 0x00000469\r | |
| 3542 | #define MSR_IA32_MC27_STATUS 0x0000046D\r | |
| 3543 | #define MSR_IA32_MC28_STATUS 0x00000471\r | |
| 3544 | /// @}\r | |
| 3545 | \r | |
| 3546 | \r | |
| 3547 | /**\r | |
| 3548 | MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r | |
| 3549 | \r | |
| 3550 | @param ECX MSR_IA32_MCn_ADDR\r | |
| 3551 | @param EAX Lower 32-bits of MSR value.\r | |
| 3552 | @param EDX Upper 32-bits of MSR value.\r | |
| 3553 | \r | |
| 3554 | <b>Example usage</b>\r | |
| 3555 | @code\r | |
| 3556 | UINT64 Msr;\r | |
| 3557 | \r | |
| 3558 | Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r | |
| 3559 | AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r | |
| 3560 | @endcode\r | |
| 7de98828 JF |
3561 | @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r |
| 3562 | MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r | |
| 3563 | MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r | |
| 3564 | MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r | |
| 3565 | MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r | |
| 3566 | MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r | |
| 3567 | MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r | |
| 3568 | MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r | |
| 3569 | MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r | |
| 3570 | MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r | |
| 3571 | MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r | |
| 3572 | MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r | |
| 3573 | MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r | |
| 3574 | MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r | |
| 3575 | MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r | |
| 3576 | MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r | |
| 3577 | MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r | |
| 3578 | MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r | |
| 3579 | MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r | |
| 3580 | MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r | |
| 3581 | MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r | |
| 3582 | MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r | |
| 3583 | MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r | |
| 3584 | MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r | |
| 3585 | MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r | |
| 3586 | MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r | |
| 3587 | MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r | |
| 3588 | MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r | |
| 3589 | MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r | |
| 04c980a6 MK |
3590 | @{\r |
| 3591 | **/\r | |
| 3592 | #define MSR_IA32_MC0_ADDR 0x00000402\r | |
| 3593 | #define MSR_IA32_MC1_ADDR 0x00000406\r | |
| 3594 | #define MSR_IA32_MC2_ADDR 0x0000040A\r | |
| 3595 | #define MSR_IA32_MC3_ADDR 0x0000040E\r | |
| 3596 | #define MSR_IA32_MC4_ADDR 0x00000412\r | |
| 3597 | #define MSR_IA32_MC5_ADDR 0x00000416\r | |
| 3598 | #define MSR_IA32_MC6_ADDR 0x0000041A\r | |
| 3599 | #define MSR_IA32_MC7_ADDR 0x0000041E\r | |
| 3600 | #define MSR_IA32_MC8_ADDR 0x00000422\r | |
| 3601 | #define MSR_IA32_MC9_ADDR 0x00000426\r | |
| 3602 | #define MSR_IA32_MC10_ADDR 0x0000042A\r | |
| 3603 | #define MSR_IA32_MC11_ADDR 0x0000042E\r | |
| 3604 | #define MSR_IA32_MC12_ADDR 0x00000432\r | |
| 3605 | #define MSR_IA32_MC13_ADDR 0x00000436\r | |
| 3606 | #define MSR_IA32_MC14_ADDR 0x0000043A\r | |
| 3607 | #define MSR_IA32_MC15_ADDR 0x0000043E\r | |
| 3608 | #define MSR_IA32_MC16_ADDR 0x00000442\r | |
| 3609 | #define MSR_IA32_MC17_ADDR 0x00000446\r | |
| 3610 | #define MSR_IA32_MC18_ADDR 0x0000044A\r | |
| 3611 | #define MSR_IA32_MC19_ADDR 0x0000044E\r | |
| 3612 | #define MSR_IA32_MC20_ADDR 0x00000452\r | |
| 3613 | #define MSR_IA32_MC21_ADDR 0x00000456\r | |
| 3614 | #define MSR_IA32_MC22_ADDR 0x0000045A\r | |
| 3615 | #define MSR_IA32_MC23_ADDR 0x0000045E\r | |
| 3616 | #define MSR_IA32_MC24_ADDR 0x00000462\r | |
| 3617 | #define MSR_IA32_MC25_ADDR 0x00000466\r | |
| 3618 | #define MSR_IA32_MC26_ADDR 0x0000046A\r | |
| 3619 | #define MSR_IA32_MC27_ADDR 0x0000046E\r | |
| 3620 | #define MSR_IA32_MC28_ADDR 0x00000472\r | |
| 3621 | /// @}\r | |
| 3622 | \r | |
| 3623 | \r | |
| 3624 | /**\r | |
| 3625 | MCn_MISC. If IA32_MCG_CAP.CNT > n.\r | |
| 3626 | \r | |
| 3627 | @param ECX MSR_IA32_MCn_MISC\r | |
| 3628 | @param EAX Lower 32-bits of MSR value.\r | |
| 3629 | @param EDX Upper 32-bits of MSR value.\r | |
| 3630 | \r | |
| 3631 | <b>Example usage</b>\r | |
| 3632 | @code\r | |
| 3633 | UINT64 Msr;\r | |
| 3634 | \r | |
| 3635 | Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r | |
| 3636 | AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r | |
| 3637 | @endcode\r | |
| 7de98828 JF |
3638 | @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r |
| 3639 | MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r | |
| 3640 | MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r | |
| 3641 | MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r | |
| 3642 | MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r | |
| 3643 | MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r | |
| 3644 | MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r | |
| 3645 | MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r | |
| 3646 | MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r | |
| 3647 | MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r | |
| 3648 | MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r | |
| 3649 | MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r | |
| 3650 | MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r | |
| 3651 | MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r | |
| 3652 | MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r | |
| 3653 | MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r | |
| 3654 | MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r | |
| 3655 | MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r | |
| 3656 | MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r | |
| 3657 | MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r | |
| 3658 | MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r | |
| 3659 | MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r | |
| 3660 | MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r | |
| 3661 | MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r | |
| 3662 | MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r | |
| 3663 | MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r | |
| 3664 | MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r | |
| 3665 | MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r | |
| 3666 | MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r | |
| 04c980a6 MK |
3667 | @{\r |
| 3668 | **/\r | |
| 3669 | #define MSR_IA32_MC0_MISC 0x00000403\r | |
| 3670 | #define MSR_IA32_MC1_MISC 0x00000407\r | |
| 3671 | #define MSR_IA32_MC2_MISC 0x0000040B\r | |
| 3672 | #define MSR_IA32_MC3_MISC 0x0000040F\r | |
| 3673 | #define MSR_IA32_MC4_MISC 0x00000413\r | |
| 3674 | #define MSR_IA32_MC5_MISC 0x00000417\r | |
| 3675 | #define MSR_IA32_MC6_MISC 0x0000041B\r | |
| 3676 | #define MSR_IA32_MC7_MISC 0x0000041F\r | |
| 3677 | #define MSR_IA32_MC8_MISC 0x00000423\r | |
| 3678 | #define MSR_IA32_MC9_MISC 0x00000427\r | |
| 3679 | #define MSR_IA32_MC10_MISC 0x0000042B\r | |
| 3680 | #define MSR_IA32_MC11_MISC 0x0000042F\r | |
| 3681 | #define MSR_IA32_MC12_MISC 0x00000433\r | |
| 3682 | #define MSR_IA32_MC13_MISC 0x00000437\r | |
| 3683 | #define MSR_IA32_MC14_MISC 0x0000043B\r | |
| 3684 | #define MSR_IA32_MC15_MISC 0x0000043F\r | |
| 3685 | #define MSR_IA32_MC16_MISC 0x00000443\r | |
| 3686 | #define MSR_IA32_MC17_MISC 0x00000447\r | |
| 3687 | #define MSR_IA32_MC18_MISC 0x0000044B\r | |
| 3688 | #define MSR_IA32_MC19_MISC 0x0000044F\r | |
| 3689 | #define MSR_IA32_MC20_MISC 0x00000453\r | |
| 3690 | #define MSR_IA32_MC21_MISC 0x00000457\r | |
| 3691 | #define MSR_IA32_MC22_MISC 0x0000045B\r | |
| 3692 | #define MSR_IA32_MC23_MISC 0x0000045F\r | |
| 3693 | #define MSR_IA32_MC24_MISC 0x00000463\r | |
| 3694 | #define MSR_IA32_MC25_MISC 0x00000467\r | |
| 3695 | #define MSR_IA32_MC26_MISC 0x0000046B\r | |
| 3696 | #define MSR_IA32_MC27_MISC 0x0000046F\r | |
| 3697 | #define MSR_IA32_MC28_MISC 0x00000473\r | |
| 3698 | /// @}\r | |
| 3699 | \r | |
| 3700 | \r | |
| 3701 | /**\r | |
| 3702 | Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r | |
| 3703 | VMX Information.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3704 | \r | |
| 3705 | @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r | |
| 3706 | @param EAX Lower 32-bits of MSR value.\r | |
| 3707 | @param EDX Upper 32-bits of MSR value.\r | |
| 3708 | \r | |
| 3709 | <b>Example usage</b>\r | |
| 3710 | @code\r | |
| 831d287a | 3711 | MSR_IA32_VMX_BASIC_REGISTER Msr;\r |
| 04c980a6 | 3712 | \r |
| 831d287a | 3713 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r |
| 04c980a6 | 3714 | @endcode\r |
| 7de98828 | 3715 | @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r |
| 04c980a6 MK |
3716 | **/\r |
| 3717 | #define MSR_IA32_VMX_BASIC 0x00000480\r | |
| 3718 | \r | |
| 831d287a MK |
3719 | /**\r |
| 3720 | MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r | |
| 3721 | **/\r | |
| 3722 | typedef union {\r | |
| 3723 | ///\r | |
| 3724 | /// Individual bit fields\r | |
| 3725 | ///\r | |
| 3726 | struct {\r | |
| 3727 | ///\r | |
| 3728 | /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r | |
| 3729 | /// that use the same VMCS revision identifier use the same size for VMCS\r | |
| 3730 | /// regions (see subsequent item on bits 44:32).\r | |
| 3731 | ///\r | |
| 3732 | /// @note Earlier versions of this manual specified that the VMCS revision\r | |
| 3733 | /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r | |
| 3734 | /// processors produced prior to this change, bit 31 of this MSR was read\r | |
| 3735 | /// as 0.\r | |
| 3736 | ///\r | |
| 3737 | UINT32 VmcsRevisonId:31;\r | |
| 3738 | UINT32 MustBeZero:1;\r | |
| 3739 | ///\r | |
| 3740 | /// [Bit 44:32] Reports the number of bytes that software should allocate\r | |
| 3741 | /// for the VMXON region and any VMCS region. It is a value greater than\r | |
| 3742 | /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r | |
| 3743 | ///\r | |
| 3744 | UINT32 VmcsSize:13;\r | |
| 3745 | UINT32 Reserved1:3;\r | |
| 3746 | ///\r | |
| 3747 | /// [Bit 48] Indicates the width of the physical addresses that may be used\r | |
| 3748 | /// for the VMXON region, each VMCS, and data structures referenced by\r | |
| 3749 | /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r | |
| 3750 | /// transitions). If the bit is 0, these addresses are limited to the\r | |
| 3751 | /// processor's physical-address width. If the bit is 1, these addresses\r | |
| 3752 | /// are limited to 32 bits. This bit is always 0 for processors that\r | |
| 3753 | /// support Intel 64 architecture.\r | |
| 3754 | ///\r | |
| 3755 | /// @note On processors that support Intel 64 architecture, the pointer\r | |
| 3756 | /// must not set bits beyond the processor's physical address width.\r | |
| 3757 | ///\r | |
| 3758 | UINT32 VmcsAddressWidth:1;\r | |
| 3759 | ///\r | |
| 3760 | /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r | |
| 3761 | /// dual-monitor treatment of system-management interrupts and\r | |
| 3762 | /// system-management mode. See Section 34.15 for details of this treatment.\r | |
| 3763 | ///\r | |
| 3764 | UINT32 DualMonitor:1;\r | |
| 3765 | ///\r | |
| 3766 | /// [Bit 53:50] report the memory type that should be used for the VMCS,\r | |
| 3767 | /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r | |
| 3768 | /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r | |
| 3769 | /// header. If software needs to access these data structures (e.g., to\r | |
| 3770 | /// modify the contents of the MSR bitmaps), it can configure the paging\r | |
| 3771 | /// structures to map them into the linear-address space. If it does so,\r | |
| 3772 | /// it should establish mappings that use the memory type reported bits\r | |
| 3773 | /// 53:50 in this MSR.\r | |
| 3774 | ///\r | |
| 3775 | /// As of this writing, all processors that support VMX operation indicate\r | |
| 3776 | /// the write-back type.\r | |
| 3777 | ///\r | |
| 3778 | /// If software needs to access these data structures (e.g., to modify\r | |
| 3779 | /// the contents of the MSR bitmaps), it can configure the paging\r | |
| 3780 | /// structures to map them into the linear-address space. If it does so,\r | |
| 3781 | /// it should establish mappings that use the memory type reported in this\r | |
| 3782 | /// MSR.\r | |
| 3783 | ///\r | |
| 3784 | /// @note Alternatively, software may map any of these regions or\r | |
| 3785 | /// structures with the UC memory type. (This may be necessary for the MSEG\r | |
| 3786 | /// header.) Doing so is discouraged unless necessary as it will cause the\r | |
| 3787 | /// performance of software accesses to those structures to suffer.\r | |
| 3788 | ///\r | |
| 3789 | ///\r | |
| 3790 | UINT32 MemoryType:4;\r | |
| 3791 | ///\r | |
| 3792 | /// [Bit 54] If bit 54 is read as 1, the logical processor reports\r | |
| 3793 | /// information in the VM-exit instruction-information field on VM exits\r | |
| 3794 | /// due to execution of the INS and OUTS instructions. This reporting is\r | |
| 3795 | /// done only if this bit is read as 1.\r | |
| 3796 | ///\r | |
| 3797 | UINT32 InsOutsReporting:1;\r | |
| 3798 | ///\r | |
| 3799 | /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r | |
| 3800 | /// be cleared to 0. See Appendix A.2 for details. It also reports support\r | |
| 3801 | /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r | |
| 3802 | /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r | |
| 3803 | /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r | |
| 3804 | /// Appendix A.4, and Appendix A.5 for details.\r | |
| 3805 | ///\r | |
| 3806 | UINT32 VmxControls:1;\r | |
| 3807 | UINT32 Reserved2:8;\r | |
| 3808 | } Bits;\r | |
| 3809 | ///\r | |
| 3810 | /// All bit fields as a 64-bit value\r | |
| 3811 | ///\r | |
| 3812 | UINT64 Uint64;\r | |
| 3813 | } MSR_IA32_VMX_BASIC_REGISTER;\r | |
| 3814 | \r | |
| 3815 | ///\r | |
| 3816 | /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r | |
| 3817 | ///\r | |
| 3818 | #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r | |
| 3819 | #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r | |
| 3820 | ///\r | |
| 3821 | /// @}\r | |
| 3822 | ///\r | |
| 3823 | \r | |
| 04c980a6 MK |
3824 | \r |
| 3825 | /**\r | |
| 3826 | Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r | |
| 3827 | Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3828 | \r | |
| 3829 | @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r | |
| 3830 | @param EAX Lower 32-bits of MSR value.\r | |
| 3831 | @param EDX Upper 32-bits of MSR value.\r | |
| 3832 | \r | |
| 3833 | <b>Example usage</b>\r | |
| 3834 | @code\r | |
| 3835 | UINT64 Msr;\r | |
| 3836 | \r | |
| 3837 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r | |
| 3838 | @endcode\r | |
| 7de98828 | 3839 | @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3840 | **/\r |
| 3841 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r | |
| 3842 | \r | |
| 3843 | \r | |
| 3844 | /**\r | |
| 3845 | Capability Reporting Register of Primary Processor-based VM-execution\r | |
| 3846 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
| 3847 | Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3848 | \r | |
| 3849 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r | |
| 3850 | @param EAX Lower 32-bits of MSR value.\r | |
| 3851 | @param EDX Upper 32-bits of MSR value.\r | |
| 3852 | \r | |
| 3853 | <b>Example usage</b>\r | |
| 3854 | @code\r | |
| 3855 | UINT64 Msr;\r | |
| 3856 | \r | |
| 3857 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r | |
| 3858 | @endcode\r | |
| 7de98828 | 3859 | @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3860 | **/\r |
| 3861 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r | |
| 3862 | \r | |
| 3863 | \r | |
| 3864 | /**\r | |
| 3865 | Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r | |
| 3866 | "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3867 | \r | |
| 3868 | @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r | |
| 3869 | @param EAX Lower 32-bits of MSR value.\r | |
| 3870 | @param EDX Upper 32-bits of MSR value.\r | |
| 3871 | \r | |
| 3872 | <b>Example usage</b>\r | |
| 3873 | @code\r | |
| 3874 | UINT64 Msr;\r | |
| 3875 | \r | |
| 3876 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r | |
| 3877 | @endcode\r | |
| 7de98828 | 3878 | @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r |
| 04c980a6 MK |
3879 | **/\r |
| 3880 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r | |
| 3881 | \r | |
| 3882 | \r | |
| 3883 | /**\r | |
| 3884 | Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r | |
| 3885 | "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3886 | \r | |
| 3887 | @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r | |
| 3888 | @param EAX Lower 32-bits of MSR value.\r | |
| 3889 | @param EDX Upper 32-bits of MSR value.\r | |
| 3890 | \r | |
| 3891 | <b>Example usage</b>\r | |
| 3892 | @code\r | |
| 3893 | UINT64 Msr;\r | |
| 3894 | \r | |
| 3895 | Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r | |
| 3896 | @endcode\r | |
| 7de98828 | 3897 | @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r |
| 04c980a6 MK |
3898 | **/\r |
| 3899 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r | |
| 3900 | \r | |
| 3901 | \r | |
| 3902 | /**\r | |
| 3903 | Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r | |
| 3904 | "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3905 | \r | |
| 3906 | @param ECX MSR_IA32_VMX_MISC (0x00000485)\r | |
| 3907 | @param EAX Lower 32-bits of MSR value.\r | |
| 3908 | @param EDX Upper 32-bits of MSR value.\r | |
| 3909 | \r | |
| 3910 | <b>Example usage</b>\r | |
| 3911 | @code\r | |
| 831d287a | 3912 | IA32_VMX_MISC_REGISTER Msr;\r |
| 04c980a6 | 3913 | \r |
| 831d287a | 3914 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r |
| 04c980a6 | 3915 | @endcode\r |
| 7de98828 | 3916 | @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r |
| 04c980a6 MK |
3917 | **/\r |
| 3918 | #define MSR_IA32_VMX_MISC 0x00000485\r | |
| 3919 | \r | |
| 831d287a MK |
3920 | /**\r |
| 3921 | MSR information returned for MSR index #IA32_VMX_MISC\r | |
| 3922 | **/\r | |
| 3923 | typedef union {\r | |
| 3924 | ///\r | |
| 3925 | /// Individual bit fields\r | |
| 3926 | ///\r | |
| 3927 | struct {\r | |
| 3928 | ///\r | |
| 3929 | /// [Bits 4:0] Reports a value X that specifies the relationship between the\r | |
| 3930 | /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r | |
| 3931 | /// Specifically, the VMX-preemption timer (if it is active) counts down by\r | |
| 3932 | /// 1 every time bit X in the TSC changes due to a TSC increment.\r | |
| 3933 | ///\r | |
| 3934 | UINT32 VmxTimerRatio:5;\r | |
| 3935 | ///\r | |
| 3936 | /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r | |
| 3937 | /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r | |
| 3938 | /// details. This bit is read as 1 on any logical processor that supports\r | |
| 3939 | /// the 1-setting of the "unrestricted guest" VM-execution control.\r | |
| 3940 | ///\r | |
| 3941 | UINT32 VmExitEferLma:1;\r | |
| 3942 | ///\r | |
| 3943 | /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r | |
| 3944 | ///\r | |
| 3945 | UINT32 HltActivityStateSupported:1;\r | |
| 3946 | ///\r | |
| 3947 | /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r | |
| 3948 | ///\r | |
| 3949 | UINT32 ShutdownActivityStateSupported:1;\r | |
| 3950 | ///\r | |
| 3951 | /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r | |
| 3952 | ///\r | |
| 3953 | UINT32 WaitForSipiActivityStateSupported:1;\r | |
| 3954 | UINT32 Reserved1:6;\r | |
| 3955 | ///\r | |
| 3956 | /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r | |
| 3957 | /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r | |
| 3958 | /// See Section 34.15.6.4.\r | |
| 3959 | ///\r | |
| 3960 | UINT32 SmBaseMsrSupported:1;\r | |
| 3961 | ///\r | |
| 3962 | /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r | |
| 3963 | /// processor. This number is a value between 0 and 256, inclusive (bit 24\r | |
| 3964 | /// is set if and only if bits 23:16 are clear).\r | |
| 3965 | ///\r | |
| 3966 | UINT32 NumberOfCr3TargetValues:9;\r | |
| 3967 | ///\r | |
| 3968 | /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r | |
| 3969 | /// number of MSRs that should appear in the VM-exit MSR-store list, the\r | |
| 3970 | /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r | |
| 3971 | /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r | |
| 3972 | /// recommended maximum number of MSRs to be included in each list. If the\r | |
| 3973 | /// limit is exceeded, undefined processor behavior may result (including a\r | |
| 3974 | /// machine check during the VMX transition).\r | |
| 3975 | ///\r | |
| 3976 | UINT32 MsrStoreListMaximum:3;\r | |
| 3977 | ///\r | |
| 3978 | /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r | |
| 3979 | /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r | |
| 3980 | /// (see Section 34.14.4).\r | |
| 3981 | ///\r | |
| 3982 | UINT32 BlockSmiSupported:1;\r | |
| 3983 | ///\r | |
| 3984 | /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r | |
| 3985 | /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r | |
| 3986 | /// information fields.\r | |
| 3987 | ///\r | |
| 3988 | UINT32 VmWriteSupported:1;\r | |
| 3989 | UINT32 Reserved2:2;\r | |
| 3990 | ///\r | |
| 3991 | /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r | |
| 3992 | /// processor.\r | |
| 3993 | ///\r | |
| 3994 | UINT32 MsegRevisionIdentifier:32;\r | |
| 3995 | } Bits;\r | |
| 3996 | ///\r | |
| 3997 | /// All bit fields as a 64-bit value\r | |
| 3998 | ///\r | |
| 3999 | UINT64 Uint64;\r | |
| 4000 | } IA32_VMX_MISC_REGISTER;\r | |
| 4001 | \r | |
| 04c980a6 MK |
4002 | \r |
| 4003 | /**\r | |
| 4004 | Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r | |
| 4005 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4006 | \r | |
| 4007 | @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r | |
| 4008 | @param EAX Lower 32-bits of MSR value.\r | |
| 4009 | @param EDX Upper 32-bits of MSR value.\r | |
| 4010 | \r | |
| 4011 | <b>Example usage</b>\r | |
| 4012 | @code\r | |
| 4013 | UINT64 Msr;\r | |
| 4014 | \r | |
| 4015 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r | |
| 4016 | @endcode\r | |
| 7de98828 | 4017 | @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r |
| 04c980a6 MK |
4018 | **/\r |
| 4019 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r | |
| 4020 | \r | |
| 4021 | \r | |
| 4022 | /**\r | |
| 4023 | Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r | |
| 4024 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4025 | \r | |
| 4026 | @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r | |
| 4027 | @param EAX Lower 32-bits of MSR value.\r | |
| 4028 | @param EDX Upper 32-bits of MSR value.\r | |
| 4029 | \r | |
| 4030 | <b>Example usage</b>\r | |
| 4031 | @code\r | |
| 4032 | UINT64 Msr;\r | |
| 4033 | \r | |
| 4034 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r | |
| 4035 | @endcode\r | |
| 7de98828 | 4036 | @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r |
| 04c980a6 MK |
4037 | **/\r |
| 4038 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r | |
| 4039 | \r | |
| 4040 | \r | |
| 4041 | /**\r | |
| 4042 | Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r | |
| 4043 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4044 | \r | |
| 4045 | @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r | |
| 4046 | @param EAX Lower 32-bits of MSR value.\r | |
| 4047 | @param EDX Upper 32-bits of MSR value.\r | |
| 4048 | \r | |
| 4049 | <b>Example usage</b>\r | |
| 4050 | @code\r | |
| 4051 | UINT64 Msr;\r | |
| 4052 | \r | |
| 4053 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r | |
| 4054 | @endcode\r | |
| 7de98828 | 4055 | @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r |
| 04c980a6 MK |
4056 | **/\r |
| 4057 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r | |
| 4058 | \r | |
| 4059 | \r | |
| 4060 | /**\r | |
| 4061 | Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r | |
| 4062 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4063 | \r | |
| 4064 | @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r | |
| 4065 | @param EAX Lower 32-bits of MSR value.\r | |
| 4066 | @param EDX Upper 32-bits of MSR value.\r | |
| 4067 | \r | |
| 4068 | <b>Example usage</b>\r | |
| 4069 | @code\r | |
| 4070 | UINT64 Msr;\r | |
| 4071 | \r | |
| 4072 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r | |
| 4073 | @endcode\r | |
| 7de98828 | 4074 | @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r |
| 04c980a6 MK |
4075 | **/\r |
| 4076 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r | |
| 4077 | \r | |
| 4078 | \r | |
| 4079 | /**\r | |
| 4080 | Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r | |
| 4081 | A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r | |
| 4082 | \r | |
| 4083 | @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r | |
| 4084 | @param EAX Lower 32-bits of MSR value.\r | |
| 4085 | @param EDX Upper 32-bits of MSR value.\r | |
| 4086 | \r | |
| 4087 | <b>Example usage</b>\r | |
| 4088 | @code\r | |
| 4089 | UINT64 Msr;\r | |
| 4090 | \r | |
| 4091 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r | |
| 4092 | @endcode\r | |
| 7de98828 | 4093 | @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r |
| 04c980a6 MK |
4094 | **/\r |
| 4095 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r | |
| 4096 | \r | |
| 4097 | \r | |
| 4098 | /**\r | |
| 4099 | Capability Reporting Register of Secondary Processor-based VM-execution\r | |
| 4100 | Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r | |
| 4101 | Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r | |
| 4102 | \r | |
| 4103 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r | |
| 4104 | @param EAX Lower 32-bits of MSR value.\r | |
| 4105 | @param EDX Upper 32-bits of MSR value.\r | |
| 4106 | \r | |
| 4107 | <b>Example usage</b>\r | |
| 4108 | @code\r | |
| 4109 | UINT64 Msr;\r | |
| 4110 | \r | |
| 4111 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r | |
| 4112 | @endcode\r | |
| 7de98828 | 4113 | @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r |
| 04c980a6 MK |
4114 | **/\r |
| 4115 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r | |
| 4116 | \r | |
| 4117 | \r | |
| 4118 | /**\r | |
| 4119 | Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r | |
| 4120 | "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r | |
| 4121 | TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r | |
| 4122 | \r | |
| 4123 | @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r | |
| 4124 | @param EAX Lower 32-bits of MSR value.\r | |
| 4125 | @param EDX Upper 32-bits of MSR value.\r | |
| 4126 | \r | |
| 4127 | <b>Example usage</b>\r | |
| 4128 | @code\r | |
| 4129 | UINT64 Msr;\r | |
| 4130 | \r | |
| 4131 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r | |
| 4132 | @endcode\r | |
| 7de98828 | 4133 | @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r |
| 04c980a6 MK |
4134 | **/\r |
| 4135 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r | |
| 4136 | \r | |
| 4137 | \r | |
| 4138 | /**\r | |
| 4139 | Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r | |
| 4140 | See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r | |
| 4141 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4142 | \r | |
| 4143 | @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r | |
| 4144 | @param EAX Lower 32-bits of MSR value.\r | |
| 4145 | @param EDX Upper 32-bits of MSR value.\r | |
| 4146 | \r | |
| 4147 | <b>Example usage</b>\r | |
| 4148 | @code\r | |
| 4149 | UINT64 Msr;\r | |
| 4150 | \r | |
| 4151 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r | |
| 4152 | @endcode\r | |
| 7de98828 | 4153 | @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r |
| 04c980a6 MK |
4154 | **/\r |
| 4155 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r | |
| 4156 | \r | |
| 4157 | \r | |
| 4158 | /**\r | |
| 4159 | Capability Reporting Register of Primary Processor-based VM-execution Flex\r | |
| 4160 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
| 4161 | Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4162 | \r | |
| 4163 | @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r | |
| 4164 | @param EAX Lower 32-bits of MSR value.\r | |
| 4165 | @param EDX Upper 32-bits of MSR value.\r | |
| 4166 | \r | |
| 4167 | <b>Example usage</b>\r | |
| 4168 | @code\r | |
| 4169 | UINT64 Msr;\r | |
| 4170 | \r | |
| 4171 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r | |
| 4172 | @endcode\r | |
| 7de98828 | 4173 | @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r |
| 04c980a6 MK |
4174 | **/\r |
| 4175 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r | |
| 4176 | \r | |
| 4177 | \r | |
| 4178 | /**\r | |
| 4179 | Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r | |
| 4180 | A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4181 | \r | |
| 4182 | @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r | |
| 4183 | @param EAX Lower 32-bits of MSR value.\r | |
| 4184 | @param EDX Upper 32-bits of MSR value.\r | |
| 4185 | \r | |
| 4186 | <b>Example usage</b>\r | |
| 4187 | @code\r | |
| 4188 | UINT64 Msr;\r | |
| 4189 | \r | |
| 4190 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r | |
| 4191 | @endcode\r | |
| 7de98828 | 4192 | @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r |
| 04c980a6 MK |
4193 | **/\r |
| 4194 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r | |
| 4195 | \r | |
| 4196 | \r | |
| 4197 | /**\r | |
| 4198 | Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r | |
| 4199 | A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4200 | \r | |
| 4201 | @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r | |
| 4202 | @param EAX Lower 32-bits of MSR value.\r | |
| 4203 | @param EDX Upper 32-bits of MSR value.\r | |
| 4204 | \r | |
| 4205 | <b>Example usage</b>\r | |
| 4206 | @code\r | |
| 4207 | UINT64 Msr;\r | |
| 4208 | \r | |
| 4209 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r | |
| 4210 | @endcode\r | |
| 7de98828 | 4211 | @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r |
| 04c980a6 MK |
4212 | **/\r |
| 4213 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r | |
| 4214 | \r | |
| 4215 | \r | |
| 4216 | /**\r | |
| 4217 | Capability Reporting Register of VMfunction Controls (R/O). If(\r | |
| 4218 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4219 | \r | |
| 4220 | @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)\r | |
| 4221 | @param EAX Lower 32-bits of MSR value.\r | |
| 4222 | @param EDX Upper 32-bits of MSR value.\r | |
| 4223 | \r | |
| 4224 | <b>Example usage</b>\r | |
| 4225 | @code\r | |
| 4226 | UINT64 Msr;\r | |
| 4227 | \r | |
| 4228 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r | |
| 4229 | @endcode\r | |
| 7de98828 | 4230 | @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r |
| 04c980a6 MK |
4231 | **/\r |
| 4232 | #define MSR_IA32_VMX_VMFUNC 0x00000491\r | |
| 4233 | \r | |
| 4234 | \r | |
| 4235 | /**\r | |
| 4236 | Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r | |
| 4237 | IA32_PERF_CAPABILITIES[ 13] = 1.\r | |
| 4238 | \r | |
| 4239 | @param ECX MSR_IA32_A_PMCn\r | |
| 4240 | @param EAX Lower 32-bits of MSR value.\r | |
| 4241 | @param EDX Upper 32-bits of MSR value.\r | |
| 4242 | \r | |
| 4243 | <b>Example usage</b>\r | |
| 4244 | @code\r | |
| 4245 | UINT64 Msr;\r | |
| 4246 | \r | |
| 4247 | Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r | |
| 4248 | AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r | |
| 4249 | @endcode\r | |
| 7de98828 JF |
4250 | @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r |
| 4251 | MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r | |
| 4252 | MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r | |
| 4253 | MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r | |
| 4254 | MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r | |
| 4255 | MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r | |
| 4256 | MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r | |
| 4257 | MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r | |
| 04c980a6 MK |
4258 | @{\r |
| 4259 | **/\r | |
| 4260 | #define MSR_IA32_A_PMC0 0x000004C1\r | |
| 4261 | #define MSR_IA32_A_PMC1 0x000004C2\r | |
| 4262 | #define MSR_IA32_A_PMC2 0x000004C3\r | |
| 4263 | #define MSR_IA32_A_PMC3 0x000004C4\r | |
| 4264 | #define MSR_IA32_A_PMC4 0x000004C5\r | |
| 4265 | #define MSR_IA32_A_PMC5 0x000004C6\r | |
| 4266 | #define MSR_IA32_A_PMC6 0x000004C7\r | |
| 4267 | #define MSR_IA32_A_PMC7 0x000004C8\r | |
| 4268 | /// @}\r | |
| 4269 | \r | |
| 4270 | \r | |
| 4271 | /**\r | |
| 4272 | (R/W). If IA32_MCG_CAP.LMCE_P =1.\r | |
| 4273 | \r | |
| 4274 | @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)\r | |
| 4275 | @param EAX Lower 32-bits of MSR value.\r | |
| 4276 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
| 4277 | @param EDX Upper 32-bits of MSR value.\r | |
| 4278 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
| 4279 | \r | |
| 4280 | <b>Example usage</b>\r | |
| 4281 | @code\r | |
| 4282 | MSR_IA32_MCG_EXT_CTL_REGISTER Msr;\r | |
| 4283 | \r | |
| 4284 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r | |
| 4285 | AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r | |
| 4286 | @endcode\r | |
| 7de98828 | 4287 | @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r |
| 04c980a6 MK |
4288 | **/\r |
| 4289 | #define MSR_IA32_MCG_EXT_CTL 0x000004D0\r | |
| 4290 | \r | |
| 4291 | /**\r | |
| 4292 | MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r | |
| 4293 | **/\r | |
| 4294 | typedef union {\r | |
| 4295 | ///\r | |
| 4296 | /// Individual bit fields\r | |
| 4297 | ///\r | |
| 4298 | struct {\r | |
| 4299 | ///\r | |
| 4300 | /// [Bit 0] LMCE_EN.\r | |
| 4301 | ///\r | |
| 4302 | UINT32 LMCE_EN:1;\r | |
| 4303 | UINT32 Reserved1:31;\r | |
| 4304 | UINT32 Reserved2:32;\r | |
| 4305 | } Bits;\r | |
| 4306 | ///\r | |
| 4307 | /// All bit fields as a 32-bit value\r | |
| 4308 | ///\r | |
| 4309 | UINT32 Uint32;\r | |
| 4310 | ///\r | |
| 4311 | /// All bit fields as a 64-bit value\r | |
| 4312 | ///\r | |
| 4313 | UINT64 Uint64;\r | |
| 4314 | } MSR_IA32_MCG_EXT_CTL_REGISTER;\r | |
| 4315 | \r | |
| 4316 | \r | |
| 4317 | /**\r | |
| 4318 | Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r | |
| 4319 | ECX=0H): EBX[2] = 1.\r | |
| 4320 | \r | |
| 4321 | @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)\r | |
| 4322 | @param EAX Lower 32-bits of MSR value.\r | |
| 4323 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
| 4324 | @param EDX Upper 32-bits of MSR value.\r | |
| 4325 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
| 4326 | \r | |
| 4327 | <b>Example usage</b>\r | |
| 4328 | @code\r | |
| 4329 | MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;\r | |
| 4330 | \r | |
| 4331 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r | |
| 4332 | @endcode\r | |
| 7de98828 | 4333 | @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r |
| 04c980a6 MK |
4334 | **/\r |
| 4335 | #define MSR_IA32_SGX_SVN_STATUS 0x00000500\r | |
| 4336 | \r | |
| 4337 | /**\r | |
| 4338 | MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r | |
| 4339 | **/\r | |
| 4340 | typedef union {\r | |
| 4341 | ///\r | |
| 4342 | /// Individual bit fields\r | |
| 4343 | ///\r | |
| 4344 | struct {\r | |
| 4345 | ///\r | |
| 4346 | /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated\r | |
| 4347 | /// Code Modules (ACMs)".\r | |
| 4348 | ///\r | |
| 4349 | UINT32 Lock:1;\r | |
| 4350 | UINT32 Reserved1:15;\r | |
| 4351 | ///\r | |
| 4352 | /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with\r | |
| 4353 | /// Authenticated Code Modules (ACMs)".\r | |
| 4354 | ///\r | |
| 4355 | UINT32 SGX_SVN_SINIT:8;\r | |
| 4356 | UINT32 Reserved2:8;\r | |
| 4357 | UINT32 Reserved3:32;\r | |
| 4358 | } Bits;\r | |
| 4359 | ///\r | |
| 4360 | /// All bit fields as a 32-bit value\r | |
| 4361 | ///\r | |
| 4362 | UINT32 Uint32;\r | |
| 4363 | ///\r | |
| 4364 | /// All bit fields as a 64-bit value\r | |
| 4365 | ///\r | |
| 4366 | UINT64 Uint64;\r | |
| 4367 | } MSR_IA32_SGX_SVN_STATUS_REGISTER;\r | |
| 4368 | \r | |
| 4369 | \r | |
| 4370 | /**\r | |
| 4371 | Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
| 4372 | && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r | |
| 4373 | ) ).\r | |
| 4374 | \r | |
| 4375 | @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r | |
| 4376 | @param EAX Lower 32-bits of MSR value.\r | |
| 4377 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
| 4378 | @param EDX Upper 32-bits of MSR value.\r | |
| 4379 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
| 4380 | \r | |
| 4381 | <b>Example usage</b>\r | |
| 4382 | @code\r | |
| 4383 | MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;\r | |
| 4384 | \r | |
| 4385 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r | |
| 4386 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r | |
| 4387 | @endcode\r | |
| 7de98828 | 4388 | @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r |
| 04c980a6 MK |
4389 | **/\r |
| 4390 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r | |
| 4391 | \r | |
| 4392 | /**\r | |
| 4393 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r | |
| 4394 | **/\r | |
| 4395 | typedef union {\r | |
| 4396 | ///\r | |
| 4397 | /// Individual bit fields\r | |
| 4398 | ///\r | |
| 4399 | struct {\r | |
| 4400 | UINT32 Reserved:7;\r | |
| 4401 | ///\r | |
| 4402 | /// [Bits 31:7] Base physical address.\r | |
| 4403 | ///\r | |
| 4404 | UINT32 Base:25;\r | |
| 4405 | ///\r | |
| 4406 | /// [Bits 63:32] Base physical address.\r | |
| 4407 | ///\r | |
| 4408 | UINT32 BaseHi:32;\r | |
| 4409 | } Bits;\r | |
| 4410 | ///\r | |
| 4411 | /// All bit fields as a 64-bit value\r | |
| 4412 | ///\r | |
| 4413 | UINT64 Uint64;\r | |
| 4414 | } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r | |
| 4415 | \r | |
| 4416 | \r | |
| 4417 | /**\r | |
| 4418 | Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r | |
| 4419 | ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r | |
| 4420 | (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r | |
| 4421 | \r | |
| 4422 | @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r | |
| 4423 | @param EAX Lower 32-bits of MSR value.\r | |
| 4424 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
| 4425 | @param EDX Upper 32-bits of MSR value.\r | |
| 4426 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
| 4427 | \r | |
| 4428 | <b>Example usage</b>\r | |
| 4429 | @code\r | |
| 4430 | MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;\r | |
| 4431 | \r | |
| 4432 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r | |
| 4433 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r | |
| 4434 | @endcode\r | |
| 7de98828 | 4435 | @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r |
| 04c980a6 MK |
4436 | **/\r |
| 4437 | #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r | |
| 4438 | \r | |
| 4439 | /**\r | |
| 4440 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r | |
| 4441 | **/\r | |
| 4442 | typedef union {\r | |
| 4443 | ///\r | |
| 4444 | /// Individual bit fields\r | |
| 4445 | ///\r | |
| 4446 | struct {\r | |
| 4447 | UINT32 Reserved:7;\r | |
| 4448 | ///\r | |
| 4449 | /// [Bits 31:7] MaskOrTableOffset.\r | |
| 4450 | ///\r | |
| 4451 | UINT32 MaskOrTableOffset:25;\r | |
| 4452 | ///\r | |
| 4453 | /// [Bits 63:32] Output Offset.\r | |
| 4454 | ///\r | |
| 4455 | UINT32 OutputOffset:32;\r | |
| 4456 | } Bits;\r | |
| 4457 | ///\r | |
| 4458 | /// All bit fields as a 64-bit value\r | |
| 4459 | ///\r | |
| 4460 | UINT64 Uint64;\r | |
| 4461 | } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r | |
| 4462 | \r | |
| 4463 | \r | |
| 4464 | /**\r | |
| 4465 | Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4466 | \r | |
| 4467 | @param ECX MSR_IA32_RTIT_CTL (0x00000570)\r | |
| 4468 | @param EAX Lower 32-bits of MSR value.\r | |
| 4469 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
| 4470 | @param EDX Upper 32-bits of MSR value.\r | |
| 4471 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
| 4472 | \r | |
| 4473 | <b>Example usage</b>\r | |
| 4474 | @code\r | |
| 4475 | MSR_IA32_RTIT_CTL_REGISTER Msr;\r | |
| 4476 | \r | |
| 4477 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r | |
| 4478 | AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r | |
| 4479 | @endcode\r | |
| 7de98828 | 4480 | @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r |
| 04c980a6 MK |
4481 | **/\r |
| 4482 | #define MSR_IA32_RTIT_CTL 0x00000570\r | |
| 4483 | \r | |
| 4484 | /**\r | |
| 4485 | MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r | |
| 4486 | **/\r | |
| 4487 | typedef union {\r | |
| 4488 | ///\r | |
| 4489 | /// Individual bit fields\r | |
| 4490 | ///\r | |
| 4491 | struct {\r | |
| 4492 | ///\r | |
| 4493 | /// [Bit 0] TraceEn.\r | |
| 4494 | ///\r | |
| 4495 | UINT32 TraceEn:1;\r | |
| 4496 | ///\r | |
| 4497 | /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4498 | ///\r | |
| 4499 | UINT32 CYCEn:1;\r | |
| 4500 | ///\r | |
| 4501 | /// [Bit 2] OS.\r | |
| 4502 | ///\r | |
| 4503 | UINT32 OS:1;\r | |
| 4504 | ///\r | |
| 4505 | /// [Bit 3] User.\r | |
| 4506 | ///\r | |
| 4507 | UINT32 User:1;\r | |
| 4508 | UINT32 Reserved1:2;\r | |
| 4509 | ///\r | |
| 4510 | /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r | |
| 4511 | ///\r | |
| 4512 | UINT32 FabricEn:1;\r | |
| 4513 | ///\r | |
| 4514 | /// [Bit 7] CR3 filter.\r | |
| 4515 | ///\r | |
| 4516 | UINT32 CR3:1;\r | |
| 4517 | ///\r | |
| 4518 | /// [Bit 8] ToPA.\r | |
| 4519 | ///\r | |
| 4520 | UINT32 ToPA:1;\r | |
| 4521 | ///\r | |
| 4522 | /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
| 4523 | ///\r | |
| 4524 | UINT32 MTCEn:1;\r | |
| 4525 | ///\r | |
| 4526 | /// [Bit 10] TSCEn.\r | |
| 4527 | ///\r | |
| 4528 | UINT32 TSCEn:1;\r | |
| 4529 | ///\r | |
| 4530 | /// [Bit 11] DisRETC.\r | |
| 4531 | ///\r | |
| 4532 | UINT32 DisRETC:1;\r | |
| 4533 | UINT32 Reserved2:1;\r | |
| 4534 | ///\r | |
| 4535 | /// [Bit 13] BranchEn.\r | |
| 4536 | ///\r | |
| 4537 | UINT32 BranchEn:1;\r | |
| 4538 | ///\r | |
| 4539 | /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
| 4540 | ///\r | |
| 4541 | UINT32 MTCFreq:4;\r | |
| 4542 | UINT32 Reserved3:1;\r | |
| 4543 | ///\r | |
| 4544 | /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4545 | ///\r | |
| 4546 | UINT32 CYCThresh:4;\r | |
| 4547 | UINT32 Reserved4:1;\r | |
| 4548 | ///\r | |
| 4549 | /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4550 | ///\r | |
| 4551 | UINT32 PSBFreq:4;\r | |
| 4552 | UINT32 Reserved5:4;\r | |
| 4553 | ///\r | |
| 4554 | /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r | |
| 4555 | ///\r | |
| 4556 | UINT32 ADDR0_CFG:4;\r | |
| 4557 | ///\r | |
| 4558 | /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r | |
| 4559 | ///\r | |
| 4560 | UINT32 ADDR1_CFG:4;\r | |
| 4561 | ///\r | |
| 4562 | /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r | |
| 4563 | ///\r | |
| 4564 | UINT32 ADDR2_CFG:4;\r | |
| 4565 | ///\r | |
| 4566 | /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r | |
| 4567 | ///\r | |
| 4568 | UINT32 ADDR3_CFG:4;\r | |
| 4569 | UINT32 Reserved6:16;\r | |
| 4570 | } Bits;\r | |
| 4571 | ///\r | |
| 4572 | /// All bit fields as a 64-bit value\r | |
| 4573 | ///\r | |
| 4574 | UINT64 Uint64;\r | |
| 4575 | } MSR_IA32_RTIT_CTL_REGISTER;\r | |
| 4576 | \r | |
| 4577 | \r | |
| 4578 | /**\r | |
| 4579 | Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4580 | \r | |
| 4581 | @param ECX MSR_IA32_RTIT_STATUS (0x00000571)\r | |
| 4582 | @param EAX Lower 32-bits of MSR value.\r | |
| 4583 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
| 4584 | @param EDX Upper 32-bits of MSR value.\r | |
| 4585 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
| 4586 | \r | |
| 4587 | <b>Example usage</b>\r | |
| 4588 | @code\r | |
| 4589 | MSR_IA32_RTIT_STATUS_REGISTER Msr;\r | |
| 4590 | \r | |
| 4591 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r | |
| 4592 | AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r | |
| 4593 | @endcode\r | |
| 7de98828 | 4594 | @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r |
| 04c980a6 MK |
4595 | **/\r |
| 4596 | #define MSR_IA32_RTIT_STATUS 0x00000571\r | |
| 4597 | \r | |
| 4598 | /**\r | |
| 4599 | MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r | |
| 4600 | **/\r | |
| 4601 | typedef union {\r | |
| 4602 | ///\r | |
| 4603 | /// Individual bit fields\r | |
| 4604 | ///\r | |
| 4605 | struct {\r | |
| 4606 | ///\r | |
| 4607 | /// [Bit 0] FilterEn, (writes ignored).\r | |
| 4608 | /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r | |
| 4609 | ///\r | |
| 4610 | UINT32 FilterEn:1;\r | |
| 4611 | ///\r | |
| 4612 | /// [Bit 1] ContexEn, (writes ignored).\r | |
| 4613 | ///\r | |
| 4614 | UINT32 ContexEn:1;\r | |
| 4615 | ///\r | |
| 4616 | /// [Bit 2] TriggerEn, (writes ignored).\r | |
| 4617 | ///\r | |
| 4618 | UINT32 TriggerEn:1;\r | |
| 4619 | UINT32 Reserved1:1;\r | |
| 4620 | ///\r | |
| 4621 | /// [Bit 4] Error.\r | |
| 4622 | ///\r | |
| 4623 | UINT32 Error:1;\r | |
| 4624 | ///\r | |
| 4625 | /// [Bit 5] Stopped.\r | |
| 4626 | ///\r | |
| 4627 | UINT32 Stopped:1;\r | |
| 4628 | UINT32 Reserved2:26;\r | |
| 4629 | ///\r | |
| 4630 | /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r | |
| 4631 | ///\r | |
| 4632 | UINT32 PacketByteCnt:17;\r | |
| 4633 | UINT32 Reserved3:15;\r | |
| 4634 | } Bits;\r | |
| 4635 | ///\r | |
| 4636 | /// All bit fields as a 64-bit value\r | |
| 4637 | ///\r | |
| 4638 | UINT64 Uint64;\r | |
| 4639 | } MSR_IA32_RTIT_STATUS_REGISTER;\r | |
| 4640 | \r | |
| 4641 | \r | |
| 4642 | /**\r | |
| 4643 | Trace Filter CR3 Match Register (R/W).\r | |
| 4644 | If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4645 | \r | |
| 4646 | @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r | |
| 4647 | @param EAX Lower 32-bits of MSR value.\r | |
| 4648 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
| 4649 | @param EDX Upper 32-bits of MSR value.\r | |
| 4650 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
| 4651 | \r | |
| 4652 | <b>Example usage</b>\r | |
| 4653 | @code\r | |
| 4654 | MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;\r | |
| 4655 | \r | |
| 4656 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r | |
| 4657 | AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r | |
| 4658 | @endcode\r | |
| 7de98828 | 4659 | @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r |
| 04c980a6 MK |
4660 | **/\r |
| 4661 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r | |
| 4662 | \r | |
| 4663 | /**\r | |
| 4664 | MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r | |
| 4665 | **/\r | |
| 4666 | typedef union {\r | |
| 4667 | ///\r | |
| 4668 | /// Individual bit fields\r | |
| 4669 | ///\r | |
| 4670 | struct {\r | |
| 4671 | UINT32 Reserved:5;\r | |
| 4672 | ///\r | |
| 4673 | /// [Bits 31:5] CR3[63:5] value to match.\r | |
| 4674 | ///\r | |
| 4675 | UINT32 Cr3:27;\r | |
| 4676 | ///\r | |
| 4677 | /// [Bits 63:32] CR3[63:5] value to match.\r | |
| 4678 | ///\r | |
| 4679 | UINT32 Cr3Hi:32;\r | |
| 4680 | } Bits;\r | |
| 4681 | ///\r | |
| 4682 | /// All bit fields as a 64-bit value\r | |
| 4683 | ///\r | |
| 4684 | UINT64 Uint64;\r | |
| 4685 | } MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r | |
| 4686 | \r | |
| 4687 | \r | |
| 4688 | /**\r | |
| 4689 | Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
| 4690 | \r | |
| 4691 | @param ECX MSR_IA32_RTIT_ADDRn_A\r | |
| 4692 | @param EAX Lower 32-bits of MSR value.\r | |
| 4693 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4694 | @param EDX Upper 32-bits of MSR value.\r | |
| 4695 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4696 | \r | |
| 4697 | <b>Example usage</b>\r | |
| 4698 | @code\r | |
| 4699 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
| 4700 | \r | |
| 4701 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r | |
| 4702 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r | |
| 4703 | @endcode\r | |
| 7de98828 JF |
4704 | @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r |
| 4705 | MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r | |
| 4706 | MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r | |
| 4707 | MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r | |
| 04c980a6 MK |
4708 | @{\r |
| 4709 | **/\r | |
| 4710 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580\r | |
| 4711 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582\r | |
| 4712 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584\r | |
| 4713 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586\r | |
| 4714 | /// @}\r | |
| 4715 | \r | |
| 4716 | \r | |
| 4717 | /**\r | |
| 4718 | Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
| 4719 | \r | |
| 4720 | @param ECX MSR_IA32_RTIT_ADDRn_B\r | |
| 4721 | @param EAX Lower 32-bits of MSR value.\r | |
| 4722 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4723 | @param EDX Upper 32-bits of MSR value.\r | |
| 4724 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4725 | \r | |
| 4726 | <b>Example usage</b>\r | |
| 4727 | @code\r | |
| 4728 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
| 4729 | \r | |
| 4730 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r | |
| 4731 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r | |
| 4732 | @endcode\r | |
| 7de98828 JF |
4733 | @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r |
| 4734 | MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r | |
| 4735 | MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r | |
| 4736 | MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r | |
| 04c980a6 MK |
4737 | @{\r |
| 4738 | **/\r | |
| 4739 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581\r | |
| 4740 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583\r | |
| 4741 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585\r | |
| 4742 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587\r | |
| 4743 | /// @}\r | |
| 4744 | \r | |
| 4745 | \r | |
| 4746 | /**\r | |
| 4747 | MSR information returned for MSR indexes\r | |
| 4748 | #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r | |
| 4749 | #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r | |
| 4750 | **/\r | |
| 4751 | typedef union {\r | |
| 4752 | ///\r | |
| 4753 | /// Individual bit fields\r | |
| 4754 | ///\r | |
| 4755 | struct {\r | |
| 4756 | ///\r | |
| 4757 | /// [Bits 31:0] Virtual Address.\r | |
| 4758 | ///\r | |
| 4759 | UINT32 VirtualAddress:32;\r | |
| 4760 | ///\r | |
| 4761 | /// [Bits 47:32] Virtual Address.\r | |
| 4762 | ///\r | |
| 4763 | UINT32 VirtualAddressHi:16;\r | |
| 4764 | ///\r | |
| 4765 | /// [Bits 63:48] SignExt_VA.\r | |
| 4766 | ///\r | |
| 4767 | UINT32 SignExt_VA:16;\r | |
| 4768 | } Bits;\r | |
| 4769 | ///\r | |
| 4770 | /// All bit fields as a 64-bit value\r | |
| 4771 | ///\r | |
| 4772 | UINT64 Uint64;\r | |
| 4773 | } MSR_IA32_RTIT_ADDR_REGISTER;\r | |
| 4774 | \r | |
| 4775 | \r | |
| 4776 | /**\r | |
| 4777 | DS Save Area (R/W) Points to the linear address of the first byte of the DS\r | |
| 4778 | buffer management area, which is used to manage the BTS and PEBS buffers.\r | |
| 4779 | See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r | |
| 4780 | = 1.\r | |
| 4781 | \r | |
| 4782 | [Bits 31..0] The linear address of the first byte of the DS buffer\r | |
| 4783 | management area, if not in IA-32e mode.\r | |
| 4784 | \r | |
| 4785 | [Bits 63..0] The linear address of the first byte of the DS buffer\r | |
| 4786 | management area, if IA-32e mode is active.\r | |
| 4787 | \r | |
| 4788 | @param ECX MSR_IA32_DS_AREA (0x00000600)\r | |
| 4789 | @param EAX Lower 32-bits of MSR value.\r | |
| 4790 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
| 4791 | @param EDX Upper 32-bits of MSR value.\r | |
| 4792 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
| 4793 | \r | |
| 4794 | <b>Example usage</b>\r | |
| 4795 | @code\r | |
| 4796 | UINT64 Msr;\r | |
| 4797 | \r | |
| 4798 | Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r | |
| 4799 | AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r | |
| 4800 | @endcode\r | |
| 7de98828 | 4801 | @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r |
| 04c980a6 MK |
4802 | **/\r |
| 4803 | #define MSR_IA32_DS_AREA 0x00000600\r | |
| 4804 | \r | |
| 4805 | \r | |
| 4806 | /**\r | |
| 4807 | TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r | |
| 4808 | 1.\r | |
| 4809 | \r | |
| 4810 | @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)\r | |
| 4811 | @param EAX Lower 32-bits of MSR value.\r | |
| 4812 | @param EDX Upper 32-bits of MSR value.\r | |
| 4813 | \r | |
| 4814 | <b>Example usage</b>\r | |
| 4815 | @code\r | |
| 4816 | UINT64 Msr;\r | |
| 4817 | \r | |
| 4818 | Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r | |
| 4819 | AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r | |
| 4820 | @endcode\r | |
| 7de98828 | 4821 | @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r |
| 04c980a6 MK |
4822 | **/\r |
| 4823 | #define MSR_IA32_TSC_DEADLINE 0x000006E0\r | |
| 4824 | \r | |
| 4825 | \r | |
| 4826 | /**\r | |
| 4827 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r | |
| 4828 | \r | |
| 4829 | @param ECX MSR_IA32_PM_ENABLE (0x00000770)\r | |
| 4830 | @param EAX Lower 32-bits of MSR value.\r | |
| 4831 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
| 4832 | @param EDX Upper 32-bits of MSR value.\r | |
| 4833 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
| 4834 | \r | |
| 4835 | <b>Example usage</b>\r | |
| 4836 | @code\r | |
| 4837 | MSR_IA32_PM_ENABLE_REGISTER Msr;\r | |
| 4838 | \r | |
| 4839 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r | |
| 4840 | AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r | |
| 4841 | @endcode\r | |
| 7de98828 | 4842 | @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r |
| 04c980a6 MK |
4843 | **/\r |
| 4844 | #define MSR_IA32_PM_ENABLE 0x00000770\r | |
| 4845 | \r | |
| 4846 | /**\r | |
| 4847 | MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r | |
| 4848 | **/\r | |
| 4849 | typedef union {\r | |
| 4850 | ///\r | |
| 4851 | /// Individual bit fields\r | |
| 4852 | ///\r | |
| 4853 | struct {\r | |
| 4854 | ///\r | |
| 4855 | /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r | |
| 4856 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 4857 | ///\r | |
| 4858 | UINT32 HWP_ENABLE:1;\r | |
| 4859 | UINT32 Reserved1:31;\r | |
| 4860 | UINT32 Reserved2:32;\r | |
| 4861 | } Bits;\r | |
| 4862 | ///\r | |
| 4863 | /// All bit fields as a 32-bit value\r | |
| 4864 | ///\r | |
| 4865 | UINT32 Uint32;\r | |
| 4866 | ///\r | |
| 4867 | /// All bit fields as a 64-bit value\r | |
| 4868 | ///\r | |
| 4869 | UINT64 Uint64;\r | |
| 4870 | } MSR_IA32_PM_ENABLE_REGISTER;\r | |
| 4871 | \r | |
| 4872 | \r | |
| 4873 | /**\r | |
| 4874 | HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r | |
| 4875 | \r | |
| 4876 | @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)\r | |
| 4877 | @param EAX Lower 32-bits of MSR value.\r | |
| 4878 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
| 4879 | @param EDX Upper 32-bits of MSR value.\r | |
| 4880 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
| 4881 | \r | |
| 4882 | <b>Example usage</b>\r | |
| 4883 | @code\r | |
| 4884 | MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;\r | |
| 4885 | \r | |
| 4886 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r | |
| 4887 | @endcode\r | |
| 7de98828 | 4888 | @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r |
| 04c980a6 MK |
4889 | **/\r |
| 4890 | #define MSR_IA32_HWP_CAPABILITIES 0x00000771\r | |
| 4891 | \r | |
| 4892 | /**\r | |
| 4893 | MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r | |
| 4894 | **/\r | |
| 4895 | typedef union {\r | |
| 4896 | ///\r | |
| 4897 | /// Individual bit fields\r | |
| 4898 | ///\r | |
| 4899 | struct {\r | |
| 4900 | ///\r | |
| 4901 | /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r | |
| 4902 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4903 | ///\r | |
| 4904 | UINT32 Highest_Performance:8;\r | |
| 4905 | ///\r | |
| 4906 | /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r | |
| 4907 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4908 | ///\r | |
| 4909 | UINT32 Guaranteed_Performance:8;\r | |
| 4910 | ///\r | |
| 4911 | /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r | |
| 4912 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4913 | ///\r | |
| 4914 | UINT32 Most_Efficient_Performance:8;\r | |
| 4915 | ///\r | |
| 4916 | /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r | |
| 4917 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4918 | ///\r | |
| 4919 | UINT32 Lowest_Performance:8;\r | |
| 4920 | UINT32 Reserved:32;\r | |
| 4921 | } Bits;\r | |
| 4922 | ///\r | |
| 4923 | /// All bit fields as a 32-bit value\r | |
| 4924 | ///\r | |
| 4925 | UINT32 Uint32;\r | |
| 4926 | ///\r | |
| 4927 | /// All bit fields as a 64-bit value\r | |
| 4928 | ///\r | |
| 4929 | UINT64 Uint64;\r | |
| 4930 | } MSR_IA32_HWP_CAPABILITIES_REGISTER;\r | |
| 4931 | \r | |
| 4932 | \r | |
| 4933 | /**\r | |
| 4934 | Power Management Control Hints for All Logical Processors in a Package\r | |
| 4935 | (R/W). If CPUID.06H:EAX.[11] = 1.\r | |
| 4936 | \r | |
| 4937 | @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r | |
| 4938 | @param EAX Lower 32-bits of MSR value.\r | |
| 4939 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
| 4940 | @param EDX Upper 32-bits of MSR value.\r | |
| 4941 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
| 4942 | \r | |
| 4943 | <b>Example usage</b>\r | |
| 4944 | @code\r | |
| 4945 | MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;\r | |
| 4946 | \r | |
| 4947 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r | |
| 4948 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r | |
| 4949 | @endcode\r | |
| 7de98828 | 4950 | @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r |
| 04c980a6 MK |
4951 | **/\r |
| 4952 | #define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r | |
| 4953 | \r | |
| 4954 | /**\r | |
| 4955 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r | |
| 4956 | **/\r | |
| 4957 | typedef union {\r | |
| 4958 | ///\r | |
| 4959 | /// Individual bit fields\r | |
| 4960 | ///\r | |
| 4961 | struct {\r | |
| 4962 | ///\r | |
| 4963 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 4964 | /// CPUID.06H:EAX.[11] = 1.\r | |
| 4965 | ///\r | |
| 4966 | UINT32 Minimum_Performance:8;\r | |
| 4967 | ///\r | |
| 4968 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 4969 | /// CPUID.06H:EAX.[11] = 1.\r | |
| 4970 | ///\r | |
| 4971 | UINT32 Maximum_Performance:8;\r | |
| 4972 | ///\r | |
| 4973 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
| 4974 | /// If CPUID.06H:EAX.[11] = 1.\r | |
| 4975 | ///\r | |
| 4976 | UINT32 Desired_Performance:8;\r | |
| 4977 | ///\r | |
| 4978 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
| 4979 | /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
| 4980 | ///\r | |
| 4981 | UINT32 Energy_Performance_Preference:8;\r | |
| 4982 | ///\r | |
| 4983 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
| 4984 | /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
| 4985 | ///\r | |
| 4986 | UINT32 Activity_Window:10;\r | |
| 4987 | UINT32 Reserved:22;\r | |
| 4988 | } Bits;\r | |
| 4989 | ///\r | |
| 4990 | /// All bit fields as a 64-bit value\r | |
| 4991 | ///\r | |
| 4992 | UINT64 Uint64;\r | |
| 4993 | } MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r | |
| 4994 | \r | |
| 4995 | \r | |
| 4996 | /**\r | |
| 4997 | Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r | |
| 4998 | \r | |
| 4999 | @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)\r | |
| 5000 | @param EAX Lower 32-bits of MSR value.\r | |
| 5001 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
| 5002 | @param EDX Upper 32-bits of MSR value.\r | |
| 5003 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
| 5004 | \r | |
| 5005 | <b>Example usage</b>\r | |
| 5006 | @code\r | |
| 5007 | MSR_IA32_HWP_INTERRUPT_REGISTER Msr;\r | |
| 5008 | \r | |
| 5009 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r | |
| 5010 | AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r | |
| 5011 | @endcode\r | |
| 7de98828 | 5012 | @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r |
| 04c980a6 MK |
5013 | **/\r |
| 5014 | #define MSR_IA32_HWP_INTERRUPT 0x00000773\r | |
| 5015 | \r | |
| 5016 | /**\r | |
| 5017 | MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r | |
| 5018 | **/\r | |
| 5019 | typedef union {\r | |
| 5020 | ///\r | |
| 5021 | /// Individual bit fields\r | |
| 5022 | ///\r | |
| 5023 | struct {\r | |
| 5024 | ///\r | |
| 5025 | /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r | |
| 5026 | /// Notifications". If CPUID.06H:EAX.[8] = 1.\r | |
| 5027 | ///\r | |
| 5028 | UINT32 EN_Guaranteed_Performance_Change:1;\r | |
| 5029 | ///\r | |
| 5030 | /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r | |
| 5031 | /// If CPUID.06H:EAX.[8] = 1.\r | |
| 5032 | ///\r | |
| 5033 | UINT32 EN_Excursion_Minimum:1;\r | |
| 5034 | UINT32 Reserved1:30;\r | |
| 5035 | UINT32 Reserved2:32;\r | |
| 5036 | } Bits;\r | |
| 5037 | ///\r | |
| 5038 | /// All bit fields as a 32-bit value\r | |
| 5039 | ///\r | |
| 5040 | UINT32 Uint32;\r | |
| 5041 | ///\r | |
| 5042 | /// All bit fields as a 64-bit value\r | |
| 5043 | ///\r | |
| 5044 | UINT64 Uint64;\r | |
| 5045 | } MSR_IA32_HWP_INTERRUPT_REGISTER;\r | |
| 5046 | \r | |
| 5047 | \r | |
| 5048 | /**\r | |
| 5049 | Power Management Control Hints to a Logical Processor (R/W). If\r | |
| 5050 | CPUID.06H:EAX.[7] = 1.\r | |
| 5051 | \r | |
| 5052 | @param ECX MSR_IA32_HWP_REQUEST (0x00000774)\r | |
| 5053 | @param EAX Lower 32-bits of MSR value.\r | |
| 5054 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
| 5055 | @param EDX Upper 32-bits of MSR value.\r | |
| 5056 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
| 5057 | \r | |
| 5058 | <b>Example usage</b>\r | |
| 5059 | @code\r | |
| 5060 | MSR_IA32_HWP_REQUEST_REGISTER Msr;\r | |
| 5061 | \r | |
| 5062 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r | |
| 5063 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r | |
| 5064 | @endcode\r | |
| 7de98828 | 5065 | @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r |
| 04c980a6 MK |
5066 | **/\r |
| 5067 | #define MSR_IA32_HWP_REQUEST 0x00000774\r | |
| 5068 | \r | |
| 5069 | /**\r | |
| 5070 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r | |
| 5071 | **/\r | |
| 5072 | typedef union {\r | |
| 5073 | ///\r | |
| 5074 | /// Individual bit fields\r | |
| 5075 | ///\r | |
| 5076 | struct {\r | |
| 5077 | ///\r | |
| 5078 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 5079 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 5080 | ///\r | |
| 5081 | UINT32 Minimum_Performance:8;\r | |
| 5082 | ///\r | |
| 5083 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 5084 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 5085 | ///\r | |
| 5086 | UINT32 Maximum_Performance:8;\r | |
| 5087 | ///\r | |
| 5088 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
| 5089 | /// If CPUID.06H:EAX.[7] = 1.\r | |
| 5090 | ///\r | |
| 5091 | UINT32 Desired_Performance:8;\r | |
| 5092 | ///\r | |
| 5093 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
| 5094 | /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
| 5095 | ///\r | |
| 5096 | UINT32 Energy_Performance_Preference:8;\r | |
| 5097 | ///\r | |
| 5098 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
| 5099 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
| 5100 | ///\r | |
| 5101 | UINT32 Activity_Window:10;\r | |
| 5102 | ///\r | |
| 5103 | /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r | |
| 5104 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r | |
| 5105 | ///\r | |
| 5106 | UINT32 Package_Control:1;\r | |
| 5107 | UINT32 Reserved:21;\r | |
| 5108 | } Bits;\r | |
| 5109 | ///\r | |
| 5110 | /// All bit fields as a 64-bit value\r | |
| 5111 | ///\r | |
| 5112 | UINT64 Uint64;\r | |
| 5113 | } MSR_IA32_HWP_REQUEST_REGISTER;\r | |
| 5114 | \r | |
| 5115 | \r | |
| 5116 | /**\r | |
| 5117 | Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r | |
| 5118 | CPUID.06H:EAX.[7] = 1.\r | |
| 5119 | \r | |
| 5120 | @param ECX MSR_IA32_HWP_STATUS (0x00000777)\r | |
| 5121 | @param EAX Lower 32-bits of MSR value.\r | |
| 5122 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
| 5123 | @param EDX Upper 32-bits of MSR value.\r | |
| 5124 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
| 5125 | \r | |
| 5126 | <b>Example usage</b>\r | |
| 5127 | @code\r | |
| 5128 | MSR_IA32_HWP_STATUS_REGISTER Msr;\r | |
| 5129 | \r | |
| 5130 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r | |
| 5131 | AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r | |
| 5132 | @endcode\r | |
| 7de98828 | 5133 | @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r |
| 04c980a6 MK |
5134 | **/\r |
| 5135 | #define MSR_IA32_HWP_STATUS 0x00000777\r | |
| 5136 | \r | |
| 5137 | /**\r | |
| 5138 | MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r | |
| 5139 | **/\r | |
| 5140 | typedef union {\r | |
| 5141 | ///\r | |
| 5142 | /// Individual bit fields\r | |
| 5143 | ///\r | |
| 5144 | struct {\r | |
| 5145 | ///\r | |
| 5146 | /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r | |
| 5147 | /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
| 5148 | ///\r | |
| 5149 | UINT32 Guaranteed_Performance_Change:1;\r | |
| 5150 | UINT32 Reserved1:1;\r | |
| 5151 | ///\r | |
| 5152 | /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r | |
| 5153 | /// Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
| 5154 | ///\r | |
| 5155 | UINT32 Excursion_To_Minimum:1;\r | |
| 5156 | UINT32 Reserved2:29;\r | |
| 5157 | UINT32 Reserved3:32;\r | |
| 5158 | } Bits;\r | |
| 5159 | ///\r | |
| 5160 | /// All bit fields as a 32-bit value\r | |
| 5161 | ///\r | |
| 5162 | UINT32 Uint32;\r | |
| 5163 | ///\r | |
| 5164 | /// All bit fields as a 64-bit value\r | |
| 5165 | ///\r | |
| 5166 | UINT64 Uint64;\r | |
| 5167 | } MSR_IA32_HWP_STATUS_REGISTER;\r | |
| 5168 | \r | |
| 5169 | \r | |
| 5170 | /**\r | |
| 5171 | x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r | |
| 5172 | && IA32_APIC_BASE.[10] = 1.\r | |
| 5173 | \r | |
| 5174 | @param ECX MSR_IA32_X2APIC_APICID (0x00000802)\r | |
| 5175 | @param EAX Lower 32-bits of MSR value.\r | |
| 5176 | @param EDX Upper 32-bits of MSR value.\r | |
| 5177 | \r | |
| 5178 | <b>Example usage</b>\r | |
| 5179 | @code\r | |
| 5180 | UINT64 Msr;\r | |
| 5181 | \r | |
| 5182 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r | |
| 5183 | @endcode\r | |
| 7de98828 | 5184 | @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r |
| 04c980a6 MK |
5185 | **/\r |
| 5186 | #define MSR_IA32_X2APIC_APICID 0x00000802\r | |
| 5187 | \r | |
| 5188 | \r | |
| 5189 | /**\r | |
| 5190 | x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5191 | IA32_APIC_BASE.[10] = 1.\r | |
| 5192 | \r | |
| 5193 | @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)\r | |
| 5194 | @param EAX Lower 32-bits of MSR value.\r | |
| 5195 | @param EDX Upper 32-bits of MSR value.\r | |
| 5196 | \r | |
| 5197 | <b>Example usage</b>\r | |
| 5198 | @code\r | |
| 5199 | UINT64 Msr;\r | |
| 5200 | \r | |
| 5201 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r | |
| 5202 | @endcode\r | |
| 7de98828 | 5203 | @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r |
| 04c980a6 MK |
5204 | **/\r |
| 5205 | #define MSR_IA32_X2APIC_VERSION 0x00000803\r | |
| 5206 | \r | |
| 5207 | \r | |
| 5208 | /**\r | |
| 5209 | x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5210 | IA32_APIC_BASE.[10] = 1.\r | |
| 5211 | \r | |
| 5212 | @param ECX MSR_IA32_X2APIC_TPR (0x00000808)\r | |
| 5213 | @param EAX Lower 32-bits of MSR value.\r | |
| 5214 | @param EDX Upper 32-bits of MSR value.\r | |
| 5215 | \r | |
| 5216 | <b>Example usage</b>\r | |
| 5217 | @code\r | |
| 5218 | UINT64 Msr;\r | |
| 5219 | \r | |
| 5220 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r | |
| 5221 | AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r | |
| 5222 | @endcode\r | |
| 7de98828 | 5223 | @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r |
| 04c980a6 MK |
5224 | **/\r |
| 5225 | #define MSR_IA32_X2APIC_TPR 0x00000808\r | |
| 5226 | \r | |
| 5227 | \r | |
| 5228 | /**\r | |
| 5229 | x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5230 | IA32_APIC_BASE.[10] = 1.\r | |
| 5231 | \r | |
| 5232 | @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)\r | |
| 5233 | @param EAX Lower 32-bits of MSR value.\r | |
| 5234 | @param EDX Upper 32-bits of MSR value.\r | |
| 5235 | \r | |
| 5236 | <b>Example usage</b>\r | |
| 5237 | @code\r | |
| 5238 | UINT64 Msr;\r | |
| 5239 | \r | |
| 5240 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r | |
| 5241 | @endcode\r | |
| 7de98828 | 5242 | @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r |
| 04c980a6 MK |
5243 | **/\r |
| 5244 | #define MSR_IA32_X2APIC_PPR 0x0000080A\r | |
| 5245 | \r | |
| 5246 | \r | |
| 5247 | /**\r | |
| 5248 | x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r | |
| 5249 | = 1.\r | |
| 5250 | \r | |
| 5251 | @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)\r | |
| 5252 | @param EAX Lower 32-bits of MSR value.\r | |
| 5253 | @param EDX Upper 32-bits of MSR value.\r | |
| 5254 | \r | |
| 5255 | <b>Example usage</b>\r | |
| 5256 | @code\r | |
| 5257 | UINT64 Msr;\r | |
| 5258 | \r | |
| 5259 | Msr = 0;\r | |
| 5260 | AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r | |
| 5261 | @endcode\r | |
| 7de98828 | 5262 | @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r |
| 04c980a6 MK |
5263 | **/\r |
| 5264 | #define MSR_IA32_X2APIC_EOI 0x0000080B\r | |
| 5265 | \r | |
| 5266 | \r | |
| 5267 | /**\r | |
| 5268 | x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5269 | IA32_APIC_BASE.[10] = 1.\r | |
| 5270 | \r | |
| 5271 | @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)\r | |
| 5272 | @param EAX Lower 32-bits of MSR value.\r | |
| 5273 | @param EDX Upper 32-bits of MSR value.\r | |
| 5274 | \r | |
| 5275 | <b>Example usage</b>\r | |
| 5276 | @code\r | |
| 5277 | UINT64 Msr;\r | |
| 5278 | \r | |
| 5279 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r | |
| 5280 | @endcode\r | |
| 7de98828 | 5281 | @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r |
| 04c980a6 MK |
5282 | **/\r |
| 5283 | #define MSR_IA32_X2APIC_LDR 0x0000080D\r | |
| 5284 | \r | |
| 5285 | \r | |
| 5286 | /**\r | |
| 5287 | x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r | |
| 5288 | && IA32_APIC_BASE.[10] = 1.\r | |
| 5289 | \r | |
| 5290 | @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)\r | |
| 5291 | @param EAX Lower 32-bits of MSR value.\r | |
| 5292 | @param EDX Upper 32-bits of MSR value.\r | |
| 5293 | \r | |
| 5294 | <b>Example usage</b>\r | |
| 5295 | @code\r | |
| 5296 | UINT64 Msr;\r | |
| 5297 | \r | |
| 5298 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r | |
| 5299 | AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r | |
| 5300 | @endcode\r | |
| 7de98828 | 5301 | @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r |
| 04c980a6 MK |
5302 | **/\r |
| 5303 | #define MSR_IA32_X2APIC_SIVR 0x0000080F\r | |
| 5304 | \r | |
| 5305 | \r | |
| 5306 | /**\r | |
| 5307 | x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r | |
| 5308 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5309 | \r | |
| 5310 | @param ECX MSR_IA32_X2APIC_ISRn\r | |
| 5311 | @param EAX Lower 32-bits of MSR value.\r | |
| 5312 | @param EDX Upper 32-bits of MSR value.\r | |
| 5313 | \r | |
| 5314 | <b>Example usage</b>\r | |
| 5315 | @code\r | |
| 5316 | UINT64 Msr;\r | |
| 5317 | \r | |
| 5318 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r | |
| 5319 | @endcode\r | |
| 7de98828 JF |
5320 | @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r |
| 5321 | MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r | |
| 5322 | MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r | |
| 5323 | MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r | |
| 5324 | MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r | |
| 5325 | MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r | |
| 5326 | MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r | |
| 5327 | MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r | |
| 04c980a6 MK |
5328 | @{\r |
| 5329 | **/\r | |
| 5330 | #define MSR_IA32_X2APIC_ISR0 0x00000810\r | |
| 5331 | #define MSR_IA32_X2APIC_ISR1 0x00000811\r | |
| 5332 | #define MSR_IA32_X2APIC_ISR2 0x00000812\r | |
| 5333 | #define MSR_IA32_X2APIC_ISR3 0x00000813\r | |
| 5334 | #define MSR_IA32_X2APIC_ISR4 0x00000814\r | |
| 5335 | #define MSR_IA32_X2APIC_ISR5 0x00000815\r | |
| 5336 | #define MSR_IA32_X2APIC_ISR6 0x00000816\r | |
| 5337 | #define MSR_IA32_X2APIC_ISR7 0x00000817\r | |
| 5338 | /// @}\r | |
| 5339 | \r | |
| 5340 | \r | |
| 5341 | /**\r | |
| 5342 | x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r | |
| 5343 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5344 | \r | |
| 5345 | @param ECX MSR_IA32_X2APIC_TMRn\r | |
| 5346 | @param EAX Lower 32-bits of MSR value.\r | |
| 5347 | @param EDX Upper 32-bits of MSR value.\r | |
| 5348 | \r | |
| 5349 | <b>Example usage</b>\r | |
| 5350 | @code\r | |
| 5351 | UINT64 Msr;\r | |
| 5352 | \r | |
| 5353 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r | |
| 5354 | @endcode\r | |
| 7de98828 JF |
5355 | @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r |
| 5356 | MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r | |
| 5357 | MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r | |
| 5358 | MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r | |
| 5359 | MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r | |
| 5360 | MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r | |
| 5361 | MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r | |
| 5362 | MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r | |
| 04c980a6 MK |
5363 | @{\r |
| 5364 | **/\r | |
| 5365 | #define MSR_IA32_X2APIC_TMR0 0x00000818\r | |
| 5366 | #define MSR_IA32_X2APIC_TMR1 0x00000819\r | |
| 5367 | #define MSR_IA32_X2APIC_TMR2 0x0000081A\r | |
| 5368 | #define MSR_IA32_X2APIC_TMR3 0x0000081B\r | |
| 5369 | #define MSR_IA32_X2APIC_TMR4 0x0000081C\r | |
| 5370 | #define MSR_IA32_X2APIC_TMR5 0x0000081D\r | |
| 5371 | #define MSR_IA32_X2APIC_TMR6 0x0000081E\r | |
| 5372 | #define MSR_IA32_X2APIC_TMR7 0x0000081F\r | |
| 5373 | /// @}\r | |
| 5374 | \r | |
| 5375 | \r | |
| 5376 | /**\r | |
| 5377 | x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r | |
| 5378 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5379 | \r | |
| 5380 | @param ECX MSR_IA32_X2APIC_IRRn\r | |
| 5381 | @param EAX Lower 32-bits of MSR value.\r | |
| 5382 | @param EDX Upper 32-bits of MSR value.\r | |
| 5383 | \r | |
| 5384 | <b>Example usage</b>\r | |
| 5385 | @code\r | |
| 5386 | UINT64 Msr;\r | |
| 5387 | \r | |
| 5388 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r | |
| 5389 | @endcode\r | |
| 7de98828 JF |
5390 | @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r |
| 5391 | MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r | |
| 5392 | MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r | |
| 5393 | MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r | |
| 5394 | MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r | |
| 5395 | MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r | |
| 5396 | MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r | |
| 5397 | MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r | |
| 04c980a6 MK |
5398 | @{\r |
| 5399 | **/\r | |
| 5400 | #define MSR_IA32_X2APIC_IRR0 0x00000820\r | |
| 5401 | #define MSR_IA32_X2APIC_IRR1 0x00000821\r | |
| 5402 | #define MSR_IA32_X2APIC_IRR2 0x00000822\r | |
| 5403 | #define MSR_IA32_X2APIC_IRR3 0x00000823\r | |
| 5404 | #define MSR_IA32_X2APIC_IRR4 0x00000824\r | |
| 5405 | #define MSR_IA32_X2APIC_IRR5 0x00000825\r | |
| 5406 | #define MSR_IA32_X2APIC_IRR6 0x00000826\r | |
| 5407 | #define MSR_IA32_X2APIC_IRR7 0x00000827\r | |
| 5408 | /// @}\r | |
| 5409 | \r | |
| 5410 | \r | |
| 5411 | /**\r | |
| 5412 | x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5413 | IA32_APIC_BASE.[10] = 1.\r | |
| 5414 | \r | |
| 5415 | @param ECX MSR_IA32_X2APIC_ESR (0x00000828)\r | |
| 5416 | @param EAX Lower 32-bits of MSR value.\r | |
| 5417 | @param EDX Upper 32-bits of MSR value.\r | |
| 5418 | \r | |
| 5419 | <b>Example usage</b>\r | |
| 5420 | @code\r | |
| 5421 | UINT64 Msr;\r | |
| 5422 | \r | |
| 5423 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r | |
| 5424 | AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r | |
| 5425 | @endcode\r | |
| 7de98828 | 5426 | @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r |
| 04c980a6 MK |
5427 | **/\r |
| 5428 | #define MSR_IA32_X2APIC_ESR 0x00000828\r | |
| 5429 | \r | |
| 5430 | \r | |
| 5431 | /**\r | |
| 5432 | x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r | |
| 5433 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5434 | \r | |
| 5435 | @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r | |
| 5436 | @param EAX Lower 32-bits of MSR value.\r | |
| 5437 | @param EDX Upper 32-bits of MSR value.\r | |
| 5438 | \r | |
| 5439 | <b>Example usage</b>\r | |
| 5440 | @code\r | |
| 5441 | UINT64 Msr;\r | |
| 5442 | \r | |
| 5443 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r | |
| 5444 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r | |
| 5445 | @endcode\r | |
| 7de98828 | 5446 | @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r |
| 04c980a6 MK |
5447 | **/\r |
| 5448 | #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r | |
| 5449 | \r | |
| 5450 | \r | |
| 5451 | /**\r | |
| 5452 | x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5453 | IA32_APIC_BASE.[10] = 1.\r | |
| 5454 | \r | |
| 5455 | @param ECX MSR_IA32_X2APIC_ICR (0x00000830)\r | |
| 5456 | @param EAX Lower 32-bits of MSR value.\r | |
| 5457 | @param EDX Upper 32-bits of MSR value.\r | |
| 5458 | \r | |
| 5459 | <b>Example usage</b>\r | |
| 5460 | @code\r | |
| 5461 | UINT64 Msr;\r | |
| 5462 | \r | |
| 5463 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r | |
| 5464 | AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r | |
| 5465 | @endcode\r | |
| 7de98828 | 5466 | @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r |
| 04c980a6 MK |
5467 | **/\r |
| 5468 | #define MSR_IA32_X2APIC_ICR 0x00000830\r | |
| 5469 | \r | |
| 5470 | \r | |
| 5471 | /**\r | |
| 5472 | x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5473 | IA32_APIC_BASE.[10] = 1.\r | |
| 5474 | \r | |
| 5475 | @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r | |
| 5476 | @param EAX Lower 32-bits of MSR value.\r | |
| 5477 | @param EDX Upper 32-bits of MSR value.\r | |
| 5478 | \r | |
| 5479 | <b>Example usage</b>\r | |
| 5480 | @code\r | |
| 5481 | UINT64 Msr;\r | |
| 5482 | \r | |
| 5483 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r | |
| 5484 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r | |
| 5485 | @endcode\r | |
| 7de98828 | 5486 | @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r |
| 04c980a6 MK |
5487 | **/\r |
| 5488 | #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r | |
| 5489 | \r | |
| 5490 | \r | |
| 5491 | /**\r | |
| 5492 | x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r | |
| 5493 | 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5494 | \r | |
| 5495 | @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r | |
| 5496 | @param EAX Lower 32-bits of MSR value.\r | |
| 5497 | @param EDX Upper 32-bits of MSR value.\r | |
| 5498 | \r | |
| 5499 | <b>Example usage</b>\r | |
| 5500 | @code\r | |
| 5501 | UINT64 Msr;\r | |
| 5502 | \r | |
| 5503 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r | |
| 5504 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r | |
| 5505 | @endcode\r | |
| 7de98828 | 5506 | @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r |
| 04c980a6 MK |
5507 | **/\r |
| 5508 | #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r | |
| 5509 | \r | |
| 5510 | \r | |
| 5511 | /**\r | |
| 5512 | x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r | |
| 5513 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5514 | \r | |
| 5515 | @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r | |
| 5516 | @param EAX Lower 32-bits of MSR value.\r | |
| 5517 | @param EDX Upper 32-bits of MSR value.\r | |
| 5518 | \r | |
| 5519 | <b>Example usage</b>\r | |
| 5520 | @code\r | |
| 5521 | UINT64 Msr;\r | |
| 5522 | \r | |
| 5523 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r | |
| 5524 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r | |
| 5525 | @endcode\r | |
| 7de98828 | 5526 | @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r |
| 04c980a6 MK |
5527 | **/\r |
| 5528 | #define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r | |
| 5529 | \r | |
| 5530 | \r | |
| 5531 | /**\r | |
| 5532 | x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5533 | IA32_APIC_BASE.[10] = 1.\r | |
| 5534 | \r | |
| 5535 | @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r | |
| 5536 | @param EAX Lower 32-bits of MSR value.\r | |
| 5537 | @param EDX Upper 32-bits of MSR value.\r | |
| 5538 | \r | |
| 5539 | <b>Example usage</b>\r | |
| 5540 | @code\r | |
| 5541 | UINT64 Msr;\r | |
| 5542 | \r | |
| 5543 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r | |
| 5544 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r | |
| 5545 | @endcode\r | |
| 7de98828 | 5546 | @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r |
| 04c980a6 MK |
5547 | **/\r |
| 5548 | #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r | |
| 5549 | \r | |
| 5550 | \r | |
| 5551 | /**\r | |
| 5552 | x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5553 | IA32_APIC_BASE.[10] = 1.\r | |
| 5554 | \r | |
| 5555 | @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r | |
| 5556 | @param EAX Lower 32-bits of MSR value.\r | |
| 5557 | @param EDX Upper 32-bits of MSR value.\r | |
| 5558 | \r | |
| 5559 | <b>Example usage</b>\r | |
| 5560 | @code\r | |
| 5561 | UINT64 Msr;\r | |
| 5562 | \r | |
| 5563 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r | |
| 5564 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r | |
| 5565 | @endcode\r | |
| 7de98828 | 5566 | @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r |
| 04c980a6 MK |
5567 | **/\r |
| 5568 | #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r | |
| 5569 | \r | |
| 5570 | \r | |
| 5571 | /**\r | |
| 5572 | x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5573 | IA32_APIC_BASE.[10] = 1.\r | |
| 5574 | \r | |
| 5575 | @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r | |
| 5576 | @param EAX Lower 32-bits of MSR value.\r | |
| 5577 | @param EDX Upper 32-bits of MSR value.\r | |
| 5578 | \r | |
| 5579 | <b>Example usage</b>\r | |
| 5580 | @code\r | |
| 5581 | UINT64 Msr;\r | |
| 5582 | \r | |
| 5583 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r | |
| 5584 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r | |
| 5585 | @endcode\r | |
| 7de98828 | 5586 | @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r |
| 04c980a6 MK |
5587 | **/\r |
| 5588 | #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r | |
| 5589 | \r | |
| 5590 | \r | |
| 5591 | /**\r | |
| 5592 | x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5593 | IA32_APIC_BASE.[10] = 1.\r | |
| 5594 | \r | |
| 5595 | @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r | |
| 5596 | @param EAX Lower 32-bits of MSR value.\r | |
| 5597 | @param EDX Upper 32-bits of MSR value.\r | |
| 5598 | \r | |
| 5599 | <b>Example usage</b>\r | |
| 5600 | @code\r | |
| 5601 | UINT64 Msr;\r | |
| 5602 | \r | |
| 5603 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r | |
| 5604 | AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r | |
| 5605 | @endcode\r | |
| 7de98828 | 5606 | @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r |
| 04c980a6 MK |
5607 | **/\r |
| 5608 | #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r | |
| 5609 | \r | |
| 5610 | \r | |
| 5611 | /**\r | |
| 5612 | x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5613 | IA32_APIC_BASE.[10] = 1.\r | |
| 5614 | \r | |
| 5615 | @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r | |
| 5616 | @param EAX Lower 32-bits of MSR value.\r | |
| 5617 | @param EDX Upper 32-bits of MSR value.\r | |
| 5618 | \r | |
| 5619 | <b>Example usage</b>\r | |
| 5620 | @code\r | |
| 5621 | UINT64 Msr;\r | |
| 5622 | \r | |
| 5623 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r | |
| 5624 | @endcode\r | |
| 7de98828 | 5625 | @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r |
| 04c980a6 MK |
5626 | **/\r |
| 5627 | #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r | |
| 5628 | \r | |
| 5629 | \r | |
| 5630 | /**\r | |
| 5631 | x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5632 | IA32_APIC_BASE.[10] = 1.\r | |
| 5633 | \r | |
| 5634 | @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r | |
| 5635 | @param EAX Lower 32-bits of MSR value.\r | |
| 5636 | @param EDX Upper 32-bits of MSR value.\r | |
| 5637 | \r | |
| 5638 | <b>Example usage</b>\r | |
| 5639 | @code\r | |
| 5640 | UINT64 Msr;\r | |
| 5641 | \r | |
| 5642 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r | |
| 5643 | AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r | |
| 5644 | @endcode\r | |
| 7de98828 | 5645 | @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r |
| 04c980a6 MK |
5646 | **/\r |
| 5647 | #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r | |
| 5648 | \r | |
| 5649 | \r | |
| 5650 | /**\r | |
| 5651 | x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5652 | IA32_APIC_BASE.[10] = 1.\r | |
| 5653 | \r | |
| 5654 | @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r | |
| 5655 | @param EAX Lower 32-bits of MSR value.\r | |
| 5656 | @param EDX Upper 32-bits of MSR value.\r | |
| 5657 | \r | |
| 5658 | <b>Example usage</b>\r | |
| 5659 | @code\r | |
| 5660 | UINT64 Msr;\r | |
| 5661 | \r | |
| 5662 | Msr = 0;\r | |
| 5663 | AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r | |
| 5664 | @endcode\r | |
| 7de98828 | 5665 | @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r |
| 04c980a6 MK |
5666 | **/\r |
| 5667 | #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r | |
| 5668 | \r | |
| 5669 | \r | |
| 5670 | /**\r | |
| 5671 | Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r | |
| 5672 | \r | |
| 5673 | @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r | |
| 5674 | @param EAX Lower 32-bits of MSR value.\r | |
| 5675 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
| 5676 | @param EDX Upper 32-bits of MSR value.\r | |
| 5677 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
| 5678 | \r | |
| 5679 | <b>Example usage</b>\r | |
| 5680 | @code\r | |
| 5681 | MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;\r | |
| 5682 | \r | |
| 5683 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r | |
| 5684 | AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r | |
| 5685 | @endcode\r | |
| 7de98828 | 5686 | @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r |
| 04c980a6 MK |
5687 | **/\r |
| 5688 | #define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r | |
| 5689 | \r | |
| 5690 | /**\r | |
| 5691 | MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r | |
| 5692 | **/\r | |
| 5693 | typedef union {\r | |
| 5694 | ///\r | |
| 5695 | /// Individual bit fields\r | |
| 5696 | ///\r | |
| 5697 | struct {\r | |
| 5698 | ///\r | |
| 5699 | /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r | |
| 5700 | /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5701 | ///\r | |
| 5702 | UINT32 Enable:1;\r | |
| 5703 | UINT32 Reserved1:29;\r | |
| 5704 | ///\r | |
| 5705 | /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r | |
| 5706 | /// lock bit is set automatically on the first SMI assertion even if not\r | |
| 5707 | /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5708 | ///\r | |
| 5709 | UINT32 Lock:1;\r | |
| 5710 | ///\r | |
| 5711 | /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r | |
| 5712 | /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5713 | ///\r | |
| 5714 | UINT32 DebugOccurred:1;\r | |
| 5715 | UINT32 Reserved2:32;\r | |
| 5716 | } Bits;\r | |
| 5717 | ///\r | |
| 5718 | /// All bit fields as a 32-bit value\r | |
| 5719 | ///\r | |
| 5720 | UINT32 Uint32;\r | |
| 5721 | ///\r | |
| 5722 | /// All bit fields as a 64-bit value\r | |
| 5723 | ///\r | |
| 5724 | UINT64 Uint64;\r | |
| 5725 | } MSR_IA32_DEBUG_INTERFACE_REGISTER;\r | |
| 5726 | \r | |
| 5727 | \r | |
| 5728 | /**\r | |
| 5729 | L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r | |
| 5730 | \r | |
| 5731 | @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)\r | |
| 5732 | @param EAX Lower 32-bits of MSR value.\r | |
| 5733 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
| 5734 | @param EDX Upper 32-bits of MSR value.\r | |
| 5735 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
| 5736 | \r | |
| 5737 | <b>Example usage</b>\r | |
| 5738 | @code\r | |
| 5739 | MSR_IA32_L3_QOS_CFG_REGISTER Msr;\r | |
| 5740 | \r | |
| 5741 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r | |
| 5742 | AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r | |
| 5743 | @endcode\r | |
| 7de98828 | 5744 | @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r |
| 04c980a6 MK |
5745 | **/\r |
| 5746 | #define MSR_IA32_L3_QOS_CFG 0x00000C81\r | |
| 5747 | \r | |
| 5748 | /**\r | |
| 5749 | MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r | |
| 5750 | **/\r | |
| 5751 | typedef union {\r | |
| 5752 | ///\r | |
| 5753 | /// Individual bit fields\r | |
| 5754 | ///\r | |
| 5755 | struct {\r | |
| 5756 | ///\r | |
| 5757 | /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r | |
| 5758 | /// in Code and Data Prioritization (CDP) mode.\r | |
| 5759 | ///\r | |
| 5760 | UINT32 Enable:1;\r | |
| 5761 | UINT32 Reserved1:31;\r | |
| 5762 | UINT32 Reserved2:32;\r | |
| 5763 | } Bits;\r | |
| 5764 | ///\r | |
| 5765 | /// All bit fields as a 32-bit value\r | |
| 5766 | ///\r | |
| 5767 | UINT32 Uint32;\r | |
| 5768 | ///\r | |
| 5769 | /// All bit fields as a 64-bit value\r | |
| 5770 | ///\r | |
| 5771 | UINT64 Uint64;\r | |
| 5772 | } MSR_IA32_L3_QOS_CFG_REGISTER;\r | |
| 5773 | \r | |
| 5774 | \r | |
| 5775 | /**\r | |
| 5776 | Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r | |
| 5777 | = 1 ).\r | |
| 5778 | \r | |
| 5779 | @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)\r | |
| 5780 | @param EAX Lower 32-bits of MSR value.\r | |
| 5781 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
| 5782 | @param EDX Upper 32-bits of MSR value.\r | |
| 5783 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
| 5784 | \r | |
| 5785 | <b>Example usage</b>\r | |
| 5786 | @code\r | |
| 5787 | MSR_IA32_QM_EVTSEL_REGISTER Msr;\r | |
| 5788 | \r | |
| 5789 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r | |
| 5790 | AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r | |
| 5791 | @endcode\r | |
| 7de98828 | 5792 | @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r |
| 04c980a6 MK |
5793 | **/\r |
| 5794 | #define MSR_IA32_QM_EVTSEL 0x00000C8D\r | |
| 5795 | \r | |
| 5796 | /**\r | |
| 5797 | MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r | |
| 5798 | **/\r | |
| 5799 | typedef union {\r | |
| 5800 | ///\r | |
| 5801 | /// Individual bit fields\r | |
| 5802 | ///\r | |
| 5803 | struct {\r | |
| 5804 | ///\r | |
| 5805 | /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r | |
| 5806 | /// IA32_QM_CTR.\r | |
| 5807 | ///\r | |
| 5808 | UINT32 EventID:8;\r | |
| 5809 | UINT32 Reserved:24;\r | |
| 5810 | ///\r | |
| 5811 | /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r | |
| 5812 | /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r | |
| 5813 | /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
| 5814 | ///\r | |
| 5815 | UINT32 ResourceMonitoringID:32;\r | |
| 5816 | } Bits;\r | |
| 5817 | ///\r | |
| 5818 | /// All bit fields as a 64-bit value\r | |
| 5819 | ///\r | |
| 5820 | UINT64 Uint64;\r | |
| 5821 | } MSR_IA32_QM_EVTSEL_REGISTER;\r | |
| 5822 | \r | |
| 5823 | \r | |
| 5824 | /**\r | |
| 5825 | Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r | |
| 5826 | ).\r | |
| 5827 | \r | |
| 5828 | @param ECX MSR_IA32_QM_CTR (0x00000C8E)\r | |
| 5829 | @param EAX Lower 32-bits of MSR value.\r | |
| 5830 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
| 5831 | @param EDX Upper 32-bits of MSR value.\r | |
| 5832 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
| 5833 | \r | |
| 5834 | <b>Example usage</b>\r | |
| 5835 | @code\r | |
| 5836 | MSR_IA32_QM_CTR_REGISTER Msr;\r | |
| 5837 | \r | |
| 5838 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r | |
| 5839 | @endcode\r | |
| 7de98828 | 5840 | @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r |
| 04c980a6 MK |
5841 | **/\r |
| 5842 | #define MSR_IA32_QM_CTR 0x00000C8E\r | |
| 5843 | \r | |
| 5844 | /**\r | |
| 5845 | MSR information returned for MSR index #MSR_IA32_QM_CTR\r | |
| 5846 | **/\r | |
| 5847 | typedef union {\r | |
| 5848 | ///\r | |
| 5849 | /// Individual bit fields\r | |
| 5850 | ///\r | |
| 5851 | struct {\r | |
| 5852 | ///\r | |
| 5853 | /// [Bits 31:0] Resource Monitored Data.\r | |
| 5854 | ///\r | |
| 5855 | UINT32 ResourceMonitoredData:32;\r | |
| 5856 | ///\r | |
| 5857 | /// [Bits 61:32] Resource Monitored Data.\r | |
| 5858 | ///\r | |
| 5859 | UINT32 ResourceMonitoredDataHi:30;\r | |
| 5860 | ///\r | |
| 5861 | /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r | |
| 5862 | /// available or not monitored for this resource or RMID.\r | |
| 5863 | ///\r | |
| 5864 | UINT32 Unavailable:1;\r | |
| 5865 | ///\r | |
| 5866 | /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r | |
| 5867 | /// written to IA32_PQR_QM_EVTSEL.\r | |
| 5868 | ///\r | |
| 5869 | UINT32 Error:1;\r | |
| 5870 | } Bits;\r | |
| 5871 | ///\r | |
| 5872 | /// All bit fields as a 64-bit value\r | |
| 5873 | ///\r | |
| 5874 | UINT64 Uint64;\r | |
| 5875 | } MSR_IA32_QM_CTR_REGISTER;\r | |
| 5876 | \r | |
| 5877 | \r | |
| 5878 | /**\r | |
| 5879 | Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =\r | |
| 5880 | 1 ).\r | |
| 5881 | \r | |
| 5882 | @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r | |
| 5883 | @param EAX Lower 32-bits of MSR value.\r | |
| 5884 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
| 5885 | @param EDX Upper 32-bits of MSR value.\r | |
| 5886 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
| 5887 | \r | |
| 5888 | <b>Example usage</b>\r | |
| 5889 | @code\r | |
| 5890 | MSR_IA32_PQR_ASSOC_REGISTER Msr;\r | |
| 5891 | \r | |
| 5892 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r | |
| 5893 | AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r | |
| 5894 | @endcode\r | |
| 7de98828 | 5895 | @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r |
| 04c980a6 MK |
5896 | **/\r |
| 5897 | #define MSR_IA32_PQR_ASSOC 0x00000C8F\r | |
| 5898 | \r | |
| 5899 | /**\r | |
| 5900 | MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r | |
| 5901 | **/\r | |
| 5902 | typedef union {\r | |
| 5903 | ///\r | |
| 5904 | /// Individual bit fields\r | |
| 5905 | ///\r | |
| 5906 | struct {\r | |
| 5907 | ///\r | |
| 5908 | /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r | |
| 5909 | /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r | |
| 5910 | /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
| 5911 | ///\r | |
| 5912 | UINT32 ResourceMonitoringID:32;\r | |
| 5913 | ///\r | |
| 5914 | /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r | |
| 5915 | /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r | |
| 5916 | /// ECX=0):EBX.[15] = 1 ).\r | |
| 5917 | ///\r | |
| 5918 | UINT32 COS:32;\r | |
| 5919 | } Bits;\r | |
| 5920 | ///\r | |
| 5921 | /// All bit fields as a 64-bit value\r | |
| 5922 | ///\r | |
| 5923 | UINT64 Uint64;\r | |
| 5924 | } MSR_IA32_PQR_ASSOC_REGISTER;\r | |
| 5925 | \r | |
| 5926 | \r | |
| 5927 | /**\r | |
| 5928 | Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r | |
| 5929 | ECX=0H):EBX[14] = 1).\r | |
| 5930 | \r | |
| 5931 | @param ECX MSR_IA32_BNDCFGS (0x00000D90)\r | |
| 5932 | @param EAX Lower 32-bits of MSR value.\r | |
| 5933 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
| 5934 | @param EDX Upper 32-bits of MSR value.\r | |
| 5935 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
| 5936 | \r | |
| 5937 | <b>Example usage</b>\r | |
| 5938 | @code\r | |
| 5939 | MSR_IA32_BNDCFGS_REGISTER Msr;\r | |
| 5940 | \r | |
| 5941 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r | |
| 5942 | AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r | |
| 5943 | @endcode\r | |
| 7de98828 | 5944 | @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r |
| 04c980a6 MK |
5945 | **/\r |
| 5946 | #define MSR_IA32_BNDCFGS 0x00000D90\r | |
| 5947 | \r | |
| 5948 | /**\r | |
| 5949 | MSR information returned for MSR index #MSR_IA32_BNDCFGS\r | |
| 5950 | **/\r | |
| 5951 | typedef union {\r | |
| 5952 | ///\r | |
| 5953 | /// Individual bit fields\r | |
| 5954 | ///\r | |
| 5955 | struct {\r | |
| 5956 | ///\r | |
| 5957 | /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r | |
| 5958 | ///\r | |
| 5959 | UINT32 EN:1;\r | |
| 5960 | ///\r | |
| 5961 | /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r | |
| 5962 | /// instructions in the absence of the BND prefix.\r | |
| 5963 | ///\r | |
| 5964 | UINT32 BNDPRESERVE:1;\r | |
| 5965 | UINT32 Reserved:10;\r | |
| 5966 | ///\r | |
| 5967 | /// [Bits 31:12] Base Address of Bound Directory.\r | |
| 5968 | ///\r | |
| 5969 | UINT32 Base:20;\r | |
| 5970 | ///\r | |
| 5971 | /// [Bits 63:32] Base Address of Bound Directory.\r | |
| 5972 | ///\r | |
| 5973 | UINT32 BaseHi:32;\r | |
| 5974 | } Bits;\r | |
| 5975 | ///\r | |
| 5976 | /// All bit fields as a 64-bit value\r | |
| 5977 | ///\r | |
| 5978 | UINT64 Uint64;\r | |
| 5979 | } MSR_IA32_BNDCFGS_REGISTER;\r | |
| 5980 | \r | |
| 5981 | \r | |
| 5982 | /**\r | |
| 5983 | Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r | |
| 5984 | \r | |
| 5985 | @param ECX MSR_IA32_XSS (0x00000DA0)\r | |
| 5986 | @param EAX Lower 32-bits of MSR value.\r | |
| 5987 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
| 5988 | @param EDX Upper 32-bits of MSR value.\r | |
| 5989 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
| 5990 | \r | |
| 5991 | <b>Example usage</b>\r | |
| 5992 | @code\r | |
| 5993 | MSR_IA32_XSS_REGISTER Msr;\r | |
| 5994 | \r | |
| 5995 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r | |
| 5996 | AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r | |
| 5997 | @endcode\r | |
| 7de98828 | 5998 | @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r |
| 04c980a6 MK |
5999 | **/\r |
| 6000 | #define MSR_IA32_XSS 0x00000DA0\r | |
| 6001 | \r | |
| 6002 | /**\r | |
| 6003 | MSR information returned for MSR index #MSR_IA32_XSS\r | |
| 6004 | **/\r | |
| 6005 | typedef union {\r | |
| 6006 | ///\r | |
| 6007 | /// Individual bit fields\r | |
| 6008 | ///\r | |
| 6009 | struct {\r | |
| 6010 | UINT32 Reserved1:8;\r | |
| 6011 | ///\r | |
| 6012 | /// [Bit 8] Trace Packet Configuration State (R/W).\r | |
| 6013 | ///\r | |
| 6014 | UINT32 TracePacketConfigurationState:1;\r | |
| 6015 | UINT32 Reserved2:23;\r | |
| 6016 | UINT32 Reserved3:32;\r | |
| 6017 | } Bits;\r | |
| 6018 | ///\r | |
| 6019 | /// All bit fields as a 32-bit value\r | |
| 6020 | ///\r | |
| 6021 | UINT32 Uint32;\r | |
| 6022 | ///\r | |
| 6023 | /// All bit fields as a 64-bit value\r | |
| 6024 | ///\r | |
| 6025 | UINT64 Uint64;\r | |
| 6026 | } MSR_IA32_XSS_REGISTER;\r | |
| 6027 | \r | |
| 6028 | \r | |
| 6029 | /**\r | |
| 6030 | Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
| 6031 | \r | |
| 6032 | @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r | |
| 6033 | @param EAX Lower 32-bits of MSR value.\r | |
| 6034 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
| 6035 | @param EDX Upper 32-bits of MSR value.\r | |
| 6036 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
| 6037 | \r | |
| 6038 | <b>Example usage</b>\r | |
| 6039 | @code\r | |
| 6040 | MSR_IA32_PKG_HDC_CTL_REGISTER Msr;\r | |
| 6041 | \r | |
| 6042 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r | |
| 6043 | AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r | |
| 6044 | @endcode\r | |
| 7de98828 | 6045 | @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r |
| 04c980a6 MK |
6046 | **/\r |
| 6047 | #define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r | |
| 6048 | \r | |
| 6049 | /**\r | |
| 6050 | MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r | |
| 6051 | **/\r | |
| 6052 | typedef union {\r | |
| 6053 | ///\r | |
| 6054 | /// Individual bit fields\r | |
| 6055 | ///\r | |
| 6056 | struct {\r | |
| 6057 | ///\r | |
| 6058 | /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r | |
| 6059 | /// logical processors in the package. See Section 14.5.2, "Package level\r | |
| 6060 | /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r | |
| 6061 | ///\r | |
| 6062 | UINT32 HDC_Pkg_Enable:1;\r | |
| 6063 | UINT32 Reserved1:31;\r | |
| 6064 | UINT32 Reserved2:32;\r | |
| 6065 | } Bits;\r | |
| 6066 | ///\r | |
| 6067 | /// All bit fields as a 32-bit value\r | |
| 6068 | ///\r | |
| 6069 | UINT32 Uint32;\r | |
| 6070 | ///\r | |
| 6071 | /// All bit fields as a 64-bit value\r | |
| 6072 | ///\r | |
| 6073 | UINT64 Uint64;\r | |
| 6074 | } MSR_IA32_PKG_HDC_CTL_REGISTER;\r | |
| 6075 | \r | |
| 6076 | \r | |
| 6077 | /**\r | |
| 6078 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
| 6079 | \r | |
| 6080 | @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)\r | |
| 6081 | @param EAX Lower 32-bits of MSR value.\r | |
| 6082 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
| 6083 | @param EDX Upper 32-bits of MSR value.\r | |
| 6084 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
| 6085 | \r | |
| 6086 | <b>Example usage</b>\r | |
| 6087 | @code\r | |
| 6088 | MSR_IA32_PM_CTL1_REGISTER Msr;\r | |
| 6089 | \r | |
| 6090 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r | |
| 6091 | AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r | |
| 6092 | @endcode\r | |
| 7de98828 | 6093 | @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r |
| 04c980a6 MK |
6094 | **/\r |
| 6095 | #define MSR_IA32_PM_CTL1 0x00000DB1\r | |
| 6096 | \r | |
| 6097 | /**\r | |
| 6098 | MSR information returned for MSR index #MSR_IA32_PM_CTL1\r | |
| 6099 | **/\r | |
| 6100 | typedef union {\r | |
| 6101 | ///\r | |
| 6102 | /// Individual bit fields\r | |
| 6103 | ///\r | |
| 6104 | struct {\r | |
| 6105 | ///\r | |
| 6106 | /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r | |
| 6107 | /// package level HDC control. See Section 14.5.3.\r | |
| 6108 | /// If CPUID.06H:EAX.[13] = 1.\r | |
| 6109 | ///\r | |
| 6110 | UINT32 HDC_Allow_Block:1;\r | |
| 6111 | UINT32 Reserved1:31;\r | |
| 6112 | UINT32 Reserved2:32;\r | |
| 6113 | } Bits;\r | |
| 6114 | ///\r | |
| 6115 | /// All bit fields as a 32-bit value\r | |
| 6116 | ///\r | |
| 6117 | UINT32 Uint32;\r | |
| 6118 | ///\r | |
| 6119 | /// All bit fields as a 64-bit value\r | |
| 6120 | ///\r | |
| 6121 | UINT64 Uint64;\r | |
| 6122 | } MSR_IA32_PM_CTL1_REGISTER;\r | |
| 6123 | \r | |
| 6124 | \r | |
| 6125 | /**\r | |
| 6126 | Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r | |
| 6127 | Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r | |
| 6128 | processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r | |
| 6129 | \r | |
| 6130 | @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)\r | |
| 6131 | @param EAX Lower 32-bits of MSR value.\r | |
| 6132 | @param EDX Upper 32-bits of MSR value.\r | |
| 6133 | \r | |
| 6134 | <b>Example usage</b>\r | |
| 6135 | @code\r | |
| 6136 | UINT64 Msr;\r | |
| 6137 | \r | |
| 6138 | Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r | |
| 6139 | @endcode\r | |
| 7de98828 | 6140 | @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r |
| 04c980a6 MK |
6141 | **/\r |
| 6142 | #define MSR_IA32_THREAD_STALL 0x00000DB2\r | |
| 6143 | \r | |
| 6144 | \r | |
| 6145 | /**\r | |
| 6146 | Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r | |
| 6147 | CPUID.80000001H:EDX.[2 9]).\r | |
| 6148 | \r | |
| 6149 | @param ECX MSR_IA32_EFER (0xC0000080)\r | |
| 6150 | @param EAX Lower 32-bits of MSR value.\r | |
| 6151 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
| 6152 | @param EDX Upper 32-bits of MSR value.\r | |
| 6153 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
| 6154 | \r | |
| 6155 | <b>Example usage</b>\r | |
| 6156 | @code\r | |
| 6157 | MSR_IA32_EFER_REGISTER Msr;\r | |
| 6158 | \r | |
| 6159 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r | |
| 6160 | AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r | |
| 6161 | @endcode\r | |
| 7de98828 | 6162 | @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r |
| 04c980a6 MK |
6163 | **/\r |
| 6164 | #define MSR_IA32_EFER 0xC0000080\r | |
| 6165 | \r | |
| 6166 | /**\r | |
| 6167 | MSR information returned for MSR index #MSR_IA32_EFER\r | |
| 6168 | **/\r | |
| 6169 | typedef union {\r | |
| 6170 | ///\r | |
| 6171 | /// Individual bit fields\r | |
| 6172 | ///\r | |
| 6173 | struct {\r | |
| 6174 | ///\r | |
| 6175 | /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r | |
| 6176 | /// instructions in 64-bit mode.\r | |
| 6177 | ///\r | |
| 6178 | UINT32 SCE:1;\r | |
| 6179 | UINT32 Reserved1:7;\r | |
| 6180 | ///\r | |
| 6181 | /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r | |
| 6182 | /// operation.\r | |
| 6183 | ///\r | |
| 6184 | UINT32 LME:1;\r | |
| 6185 | UINT32 Reserved2:1;\r | |
| 6186 | ///\r | |
| 6187 | /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r | |
| 6188 | /// is active when set.\r | |
| 6189 | ///\r | |
| 6190 | UINT32 LMA:1;\r | |
| 6191 | ///\r | |
| 6192 | /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r | |
| 6193 | ///\r | |
| 6194 | UINT32 NXE:1;\r | |
| 6195 | UINT32 Reserved3:20;\r | |
| 6196 | UINT32 Reserved4:32;\r | |
| 6197 | } Bits;\r | |
| 6198 | ///\r | |
| 6199 | /// All bit fields as a 32-bit value\r | |
| 6200 | ///\r | |
| 6201 | UINT32 Uint32;\r | |
| 6202 | ///\r | |
| 6203 | /// All bit fields as a 64-bit value\r | |
| 6204 | ///\r | |
| 6205 | UINT64 Uint64;\r | |
| 6206 | } MSR_IA32_EFER_REGISTER;\r | |
| 6207 | \r | |
| 6208 | \r | |
| 6209 | /**\r | |
| 6210 | System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6211 | \r | |
| 6212 | @param ECX MSR_IA32_STAR (0xC0000081)\r | |
| 6213 | @param EAX Lower 32-bits of MSR value.\r | |
| 6214 | @param EDX Upper 32-bits of MSR value.\r | |
| 6215 | \r | |
| 6216 | <b>Example usage</b>\r | |
| 6217 | @code\r | |
| 6218 | UINT64 Msr;\r | |
| 6219 | \r | |
| 6220 | Msr = AsmReadMsr64 (MSR_IA32_STAR);\r | |
| 6221 | AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r | |
| 6222 | @endcode\r | |
| 7de98828 | 6223 | @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r |
| 04c980a6 MK |
6224 | **/\r |
| 6225 | #define MSR_IA32_STAR 0xC0000081\r | |
| 6226 | \r | |
| 6227 | \r | |
| 6228 | /**\r | |
| 6229 | IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6230 | \r | |
| 6231 | @param ECX MSR_IA32_LSTAR (0xC0000082)\r | |
| 6232 | @param EAX Lower 32-bits of MSR value.\r | |
| 6233 | @param EDX Upper 32-bits of MSR value.\r | |
| 6234 | \r | |
| 6235 | <b>Example usage</b>\r | |
| 6236 | @code\r | |
| 6237 | UINT64 Msr;\r | |
| 6238 | \r | |
| 6239 | Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r | |
| 6240 | AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r | |
| 6241 | @endcode\r | |
| 7de98828 | 6242 | @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r |
| 04c980a6 MK |
6243 | **/\r |
| 6244 | #define MSR_IA32_LSTAR 0xC0000082\r | |
| 6245 | \r | |
| 6246 | \r | |
| 6247 | /**\r | |
| 6248 | System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6249 | \r | |
| 6250 | @param ECX MSR_IA32_FMASK (0xC0000084)\r | |
| 6251 | @param EAX Lower 32-bits of MSR value.\r | |
| 6252 | @param EDX Upper 32-bits of MSR value.\r | |
| 6253 | \r | |
| 6254 | <b>Example usage</b>\r | |
| 6255 | @code\r | |
| 6256 | UINT64 Msr;\r | |
| 6257 | \r | |
| 6258 | Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r | |
| 6259 | AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r | |
| 6260 | @endcode\r | |
| 7de98828 | 6261 | @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r |
| 04c980a6 MK |
6262 | **/\r |
| 6263 | #define MSR_IA32_FMASK 0xC0000084\r | |
| 6264 | \r | |
| 6265 | \r | |
| 6266 | /**\r | |
| 6267 | Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6268 | \r | |
| 6269 | @param ECX MSR_IA32_FS_BASE (0xC0000100)\r | |
| 6270 | @param EAX Lower 32-bits of MSR value.\r | |
| 6271 | @param EDX Upper 32-bits of MSR value.\r | |
| 6272 | \r | |
| 6273 | <b>Example usage</b>\r | |
| 6274 | @code\r | |
| 6275 | UINT64 Msr;\r | |
| 6276 | \r | |
| 6277 | Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r | |
| 6278 | AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r | |
| 6279 | @endcode\r | |
| 7de98828 | 6280 | @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r |
| 04c980a6 MK |
6281 | **/\r |
| 6282 | #define MSR_IA32_FS_BASE 0xC0000100\r | |
| 6283 | \r | |
| 6284 | \r | |
| 6285 | /**\r | |
| 6286 | Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6287 | \r | |
| 6288 | @param ECX MSR_IA32_GS_BASE (0xC0000101)\r | |
| 6289 | @param EAX Lower 32-bits of MSR value.\r | |
| 6290 | @param EDX Upper 32-bits of MSR value.\r | |
| 6291 | \r | |
| 6292 | <b>Example usage</b>\r | |
| 6293 | @code\r | |
| 6294 | UINT64 Msr;\r | |
| 6295 | \r | |
| 6296 | Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r | |
| 6297 | AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r | |
| 6298 | @endcode\r | |
| 7de98828 | 6299 | @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r |
| 04c980a6 MK |
6300 | **/\r |
| 6301 | #define MSR_IA32_GS_BASE 0xC0000101\r | |
| 6302 | \r | |
| 6303 | \r | |
| 6304 | /**\r | |
| 6305 | Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6306 | \r | |
| 6307 | @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r | |
| 6308 | @param EAX Lower 32-bits of MSR value.\r | |
| 6309 | @param EDX Upper 32-bits of MSR value.\r | |
| 6310 | \r | |
| 6311 | <b>Example usage</b>\r | |
| 6312 | @code\r | |
| 6313 | UINT64 Msr;\r | |
| 6314 | \r | |
| 6315 | Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r | |
| 6316 | AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r | |
| 6317 | @endcode\r | |
| 7de98828 | 6318 | @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r |
| 04c980a6 MK |
6319 | **/\r |
| 6320 | #define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r | |
| 6321 | \r | |
| 6322 | \r | |
| 6323 | /**\r | |
| 6324 | Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r | |
| 6325 | \r | |
| 6326 | @param ECX MSR_IA32_TSC_AUX (0xC0000103)\r | |
| 6327 | @param EAX Lower 32-bits of MSR value.\r | |
| 6328 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
| 6329 | @param EDX Upper 32-bits of MSR value.\r | |
| 6330 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
| 6331 | \r | |
| 6332 | <b>Example usage</b>\r | |
| 6333 | @code\r | |
| 6334 | MSR_IA32_TSC_AUX_REGISTER Msr;\r | |
| 6335 | \r | |
| 6336 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r | |
| 6337 | AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r | |
| 6338 | @endcode\r | |
| 7de98828 | 6339 | @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r |
| 04c980a6 MK |
6340 | **/\r |
| 6341 | #define MSR_IA32_TSC_AUX 0xC0000103\r | |
| 6342 | \r | |
| 6343 | /**\r | |
| 6344 | MSR information returned for MSR index #MSR_IA32_TSC_AUX\r | |
| 6345 | **/\r | |
| 6346 | typedef union {\r | |
| 6347 | ///\r | |
| 6348 | /// Individual bit fields\r | |
| 6349 | ///\r | |
| 6350 | struct {\r | |
| 6351 | ///\r | |
| 6352 | /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r | |
| 6353 | ///\r | |
| 6354 | UINT32 AUX:32;\r | |
| 6355 | UINT32 Reserved:32;\r | |
| 6356 | } Bits;\r | |
| 6357 | ///\r | |
| 6358 | /// All bit fields as a 32-bit value\r | |
| 6359 | ///\r | |
| 6360 | UINT32 Uint32;\r | |
| 6361 | ///\r | |
| 6362 | /// All bit fields as a 64-bit value\r | |
| 6363 | ///\r | |
| 6364 | UINT64 Uint64;\r | |
| 6365 | } MSR_IA32_TSC_AUX_REGISTER;\r | |
| 6366 | \r | |
| 6367 | #endif\r |