UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Cpuid.h
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28a7ddf0 1/** @file\r
57d16ba1 2 CPUID leaf definitions.\r
28a7ddf0 3\r
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4 Provides defines for CPUID leaf indexes. Data structures are provided for\r
5 registers returned by a CPUID leaf that contain one or more bit fields.\r
6 If a register returned is a single 32-bit value, then a data structure is\r
7 not provided for that register.\r
28a7ddf0 8\r
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9 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials are licensed and made available under\r
11 the terms and conditions of the BSD License which accompanies this distribution.\r
12 The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
28a7ddf0 14\r
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15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r
14806d7b 20 September 2016, CPUID instruction.\r
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21\r
22**/\r
23\r
24#ifndef __CPUID_H__\r
25#define __CPUID_H__\r
26\r
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27/**\r
28 CPUID Signature Information\r
29\r
30 @param EAX CPUID_SIGNATURE (0x00)\r
31\r
32 @retval EAX Returns the highest value the CPUID instruction recognizes for\r
33 returning basic processor information. The value is returned is\r
34 processor specific.\r
35 @retval EBX First 4 characters of a vendor identification string.\r
36 @retval ECX Last 4 characters of a vendor identification string.\r
37 @retval EDX Middle 4 characters of a vendor identification string.\r
38\r
39 <b>Example usage</b>\r
40 @code\r
41 UINT32 Eax;\r
42 UINT32 Ebx;\r
43 UINT32 Ecx;\r
44 UINT32 Edx;\r
45\r
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
47 @endcode\r
48**/\r
49#define CPUID_SIGNATURE 0x00\r
50\r
51///\r
52/// @{ CPUID signature values returned by Intel processors\r
53///\r
54#define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')\r
55#define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')\r
56#define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')\r
57///\r
58/// @}\r
59///\r
60\r
61\r
62/**\r
63 CPUID Version Information\r
64\r
65 @param EAX CPUID_VERSION_INFO (0x01)\r
66\r
67 @retval EAX Returns Model, Family, Stepping Information described by the\r
68 type CPUID_VERSION_INFO_EAX.\r
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by\r
70 the type CPUID_VERSION_INFO_EBX.\r
71 @retval ECX CPU Feature Information described by the type\r
72 CPUID_VERSION_INFO_ECX.\r
73 @retval EDX CPU Feature Information described by the type\r
74 CPUID_VERSION_INFO_EDX.\r
75\r
76 <b>Example usage</b>\r
77 @code\r
78 CPUID_VERSION_INFO_EAX Eax;\r
79 CPUID_VERSION_INFO_EBX Ebx;\r
80 CPUID_VERSION_INFO_ECX Ecx;\r
81 CPUID_VERSION_INFO_EDX Edx;\r
82\r
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
84 @endcode\r
85**/\r
86#define CPUID_VERSION_INFO 0x01\r
87\r
88/**\r
89 CPUID Version Information returned in EAX for CPUID leaf\r
90 #CPUID_VERSION_INFO.\r
91**/\r
92typedef union {\r
93 ///\r
94 /// Individual bit fields\r
95 ///\r
96 struct {\r
97 UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID\r
98 UINT32 Model:4; ///< [Bits 7:4] Model\r
99 UINT32 FamilyId:4; ///< [Bits 11:8] Family\r
100 UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type\r
101 UINT32 Reserved1:2; ///< [Bits 15:14] Reserved\r
102 UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID\r
103 UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID\r
104 UINT32 Reserved2:4; ///< Reserved\r
105 } Bits;\r
106 ///\r
107 /// All bit fields as a 32-bit value\r
108 ///\r
109 UINT32 Uint32;\r
110} CPUID_VERSION_INFO_EAX;\r
111\r
112///\r
113/// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType\r
114///\r
115#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00\r
116#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01\r
117#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02\r
118///\r
119/// @}\r
120///\r
121\r
122/**\r
123 CPUID Version Information returned in EBX for CPUID leaf\r
124 #CPUID_VERSION_INFO.\r
125**/\r
126typedef union {\r
127 ///\r
128 /// Individual bit fields\r
129 ///\r
130 struct {\r
131 ///\r
132 /// [Bits 7:0] Provides an entry into a brand string table that contains\r
133 /// brand strings for IA-32 processors.\r
134 ///\r
135 UINT32 BrandIndex:8;\r
136 ///\r
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH\r
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was\r
139 /// introduced in the Pentium 4 processor.\r
140 ///\r
141 UINT32 CacheLineSize:8;\r
142 ///\r
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors\r
144 /// in this physical package.\r
145 ///\r
146 /// @note\r
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is\r
148 /// the number of unique initial APICIDs reserved for addressing different\r
149 /// logical processors in a physical package. This field is only valid if\r
150 /// CPUID.1.EDX.HTT[bit 28]= 1.\r
151 ///\r
152 UINT32 MaximumAddressableIdsForLogicalProcessors:8;\r
153 ///\r
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the\r
155 /// processor during power up. This field was introduced in the Pentium 4\r
156 /// processor.\r
157 ///\r
158 UINT32 InitialLocalApicId:8;\r
159 } Bits;\r
160 ///\r
161 /// All bit fields as a 32-bit value\r
162 ///\r
163 UINT32 Uint32;\r
164} CPUID_VERSION_INFO_EBX;\r
165\r
166/**\r
167 CPUID Version Information returned in ECX for CPUID leaf\r
168 #CPUID_VERSION_INFO.\r
169**/\r
170typedef union {\r
171 ///\r
172 /// Individual bit fields\r
173 ///\r
174 struct {\r
175 ///\r
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the\r
177 /// processor supports this technology\r
178 ///\r
179 UINT32 SSE3:1;\r
180 ///\r
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ\r
182 /// instruction. Carryless Multiplication\r
183 ///\r
184 UINT32 PCLMULQDQ:1;\r
185 ///\r
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports\r
187 /// DS area using 64-bit layout.\r
188 ///\r
189 UINT32 DTES64:1;\r
190 ///\r
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports\r
192 /// this feature.\r
193 ///\r
194 UINT32 MONITOR:1;\r
195 ///\r
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor\r
197 /// supports the extensions to the Debug Store feature to allow for branch\r
198 /// message storage qualified by CPL\r
199 ///\r
200 UINT32 DS_CPL:1;\r
201 ///\r
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the\r
203 /// processor supports this technology.\r
204 ///\r
205 UINT32 VMX:1;\r
206 ///\r
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor\r
208 /// supports this technology\r
209 ///\r
210 UINT32 SMX:1;\r
211 ///\r
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates\r
213 /// that the processor supports this technology\r
214 ///\r
215 UINT32 EIST:1;\r
216 ///\r
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor\r
218 /// supports this technology\r
219 ///\r
220 UINT32 TM2:1;\r
221 ///\r
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming\r
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction\r
224 /// extensions are not present in the processor.\r
225 ///\r
226 UINT32 SSSE3:1;\r
227 ///\r
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode\r
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates\r
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR\r
231 /// Bit 24 (L1 Data Cache Context Mode) for details\r
232 ///\r
233 UINT32 CNXT_ID:1;\r
234 ///\r
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE\r
236 /// MSR for silicon debug\r
237 ///\r
238 UINT32 SDBG:1;\r
239 ///\r
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple\r
241 /// Add) extensions using YMM state.\r
242 ///\r
243 UINT32 FMA:1;\r
244 ///\r
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature\r
246 /// is available.\r
247 ///\r
248 UINT32 CMPXCHG16B:1;\r
249 ///\r
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor\r
251 /// supports changing IA32_MISC_ENABLE[Bit 23].\r
252 ///\r
253 UINT32 xTPR_Update_Control:1;\r
254 ///\r
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the\r
256 /// processor supports the performance and debug feature indication MSR\r
257 /// IA32_PERF_CAPABILITIES.\r
258 ///\r
259 UINT32 PDCM:1;\r
260 UINT32 Reserved:1;\r
261 ///\r
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the\r
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.\r
264 ///\r
265 UINT32 PCID:1;\r
266 ///\r
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to\r
268 /// prefetch data from a memory mapped device. Direct Cache Access.\r
269 ///\r
270 UINT32 DCA:1;\r
271 ///\r
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.\r
273 ///\r
274 UINT32 SSE4_1:1;\r
275 ///\r
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.\r
277 ///\r
278 UINT32 SSE4_2:1;\r
279 ///\r
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC\r
281 /// feature.\r
282 ///\r
283 UINT32 x2APIC:1;\r
284 ///\r
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE\r
286 /// instruction.\r
287 ///\r
288 UINT32 MOVBE:1;\r
289 ///\r
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT\r
291 /// instruction.\r
292 ///\r
293 UINT32 POPCNT:1;\r
294 ///\r
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer\r
296 /// supports one-shot operation using a TSC deadline value.\r
297 ///\r
298 UINT32 TSC_Deadline:1;\r
299 ///\r
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI\r
301 /// instruction extensions.\r
302 ///\r
303 UINT32 AESNI:1;\r
304 ///\r
305 /// [Bit 26] A value of 1 indicates that the processor supports the\r
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV\r
307 /// instructions, and XCR0.\r
308 ///\r
309 UINT32 XSAVE:1;\r
310 ///\r
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]\r
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support\r
313 /// processor extended state management using XSAVE/XRSTOR.\r
314 ///\r
315 UINT32 OSXSAVE:1;\r
316 ///\r
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction\r
318 /// extensions.\r
319 ///\r
320 UINT32 AVX:1;\r
321 ///\r
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit\r
323 /// floating-point conversion instructions.\r
324 ///\r
325 UINT32 F16C:1;\r
326 ///\r
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.\r
328 ///\r
329 UINT32 RDRAND:1;\r
330 ///\r
331 /// [Bit 31] Always returns 0.\r
332 ///\r
333 UINT32 NotUsed:1;\r
334 } Bits;\r
335 ///\r
336 /// All bit fields as a 32-bit value\r
337 ///\r
338 UINT32 Uint32;\r
339} CPUID_VERSION_INFO_ECX;\r
340\r
341/**\r
342 CPUID Version Information returned in EDX for CPUID leaf\r
343 #CPUID_VERSION_INFO.\r
344**/\r
345typedef union {\r
346 ///\r
347 /// Individual bit fields\r
348 ///\r
349 struct {\r
350 ///\r
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.\r
352 ///\r
353 UINT32 FPU:1;\r
354 ///\r
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,\r
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected\r
357 /// mode virtual interrupts, software interrupt indirection, expansion of\r
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and\r
359 /// EFLAGS.VIP flags.\r
360 ///\r
361 UINT32 VME:1;\r
362 ///\r
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including\r
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to\r
365 /// DR4 and DR5.\r
366 ///\r
367 UINT32 DE:1;\r
368 ///\r
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,\r
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in\r
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,\r
372 /// PDEs, and PTEs.\r
373 ///\r
374 UINT32 PSE:1;\r
375 ///\r
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,\r
377 /// including CR4.TSD for controlling privilege.\r
378 ///\r
379 UINT32 TSC:1;\r
380 ///\r
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The\r
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are\r
383 /// implementation dependent.\r
384 ///\r
385 UINT32 MSR:1;\r
386 ///\r
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32\r
388 /// bits are supported: extended page table entry formats, an extra level in\r
389 /// the page translation tables is defined, 2-MByte pages are supported\r
390 /// instead of 4 Mbyte pages if PAE bit is 1.\r
391 ///\r
392 UINT32 PAE:1;\r
393 ///\r
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine\r
395 /// Checks, including CR4.MCE for controlling the feature. This feature does\r
396 /// not define the model-specific implementations of machine-check error\r
397 /// logging, reporting, and processor shutdowns. Machine Check exception\r
398 /// handlers may have to depend on processor version to do model specific\r
399 /// processing of the exception, or test for the presence of the Machine\r
400 /// Check feature.\r
401 ///\r
402 UINT32 MCE:1;\r
403 ///\r
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)\r
405 /// instruction is supported (implicitly locked and atomic).\r
406 ///\r
407 UINT32 CX8:1;\r
408 ///\r
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable\r
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the\r
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some\r
412 /// processors permit the APIC to be relocated).\r
413 ///\r
414 UINT32 APIC:1;\r
415 UINT32 Reserved1:1;\r
416 ///\r
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT\r
418 /// and associated MSRs are supported.\r
419 ///\r
420 UINT32 SEP:1;\r
421 ///\r
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap\r
423 /// MSR contains feature bits that describe what memory types are supported,\r
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are\r
425 /// supported.\r
426 ///\r
427 UINT32 MTRR:1;\r
428 ///\r
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure\r
430 /// entries that map a page, indicating TLB entries that are common to\r
431 /// different processes and need not be flushed. The CR4.PGE bit controls\r
432 /// this feature.\r
433 ///\r
434 UINT32 PGE:1;\r
435 ///\r
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436 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine\r
437 /// Check Architecture of reporting machine errors is supported. The MCG_CAP\r
438 /// MSR contains feature bits describing how many banks of error reporting\r
439 /// MSRs are supported.\r
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440 ///\r
441 UINT32 MCA:1;\r
442 ///\r
443 /// [Bit 15] Conditional Move Instructions. The conditional move instruction\r
444 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the\r
445 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.\r
446 ///\r
447 UINT32 CMOV:1;\r
448 ///\r
449 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This\r
450 /// feature augments the Memory Type Range Registers (MTRRs), allowing an\r
451 /// operating system to specify attributes of memory accessed through a\r
452 /// linear address on a 4KB granularity.\r
453 ///\r
454 UINT32 PAT:1;\r
455 ///\r
456 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical\r
457 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature\r
458 /// indicates that upper bits of the physical address of a 4-MByte page are\r
459 /// encoded in bits 20:13 of the page-directory entry. Such physical\r
460 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.\r
461 ///\r
462 UINT32 PSE_36:1;\r
463 ///\r
464 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit\r
465 /// processor identification number feature and the feature is enabled.\r
466 ///\r
467 UINT32 PSN:1;\r
468 ///\r
469 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.\r
470 ///\r
471 UINT32 CLFSH:1;\r
472 UINT32 Reserved2:1;\r
473 ///\r
474 /// [Bit 21] Debug Store. The processor supports the ability to write debug\r
475 /// information into a memory resident buffer. This feature is used by the\r
476 /// branch trace store (BTS) and precise event-based sampling (PEBS)\r
477 /// facilities.\r
478 ///\r
479 UINT32 DS:1;\r
480 ///\r
481 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The\r
482 /// processor implements internal MSRs that allow processor temperature to\r
483 /// be monitored and processor performance to be modulated in predefined\r
484 /// duty cycles under software control.\r
485 ///\r
486 UINT32 ACPI:1;\r
487 ///\r
488 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX\r
489 /// technology.\r
490 ///\r
491 UINT32 MMX:1;\r
492 ///\r
493 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR\r
494 /// instructions are supported for fast save and restore of the floating\r
495 /// point context. Presence of this bit also indicates that CR4.OSFXSR is\r
496 /// available for an operating system to indicate that it supports the\r
497 /// FXSAVE and FXRSTOR instructions.\r
498 ///\r
499 UINT32 FXSR:1;\r
500 ///\r
501 /// [Bit 25] SSE. The processor supports the SSE extensions.\r
502 ///\r
503 UINT32 SSE:1;\r
504 ///\r
505 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.\r
506 ///\r
507 UINT32 SSE2:1;\r
508 ///\r
509 /// [Bit 27] Self Snoop. The processor supports the management of\r
510 /// conflicting memory types by performing a snoop of its own cache\r
511 /// structure for transactions issued to the bus.\r
512 ///\r
513 UINT32 SS:1;\r
514 ///\r
515 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT\r
516 /// indicates there is only a single logical processor in the package and\r
517 /// software should assume only a single APIC ID is reserved. A value of 1\r
518 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of\r
519 /// addressable IDs for logical processors in this package) is valid for the\r
520 /// package.\r
521 ///\r
522 UINT32 HTT:1;\r
523 ///\r
524 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor\r
525 /// automatic thermal control circuitry (TCC).\r
526 ///\r
527 UINT32 TM:1;\r
528 UINT32 Reserved3:1;\r
529 ///\r
530 /// [Bit 31] Pending Break Enable. The processor supports the use of the\r
531 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is\r
532 /// asserted) to signal the processor that an interrupt is pending and that\r
533 /// the processor should return to normal operation to handle the interrupt.\r
534 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.\r
535 ///\r
536 UINT32 PBE:1;\r
537 } Bits;\r
538 ///\r
539 /// All bit fields as a 32-bit value\r
540 ///\r
541 UINT32 Uint32;\r
542} CPUID_VERSION_INFO_EDX;\r
543\r
544\r
545/**\r
546 CPUID Cache and TLB Information\r
547\r
548 @param EAX CPUID_CACHE_INFO (0x02)\r
549\r
550 @retval EAX Cache and TLB Information described by the type\r
551 CPUID_CACHE_INFO_CACHE_TLB.\r
552 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns\r
553 0x01 and must be ignored. Only valid if\r
554 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
555 @retval EBX Cache and TLB Information described by the type\r
556 CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
557 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
558 @retval ECX Cache and TLB Information described by the type\r
559 CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
560 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
561 @retval EDX Cache and TLB Information described by the type\r
562 CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
563 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
564\r
565 <b>Example usage</b>\r
566 @code\r
567 CPUID_CACHE_INFO_CACHE_TLB Eax;\r
568 CPUID_CACHE_INFO_CACHE_TLB Ebx;\r
569 CPUID_CACHE_INFO_CACHE_TLB Ecx;\r
570 CPUID_CACHE_INFO_CACHE_TLB Edx;\r
571\r
572 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
573 @endcode\r
574\r
575 <b>Cache Descriptor values</b>\r
576 <table>\r
577 <tr><th>Value </th><th> Type </th><th> Description </th></tr>\r
578 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>\r
579 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>\r
580 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>\r
581 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>\r
582 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>\r
583 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
584 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,\r
585 32 byte line size</td></tr>\r
586 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,\r
587 32 byte line size</td></tr>\r
588 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,\r
589 64 byte line size</td></tr>\r
590 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>\r
591 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>\r
592 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
593 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>\r
594 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>\r
595 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>\r
596 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>\r
597 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,\r
598 2 lines per sector</td></tr>\r
599 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,\r
600 2 lines per sector</td></tr>\r
601 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>\r
602 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,\r
603 2 lines per sector</td></tr>\r
604 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,\r
605 2 lines per sector</td></tr>\r
606 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,\r
607 64 byte line size</td></tr>\r
608 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,\r
609 64 byte line size</td></tr>\r
610 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,\r
611 no 3rd-level cache</td></tr>\r
612 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
613 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
614 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
615 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>\r
616 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>\r
617 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>\r
618 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>\r
619 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>\r
620 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size\r
621 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>\r
622 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r
623 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>\r
624 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>\r
625 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>\r
626 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>\r
627 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>\r
628 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>\r
629 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>\r
630 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>\r
631 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>\r
632 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>\r
633 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r
634 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r
635 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r
14806d7b 636 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
57d16ba1
MK
637 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r
638 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r
639 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r
640 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r
641 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r
14806d7b
HW
642 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,\r
643 32 entries and a separate array with 1 GByte pages, 4-way set associative,\r
644 4 entries</td></tr>\r
645 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>\r
57d16ba1
MK
646 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r
647 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r
648 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r
649 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>\r
650 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>\r
651 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>\r
652 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>\r
653 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>\r
654 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>\r
655 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>\r
656 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>\r
657 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>\r
658 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,\r
659 2 lines per sector</td></tr>\r
660 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,\r
661 2 lines per sector</td></tr>\r
662 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,\r
663 2 lines per sector</td></tr>\r
664 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,\r
665 2 lines per sector</td></tr>\r
666 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>\r
667 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>\r
668 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>\r
669 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>\r
670 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>\r
671 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>\r
672 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>\r
673 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
674 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r
675 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>\r
676 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r
677 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>\r
678 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>\r
679 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r
680 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>\r
681 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>\r
682 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,\r
683 128 entries</td></tr>\r
684 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>\r
685 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>\r
686 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,\r
687 1024 entries</td></tr>\r
688 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r
689 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r
690 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r
14806d7b 691 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>\r
57d16ba1
MK
692 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r
693 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
694 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r
695 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>\r
696 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r
697 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>\r
698 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>\r
699 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>\r
700 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>\r
701 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>\r
702 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>\r
703 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r
704 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>\r
705 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>\r
706 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>\r
707 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>\r
708 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>\r
709 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>\r
710 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,\r
711 use CPUID leaf 4 to query cache parameters</td></tr>\r
712 </table>\r
713**/\r
714#define CPUID_CACHE_INFO 0x02\r
715\r
716/**\r
717 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID\r
718 leaf #CPUID_CACHE_INFO.\r
719**/\r
720typedef union {\r
721 ///\r
722 /// Individual bit fields\r
723 ///\r
724 struct {\r
725 UINT32 Reserved:31;\r
726 ///\r
727 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.\r
728 /// if 1, then none of the cache descriptor bytes in the register are valid.\r
729 ///\r
730 UINT32 NotValid:1;\r
731 } Bits;\r
732 ///\r
733 /// Array of Cache and TLB descriptor bytes\r
734 ///\r
735 UINT8 CacheDescriptor[4];\r
736 ///\r
737 /// All bit fields as a 32-bit value\r
738 ///\r
739 UINT32 Uint32;\r
740} CPUID_CACHE_INFO_CACHE_TLB;\r
741\r
742\r
743/**\r
744 CPUID Processor Serial Number\r
745\r
746 Processor serial number (PSN) is not supported in the Pentium 4 processor\r
747 or later. On all models, use the PSN flag (returned using CPUID) to check\r
748 for PSN support before accessing the feature.\r
749\r
750 @param EAX CPUID_SERIAL_NUMBER (0x03)\r
751\r
752 @retval EAX Reserved.\r
753 @retval EBX Reserved.\r
754 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in\r
755 Pentium III processor only; otherwise, the value in this\r
756 register is reserved.)\r
757 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in\r
758 Pentium III processor only; otherwise, the value in this\r
759 register is reserved.)\r
760\r
761 <b>Example usage</b>\r
762 @code\r
763 UINT32 Ecx;\r
764 UINT32 Edx;\r
765\r
766 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
767 @endcode\r
768**/\r
769#define CPUID_SERIAL_NUMBER 0x03\r
770\r
771\r
772/**\r
773 CPUID Cache Parameters\r
774\r
775 @param EAX CPUID_CACHE_PARAMS (0x04)\r
776 @param ECX Cache Level. Valid values start at 0. Software can enumerate\r
777 the deterministic cache parameters for each level of the cache\r
778 hierarchy starting with an index value of 0, until the\r
779 parameters report the value associated with the CacheType\r
780 field in CPUID_CACHE_PARAMS_EAX is 0.\r
781\r
782 @retval EAX Returns cache type information described by the type\r
783 CPUID_CACHE_PARAMS_EAX.\r
784 @retval EBX Returns cache line and associativity information described by\r
785 the type CPUID_CACHE_PARAMS_EBX.\r
786 @retval ECX Returns the number of sets in the cache.\r
787 @retval EDX Returns cache WINVD/INVD behavior described by the type\r
788 CPUID_CACHE_PARAMS_EDX.\r
789\r
790 <b>Example usage</b>\r
791 @code\r
792 UINT32 CacheLevel;\r
793 CPUID_CACHE_PARAMS_EAX Eax;\r
794 CPUID_CACHE_PARAMS_EBX Ebx;\r
795 UINT32 Ecx;\r
796 CPUID_CACHE_PARAMS_EDX Edx;\r
797\r
798 CacheLevel = 0;\r
799 do {\r
800 AsmCpuidEx (\r
801 CPUID_CACHE_PARAMS, CacheLevel,\r
802 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
803 );\r
804 CacheLevel++;\r
805 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
806 @endcode\r
807**/\r
808#define CPUID_CACHE_PARAMS 0x04\r
809\r
810/**\r
811 CPUID Cache Parameters Information returned in EAX for CPUID leaf\r
812 #CPUID_CACHE_PARAMS.\r
813**/\r
814typedef union {\r
815 ///\r
816 /// Individual bit fields\r
817 ///\r
818 struct {\r
819 ///\r
820 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,\r
821 /// then there is no information for the requested cache level.\r
822 ///\r
823 UINT32 CacheType:5;\r
824 ///\r
825 /// [Bits 7:5] Cache level (Starts at 1).\r
826 ///\r
827 UINT32 CacheLevel:3;\r
828 ///\r
829 /// [Bit 8] Self Initializing cache level (does not need SW initialization).\r
830 ///\r
831 UINT32 SelfInitializingCache:1;\r
832 ///\r
833 /// [Bit 9] Fully Associative cache.\r
834 ///\r
835 UINT32 FullyAssociativeCache:1;\r
836 ///\r
837 /// [Bits 13:10] Reserved.\r
838 ///\r
839 UINT32 Reserved:4;\r
840 ///\r
841 /// [Bits 25:14] Maximum number of addressable IDs for logical processors\r
842 /// sharing this cache.\r
843 ///\r
844 /// Add one to the return value to get the result.\r
845 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])\r
846 /// is the number of unique initial APIC IDs reserved for addressing\r
847 /// different logical processors sharing this cache.\r
848 ///\r
849 UINT32 MaximumAddressableIdsForLogicalProcessors:12;\r
850 ///\r
851 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in\r
852 /// the physical package.\r
853 ///\r
854 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])\r
855 /// is the number of unique Core_IDs reserved for addressing different\r
856 /// processor cores in a physical package. Core ID is a subset of bits of\r
857 /// the initial APIC ID.\r
858 /// The returned value is constant for valid initial values in ECX. Valid\r
859 /// ECX values start from 0.\r
860 ///\r
861 UINT32 MaximumAddressableIdsForProcessorCores:6;\r
862 } Bits;\r
863 ///\r
864 /// All bit fields as a 32-bit value\r
865 ///\r
866 UINT32 Uint32;\r
867} CPUID_CACHE_PARAMS_EAX;\r
868\r
869///\r
870/// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType\r
871///\r
872#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00\r
873#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01\r
874#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02\r
875#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03\r
876///\r
877/// @}\r
878///\r
879\r
880/**\r
881 CPUID Cache Parameters Information returned in EBX for CPUID leaf\r
882 #CPUID_CACHE_PARAMS.\r
883**/\r
884typedef union {\r
885 ///\r
886 /// Individual bit fields\r
887 ///\r
888 struct {\r
889 ///\r
890 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to\r
891 /// get the result.\r
892 ///\r
893 UINT32 LineSize:12;\r
894 ///\r
895 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to\r
896 /// get the result.\r
897 ///\r
898 UINT32 LinePartitions:10;\r
899 ///\r
900 /// [Bits 31:22] Ways of associativity. Add one to the return value to get\r
901 /// the result.\r
902 ///\r
903 UINT32 Ways:10;\r
904 } Bits;\r
905 ///\r
906 /// All bit fields as a 32-bit value\r
907 ///\r
908 UINT32 Uint32;\r
909} CPUID_CACHE_PARAMS_EBX;\r
910\r
911/**\r
912 CPUID Cache Parameters Information returned in EDX for CPUID leaf\r
913 #CPUID_CACHE_PARAMS.\r
914**/\r
915typedef union {\r
916 ///\r
917 /// Individual bit fields\r
918 ///\r
919 struct {\r
920 ///\r
921 /// [Bit 0] Write-Back Invalidate/Invalidate.\r
922 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level\r
923 /// caches for threads sharing this cache.\r
924 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of\r
925 /// non-originating threads sharing this cache.\r
926 ///\r
927 UINT32 Invalidate:1;\r
928 ///\r
929 /// [Bit 1] Cache Inclusiveness.\r
930 /// 0 = Cache is not inclusive of lower cache levels.\r
931 /// 1 = Cache is inclusive of lower cache levels.\r
932 ///\r
933 UINT32 CacheInclusiveness:1;\r
934 ///\r
935 /// [Bit 2] Complex Cache Indexing.\r
936 /// 0 = Direct mapped cache.\r
937 /// 1 = A complex function is used to index the cache, potentially using all\r
938 /// address bits.\r
939 ///\r
940 UINT32 ComplexCacheIndexing:1;\r
941 UINT32 Reserved:29;\r
942 } Bits;\r
943 ///\r
944 /// All bit fields as a 32-bit value\r
945 ///\r
946 UINT32 Uint32;\r
947} CPUID_CACHE_PARAMS_EDX;\r
948\r
949\r
950/**\r
951 CPUID MONITOR/MWAIT Information\r
952\r
953 @param EAX CPUID_MONITOR_MWAIT (0x05)\r
954\r
955 @retval EAX Smallest monitor-line size in bytes described by the type\r
956 CPUID_MONITOR_MWAIT_EAX.\r
957 @retval EBX Largest monitor-line size in bytes described by the type\r
958 CPUID_MONITOR_MWAIT_EBX.\r
959 @retval ECX Enumeration of Monitor-Mwait extensions support described by\r
960 the type CPUID_MONITOR_MWAIT_ECX.\r
961 @retval EDX Sub C-states supported described by the type\r
962 CPUID_MONITOR_MWAIT_EDX.\r
963\r
964 <b>Example usage</b>\r
965 @code\r
966 CPUID_MONITOR_MWAIT_EAX Eax;\r
967 CPUID_MONITOR_MWAIT_EBX Ebx;\r
968 CPUID_MONITOR_MWAIT_ECX Ecx;\r
969 CPUID_MONITOR_MWAIT_EDX Edx;\r
970\r
971 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
972 @endcode\r
973**/\r
974#define CPUID_MONITOR_MWAIT 0x05\r
975\r
976/**\r
977 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf\r
978 #CPUID_MONITOR_MWAIT.\r
979**/\r
980typedef union {\r
981 ///\r
982 /// Individual bit fields\r
983 ///\r
984 struct {\r
985 ///\r
986 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's\r
987 /// monitor granularity).\r
988 ///\r
989 UINT32 SmallestMonitorLineSize:16;\r
990 UINT32 Reserved:16;\r
991 } Bits;\r
992 ///\r
993 /// All bit fields as a 32-bit value\r
994 ///\r
995 UINT32 Uint32;\r
996} CPUID_MONITOR_MWAIT_EAX;\r
997\r
998/**\r
999 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf\r
1000 #CPUID_MONITOR_MWAIT.\r
1001**/\r
1002typedef union {\r
1003 ///\r
1004 /// Individual bit fields\r
1005 ///\r
1006 struct {\r
1007 ///\r
1008 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's\r
1009 /// monitor granularity).\r
1010 ///\r
1011 UINT32 LargestMonitorLineSize:16;\r
1012 UINT32 Reserved:16;\r
1013 } Bits;\r
1014 ///\r
1015 /// All bit fields as a 32-bit value\r
1016 ///\r
1017 UINT32 Uint32;\r
1018} CPUID_MONITOR_MWAIT_EBX;\r
1019\r
1020/**\r
1021 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf\r
1022 #CPUID_MONITOR_MWAIT.\r
1023**/\r
1024typedef union {\r
1025 ///\r
1026 /// Individual bit fields\r
1027 ///\r
1028 struct {\r
1029 ///\r
1030 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,\r
1031 /// and EDX are valid.\r
1032 ///\r
1033 UINT32 ExtensionsSupported:1;\r
1034 ///\r
1035 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when\r
1036 /// interrupts disabled.\r
1037 ///\r
1038 UINT32 InterruptAsBreak:1;\r
1039 UINT32 Reserved:30;\r
1040 } Bits;\r
1041 ///\r
1042 /// All bit fields as a 32-bit value\r
1043 ///\r
1044 UINT32 Uint32;\r
1045} CPUID_MONITOR_MWAIT_ECX;\r
1046\r
1047/**\r
1048 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf\r
1049 #CPUID_MONITOR_MWAIT.\r
1050\r
1051 @note\r
1052 The definition of C0 through C7 states for MWAIT extension are\r
1053 processor-specific C-states, not ACPI C-states.\r
1054**/\r
1055typedef union {\r
1056 ///\r
1057 /// Individual bit fields\r
1058 ///\r
1059 struct {\r
1060 ///\r
1061 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.\r
1062 ///\r
1063 UINT32 C0States:4;\r
1064 ///\r
1065 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.\r
1066 ///\r
1067 UINT32 C1States:4;\r
1068 ///\r
1069 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.\r
1070 ///\r
1071 UINT32 C2States:4;\r
1072 ///\r
1073 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.\r
1074 ///\r
1075 UINT32 C3States:4;\r
1076 ///\r
1077 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.\r
1078 ///\r
1079 UINT32 C4States:4;\r
1080 ///\r
1081 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.\r
1082 ///\r
1083 UINT32 C5States:4;\r
1084 ///\r
1085 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.\r
1086 ///\r
1087 UINT32 C6States:4;\r
1088 ///\r
1089 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.\r
1090 ///\r
1091 UINT32 C7States:4;\r
1092 } Bits;\r
1093 ///\r
1094 /// All bit fields as a 32-bit value\r
1095 ///\r
1096 UINT32 Uint32;\r
1097} CPUID_MONITOR_MWAIT_EDX;\r
1098\r
1099\r
1100/**\r
1101 CPUID Thermal and Power Management\r
1102\r
1103 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)\r
1104\r
1105 @retval EAX Thermal and power management features described by the type\r
1106 CPUID_THERMAL_POWER_MANAGEMENT_EAX.\r
1107 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor\r
1108 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.\r
1109 @retval ECX Performance features described by the type\r
1110 CPUID_THERMAL_POWER_MANAGEMENT_ECX.\r
1111 @retval EDX Reserved.\r
1112\r
1113 <b>Example usage</b>\r
1114 @code\r
1115 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r
1116 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r
1117 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r
1118\r
1119 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
1120 @endcode\r
1121**/\r
1122#define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r
1123\r
1124/**\r
1125 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf\r
1126 #CPUID_THERMAL_POWER_MANAGEMENT.\r
1127**/\r
1128typedef union {\r
1129 ///\r
1130 /// Individual bit fields\r
1131 ///\r
1132 struct {\r
1133 ///\r
1134 /// [Bit 0] Digital temperature sensor is supported if set.\r
1135 ///\r
1136 UINT32 DigitalTemperatureSensor:1;\r
1137 ///\r
1138 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).\r
1139 ///\r
1140 UINT32 TurboBoostTechnology:1;\r
1141 ///\r
1142 /// [Bit 2] APIC-Timer-always-running feature is supported if set.\r
1143 ///\r
1144 UINT32 ARAT:1;\r
1145 UINT32 Reserved1:1;\r
1146 ///\r
1147 /// [Bit 4] Power limit notification controls are supported if set.\r
1148 ///\r
1149 UINT32 PLN:1;\r
1150 ///\r
1151 /// [Bit 5] Clock modulation duty cycle extension is supported if set.\r
1152 ///\r
1153 UINT32 ECMD:1;\r
1154 ///\r
1155 /// [Bit 6] Package thermal management is supported if set.\r
1156 ///\r
1157 UINT32 PTM:1;\r
1158 ///\r
1159 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,\r
1160 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r
1161 ///\r
1162 UINT32 HWP:1;\r
1163 ///\r
1164 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.\r
1165 ///\r
1166 UINT32 HWP_Notification:1;\r
1167 ///\r
1168 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.\r
1169 ///\r
1170 UINT32 HWP_Activity_Window:1;\r
1171 ///\r
1172 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.\r
1173 ///\r
1174 UINT32 HWP_Energy_Performance_Preference:1;\r
1175 ///\r
1176 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.\r
1177 ///\r
1178 UINT32 HWP_Package_Level_Request:1;\r
1179 UINT32 Reserved2:1;\r
1180 ///\r
1181 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,\r
1182 /// IA32_THREAD_STALL MSRs are supported if set.\r
1183 ///\r
1184 UINT32 HDC:1;\r
1185 UINT32 Reserved3:18;\r
1186 } Bits;\r
1187 ///\r
1188 /// All bit fields as a 32-bit value\r
1189 ///\r
1190 UINT32 Uint32;\r
1191} CPUID_THERMAL_POWER_MANAGEMENT_EAX;\r
1192\r
1193/**\r
1194 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf\r
1195 #CPUID_THERMAL_POWER_MANAGEMENT.\r
1196**/\r
1197typedef union {\r
1198 ///\r
1199 /// Individual bit fields\r
1200 ///\r
1201 struct {\r
1202 ///\r
1203 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.\r
1204 ///\r
1205 UINT32 InterruptThresholds:4;\r
1206 UINT32 Reserved:28;\r
1207 } Bits;\r
1208 ///\r
1209 /// All bit fields as a 32-bit value\r
1210 ///\r
1211 UINT32 Uint32;\r
1212} CPUID_THERMAL_POWER_MANAGEMENT_EBX;\r
1213\r
1214/**\r
1215 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf\r
1216 #CPUID_THERMAL_POWER_MANAGEMENT.\r
1217**/\r
1218typedef union {\r
1219 ///\r
1220 /// Individual bit fields\r
1221 ///\r
1222 struct {\r
1223 ///\r
1224 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF\r
1225 /// and IA32_APERF). The capability to provide a measure of delivered\r
1226 /// processor performance (since last reset of the counters), as a percentage\r
1227 /// of the expected processor performance when running at the TSC frequency.\r
1228 ///\r
1229 UINT32 HardwareCoordinationFeedback:1;\r
1230 UINT32 Reserved1:2;\r
1231 ///\r
1232 /// [Bit 3] If this bit is set, then the processor supports performance-energy\r
1233 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS\r
1234 /// (1B0H).\r
1235 ///\r
1236 UINT32 PerformanceEnergyBias:1;\r
1237 UINT32 Reserved2:28;\r
1238 } Bits;\r
1239 ///\r
1240 /// All bit fields as a 32-bit value\r
1241 ///\r
1242 UINT32 Uint32;\r
1243} CPUID_THERMAL_POWER_MANAGEMENT_ECX;\r
1244\r
1245\r
1246/**\r
1247 CPUID Structured Extended Feature Flags Enumeration\r
1248\r
1249 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)\r
1250 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).\r
1251\r
1252 @note\r
1253 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
1254 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.\r
1255\r
1256 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.\r
1257 @retval EBX Structured Extended Feature Flags described by the type\r
1258 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.\r
1259 @retval EBX Structured Extended Feature Flags described by the type\r
1260 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.\r
1261 @retval EDX Reserved.\r
1262\r
1263 <b>Example usage</b>\r
1264 @code\r
1265 UINT32 Eax;\r
1266 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
1267 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r
1268 UINT32 SubLeaf;\r
1269\r
1270 AsmCpuidEx (\r
1271 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
1272 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
1273 &Eax, NULL, NULL, NULL\r
1274 );\r
1275 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
1276 AsmCpuidEx (\r
1277 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
1278 SubLeaf,\r
1279 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r
1280 );\r
d93a10c0 1281 }\r
57d16ba1
MK
1282 @endcode\r
1283**/\r
1284#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
1285\r
1286///\r
1287/// CPUID Structured Extended Feature Flags Enumeration sub-leaf\r
1288///\r
1289#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00\r
1290\r
1291/**\r
1292 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf\r
1293 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r
1294 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r
1295**/\r
1296typedef union {\r
1297 ///\r
1298 /// Individual bit fields\r
1299 ///\r
1300 struct {\r
1301 ///\r
1302 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r
1303 ///\r
1304 UINT32 FSGSBASE:1;\r
1305 ///\r
1306 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r
1307 ///\r
1308 UINT32 IA32_TSC_ADJUST:1;\r
c606a9a5
JF
1309 ///\r
1310 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT\r
1311 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".\r
1312 ///\r
1313 UINT32 SGX:1;\r
57d16ba1
MK
1314 ///\r
1315 /// [Bit 3] If 1 indicates the processor supports the first group of advanced\r
1316 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r
1317 ///\r
1318 UINT32 BMI1:1;\r
1319 ///\r
1320 /// [Bit 4] Hardware Lock Elision\r
1321 ///\r
1322 UINT32 HLE:1;\r
1323 ///\r
1324 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.\r
1325 ///\r
1326 UINT32 AVX2:1;\r
1327 ///\r
1328 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.\r
1329 ///\r
1330 UINT32 FDP_EXCPTN_ONLY:1;\r
1331 ///\r
1332 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.\r
1333 ///\r
1334 UINT32 SMEP:1;\r
1335 ///\r
1336 /// [Bit 8] If 1 indicates the processor supports the second group of\r
1337 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,\r
1338 /// SARX, SHLX, SHRX)\r
1339 ///\r
1340 UINT32 BMI2:1;\r
1341 ///\r
1342 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.\r
1343 ///\r
1344 UINT32 EnhancedRepMovsbStosb:1;\r
1345 ///\r
1346 /// [Bit 10] If 1, supports INVPCID instruction for system software that\r
1347 /// manages process-context identifiers.\r
1348 ///\r
1349 UINT32 INVPCID:1;\r
1350 ///\r
1351 /// [Bit 11] Restricted Transactional Memory\r
1352 ///\r
1353 UINT32 RTM:1;\r
1354 ///\r
14806d7b
HW
1355 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
1356 /// Monitoring capability if 1.\r
57d16ba1 1357 ///\r
14806d7b 1358 UINT32 RDT_M:1;\r
57d16ba1
MK
1359 ///\r
1360 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
1361 ///\r
1362 UINT32 DeprecateFpuCsDs:1;\r
1363 ///\r
1364 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.\r
1365 ///\r
1366 UINT32 MPX:1;\r
1367 ///\r
14806d7b
HW
1368 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
1369 /// Allocation capability if 1.\r
57d16ba1 1370 ///\r
14806d7b 1371 UINT32 RDT_A:1;\r
57d16ba1
MK
1372 UINT32 Reserved2:2;\r
1373 ///\r
1374 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
1375 ///\r
1376 UINT32 RDSEED:1;\r
1377 ///\r
1378 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX\r
1379 /// instructions.\r
1380 ///\r
1381 UINT32 ADX:1;\r
1382 ///\r
1383 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC\r
1384 /// instructions) if 1.\r
1385 ///\r
1386 UINT32 SMAP:1;\r
1387 UINT32 Reserved3:2;\r
1388 ///\r
1389 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
1390 ///\r
1391 UINT32 CLFLUSHOPT:1;\r
14806d7b
HW
1392 ///\r
1393 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.\r
1394 ///\r
1395 UINT32 CLWB:1;\r
57d16ba1
MK
1396 ///\r
1397 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
1398 /// extensions.\r
1399 ///\r
1400 UINT32 IntelProcessorTrace:1;\r
14806d7b
HW
1401 UINT32 Reserved4:3;\r
1402 ///\r
1403 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)\r
1404 /// SHA Extensions) if 1.\r
1405 ///\r
1406 UINT32 SHA:1;\r
1407 UINT32 Reserved5:2;\r
57d16ba1
MK
1408 } Bits;\r
1409 ///\r
1410 /// All bit fields as a 32-bit value\r
1411 ///\r
1412 UINT32 Uint32;\r
1413} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;\r
1414\r
1415/**\r
1416 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf\r
1417 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r
1418 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r
1419**/\r
1420typedef union {\r
1421 ///\r
1422 /// Individual bit fields\r
1423 ///\r
1424 struct {\r
1425 ///\r
1426 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
1427 ///\r
1428 UINT32 PREFETCHWT1:1;\r
14806d7b
HW
1429 UINT32 Reserved1:1;\r
1430 ///\r
1431 /// [Bit 2] Supports user-mode instruction prevention if 1.\r
1432 ///\r
1433 UINT32 UMIP:1;\r
57d16ba1
MK
1434 ///\r
1435 /// [Bit 3] Supports protection keys for user-mode pages if 1.\r
1436 ///\r
1437 UINT32 PKU:1;\r
1438 ///\r
1439 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the\r
1440 /// RDPKRU/WRPKRU instructions).\r
1441 ///\r
1442 UINT32 OSPKE:1;\r
14806d7b
HW
1443 UINT32 Reserved2:12;\r
1444 ///\r
1445 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
1446 /// in 64-bit mode.\r
1447 ///\r
1448 UINT32 MAWAU:5;\r
1449 ///\r
1450 /// [Bit 22] Supports Read Processor ID if 1.\r
1451 ///\r
1452 UINT32 RDPID:1;\r
1453 UINT32 Reserved3:7;\r
1454 ///\r
1455 /// [Bit 30] Supports SGX Launch Configuration if 1.\r
1456 ///\r
1457 UINT32 SGX_LC:1;\r
1458 UINT32 Reserved4:1;\r
57d16ba1
MK
1459 } Bits;\r
1460 ///\r
1461 /// All bit fields as a 32-bit value\r
1462 ///\r
1463 UINT32 Uint32;\r
1464} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r
1465\r
1466\r
1467/**\r
1468 CPUID Direct Cache Access Information\r
1469\r
1470 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)\r
1471\r
1472 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).\r
1473 @retval EBX Reserved.\r
1474 @retval ECX Reserved.\r
1475 @retval EDX Reserved.\r
1476\r
1477 <b>Example usage</b>\r
1478 @code\r
1479 UINT32 Eax;\r
1480\r
1481 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
1482 @endcode\r
1483**/\r
1484#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r
1485\r
1486\r
1487/**\r
1488 CPUID Architectural Performance Monitoring\r
1489\r
1490 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)\r
1491\r
1492 @retval EAX Architectural Performance Monitoring information described by\r
1493 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.\r
1494 @retval EBX Architectural Performance Monitoring information described by\r
1495 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.\r
1496 @retval ECX Reserved.\r
1497 @retval EDX Architectural Performance Monitoring information described by\r
1498 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.\r
1499\r
1500 <b>Example usage</b>\r
1501 @code\r
1502 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r
1503 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r
1504 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r
1505\r
1506 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r
1507 @endcode\r
1508**/\r
1509#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A\r
1510\r
1511/**\r
1512 CPUID Architectural Performance Monitoring EAX for CPUID leaf\r
1513 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
1514**/\r
1515typedef union {\r
1516 ///\r
1517 /// Individual bit fields\r
1518 ///\r
1519 struct {\r
1520 ///\r
1521 /// [Bit 7:0] Version ID of architectural performance monitoring.\r
1522 ///\r
1523 UINT32 ArchPerfMonVerID:8;\r
1524 ///\r
1525 /// [Bits 15:8] Number of general-purpose performance monitoring counter\r
1526 /// per logical processor.\r
1527 ///\r
1528 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous\r
1529 /// block of MSR address space. Each performance event select register is\r
1530 /// paired with a corresponding performance counter in the 0C1H address\r
1531 /// block.\r
1532 ///\r
1533 UINT32 PerformanceMonitorCounters:8;\r
1534 ///\r
1535 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r
1536 ///\r
1537 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for\r
1538 /// read operation. On write operations, the lower-order 32 bits of the MSR\r
1539 /// may be written with any value, and the high-order bits are sign-extended\r
1540 /// from the value of bit 31.\r
1541 ///\r
1542 UINT32 PerformanceMonitorCounterWidth:8;\r
1543 ///\r
1544 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r
1545 /// performance monitoring events.\r
1546 ///\r
1547 UINT32 EbxBitVectorLength:8;\r
1548 } Bits;\r
1549 ///\r
1550 /// All bit fields as a 32-bit value\r
1551 ///\r
1552 UINT32 Uint32;\r
1553} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r
1554\r
1555/**\r
1556 CPUID Architectural Performance Monitoring EBX for CPUID leaf\r
1557 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
1558**/\r
1559typedef union {\r
1560 ///\r
1561 /// Individual bit fields\r
1562 ///\r
1563 struct {\r
1564 ///\r
1565 /// [Bit 0] Core cycle event not available if 1.\r
1566 ///\r
1567 UINT32 UnhaltedCoreCycles:1;\r
1568 ///\r
1569 /// [Bit 1] Instruction retired event not available if 1.\r
1570 ///\r
1571 UINT32 InstructionsRetired:1;\r
1572 ///\r
1573 /// [Bit 2] Reference cycles event not available if 1.\r
1574 ///\r
1575 UINT32 UnhaltedReferenceCycles:1;\r
1576 ///\r
1577 /// [Bit 3] Last-level cache reference event not available if 1.\r
1578 ///\r
1579 UINT32 LastLevelCacheReferences:1;\r
1580 ///\r
1581 /// [Bit 4] Last-level cache misses event not available if 1.\r
1582 ///\r
1583 UINT32 LastLevelCacheMisses:1;\r
1584 ///\r
1585 /// [Bit 5] Branch instruction retired event not available if 1.\r
1586 ///\r
1587 UINT32 BranchInstructionsRetired:1;\r
1588 ///\r
1589 /// [Bit 6] Branch mispredict retired event not available if 1.\r
1590 ///\r
1591 UINT32 AllBranchMispredictRetired:1;\r
1592 UINT32 Reserved:25;\r
1593 } Bits;\r
1594 ///\r
1595 /// All bit fields as a 32-bit value\r
1596 ///\r
1597 UINT32 Uint32;\r
1598} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r
1599\r
1600/**\r
1601 CPUID Architectural Performance Monitoring EDX for CPUID leaf\r
1602 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
1603**/\r
1604typedef union {\r
1605 ///\r
1606 /// Individual bit fields\r
1607 ///\r
1608 struct {\r
1609 ///\r
1610 /// [Bits 4:0] Number of fixed-function performance counters\r
1611 /// (if Version ID > 1).\r
1612 ///\r
1613 UINT32 FixedFunctionPerformanceCounters:5;\r
1614 ///\r
1615 /// [Bits 12:5] Bit width of fixed-function performance counters\r
1616 /// (if Version ID > 1).\r
1617 ///\r
1618 UINT32 FixedFunctionPerformanceCounterWidth:8;\r
1619 UINT32 Reserved:19;\r
1620 } Bits;\r
1621 ///\r
1622 /// All bit fields as a 32-bit value\r
1623 ///\r
1624 UINT32 Uint32;\r
1625} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r
1626\r
1627\r
1628/**\r
1629 CPUID Extended Topology Information\r
1630\r
1631 @note\r
1632 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output\r
1633 of leaf 0BH is always valid and does not vary with input value in ECX. Output\r
1634 value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that\r
1635 return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If\r
1636 an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r
1637 other input values with ECX > n also return 0 in ECX[15:8].\r
1638\r
1639 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)\r
1640 @param ECX Level number\r
1641\r
1642 @retval EAX Extended topology information described by the type\r
1643 CPUID_EXTENDED_TOPOLOGY_EAX.\r
1644 @retval EBX Extended topology information described by the type\r
1645 CPUID_EXTENDED_TOPOLOGY_EBX.\r
1646 @retval ECX Extended topology information described by the type\r
1647 CPUID_EXTENDED_TOPOLOGY_ECX.\r
1648 @retval EDX x2APIC ID the current logical processor.\r
1649\r
1650 <b>Example usage</b>\r
1651 @code\r
1652 CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
1653 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r
1654 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r
1655 UINT32 Edx;\r
1656 UINT32 LevelNumber;\r
1657\r
1658 LevelNumber = 0;\r
1659 do {\r
1660 AsmCpuidEx (\r
1661 CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r
1662 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
1663 );\r
1664 LevelNumber++;\r
1665 } while (Eax.Bits.ApicIdShift != 0);\r
1666 @endcode\r
1667**/\r
1668#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
1669\r
1670/**\r
1671 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
1672**/\r
1673typedef union {\r
1674 ///\r
1675 /// Individual bit fields\r
1676 ///\r
1677 struct {\r
1678 ///\r
1679 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique\r
1680 /// topology ID of the next level type. All logical processors with the\r
1681 /// same next level ID share current level.\r
1682 ///\r
1683 /// @note\r
1684 /// Software should use this field (EAX[4:0]) to enumerate processor\r
1685 /// topology of the system.\r
1686 ///\r
1687 UINT32 ApicIdShift:5;\r
1688 UINT32 Reserved:27;\r
1689 } Bits;\r
1690 ///\r
1691 /// All bit fields as a 32-bit value\r
1692 ///\r
1693 UINT32 Uint32;\r
1694} CPUID_EXTENDED_TOPOLOGY_EAX;\r
1695\r
1696/**\r
1697 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
1698**/\r
1699typedef union {\r
1700 ///\r
1701 /// Individual bit fields\r
1702 ///\r
1703 struct {\r
1704 ///\r
1705 /// [Bits 15:0] Number of logical processors at this level type. The number\r
1706 /// reflects configuration as shipped by Intel.\r
1707 ///\r
1708 /// @note\r
1709 /// Software must not use EBX[15:0] to enumerate processor topology of the\r
1710 /// system. This value in this field (EBX[15:0]) is only intended for\r
1711 /// display/diagnostic purposes. The actual number of logical processors\r
1712 /// available to BIOS/OS/Applications may be different from the value of\r
1713 /// EBX[15:0], depending on software and platform hardware configurations.\r
1714 ///\r
1715 UINT32 LogicalProcessors:16;\r
1716 UINT32 Reserved:16;\r
1717 } Bits;\r
1718 ///\r
1719 /// All bit fields as a 32-bit value\r
1720 ///\r
1721 UINT32 Uint32;\r
1722} CPUID_EXTENDED_TOPOLOGY_EBX;\r
1723\r
1724/**\r
1725 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
1726**/\r
1727typedef union {\r
1728 ///\r
1729 /// Individual bit fields\r
1730 ///\r
1731 struct {\r
1732 ///\r
1733 /// [Bits 7:0] Level number. Same value in ECX input.\r
1734 ///\r
1735 UINT32 LevelNumber:8;\r
1736 ///\r
1737 /// [Bits 15:8] Level type.\r
1738 ///\r
1739 /// @note\r
1740 /// The value of the "level type" field is not related to level numbers in\r
1741 /// any way, higher "level type" values do not mean higher levels.\r
1742 ///\r
1743 UINT32 LevelType:8;\r
1744 UINT32 Reserved:16;\r
1745 } Bits;\r
1746 ///\r
1747 /// All bit fields as a 32-bit value\r
1748 ///\r
1749 UINT32 Uint32;\r
1750} CPUID_EXTENDED_TOPOLOGY_ECX;\r
1751\r
1752///\r
1753/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
1754///\r
1755#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
1756#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
1757#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
1758///\r
1759/// @}\r
1760///\r
1761\r
1762\r
1763/**\r
1764 CPUID Extended State Information\r
1765\r
1766 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1767 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).\r
1768 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).\r
1769 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r
1770 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r
1771**/\r
1772#define CPUID_EXTENDED_STATE 0x0D\r
1773\r
1774/**\r
1775 CPUID Extended State Information Main Leaf\r
1776\r
1777 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1778 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)\r
1779\r
1780 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]\r
1781 can be set to 1 only if EAX[n] is 1. The format of the extended\r
1782 state main leaf is described by the type\r
1783 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.\r
1784 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
1785 area) required by enabled features in XCR0. May be different than\r
1786 ECX if some features at the end of the XSAVE save area are not\r
1787 enabled.\r
1788 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
1789 area) of the XSAVE/XRSTOR save area required by all supported\r
14806d7b 1790 features in the processor, i.e., all the valid bit fields in XCR0.\r
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1791 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r
1792 XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
1793\r
1794 <b>Example usage</b>\r
1795 @code\r
1796 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r
1797 UINT32 Ebx;\r
1798 UINT32 Ecx;\r
1799 UINT32 Edx;\r
1800\r
1801 AsmCpuidEx (\r
1802 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
1803 &Eax.Uint32, &Ebx, &Ecx, &Edx\r
1804 );\r
1805 @endcode\r
1806**/\r
1807#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
1808\r
1809/**\r
1810 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1811 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.\r
1812**/\r
1813typedef union {\r
1814 ///\r
1815 /// Individual bit fields\r
1816 ///\r
1817 struct {\r
1818 ///\r
1819 /// [Bit 0] x87 state.\r
1820 ///\r
1821 UINT32 x87:1;\r
1822 ///\r
1823 /// [Bit 1] SSE state.\r
1824 ///\r
1825 UINT32 SSE:1;\r
1826 ///\r
1827 /// [Bit 2] AVX state.\r
1828 ///\r
1829 UINT32 AVX:1;\r
1830 ///\r
1831 /// [Bits 4:3] MPX state.\r
1832 ///\r
1833 UINT32 MPX:2;\r
1834 ///\r
1835 /// [Bits 7:5] AVX-512 state.\r
1836 ///\r
1837 UINT32 AVX_512:3;\r
1838 ///\r
1839 /// [Bit 8] Used for IA32_XSS.\r
1840 ///\r
1841 UINT32 IA32_XSS:1;\r
1842 ///\r
1843 /// [Bit 9] PKRU state.\r
1844 ///\r
1845 UINT32 PKRU:1;\r
1846 UINT32 Reserved:22;\r
1847 } Bits;\r
1848 ///\r
1849 /// All bit fields as a 32-bit value\r
1850 ///\r
1851 UINT32 Uint32;\r
1852} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r
1853\r
1854/**\r
1855 CPUID Extended State Information Sub Leaf\r
1856\r
1857 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1858 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)\r
1859\r
1860 @retval EAX The format of the extended state sub-leaf is described by the\r
1861 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.\r
1862 @retval EBX The size in bytes of the XSAVE area containing all states\r
1863 enabled by XCRO | IA32_XSS.\r
1864 @retval ECX The format of the extended state sub-leaf is described by the\r
1865 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.\r
1866 @retval EDX Reports the supported bits of the upper 32 bits of the\r
1867 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.\r
1868\r
1869 <b>Example usage</b>\r
1870 @code\r
1871 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r
1872 UINT32 Ebx;\r
1873 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r
1874 UINT32 Edx;\r
1875\r
1876 AsmCpuidEx (\r
1877 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
1878 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
1879 );\r
1880 @endcode\r
1881**/\r
1882#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
1883\r
1884/**\r
1885 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1886 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
1887**/\r
1888typedef union {\r
1889 ///\r
1890 /// Individual bit fields\r
1891 ///\r
1892 struct {\r
1893 ///\r
1894 /// [Bit 0] XSAVEOPT is available.\r
1895 ///\r
1896 UINT32 XSAVEOPT:1;\r
1897 ///\r
1898 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r
1899 ///\r
1900 UINT32 XSAVEC:1;\r
1901 ///\r
1902 /// [Bit 2] Supports XGETBV with ECX = 1 if set.\r
1903 ///\r
1904 UINT32 XGETBV:1;\r
1905 ///\r
1906 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r
1907 ///\r
1908 UINT32 XSAVES:1;\r
1909 UINT32 Reserved:28;\r
1910 } Bits;\r
1911 ///\r
1912 /// All bit fields as a 32-bit value\r
1913 ///\r
1914 UINT32 Uint32;\r
1915} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r
1916\r
1917/**\r
1918 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1919 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
1920**/\r
1921typedef union {\r
1922 ///\r
1923 /// Individual bit fields\r
1924 ///\r
1925 struct {\r
1926 ///\r
1927 /// [Bits 7:0] Used for XCR0.\r
1928 ///\r
1929 UINT32 XCR0:1;\r
1930 ///\r
1931 /// [Bit 8] PT STate.\r
1932 ///\r
1933 UINT32 PT:1;\r
1934 ///\r
1935 /// [Bit 9] Used for XCR0.\r
1936 ///\r
1937 UINT32 XCR0_1:1;\r
1938 UINT32 Reserved:22;\r
1939 } Bits;\r
1940 ///\r
1941 /// All bit fields as a 32-bit value\r
1942 ///\r
1943 UINT32 Uint32;\r
1944} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r
1945\r
1946/**\r
1947 CPUID Extended State Information Size and Offset Sub Leaf\r
1948\r
1949 @note\r
1950 Leaf 0DH output depends on the initial value in ECX.\r
1951 Each sub-leaf index (starting at position 2) is supported if it corresponds to\r
1952 a supported bit in either the XCR0 register or the IA32_XSS MSR.\r
1953 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
1954 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1\r
1955 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0\r
1956 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].\r
1957\r
1958 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1959 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based\r
1960 on supported bits in XCR0 or IA32_XSS_MSR.\r
1961\r
1962 @retval EAX The size in bytes (from the offset specified in EBX) of the save\r
1963 area for an extended state feature associated with a valid\r
1964 sub-leaf index, n.\r
1965 @retval EBX The offset in bytes of this extended state component's save area\r
1966 from the beginning of the XSAVE/XRSTOR area. This field reports\r
1967 0 if the sub-leaf index, n, does not map to a valid bit in the\r
1968 XCR0 register.\r
1969 @retval ECX The format of the extended state components's save area as\r
1970 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.\r
1971 This field reports 0 if the sub-leaf index, n, is invalid.\r
1972 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;\r
1973 otherwise it is reserved.\r
1974\r
1975 <b>Example usage</b>\r
1976 @code\r
1977 UINT32 Eax;\r
1978 UINT32 Ebx;\r
1979 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r
1980 UINT32 Edx;\r
1981 UINTN SubLeaf;\r
1982\r
1983 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
1984 AsmCpuidEx (\r
1985 CPUID_EXTENDED_STATE, SubLeaf,\r
1986 &Eax, &Ebx, &Ecx.Uint32, &Edx\r
1987 );\r
1988 }\r
1989 @endcode\r
1990**/\r
1991#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
1992\r
1993/**\r
1994 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1995 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.\r
1996**/\r
1997typedef union {\r
1998 ///\r
1999 /// Individual bit fields\r
2000 ///\r
2001 struct {\r
2002 ///\r
2003 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is\r
2004 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r
2005 /// in XCR0.\r
2006 ///\r
2007 UINT32 XSS:1;\r
2008 ///\r
2009 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r
2010 /// this extended state component located on the next 64-byte boundary\r
2011 /// following the preceding state component (otherwise, it is located\r
2012 /// immediately following the preceding state component).\r
2013 ///\r
2014 UINT32 Compacted:1;\r
2015 UINT32 Reserved:30;\r
2016 } Bits;\r
2017 ///\r
2018 /// All bit fields as a 32-bit value\r
2019 ///\r
2020 UINT32 Uint32;\r
2021} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r
2022\r
2023\r
2024/**\r
14806d7b 2025 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
57d16ba1 2026\r
14806d7b
HW
2027 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
2028 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
2029 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r
57d16ba1
MK
2030\r
2031**/\r
14806d7b 2032#define CPUID_INTEL_RDT_MONITORING 0x0F\r
57d16ba1
MK
2033\r
2034/**\r
14806d7b
HW
2035 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
2036 Enumeration Sub-leaf\r
57d16ba1 2037\r
14806d7b
HW
2038 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
2039 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
57d16ba1
MK
2040\r
2041 @retval EAX Reserved.\r
2042 @retval EBX Maximum range (zero-based) of RMID within this physical\r
2043 processor of all types.\r
2044 @retval ECX Reserved.\r
14806d7b
HW
2045 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by\r
2046 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
57d16ba1
MK
2047\r
2048 <b>Example usage</b>\r
2049 @code\r
2050 UINT32 Ebx;\r
14806d7b 2051 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
57d16ba1
MK
2052\r
2053 AsmCpuidEx (\r
14806d7b 2054 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
57d16ba1
MK
2055 NULL, &Ebx, NULL, &Edx.Uint32\r
2056 );\r
2057 @endcode\r
2058**/\r
14806d7b 2059#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
57d16ba1
MK
2060\r
2061/**\r
14806d7b
HW
2062 CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r
2063 #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
2064 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.\r
57d16ba1
MK
2065**/\r
2066typedef union {\r
2067 ///\r
2068 /// Individual bit fields\r
2069 ///\r
2070 struct {\r
2071 UINT32 Reserved1:1;\r
2072 ///\r
14806d7b 2073 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r
57d16ba1 2074 ///\r
14806d7b 2075 UINT32 L3CacheRDT_M:1;\r
57d16ba1
MK
2076 UINT32 Reserved2:30;\r
2077 } Bits;\r
2078 ///\r
2079 /// All bit fields as a 32-bit value\r
2080 ///\r
2081 UINT32 Uint32;\r
14806d7b 2082} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
57d16ba1
MK
2083\r
2084/**\r
14806d7b 2085 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf\r
57d16ba1 2086\r
14806d7b
HW
2087 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
2088 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)\r
57d16ba1
MK
2089\r
2090 @retval EAX Reserved.\r
2091 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
2092 @retval ECX Maximum range (zero-based) of RMID of this resource type.\r
14806d7b
HW
2093 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the\r
2094 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.\r
57d16ba1
MK
2095\r
2096 <b>Example usage</b>\r
2097 @code\r
14806d7b
HW
2098 UINT32 Ebx;\r
2099 UINT32 Ecx;\r
2100 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
57d16ba1
MK
2101\r
2102 AsmCpuidEx (\r
14806d7b 2103 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
57d16ba1
MK
2104 NULL, &Ebx, &Ecx, &Edx.Uint32\r
2105 );\r
2106 @endcode\r
2107**/\r
14806d7b 2108#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
57d16ba1
MK
2109\r
2110/**\r
14806d7b
HW
2111 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r
2112 #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
2113 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.\r
57d16ba1
MK
2114**/\r
2115typedef union {\r
2116 ///\r
2117 /// Individual bit fields\r
2118 ///\r
2119 struct {\r
2120 ///\r
2121 /// [Bit 0] Supports L3 occupancy monitoring if 1.\r
2122 ///\r
2123 UINT32 L3CacheOccupancyMonitoring:1;\r
14806d7b
HW
2124 ///\r
2125 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r
2126 ///\r
2127 UINT32 L3CacheTotalBandwidthMonitoring:1;\r
2128 ///\r
2129 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r
2130 ///\r
2131 UINT32 L3CacheLocalBandwidthMonitoring:1;\r
2132 UINT32 Reserved:29;\r
57d16ba1
MK
2133 } Bits;\r
2134 ///\r
2135 /// All bit fields as a 32-bit value\r
2136 ///\r
2137 UINT32 Uint32;\r
14806d7b 2138} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r
57d16ba1
MK
2139\r
2140\r
2141/**\r
14806d7b 2142 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r
57d16ba1 2143\r
14806d7b
HW
2144 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).\r
2145 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
2146 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r
2147 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r
57d16ba1 2148**/\r
14806d7b 2149#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
57d16ba1
MK
2150\r
2151/**\r
14806d7b 2152 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r
57d16ba1 2153\r
14806d7b
HW
2154 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
2155 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
57d16ba1
MK
2156\r
2157 @retval EAX Reserved.\r
14806d7b
HW
2158 @retval EBX L3 and L2 Cache Allocation Technology information described by\r
2159 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.\r
57d16ba1
MK
2160 @retval ECX Reserved.\r
2161 @retval EDX Reserved.\r
2162\r
2163 <b>Example usage</b>\r
2164 @code\r
14806d7b 2165 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r
57d16ba1
MK
2166\r
2167 AsmCpuidEx (\r
14806d7b 2168 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
57d16ba1
MK
2169 NULL, &Ebx.Uint32, NULL, NULL\r
2170 );\r
2171 @endcode\r
2172**/\r
14806d7b 2173#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
57d16ba1
MK
2174\r
2175/**\r
14806d7b
HW
2176 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r
2177 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
2178 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.\r
57d16ba1
MK
2179**/\r
2180typedef union {\r
2181 ///\r
2182 /// Individual bit fields\r
2183 ///\r
2184 struct {\r
2185 UINT32 Reserved1:1;\r
2186 ///\r
14806d7b 2187 /// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r
57d16ba1 2188 ///\r
14806d7b
HW
2189 UINT32 L3CacheAllocation:1;\r
2190 ///\r
2191 /// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r
2192 ///\r
2193 UINT32 L2CacheAllocation:1;\r
2194 UINT32 Reserved2:29;\r
57d16ba1
MK
2195 } Bits;\r
2196 ///\r
2197 /// All bit fields as a 32-bit value\r
2198 ///\r
2199 UINT32 Uint32;\r
14806d7b 2200} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r
57d16ba1
MK
2201\r
2202\r
2203/**\r
14806d7b 2204 L3 Cache Allocation Technology Enumeration Sub-leaf\r
57d16ba1 2205\r
14806d7b
HW
2206 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
2207 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)\r
57d16ba1 2208\r
14806d7b
HW
2209 @retval EAX RESID L3 Cache Allocation Technology information described by\r
2210 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.\r
57d16ba1 2211 @retval EBX Bit-granular map of isolation/contention of allocation units.\r
14806d7b
HW
2212 @retval ECX RESID L3 Cache Allocation Technology information described by\r
2213 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.\r
2214 @retval EDX RESID L3 Cache Allocation Technology information described by\r
2215 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.\r
57d16ba1
MK
2216\r
2217 <b>Example usage</b>\r
2218 @code\r
14806d7b 2219 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r
57d16ba1 2220 UINT32 Ebx;\r
14806d7b
HW
2221 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r
2222 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
57d16ba1
MK
2223\r
2224 AsmCpuidEx (\r
14806d7b 2225 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
57d16ba1
MK
2226 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
2227 );\r
2228 @endcode\r
2229**/\r
14806d7b 2230#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
57d16ba1
MK
2231\r
2232/**\r
14806d7b
HW
2233 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r
2234 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
2235 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
57d16ba1
MK
2236**/\r
2237typedef union {\r
2238 ///\r
2239 /// Individual bit fields\r
2240 ///\r
2241 struct {\r
2242 ///\r
14806d7b
HW
2243 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
2244 /// using minus-one notation.\r
57d16ba1 2245 ///\r
14806d7b
HW
2246 UINT32 CapacityLength:5;\r
2247 UINT32 Reserved:27;\r
57d16ba1
MK
2248 } Bits;\r
2249 ///\r
2250 /// All bit fields as a 32-bit value\r
2251 ///\r
2252 UINT32 Uint32;\r
14806d7b 2253} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r
57d16ba1
MK
2254\r
2255/**\r
14806d7b
HW
2256 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf\r
2257 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
2258 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
57d16ba1
MK
2259**/\r
2260typedef union {\r
2261 ///\r
2262 /// Individual bit fields\r
2263 ///\r
2264 struct {\r
2265 UINT32 Reserved1:1;\r
2266 ///\r
2267 /// [Bit 1] Updates of COS should be infrequent if 1.\r
2268 ///\r
2269 UINT32 CosUpdatesInfrequent:1;\r
2270 ///\r
2271 /// [Bit 2] Code and Data Prioritization Technology supported if 1.\r
2272 ///\r
2273 UINT32 CodeDataPrioritization:1;\r
2274 UINT32 Reserved2:29;\r
2275 } Bits;\r
2276 ///\r
2277 /// All bit fields as a 32-bit value\r
2278 ///\r
2279 UINT32 Uint32;\r
14806d7b
HW
2280} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r
2281\r
2282/**\r
2283 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf\r
2284 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
2285 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
2286**/\r
2287typedef union {\r
2288 ///\r
2289 /// Individual bit fields\r
2290 ///\r
2291 struct {\r
2292 ///\r
2293 /// [Bits 15:0] Highest COS number supported for this ResID.\r
2294 ///\r
2295 UINT32 HighestCosNumber:16;\r
2296 UINT32 Reserved:16;\r
2297 } Bits;\r
2298 ///\r
2299 /// All bit fields as a 32-bit value\r
2300 ///\r
2301 UINT32 Uint32;\r
2302} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
2303\r
2304/**\r
2305 L2 Cache Allocation Technology Enumeration Sub-leaf\r
2306\r
2307 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
2308 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)\r
2309\r
2310 @retval EAX RESID L2 Cache Allocation Technology information described by\r
2311 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.\r
2312 @retval EBX Bit-granular map of isolation/contention of allocation units.\r
2313 @retval ECX Reserved.\r
2314 @retval EDX RESID L2 Cache Allocation Technology information described by\r
2315 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.\r
2316\r
2317 <b>Example usage</b>\r
2318 @code\r
2319 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
2320 UINT32 Ebx;\r
2321 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
2322\r
2323 AsmCpuidEx (\r
2324 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
2325 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
2326 );\r
2327 @endcode\r
2328**/\r
2329#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
57d16ba1
MK
2330\r
2331/**\r
14806d7b
HW
2332 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
2333 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
2334 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
2335**/\r
2336typedef union {\r
2337 ///\r
2338 /// Individual bit fields\r
2339 ///\r
2340 struct {\r
2341 ///\r
2342 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
2343 /// using minus-one notation.\r
2344 ///\r
2345 UINT32 CapacityLength:5;\r
2346 UINT32 Reserved:27;\r
2347 } Bits;\r
2348 ///\r
2349 /// All bit fields as a 32-bit value\r
2350 ///\r
2351 UINT32 Uint32;\r
2352} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
2353\r
2354/**\r
2355 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf\r
2356 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
2357 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
57d16ba1
MK
2358**/\r
2359typedef union {\r
2360 ///\r
2361 /// Individual bit fields\r
2362 ///\r
2363 struct {\r
2364 ///\r
2365 /// [Bits 15:0] Highest COS number supported for this ResID.\r
2366 ///\r
2367 UINT32 HighestCosNumber:16;\r
2368 UINT32 Reserved:16;\r
2369 } Bits;\r
2370 ///\r
2371 /// All bit fields as a 32-bit value\r
2372 ///\r
2373 UINT32 Uint32;\r
14806d7b 2374} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r
57d16ba1
MK
2375\r
2376\r
c606a9a5
JF
2377/**\r
2378 Intel SGX resource capability and configuration.\r
2379 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".\r
2380\r
2381 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying\r
2382 CPUID with EAX=12H on Intel SGX resource capability and configuration.\r
2383\r
2384 @param EAX CPUID_INTEL_SGX (0x12)\r
2385 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).\r
2386 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).\r
2387 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).\r
2388 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])\r
2389 until the sub-leaf type is invalid.\r
2390\r
2391**/\r
2392#define CPUID_INTEL_SGX 0x12\r
2393\r
2394/**\r
2395 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
2396 Enumerates Intel SGX capability, including enclave instruction opcode support.\r
2397\r
2398 @param EAX CPUID_INTEL_SGX (0x12)\r
2399 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)\r
2400\r
2401 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
2402 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.\r
2403 @retval EBX MISCSELECT: Reports the bit vector of supported extended features\r
2404 that can be written to the MISC region of the SSA.\r
2405 @retval ECX Reserved.\r
2406 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
2407 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.\r
2408\r
2409 <b>Example usage</b>\r
2410 @code\r
2411 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
2412 UINT32 Ebx;\r
2413 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
2414\r
2415 AsmCpuidEx (\r
2416 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
2417 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
2418 );\r
2419 @endcode\r
2420**/\r
2421#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
2422\r
2423/**\r
2424 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r
2425 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
2426**/\r
2427typedef union {\r
2428 ///\r
2429 /// Individual bit fields\r
2430 ///\r
2431 struct {\r
2432 ///\r
2433 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r
2434 ///\r
2435 UINT32 SGX1:1;\r
2436 ///\r
2437 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
2438 ///\r
2439 UINT32 SGX2:1;\r
2440 UINT32 Reserved:30;\r
2441 } Bits;\r
2442 ///\r
2443 /// All bit fields as a 32-bit value\r
2444 ///\r
2445 UINT32 Uint32;\r
2446} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r
2447\r
2448/**\r
2449 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,\r
2450 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
2451**/\r
2452typedef union {\r
2453 ///\r
2454 /// Individual bit fields\r
2455 ///\r
2456 struct {\r
2457 ///\r
2458 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r
2459 /// when not in 64-bit mode.\r
2460 ///\r
2461 UINT32 MaxEnclaveSize_Not64:8;\r
2462 ///\r
2463 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r
2464 /// when operating in 64-bit mode.\r
2465 ///\r
2466 UINT32 MaxEnclaveSize_64:8;\r
2467 UINT32 Reserved:16;\r
2468 } Bits;\r
2469 ///\r
2470 /// All bit fields as a 32-bit value\r
2471 ///\r
2472 UINT32 Uint32;\r
2473} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r
2474\r
2475\r
2476/**\r
2477 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
2478 Enumerates Intel SGX capability of processor state configuration and enclave\r
2479 configuration in the SECS structure.\r
2480\r
2481 @param EAX CPUID_INTEL_SGX (0x12)\r
2482 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)\r
2483\r
2484 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can\r
2485 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE\r
2486 only if EAX[n] is 1, where n < 32.\r
2487 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can\r
2488 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE\r
2489 only if EBX[n] is 1, where n < 32.\r
2490 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can\r
2491 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE\r
2492 only if ECX[n] is 1, where n < 32.\r
2493 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can\r
2494 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE\r
2495 only if EDX[n] is 1, where n < 32.\r
2496\r
2497 <b>Example usage</b>\r
2498 @code\r
2499 UINT32 Eax;\r
2500 UINT32 Ebx;\r
2501 UINT32 Ecx;\r
2502 UINT32 Edx;\r
2503\r
2504 AsmCpuidEx (\r
2505 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
2506 &Eax, &Ebx, &Ecx, &Edx\r
2507 );\r
2508 @endcode\r
2509**/\r
2510#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
2511\r
2512\r
2513/**\r
2514 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
2515 Enumerates available EPC resources.\r
2516\r
2517 @param EAX CPUID_INTEL_SGX (0x12)\r
2518 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)\r
2519\r
2520 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2521 Resources is described by the type\r
2522 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.\r
2523 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2524 Resources is described by the type\r
2525 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.\r
2526 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2527 Resources is described by the type\r
2528 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.\r
2529 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2530 Resources is described by the type\r
2531 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.\r
2532\r
2533 <b>Example usage</b>\r
2534 @code\r
2535 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
2536 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
2537 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
2538 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
2539\r
2540 AsmCpuidEx (\r
2541 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,\r
2542 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
2543 );\r
2544 @endcode\r
2545**/\r
2546#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02\r
2547\r
2548/**\r
2549 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID\r
2550 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2551**/\r
2552typedef union {\r
2553 ///\r
2554 /// Individual bit fields\r
2555 ///\r
2556 struct {\r
2557 ///\r
2558 /// [Bit 3:0] Sub-leaf-type encoding.\r
2559 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.\r
2560 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)\r
2561 /// in EBX:EAX and EDX:ECX.\r
2562 /// All other encoding are reserved.\r
2563 ///\r
2564 UINT32 SubLeafType:4;\r
2565 UINT32 Reserved:8;\r
2566 ///\r
2567 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r
2568 /// the base of the EPC section.\r
2569 ///\r
2570 UINT32 LowAddressOfEpcSection:20;\r
2571 } Bits;\r
2572 ///\r
2573 /// All bit fields as a 32-bit value\r
2574 ///\r
2575 UINT32 Uint32;\r
2576} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r
2577\r
2578/**\r
2579 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID\r
2580 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2581**/\r
2582typedef union {\r
2583 ///\r
2584 /// Individual bit fields\r
2585 ///\r
2586 struct {\r
2587 ///\r
2588 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r
2589 /// the base of the EPC section.\r
2590 ///\r
2591 UINT32 HighAddressOfEpcSection:20;\r
2592 UINT32 Reserved:12;\r
2593 } Bits;\r
2594 ///\r
2595 /// All bit fields as a 32-bit value\r
2596 ///\r
2597 UINT32 Uint32;\r
2598} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r
2599\r
2600/**\r
2601 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID\r
2602 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2603**/\r
2604typedef union {\r
2605 ///\r
2606 /// Individual bit fields\r
2607 ///\r
2608 struct {\r
2609 ///\r
2610 /// [Bit 3:0] The EPC section encoding.\r
2611 /// 0000b: Not valid.\r
2612 /// 0001b: The EPC section is confidentiality, integrity and replay protected.\r
2613 /// All other encoding are reserved.\r
2614 ///\r
2615 UINT32 EpcSection:4;\r
2616 UINT32 Reserved:8;\r
2617 ///\r
2618 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r
2619 /// corresponding EPC section within the Processor Reserved Memory.\r
2620 ///\r
2621 UINT32 LowSizeOfEpcSection:20;\r
2622 } Bits;\r
2623 ///\r
2624 /// All bit fields as a 32-bit value\r
2625 ///\r
2626 UINT32 Uint32;\r
2627} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r
2628\r
2629/**\r
2630 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID\r
2631 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2632**/\r
2633typedef union {\r
2634 ///\r
2635 /// Individual bit fields\r
2636 ///\r
2637 struct {\r
2638 ///\r
2639 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r
2640 /// corresponding EPC section within the Processor Reserved Memory.\r
2641 ///\r
2642 UINT32 HighSizeOfEpcSection:20;\r
2643 UINT32 Reserved:12;\r
2644 } Bits;\r
2645 ///\r
2646 /// All bit fields as a 32-bit value\r
2647 ///\r
2648 UINT32 Uint32;\r
2649} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r
2650\r
2651\r
57d16ba1
MK
2652/**\r
2653 CPUID Intel Processor Trace Information\r
2654\r
2655 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)\r
2656 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).\r
2657 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r
2658\r
2659**/\r
2660#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
2661\r
2662/**\r
2663 CPUID Intel Processor Trace Information Main Leaf\r
2664\r
2665 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
2666 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)\r
2667\r
2668 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.\r
2669 @retval EBX Returns Intel processor trace information described by the\r
2670 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.\r
2671 @retval ECX Returns Intel processor trace information described by the\r
2672 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.\r
2673 @retval EDX Reserved.\r
2674\r
2675 <b>Example usage</b>\r
2676 @code\r
2677 UINT32 Eax;\r
2678 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r
2679 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r
2680\r
2681 AsmCpuidEx (\r
2682 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
2683 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
2684 );\r
2685 @endcode\r
2686**/\r
2687#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
2688\r
2689/**\r
2690 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2691 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
2692**/\r
2693typedef union {\r
2694 ///\r
2695 /// Individual bit fields\r
2696 ///\r
2697 struct {\r
2698 ///\r
14806d7b 2699 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
57d16ba1
MK
2700 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
2701 ///\r
2702 UINT32 Cr3Filter:1;\r
2703 ///\r
14806d7b 2704 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r
57d16ba1
MK
2705 /// Mode.\r
2706 ///\r
2707 UINT32 ConfigurablePsb:1;\r
2708 ///\r
14806d7b 2709 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r
57d16ba1
MK
2710 /// and preservation of Intel PT MSRs across warm reset.\r
2711 ///\r
2712 UINT32 IpTraceStopFiltering:1;\r
2713 ///\r
14806d7b 2714 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r
57d16ba1
MK
2715 /// COFI-based packets.\r
2716 ///\r
2717 UINT32 Mtc:1;\r
14806d7b
HW
2718 ///\r
2719 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r
2720 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r
2721 /// can generate packets.\r
2722 ///\r
2723 UINT32 PTWrite:1;\r
2724 ///\r
2725 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r
2726 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r
2727 /// generation.\r
2728 ///\r
2729 UINT32 PowerEventTrace:1;\r
2730 UINT32 Reserved:26;\r
57d16ba1
MK
2731 } Bits;\r
2732 ///\r
2733 /// All bit fields as a 32-bit value\r
2734 ///\r
2735 UINT32 Uint32;\r
2736} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r
2737\r
2738/**\r
2739 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2740 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
2741**/\r
2742typedef union {\r
2743 ///\r
2744 /// Individual bit fields\r
2745 ///\r
2746 struct {\r
2747 ///\r
2748 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence\r
2749 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r
2750 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r
2751 ///\r
2752 UINT32 RTIT:1;\r
2753 ///\r
2754 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r
2755 /// the maximum allowed by the MaskOrTableOffset field of\r
2756 /// IA32_RTIT_OUTPUT_MASK_PTRS.\r
2757 ///\r
2758 UINT32 ToPA:1;\r
2759 ///\r
14806d7b 2760 /// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r
57d16ba1
MK
2761 ///\r
2762 UINT32 SingleRangeOutput:1;\r
2763 ///\r
14806d7b 2764 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r
57d16ba1
MK
2765 ///\r
2766 UINT32 TraceTransportSubsystem:1;\r
2767 UINT32 Reserved:27;\r
2768 ///\r
14806d7b 2769 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r
57d16ba1
MK
2770 /// values, which include the CS base component.\r
2771 ///\r
2772 UINT32 LIP:1;\r
2773 } Bits;\r
2774 ///\r
2775 /// All bit fields as a 32-bit value\r
2776 ///\r
2777 UINT32 Uint32;\r
2778} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r
2779\r
2780\r
2781/**\r
2782 CPUID Intel Processor Trace Information Sub-leaf\r
2783\r
2784 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
2785 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)\r
2786\r
2787 @retval EAX Returns Intel processor trace information described by the\r
2788 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.\r
2789 @retval EBX Returns Intel processor trace information described by the\r
2790 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.\r
2791 @retval ECX Reserved.\r
2792 @retval EDX Reserved.\r
2793\r
2794 <b>Example usage</b>\r
2795 @code\r
2796 UINT32 MaximumSubLeaf;\r
2797 UINT32 SubLeaf;\r
2798 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r
2799 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r
2800\r
2801 AsmCpuidEx (\r
2802 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
2803 &MaximumSubLeaf, NULL, NULL, NULL\r
2804 );\r
2805\r
2806 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
2807 AsmCpuidEx (\r
2808 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
2809 &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
2810 );\r
2811 }\r
2812 @endcode\r
2813**/\r
2814#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
2815\r
2816/**\r
2817 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2818 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
2819**/\r
2820typedef union {\r
2821 ///\r
2822 /// Individual bit fields\r
2823 ///\r
2824 struct {\r
2825 ///\r
2826 /// [Bits 2:0] Number of configurable Address Ranges for filtering.\r
2827 ///\r
2828 UINT32 ConfigurableAddressRanges:3;\r
2829 UINT32 Reserved:13;\r
2830 ///\r
2831 /// [Bits 31:16] Bitmap of supported MTC period encodings\r
2832 ///\r
2833 UINT32 MtcPeriodEncodings:16;\r
2834\r
2835 } Bits;\r
2836 ///\r
2837 /// All bit fields as a 32-bit value\r
2838 ///\r
2839 UINT32 Uint32;\r
2840} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r
2841\r
2842/**\r
2843 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2844 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
2845**/\r
2846typedef union {\r
2847 ///\r
2848 /// Individual bit fields\r
2849 ///\r
2850 struct {\r
2851 ///\r
2852 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r
2853 ///\r
2854 UINT32 CycleThresholdEncodings:16;\r
2855 ///\r
2856 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r
2857 ///\r
2858 UINT32 PsbFrequencyEncodings:16;\r
2859\r
2860 } Bits;\r
2861 ///\r
2862 /// All bit fields as a 32-bit value\r
2863 ///\r
2864 UINT32 Uint32;\r
2865} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r
2866\r
2867\r
2868/**\r
14806d7b 2869 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r
57d16ba1
MK
2870\r
2871 @note\r
2872 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
2873 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
2874 crystal clock frequency.\r
14806d7b
HW
2875 If ECX is 0, the nominal core crystal clock frequency is not enumerated.\r
2876 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
57d16ba1
MK
2877 The core crystal clock may differ from the reference clock, bus clock, or core\r
2878 clock frequencies.\r
2879\r
2880 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)\r
2881\r
2882 @retval EAX An unsigned integer which is the denominator of the\r
2883 TSC/"core crystal clock" ratio\r
2884 @retval EBX An unsigned integer which is the numerator of the\r
2885 TSC/"core crystal clock" ratio.\r
14806d7b
HW
2886 @retval ECX An unsigned integer which is the nominal frequency\r
2887 of the core crystal clock in Hz.\r
57d16ba1
MK
2888 @retval EDX Reserved.\r
2889\r
2890 <b>Example usage</b>\r
2891 @code\r
2892 UINT32 Eax;\r
2893 UINT32 Ebx;\r
14806d7b 2894 UINT32 Ecx;\r
57d16ba1 2895\r
14806d7b 2896 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
57d16ba1
MK
2897 @endcode\r
2898**/\r
2899#define CPUID_TIME_STAMP_COUNTER 0x15\r
2900\r
2901\r
2902/**\r
2903 CPUID Processor Frequency Information\r
2904\r
2905 @note\r
2906 Data is returned from this interface in accordance with the processor's\r
2907 specification and does not reflect actual values. Suitable use of this data\r
2908 includes the display of processor information in like manner to the processor\r
2909 brand string and for determining the appropriate range to use when displaying\r
2910 processor information e.g. frequency history graphs. The returned information\r
2911 should not be used for any other purpose as the returned information does not\r
2912 accurately correlate to information / counters returned by other processor\r
2913 interfaces. While a processor may support the Processor Frequency Information\r
2914 leaf, fields that return a value of zero are not supported.\r
2915\r
2916 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)\r
2917\r
2918 @retval EAX Returns processor base frequency information described by the\r
2919 type CPUID_PROCESSOR_FREQUENCY_EAX.\r
2920 @retval EBX Returns maximum frequency information described by the type\r
2921 CPUID_PROCESSOR_FREQUENCY_EBX.\r
2922 @retval ECX Returns bus frequency information described by the type\r
2923 CPUID_PROCESSOR_FREQUENCY_ECX.\r
2924 @retval EDX Reserved.\r
2925\r
2926 <b>Example usage</b>\r
2927 @code\r
2928 CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r
2929 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r
2930 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r
2931\r
2932 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
2933 @endcode\r
2934**/\r
2935#define CPUID_PROCESSOR_FREQUENCY 0x16\r
2936\r
2937/**\r
2938 CPUID Processor Frequency Information EAX for CPUID leaf\r
2939 #CPUID_PROCESSOR_FREQUENCY.\r
2940**/\r
2941typedef union {\r
2942 ///\r
2943 /// Individual bit fields\r
2944 ///\r
2945 struct {\r
2946 ///\r
2947 /// [Bits 15:0] Processor Base Frequency (in MHz).\r
2948 ///\r
2949 UINT32 ProcessorBaseFrequency:16;\r
2950 UINT32 Reserved:16;\r
2951 } Bits;\r
2952 ///\r
2953 /// All bit fields as a 32-bit value\r
2954 ///\r
2955 UINT32 Uint32;\r
2956} CPUID_PROCESSOR_FREQUENCY_EAX;\r
2957\r
2958/**\r
2959 CPUID Processor Frequency Information EBX for CPUID leaf\r
2960 #CPUID_PROCESSOR_FREQUENCY.\r
2961**/\r
2962typedef union {\r
2963 ///\r
2964 /// Individual bit fields\r
2965 ///\r
2966 struct {\r
2967 ///\r
2968 /// [Bits 15:0] Maximum Frequency (in MHz).\r
2969 ///\r
2970 UINT32 MaximumFrequency:16;\r
2971 UINT32 Reserved:16;\r
2972 } Bits;\r
2973 ///\r
2974 /// All bit fields as a 32-bit value\r
2975 ///\r
2976 UINT32 Uint32;\r
2977} CPUID_PROCESSOR_FREQUENCY_EBX;\r
2978\r
2979/**\r
2980 CPUID Processor Frequency Information ECX for CPUID leaf\r
2981 #CPUID_PROCESSOR_FREQUENCY.\r
2982**/\r
2983typedef union {\r
2984 ///\r
2985 /// Individual bit fields\r
2986 ///\r
2987 struct {\r
2988 ///\r
2989 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r
2990 ///\r
2991 UINT32 BusFrequency:16;\r
2992 UINT32 Reserved:16;\r
2993 } Bits;\r
2994 ///\r
2995 /// All bit fields as a 32-bit value\r
2996 ///\r
2997 UINT32 Uint32;\r
2998} CPUID_PROCESSOR_FREQUENCY_ECX;\r
2999\r
28a7ddf0 3000\r
57d16ba1
MK
3001/**\r
3002 CPUID SoC Vendor Information\r
28a7ddf0 3003\r
57d16ba1
MK
3004 @param EAX CPUID_SOC_VENDOR (0x17)\r
3005 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
3006 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
3007 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)\r
3008 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)\r
28a7ddf0 3009\r
57d16ba1
MK
3010 @note\r
3011 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String\r
3012 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC\r
3013 Vendor Brand String is constructed by concatenating in ascending order of\r
3014 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r
28a7ddf0 3015\r
57d16ba1
MK
3016**/\r
3017#define CPUID_SOC_VENDOR 0x17\r
3018\r
3019/**\r
3020 CPUID SoC Vendor Information\r
3021\r
3022 @param EAX CPUID_SOC_VENDOR (0x17)\r
3023 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
3024\r
3025 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported\r
3026 sub-leaf in leaf 17H.\r
3027 @retval EBX Returns SoC Vendor information described by the type\r
3028 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.\r
3029 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC\r
3030 projects.\r
3031 @retval EDX Stepping ID. A unique number within an SOC project that an SOC\r
3032 vendor assigns.\r
3033\r
3034 <b>Example usage</b>\r
3035 @code\r
3036 UINT32 Eax;\r
3037 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r
3038 UINT32 Ecx;\r
3039 UINT32 Edx;\r
3040\r
3041 AsmCpuidEx (\r
3042 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
3043 &Eax, &Ebx.Uint32, &Ecx, &Edx\r
3044 );\r
3045 @endcode\r
3046**/\r
3047#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
3048\r
3049/**\r
3050 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r
3051 #CPUID_SOC_VENDOR_MAIN_LEAF.\r
3052**/\r
3053typedef union {\r
3054 ///\r
3055 /// Individual bit fields\r
3056 ///\r
3057 struct {\r
3058 ///\r
3059 /// [Bits 15:0] SOC Vendor ID.\r
3060 ///\r
3061 UINT32 SocVendorId:16;\r
3062 ///\r
3063 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r
3064 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r
3065 /// assigned by Intel.\r
3066 ///\r
3067 UINT32 IsVendorScheme:1;\r
3068 UINT32 Reserved:15;\r
3069 } Bits;\r
3070 ///\r
3071 /// All bit fields as a 32-bit value\r
3072 ///\r
3073 UINT32 Uint32;\r
3074} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r
3075\r
3076/**\r
3077 CPUID SoC Vendor Information\r
3078\r
3079 @param EAX CPUID_SOC_VENDOR (0x17)\r
3080 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
3081\r
3082 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
3083 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3084 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
3085 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3086 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
3087 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3088 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
3089 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3090\r
3091 <b>Example usage</b>\r
3092 @code\r
3093 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
3094 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
3095 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
3096 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
3097\r
3098 AsmCpuidEx (\r
3099 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
3100 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
3101 );\r
3102 @endcode\r
3103**/\r
3104#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
3105\r
3106/**\r
3107 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r
3108 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.\r
3109**/\r
3110typedef union {\r
3111 ///\r
3112 /// 4 UTF-8 characters of Soc Vendor Brand String\r
3113 ///\r
3114 CHAR8 BrandString[4];\r
3115 ///\r
3116 /// All fields as a 32-bit value\r
3117 ///\r
3118 UINT32 Uint32;\r
3119} CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r
3120\r
3121/**\r
3122 CPUID SoC Vendor Information\r
3123\r
3124 @param EAX CPUID_SOC_VENDOR (0x17)\r
3125 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)\r
3126\r
3127 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
3128 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3129 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
3130 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3131 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
3132 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3133 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
3134 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3135\r
3136 <b>Example usage</b>\r
3137 @code\r
3138 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
3139 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
3140 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
3141 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
3142\r
3143 AsmCpuidEx (\r
3144 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
3145 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
3146 );\r
3147 @endcode\r
3148**/\r
3149#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
3150\r
3151/**\r
3152 CPUID SoC Vendor Information\r
3153\r
3154 @param EAX CPUID_SOC_VENDOR (0x17)\r
3155 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)\r
28a7ddf0 3156\r
57d16ba1
MK
3157 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
3158 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3159 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
3160 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3161 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
3162 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3163 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
3164 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3165\r
3166 <b>Example usage</b>\r
3167 @code\r
3168 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
3169 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
3170 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
3171 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
3172\r
3173 AsmCpuidEx (\r
3174 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
3175 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
3176 );\r
3177 @endcode\r
3178**/\r
3179#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
4de216c0 3180\r
28a7ddf0 3181\r
57d16ba1
MK
3182/**\r
3183 CPUID Extended Function\r
3184\r
3185 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)\r
3186\r
3187 @retval EAX Maximum Input Value for Extended Function CPUID Information.\r
3188 @retval EBX Reserved.\r
3189 @retval ECX Reserved.\r
3190 @retval EDX Reserved.\r
3191\r
3192 <b>Example usage</b>\r
3193 @code\r
3194 UINT32 Eax;\r
3195\r
3196 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
3197 @endcode\r
3198**/\r
28a7ddf0
MK
3199#define CPUID_EXTENDED_FUNCTION 0x80000000\r
3200\r
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3201\r
3202/**\r
3203 CPUID Extended Processor Signature and Feature Bits\r
3204\r
3205 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r
3206\r
3207 @retval EAX CPUID_EXTENDED_CPU_SIG.\r
3208 @retval EBX Reserved.\r
3209 @retval ECX Extended Processor Signature and Feature Bits information\r
3210 described by the type CPUID_EXTENDED_CPU_SIG_ECX.\r
3211 @retval EDX Extended Processor Signature and Feature Bits information\r
3212 described by the type CPUID_EXTENDED_CPU_SIG_EDX.\r
3213\r
3214 <b>Example usage</b>\r
3215 @code\r
3216 UINT32 Eax;\r
3217 CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r
3218 CPUID_EXTENDED_CPU_SIG_EDX Edx;\r
3219\r
3220 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
3221 @endcode\r
3222**/\r
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3223#define CPUID_EXTENDED_CPU_SIG 0x80000001\r
3224\r
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3225/**\r
3226 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf\r
3227 #CPUID_EXTENDED_CPU_SIG.\r
3228**/\r
3229typedef union {\r
3230 ///\r
3231 /// Individual bit fields\r
3232 ///\r
3233 struct {\r
3234 ///\r
3235 /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
3236 ///\r
3237 UINT32 LAHF_SAHF:1;\r
3238 UINT32 Reserved1:4;\r
3239 ///\r
3240 /// [Bit 5] LZCNT.\r
3241 ///\r
3242 UINT32 LZCNT:1;\r
3243 UINT32 Reserved2:2;\r
3244 ///\r
3245 /// [Bit 8] PREFETCHW.\r
3246 ///\r
3247 UINT32 PREFETCHW:1;\r
3248 UINT32 Reserved3:23;\r
3249 } Bits;\r
3250 ///\r
3251 /// All bit fields as a 32-bit value\r
3252 ///\r
3253 UINT32 Uint32;\r
3254} CPUID_EXTENDED_CPU_SIG_ECX;\r
3255\r
3256/**\r
3257 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf\r
3258 #CPUID_EXTENDED_CPU_SIG.\r
3259**/\r
3260typedef union {\r
3261 ///\r
3262 /// Individual bit fields\r
3263 ///\r
3264 struct {\r
3265 UINT32 Reserved1:11;\r
3266 ///\r
3267 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.\r
3268 ///\r
3269 UINT32 SYSCALL_SYSRET:1;\r
3270 UINT32 Reserved2:8;\r
3271 ///\r
3272 /// [Bit 20] Execute Disable Bit available.\r
3273 ///\r
3274 UINT32 NX:1;\r
3275 UINT32 Reserved3:5;\r
3276 ///\r
3277 /// [Bit 26] 1-GByte pages are available if 1.\r
3278 ///\r
3279 UINT32 Page1GB:1;\r
3280 ///\r
3281 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.\r
3282 ///\r
3283 UINT32 RDTSCP:1;\r
3284 UINT32 Reserved4:1;\r
3285 ///\r
3286 /// [Bit 29] Intel(R) 64 Architecture available if 1.\r
3287 ///\r
3288 UINT32 LM:1;\r
3289 UINT32 Reserved5:2;\r
3290 } Bits;\r
3291 ///\r
3292 /// All bit fields as a 32-bit value\r
3293 ///\r
3294 UINT32 Uint32;\r
3295} CPUID_EXTENDED_CPU_SIG_EDX;\r
3296\r
3297\r
3298/**\r
3299 CPUID Processor Brand String\r
3300\r
3301 @param EAX CPUID_BRAND_STRING1 (0x80000002)\r
3302\r
3303 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.\r
3304 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3305 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3306 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3307\r
3308 <b>Example usage</b>\r
3309 @code\r
3310 CPUID_BRAND_STRING_DATA Eax;\r
3311 CPUID_BRAND_STRING_DATA Ebx;\r
3312 CPUID_BRAND_STRING_DATA Ecx;\r
3313 CPUID_BRAND_STRING_DATA Edx;\r
3314\r
3315 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
3316 @endcode\r
3317**/\r
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3318#define CPUID_BRAND_STRING1 0x80000002\r
3319\r
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3320/**\r
3321 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,\r
3322 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.\r
3323**/\r
3324typedef union {\r
3325 ///\r
3326 /// 4 ASCII characters of Processor Brand String\r
3327 ///\r
3328 CHAR8 BrandString[4];\r
3329 ///\r
3330 /// All fields as a 32-bit value\r
3331 ///\r
3332 UINT32 Uint32;\r
3333} CPUID_BRAND_STRING_DATA;\r
3334\r
3335/**\r
3336 CPUID Processor Brand String\r
3337\r
3338 @param EAX CPUID_BRAND_STRING2 (0x80000003)\r
3339\r
3340 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3341 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3342 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3343 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3344\r
3345 <b>Example usage</b>\r
3346 @code\r
3347 CPUID_BRAND_STRING_DATA Eax;\r
3348 CPUID_BRAND_STRING_DATA Ebx;\r
3349 CPUID_BRAND_STRING_DATA Ecx;\r
3350 CPUID_BRAND_STRING_DATA Edx;\r
3351\r
3352 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
3353 @endcode\r
3354**/\r
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3355#define CPUID_BRAND_STRING2 0x80000003\r
3356\r
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3357/**\r
3358 CPUID Processor Brand String\r
3359\r
3360 @param EAX CPUID_BRAND_STRING3 (0x80000004)\r
3361\r
3362 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3363 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3364 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3365 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3366\r
3367 <b>Example usage</b>\r
3368 @code\r
3369 CPUID_BRAND_STRING_DATA Eax;\r
3370 CPUID_BRAND_STRING_DATA Ebx;\r
3371 CPUID_BRAND_STRING_DATA Ecx;\r
3372 CPUID_BRAND_STRING_DATA Edx;\r
3373\r
3374 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
3375 @endcode\r
3376**/\r
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3377#define CPUID_BRAND_STRING3 0x80000004\r
3378\r
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3379\r
3380/**\r
3381 CPUID Extended Cache information\r
3382\r
3383 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)\r
3384\r
3385 @retval EAX Reserved.\r
3386 @retval EBX Reserved.\r
3387 @retval ECX Extended cache information described by the type\r
3388 CPUID_EXTENDED_CACHE_INFO_ECX.\r
3389 @retval EDX Reserved.\r
3390\r
3391 <b>Example usage</b>\r
3392 @code\r
3393 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r
3394\r
3395 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
3396 @endcode\r
3397**/\r
3398#define CPUID_EXTENDED_CACHE_INFO 0x80000006\r
3399\r
3400/**\r
3401 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.\r
3402**/\r
3403typedef union {\r
3404 ///\r
3405 /// Individual bit fields\r
3406 ///\r
3407 struct {\r
3408 ///\r
3409 /// [Bits 7:0] Cache line size in bytes.\r
3410 ///\r
3411 UINT32 CacheLineSize:8;\r
3412 UINT32 Reserved:4;\r
3413 ///\r
3414 /// [Bits 15:12] L2 Associativity field. Supported values are in the range\r
3415 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to\r
3416 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL\r
3417 ///\r
3418 UINT32 L2Associativity:4;\r
3419 ///\r
3420 /// [Bits 31:16] Cache size in 1K units.\r
3421 ///\r
3422 UINT32 CacheSize:16;\r
3423 } Bits;\r
3424 ///\r