Fix build break when doing 32-bit build with some certain C compiler option combinations.
[mirror_edk2.git] / UefiCpuPkg / Include / Register / LocalApic.h
CommitLineData
bf73cc4b 1/** @file\r
2 IA32 Local APIC Definitions.\r
3\r
4 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef __LOCAL_APIC_H__\r
16#define __LOCAL_APIC_H__\r
17\r
18//\r
19// Definitions for IA32 architectural MSRs\r
20//\r
21#define MSR_IA32_APIC_BASE_ADDRESS 0x1B\r
22\r
23//\r
24// Definitions for CPUID instruction\r
25//\r
26#define CPUID_VERSION_INFO 0x1\r
27#define CPUID_EXTENDED_FUNCTION 0x80000000\r
28#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
29\r
30//\r
31// Definition for Local APIC registers and related values\r
32//\r
ae40aef1 33#define XAPIC_ID_OFFSET 0x20\r
34#define XAPIC_VERSION_OFFSET 0x30\r
bf73cc4b 35#define XAPIC_EOI_OFFSET 0x0b0\r
36#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
37#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
38#define XAPIC_ICR_LOW_OFFSET 0x300\r
39#define XAPIC_ICR_HIGH_OFFSET 0x310\r
40#define XAPIC_LVT_TIMER_OFFSET 0x320\r
ae40aef1 41#define XAPIC_LVT_LINT0_OFFSET 0x350\r
42#define XAPIC_LVT_LINT1_OFFSET 0x360\r
bf73cc4b 43#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
44#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
45#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
46\r
47#define X2APIC_MSR_BASE_ADDRESS 0x800\r
48#define X2APIC_MSR_ICR_ADDRESS 0x830\r
49\r
50#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
51#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
52#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
53#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
54#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
55#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
56#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
57\r
58#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
59#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
60#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
61#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
62\r
63typedef union {\r
64 struct {\r
23394428 65 UINT32 Reserved0:8; ///< Reserved.\r
66 UINT32 Bsp:1; ///< Processor is BSP.\r
67 UINT32 Reserved1:1; ///< Reserved.\r
68 UINT32 Extd:1; ///< Enable x2APIC mode.\r
69 UINT32 En:1; ///< xAPIC global enable/disable.\r
70 UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.\r
71 UINT32 ApicBaseHigh:32;\r
bf73cc4b 72 } Bits;\r
73 UINT64 Uint64;\r
74} MSR_IA32_APIC_BASE;\r
75\r
ae40aef1 76//\r
77// Local APIC Version Register.\r
78//\r
79typedef union {\r
80 struct {\r
81 UINT32 Version:8; ///< The version numbers of the local APIC.\r
82 UINT32 Reserved0:8; ///< Reserved.\r
83 UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r
84 UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r
85 UINT32 Reserved1:7; ///< Reserved.\r
86 } Bits;\r
87 UINT32 Uint32;\r
88} LOCAL_APIC_VERSION;\r
89\r
bf73cc4b 90//\r
91// Low half of Interrupt Command Register (ICR).\r
92//\r
93typedef union {\r
94 struct {\r
95 UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
96 UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r
97 UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r
98 UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
99 UINT32 Reserved0:1; ///< Reserved.\r
100 UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
101 UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
102 UINT32 Reserved1:2; ///< Reserved.\r
103 UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r
104 UINT32 Reserved2:12; ///< Reserved.\r
105 } Bits;\r
106 UINT32 Uint32;\r
107} LOCAL_APIC_ICR_LOW;\r
108\r
109//\r
110// High half of Interrupt Command Register (ICR)\r
111//\r
112typedef union {\r
113 struct {\r
114 UINT32 Reserved0:24; ///< Reserved.\r
115 UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r
116 } Bits;\r
117 UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r
118} LOCAL_APIC_ICR_HIGH;\r
119\r
120//\r
121// Spurious-Interrupt Vector Register (SVR)\r
122//\r
123typedef union {\r
124 struct {\r
125 UINT32 SpuriousVector:8; ///< Spurious Vector.\r
126 UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r
127 UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r
128 UINT32 Reserved0:2; ///< Reserved.\r
129 UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r
130 UINT32 Reserved1:19; ///< Reserved.\r
131 } Bits;\r
132 UINT32 Uint32;\r
133} LOCAL_APIC_SVR;\r
134\r
135//\r
136// Divide Configuration Register (DCR)\r
137//\r
138typedef union {\r
139 struct {\r
140 UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r
141 UINT32 Reserved0:1; ///< Always 0.\r
142 UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r
143 UINT32 Reserved1:28; ///< Reserved.\r
144 } Bits;\r
145 UINT32 Uint32;\r
146} LOCAL_APIC_DCR;\r
147\r
148//\r
149// LVT Timer Register\r
150//\r
151typedef union {\r
152 struct {\r
153 UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
154 UINT32 Reserved0:4; ///< Reserved.\r
155 UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
156 UINT32 Reserved1:3; ///< Reserved.\r
157 UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
158 UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r
159 UINT32 Reserved2:14; ///< Reserved.\r
160 } Bits;\r
161 UINT32 Uint32;\r
162} LOCAL_APIC_LVT_TIMER;\r
163\r
164//\r
165// LVT LINT0/LINT1 Register\r
166//\r
167typedef union {\r
168 struct {\r
169 UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
170 UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
171 UINT32 Reserved0:1; ///< Reserved.\r
172 UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
173 UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r
174 UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
175 UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r
176 UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
177 UINT32 Reserved1:15; ///< Reserved.\r
178 } Bits;\r
179 UINT32 Uint32;\r
180} LOCAL_APIC_LVT_LINT;\r
181\r
182#endif\r
183\r