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1 | /** @file\r |
2 | MSR Definitions.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
b715c37e | 9 | Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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11 | \r |
12 | @par Specification Reference:\r | |
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13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
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15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __MSR_H__\r | |
19 | #define __MSR_H__\r | |
20 | \r | |
21 | #include <Register/ArchitecturalMsr.h>\r | |
22 | #include <Register/Msr/Core2Msr.h>\r | |
23 | #include <Register/Msr/AtomMsr.h>\r | |
24 | #include <Register/Msr/SilvermontMsr.h>\r | |
35fd9411 | 25 | #include <Register/Msr/GoldmontMsr.h>\r |
b715c37e | 26 | #include <Register/Msr/GoldmontPlusMsr.h>\r |
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27 | #include <Register/Msr/NehalemMsr.h>\r |
28 | #include <Register/Msr/Xeon5600Msr.h>\r | |
29 | #include <Register/Msr/XeonE7Msr.h>\r | |
30 | #include <Register/Msr/SandyBridgeMsr.h>\r | |
31 | #include <Register/Msr/IvyBridgeMsr.h>\r | |
32 | #include <Register/Msr/HaswellMsr.h>\r | |
33 | #include <Register/Msr/HaswellEMsr.h>\r | |
34 | #include <Register/Msr/BroadwellMsr.h>\r | |
35 | #include <Register/Msr/XeonDMsr.h>\r | |
36 | #include <Register/Msr/SkylakeMsr.h>\r | |
37 | #include <Register/Msr/XeonPhiMsr.h>\r | |
38 | #include <Register/Msr/Pentium4Msr.h>\r | |
39 | #include <Register/Msr/CoreMsr.h>\r | |
40 | #include <Register/Msr/PentiumMMsr.h>\r | |
41 | #include <Register/Msr/P6Msr.h>\r | |
42 | #include <Register/Msr/PentiumMsr.h>\r | |
43 | \r | |
44 | #endif\r |