projects / mirror_edk2.git / blame
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| 7ae88a62 MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel processors based on the Haswell microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 7ae88a62 MK |
11 | \r |
| 12 | @par Specification Reference:\r | |
| ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| 7ae88a62 MK |
15 | \r |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #ifndef __HASWELL_MSR_H__\r | |
| 19 | #define __HASWELL_MSR_H__\r | |
| 20 | \r | |
| 21 | #include <Register/ArchitecturalMsr.h>\r | |
| 22 | \r | |
| f4c982bf JF |
23 | /**\r |
| 24 | Is Intel processors based on the Haswell microarchitecture?\r | |
| 25 | \r | |
| 26 | @param DisplayFamily Display Family ID\r | |
| 27 | @param DisplayModel Display Model ID\r | |
| 28 | \r | |
| 29 | @retval TRUE Yes, it is.\r | |
| 30 | @retval FALSE No, it isn't.\r | |
| 31 | **/\r | |
| 32 | #define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 33 | (DisplayFamily == 0x06 && \\r | |
| 34 | ( \\r | |
| 35 | DisplayModel == 0x3C || \\r | |
| 36 | DisplayModel == 0x45 || \\r | |
| 37 | DisplayModel == 0x46 \\r | |
| 38 | ) \\r | |
| 39 | )\r | |
| 40 | \r | |
| 7ae88a62 MK |
41 | /**\r |
| 42 | Package.\r | |
| 43 | \r | |
| 44 | @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)\r | |
| 45 | @param EAX Lower 32-bits of MSR value.\r | |
| 46 | Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r | |
| 47 | @param EDX Upper 32-bits of MSR value.\r | |
| 48 | Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r | |
| 49 | \r | |
| 50 | <b>Example usage</b>\r | |
| 51 | @code\r | |
| 52 | MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;\r | |
| 53 | \r | |
| 54 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);\r | |
| 55 | AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);\r | |
| 56 | @endcode\r | |
| e108c3f6 | 57 | @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
| 7ae88a62 MK |
58 | **/\r |
| 59 | #define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r | |
| 60 | \r | |
| 61 | /**\r | |
| 62 | MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO\r | |
| 63 | **/\r | |
| 64 | typedef union {\r | |
| 65 | ///\r | |
| 66 | /// Individual bit fields\r | |
| 67 | ///\r | |
| 68 | struct {\r | |
| 69 | UINT32 Reserved1:8;\r | |
| 70 | ///\r | |
| 71 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 72 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 73 | /// MHz.\r | |
| 74 | ///\r | |
| 75 | UINT32 MaximumNonTurboRatio:8;\r | |
| 76 | UINT32 Reserved2:12;\r | |
| 77 | ///\r | |
| 78 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 79 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 80 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 81 | /// Turbo mode is disabled.\r | |
| 82 | ///\r | |
| 83 | UINT32 RatioLimit:1;\r | |
| 84 | ///\r | |
| 85 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 86 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 87 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 88 | /// programmable.\r | |
| 89 | ///\r | |
| 90 | UINT32 TDPLimit:1;\r | |
| 91 | UINT32 Reserved3:2;\r | |
| 92 | ///\r | |
| 93 | /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r | |
| 94 | /// indicates that LPM is supported, and when set to 0, indicates LPM is\r | |
| 95 | /// not supported.\r | |
| 96 | ///\r | |
| 97 | UINT32 LowPowerModeSupport:1;\r | |
| 98 | ///\r | |
| 99 | /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r | |
| 100 | /// TDP level available. 01: One additional TDP level available. 02: Two\r | |
| 101 | /// additional TDP level available. 11: Reserved.\r | |
| 102 | ///\r | |
| 103 | UINT32 ConfigTDPLevels:2;\r | |
| 104 | UINT32 Reserved4:5;\r | |
| 105 | ///\r | |
| 106 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 107 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 108 | /// units of 100MHz.\r | |
| 109 | ///\r | |
| 110 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 111 | ///\r | |
| 112 | /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r | |
| 113 | /// minimum supported operating ratio in units of 100 MHz.\r | |
| 114 | ///\r | |
| 115 | UINT32 MinimumOperatingRatio:8;\r | |
| 116 | UINT32 Reserved5:8;\r | |
| 117 | } Bits;\r | |
| 118 | ///\r | |
| 119 | /// All bit fields as a 64-bit value\r | |
| 120 | ///\r | |
| 121 | UINT64 Uint64;\r | |
| 122 | } MSR_HASWELL_PLATFORM_INFO_REGISTER;\r | |
| 123 | \r | |
| 124 | \r | |
| 125 | /**\r | |
| ba1a2d11 ED |
126 | Thread. Performance Event Select for Counter n (R/W) Supports all fields\r |
| 127 | described inTable 2-2 and the fields below.\r | |
| 7ae88a62 MK |
128 | \r |
| 129 | @param ECX MSR_HASWELL_IA32_PERFEVTSELn\r | |
| 130 | @param EAX Lower 32-bits of MSR value.\r | |
| 131 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r | |
| 132 | @param EDX Upper 32-bits of MSR value.\r | |
| 133 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r | |
| 134 | \r | |
| 135 | <b>Example usage</b>\r | |
| 136 | @code\r | |
| 137 | MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;\r | |
| 138 | \r | |
| 139 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);\r | |
| 140 | AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);\r | |
| 141 | @endcode\r | |
| e108c3f6 JF |
142 | @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r |
| 143 | MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r | |
| 144 | MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r | |
| 7ae88a62 MK |
145 | @{\r |
| 146 | **/\r | |
| 147 | #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r | |
| 148 | #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r | |
| 149 | #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r | |
| 150 | /// @}\r | |
| 151 | \r | |
| 152 | /**\r | |
| 153 | MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,\r | |
| 154 | #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.\r | |
| 155 | **/\r | |
| 156 | typedef union {\r | |
| 157 | ///\r | |
| 158 | /// Individual bit fields\r | |
| 159 | ///\r | |
| 160 | struct {\r | |
| 161 | ///\r | |
| 162 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 163 | ///\r | |
| 164 | UINT32 EventSelect:8;\r | |
| 165 | ///\r | |
| 166 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 167 | /// detect on the selected event logic.\r | |
| 168 | ///\r | |
| 169 | UINT32 UMASK:8;\r | |
| 170 | ///\r | |
| 171 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 172 | ///\r | |
| 173 | UINT32 USR:1;\r | |
| 174 | ///\r | |
| 175 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 176 | ///\r | |
| 177 | UINT32 OS:1;\r | |
| 178 | ///\r | |
| 179 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 180 | ///\r | |
| 181 | UINT32 E:1;\r | |
| 182 | ///\r | |
| 183 | /// [Bit 19] PC: enables pin control.\r | |
| 184 | ///\r | |
| 185 | UINT32 PC:1;\r | |
| 186 | ///\r | |
| 187 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 188 | ///\r | |
| 189 | UINT32 INT:1;\r | |
| 190 | ///\r | |
| 191 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 192 | /// event conditions occurring across all logical processors sharing a\r | |
| 193 | /// processor core. When set to 0, the counter only increments the\r | |
| 194 | /// associated event conditions occurring in the logical processor which\r | |
| 195 | /// programmed the MSR.\r | |
| 196 | ///\r | |
| 197 | UINT32 ANY:1;\r | |
| 198 | ///\r | |
| 199 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 200 | /// counting when this bit is set.\r | |
| 201 | ///\r | |
| 202 | UINT32 EN:1;\r | |
| 203 | ///\r | |
| 204 | /// [Bit 23] INV: invert the CMASK.\r | |
| 205 | ///\r | |
| 206 | UINT32 INV:1;\r | |
| 207 | ///\r | |
| 208 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 209 | /// performance counter increments each cycle if the event count is\r | |
| 210 | /// greater than or equal to the CMASK.\r | |
| 211 | ///\r | |
| 212 | UINT32 CMASK:8;\r | |
| 213 | UINT32 Reserved:32;\r | |
| 214 | ///\r | |
| ba1a2d11 | 215 | /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r |
| 7ae88a62 MK |
216 | /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r |
| 217 | ///\r | |
| 218 | UINT32 IN_TX:1;\r | |
| 219 | UINT32 Reserved2:31;\r | |
| 220 | } Bits;\r | |
| 221 | ///\r | |
| 222 | /// All bit fields as a 64-bit value\r | |
| 223 | ///\r | |
| 224 | UINT64 Uint64;\r | |
| 225 | } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;\r | |
| 226 | \r | |
| 227 | \r | |
| 228 | /**\r | |
| ba1a2d11 ED |
229 | Thread. Performance Event Select for Counter 2 (R/W) Supports all fields\r |
| 230 | described inTable 2-2 and the fields below.\r | |
| 7ae88a62 MK |
231 | \r |
| 232 | @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)\r | |
| 233 | @param EAX Lower 32-bits of MSR value.\r | |
| 234 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r | |
| 235 | @param EDX Upper 32-bits of MSR value.\r | |
| 236 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r | |
| 237 | \r | |
| 238 | <b>Example usage</b>\r | |
| 239 | @code\r | |
| 240 | MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;\r | |
| 241 | \r | |
| 242 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);\r | |
| 243 | AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);\r | |
| 244 | @endcode\r | |
| e108c3f6 | 245 | @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r |
| 7ae88a62 MK |
246 | **/\r |
| 247 | #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r | |
| 248 | \r | |
| 249 | /**\r | |
| 250 | MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2\r | |
| 251 | **/\r | |
| 252 | typedef union {\r | |
| 253 | ///\r | |
| 254 | /// Individual bit fields\r | |
| 255 | ///\r | |
| 256 | struct {\r | |
| 257 | ///\r | |
| 258 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 259 | ///\r | |
| 260 | UINT32 EventSelect:8;\r | |
| 261 | ///\r | |
| 262 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 263 | /// detect on the selected event logic.\r | |
| 264 | ///\r | |
| 265 | UINT32 UMASK:8;\r | |
| 266 | ///\r | |
| 267 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 268 | ///\r | |
| 269 | UINT32 USR:1;\r | |
| 270 | ///\r | |
| 271 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 272 | ///\r | |
| 273 | UINT32 OS:1;\r | |
| 274 | ///\r | |
| 275 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 276 | ///\r | |
| 277 | UINT32 E:1;\r | |
| 278 | ///\r | |
| 279 | /// [Bit 19] PC: enables pin control.\r | |
| 280 | ///\r | |
| 281 | UINT32 PC:1;\r | |
| 282 | ///\r | |
| 283 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 284 | ///\r | |
| 285 | UINT32 INT:1;\r | |
| 286 | ///\r | |
| 287 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 288 | /// event conditions occurring across all logical processors sharing a\r | |
| 289 | /// processor core. When set to 0, the counter only increments the\r | |
| 290 | /// associated event conditions occurring in the logical processor which\r | |
| 291 | /// programmed the MSR.\r | |
| 292 | ///\r | |
| 293 | UINT32 ANY:1;\r | |
| 294 | ///\r | |
| 295 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 296 | /// counting when this bit is set.\r | |
| 297 | ///\r | |
| 298 | UINT32 EN:1;\r | |
| 299 | ///\r | |
| 300 | /// [Bit 23] INV: invert the CMASK.\r | |
| 301 | ///\r | |
| 302 | UINT32 INV:1;\r | |
| 303 | ///\r | |
| 304 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 305 | /// performance counter increments each cycle if the event count is\r | |
| 306 | /// greater than or equal to the CMASK.\r | |
| 307 | ///\r | |
| 308 | UINT32 CMASK:8;\r | |
| 309 | UINT32 Reserved:32;\r | |
| 310 | ///\r | |
| ba1a2d11 | 311 | /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r |
| 7ae88a62 MK |
312 | /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r |
| 313 | ///\r | |
| 314 | UINT32 IN_TX:1;\r | |
| 315 | ///\r | |
| ba1a2d11 | 316 | /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and\r |
| 7ae88a62 MK |
317 | /// in sampling, spurious PMI may occur and transactions may continuously\r |
| 318 | /// abort near overflow conditions. Software should favor using IN_TXCP\r | |
| 319 | /// for counting over sampling. If sampling, software should use large\r | |
| 320 | /// "sample-after" value after clearing the counter configured to use\r | |
| 321 | /// IN_TXCP and also always reset the counter even when no overflow\r | |
| 322 | /// condition was reported.\r | |
| 323 | ///\r | |
| 324 | UINT32 IN_TXCP:1;\r | |
| 325 | UINT32 Reserved2:30;\r | |
| 326 | } Bits;\r | |
| 327 | ///\r | |
| 328 | /// All bit fields as a 64-bit value\r | |
| 329 | ///\r | |
| 330 | UINT64 Uint64;\r | |
| 331 | } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;\r | |
| 332 | \r | |
| 333 | \r | |
| 334 | /**\r | |
| 335 | Thread. Last Branch Record Filtering Select Register (R/W).\r | |
| 336 | \r | |
| 337 | @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)\r | |
| 338 | @param EAX Lower 32-bits of MSR value.\r | |
| 339 | Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r | |
| 340 | @param EDX Upper 32-bits of MSR value.\r | |
| 341 | Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r | |
| 342 | \r | |
| 343 | <b>Example usage</b>\r | |
| 344 | @code\r | |
| 345 | MSR_HASWELL_LBR_SELECT_REGISTER Msr;\r | |
| 346 | \r | |
| 347 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);\r | |
| 348 | AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);\r | |
| 349 | @endcode\r | |
| e108c3f6 | 350 | @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r |
| 7ae88a62 MK |
351 | **/\r |
| 352 | #define MSR_HASWELL_LBR_SELECT 0x000001C8\r | |
| 353 | \r | |
| 354 | /**\r | |
| 355 | MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT\r | |
| 356 | **/\r | |
| 357 | typedef union {\r | |
| 358 | ///\r | |
| 359 | /// Individual bit fields\r | |
| 360 | ///\r | |
| 361 | struct {\r | |
| 362 | ///\r | |
| 363 | /// [Bit 0] CPL_EQ_0.\r | |
| 364 | ///\r | |
| 365 | UINT32 CPL_EQ_0:1;\r | |
| 366 | ///\r | |
| 367 | /// [Bit 1] CPL_NEQ_0.\r | |
| 368 | ///\r | |
| 369 | UINT32 CPL_NEQ_0:1;\r | |
| 370 | ///\r | |
| 371 | /// [Bit 2] JCC.\r | |
| 372 | ///\r | |
| 373 | UINT32 JCC:1;\r | |
| 374 | ///\r | |
| 375 | /// [Bit 3] NEAR_REL_CALL.\r | |
| 376 | ///\r | |
| 377 | UINT32 NEAR_REL_CALL:1;\r | |
| 378 | ///\r | |
| 379 | /// [Bit 4] NEAR_IND_CALL.\r | |
| 380 | ///\r | |
| 381 | UINT32 NEAR_IND_CALL:1;\r | |
| 382 | ///\r | |
| 383 | /// [Bit 5] NEAR_RET.\r | |
| 384 | ///\r | |
| 385 | UINT32 NEAR_RET:1;\r | |
| 386 | ///\r | |
| 387 | /// [Bit 6] NEAR_IND_JMP.\r | |
| 388 | ///\r | |
| 389 | UINT32 NEAR_IND_JMP:1;\r | |
| 390 | ///\r | |
| 391 | /// [Bit 7] NEAR_REL_JMP.\r | |
| 392 | ///\r | |
| 393 | UINT32 NEAR_REL_JMP:1;\r | |
| 394 | ///\r | |
| 395 | /// [Bit 8] FAR_BRANCH.\r | |
| 396 | ///\r | |
| 397 | UINT32 FAR_BRANCH:1;\r | |
| 398 | ///\r | |
| 399 | /// [Bit 9] EN_CALL_STACK.\r | |
| 400 | ///\r | |
| 401 | UINT32 EN_CALL_STACK:1;\r | |
| 402 | UINT32 Reserved1:22;\r | |
| 403 | UINT32 Reserved2:32;\r | |
| 404 | } Bits;\r | |
| 405 | ///\r | |
| 406 | /// All bit fields as a 32-bit value\r | |
| 407 | ///\r | |
| 408 | UINT32 Uint32;\r | |
| 409 | ///\r | |
| 410 | /// All bit fields as a 64-bit value\r | |
| 411 | ///\r | |
| 412 | UINT64 Uint64;\r | |
| 413 | } MSR_HASWELL_LBR_SELECT_REGISTER;\r | |
| 414 | \r | |
| 415 | \r | |
| 416 | /**\r | |
| 417 | Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines\r | |
| 418 | the interrupt response time limit used by the processor to manage transition\r | |
| 419 | to package C6 or C7 state. The latency programmed in this register is for\r | |
| 420 | the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.\r | |
| 421 | Note: C-state values are processor specific C-state code names, unrelated to\r | |
| 422 | MWAIT extension C-state parameters or ACPI C-States.\r | |
| 423 | \r | |
| 424 | @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)\r | |
| 425 | @param EAX Lower 32-bits of MSR value.\r | |
| 426 | Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r | |
| 427 | @param EDX Upper 32-bits of MSR value.\r | |
| 428 | Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r | |
| 429 | \r | |
| 430 | <b>Example usage</b>\r | |
| 431 | @code\r | |
| 432 | MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;\r | |
| 433 | \r | |
| 434 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);\r | |
| 435 | AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);\r | |
| 436 | @endcode\r | |
| e108c3f6 | 437 | @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r |
| 7ae88a62 MK |
438 | **/\r |
| 439 | #define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r | |
| 440 | \r | |
| 441 | /**\r | |
| 442 | MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1\r | |
| 443 | **/\r | |
| 444 | typedef union {\r | |
| 445 | ///\r | |
| 446 | /// Individual bit fields\r | |
| 447 | ///\r | |
| 448 | struct {\r | |
| 449 | ///\r | |
| 450 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
| 451 | /// that should be used to decide if the package should be put into a\r | |
| 452 | /// package C6 or C7 state.\r | |
| 453 | ///\r | |
| 454 | UINT32 InterruptResponseTimeLimit:10;\r | |
| 455 | ///\r | |
| ba1a2d11 ED |
456 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
| 457 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
| 458 | /// time unit encodings.\r | |
| 7ae88a62 MK |
459 | ///\r |
| 460 | UINT32 TimeUnit:3;\r | |
| 461 | UINT32 Reserved1:2;\r | |
| 462 | ///\r | |
| 463 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
| 464 | /// valid and can be used by the processor for package C-sate management.\r | |
| 465 | ///\r | |
| 466 | UINT32 Valid:1;\r | |
| 467 | UINT32 Reserved2:16;\r | |
| 468 | UINT32 Reserved3:32;\r | |
| 469 | } Bits;\r | |
| 470 | ///\r | |
| 471 | /// All bit fields as a 32-bit value\r | |
| 472 | ///\r | |
| 473 | UINT32 Uint32;\r | |
| 474 | ///\r | |
| 475 | /// All bit fields as a 64-bit value\r | |
| 476 | ///\r | |
| 477 | UINT64 Uint64;\r | |
| 478 | } MSR_HASWELL_PKGC_IRTL1_REGISTER;\r | |
| 479 | \r | |
| 480 | \r | |
| 481 | /**\r | |
| 482 | Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines\r | |
| 483 | the interrupt response time limit used by the processor to manage transition\r | |
| 484 | to package C6 or C7 state. The latency programmed in this register is for\r | |
| 485 | the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.\r | |
| 486 | Note: C-state values are processor specific C-state code names, unrelated to\r | |
| 487 | MWAIT extension C-state parameters or ACPI C-States.\r | |
| 488 | \r | |
| 489 | @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)\r | |
| 490 | @param EAX Lower 32-bits of MSR value.\r | |
| 491 | Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r | |
| 492 | @param EDX Upper 32-bits of MSR value.\r | |
| 493 | Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r | |
| 494 | \r | |
| 495 | <b>Example usage</b>\r | |
| 496 | @code\r | |
| 497 | MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;\r | |
| 498 | \r | |
| 499 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);\r | |
| 500 | AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);\r | |
| 501 | @endcode\r | |
| e108c3f6 | 502 | @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r |
| 7ae88a62 MK |
503 | **/\r |
| 504 | #define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r | |
| 505 | \r | |
| 506 | /**\r | |
| 507 | MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2\r | |
| 508 | **/\r | |
| 509 | typedef union {\r | |
| 510 | ///\r | |
| 511 | /// Individual bit fields\r | |
| 512 | ///\r | |
| 513 | struct {\r | |
| 514 | ///\r | |
| ba1a2d11 | 515 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r |
| 7ae88a62 MK |
516 | /// that should be used to decide if the package should be put into a\r |
| 517 | /// package C6 or C7 state.\r | |
| 518 | ///\r | |
| 519 | UINT32 InterruptResponseTimeLimit:10;\r | |
| 520 | ///\r | |
| ba1a2d11 ED |
521 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
| 522 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
| 523 | /// time unit encodings.\r | |
| 7ae88a62 MK |
524 | ///\r |
| 525 | UINT32 TimeUnit:3;\r | |
| 526 | UINT32 Reserved1:2;\r | |
| 527 | ///\r | |
| 528 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
| 529 | /// valid and can be used by the processor for package C-sate management.\r | |
| 530 | ///\r | |
| 531 | UINT32 Valid:1;\r | |
| 532 | UINT32 Reserved2:16;\r | |
| 533 | UINT32 Reserved3:32;\r | |
| 534 | } Bits;\r | |
| 535 | ///\r | |
| 536 | /// All bit fields as a 32-bit value\r | |
| 537 | ///\r | |
| 538 | UINT32 Uint32;\r | |
| 539 | ///\r | |
| 540 | /// All bit fields as a 64-bit value\r | |
| 541 | ///\r | |
| 542 | UINT64 Uint64;\r | |
| 543 | } MSR_HASWELL_PKGC_IRTL2_REGISTER;\r | |
| 544 | \r | |
| 545 | \r | |
| 546 | /**\r | |
| 547 | Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
| 548 | \r | |
| 549 | @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)\r | |
| 550 | @param EAX Lower 32-bits of MSR value.\r | |
| 551 | @param EDX Upper 32-bits of MSR value.\r | |
| 552 | \r | |
| 553 | <b>Example usage</b>\r | |
| 554 | @code\r | |
| 555 | UINT64 Msr;\r | |
| 556 | \r | |
| 557 | Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);\r | |
| 558 | @endcode\r | |
| e108c3f6 | 559 | @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
| 7ae88a62 MK |
560 | **/\r |
| 561 | #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r | |
| 562 | \r | |
| 563 | \r | |
| 564 | /**\r | |
| 565 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 566 | \r | |
| 567 | @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 568 | @param EAX Lower 32-bits of MSR value.\r | |
| 569 | @param EDX Upper 32-bits of MSR value.\r | |
| 570 | \r | |
| 571 | <b>Example usage</b>\r | |
| 572 | @code\r | |
| 573 | UINT64 Msr;\r | |
| 574 | \r | |
| 575 | Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);\r | |
| 576 | @endcode\r | |
| e108c3f6 | 577 | @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
| 7ae88a62 MK |
578 | **/\r |
| 579 | #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r | |
| 580 | \r | |
| 581 | \r | |
| 582 | /**\r | |
| 583 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 584 | RAPL Domain.".\r | |
| 585 | \r | |
| 586 | @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)\r | |
| 587 | @param EAX Lower 32-bits of MSR value.\r | |
| 588 | @param EDX Upper 32-bits of MSR value.\r | |
| 589 | \r | |
| 590 | <b>Example usage</b>\r | |
| 591 | @code\r | |
| 592 | UINT64 Msr;\r | |
| 593 | \r | |
| 594 | Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);\r | |
| 595 | @endcode\r | |
| e108c3f6 | 596 | @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
| 7ae88a62 MK |
597 | **/\r |
| 598 | #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r | |
| 599 | \r | |
| 600 | \r | |
| 601 | /**\r | |
| 602 | Package. Base TDP Ratio (R/O).\r | |
| 603 | \r | |
| 604 | @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)\r | |
| 605 | @param EAX Lower 32-bits of MSR value.\r | |
| 606 | Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 607 | @param EDX Upper 32-bits of MSR value.\r | |
| 608 | Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 609 | \r | |
| 610 | <b>Example usage</b>\r | |
| 611 | @code\r | |
| 612 | MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;\r | |
| 613 | \r | |
| 614 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);\r | |
| 615 | @endcode\r | |
| e108c3f6 | 616 | @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r |
| 7ae88a62 MK |
617 | **/\r |
| 618 | #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r | |
| 619 | \r | |
| 620 | /**\r | |
| 621 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL\r | |
| 622 | **/\r | |
| 623 | typedef union {\r | |
| 624 | ///\r | |
| 625 | /// Individual bit fields\r | |
| 626 | ///\r | |
| 627 | struct {\r | |
| 628 | ///\r | |
| 629 | /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r | |
| 630 | /// specific processor (in units of 100 MHz).\r | |
| 631 | ///\r | |
| 632 | UINT32 Config_TDP_Base:8;\r | |
| 633 | UINT32 Reserved1:24;\r | |
| 634 | UINT32 Reserved2:32;\r | |
| 635 | } Bits;\r | |
| 636 | ///\r | |
| 637 | /// All bit fields as a 32-bit value\r | |
| 638 | ///\r | |
| 639 | UINT32 Uint32;\r | |
| 640 | ///\r | |
| 641 | /// All bit fields as a 64-bit value\r | |
| 642 | ///\r | |
| 643 | UINT64 Uint64;\r | |
| 644 | } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;\r | |
| 645 | \r | |
| 646 | \r | |
| 647 | /**\r | |
| 648 | Package. ConfigTDP Level 1 ratio and power level (R/O).\r | |
| 649 | \r | |
| 650 | @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)\r | |
| 651 | @param EAX Lower 32-bits of MSR value.\r | |
| 652 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 653 | @param EDX Upper 32-bits of MSR value.\r | |
| 654 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 655 | \r | |
| 656 | <b>Example usage</b>\r | |
| 657 | @code\r | |
| 658 | MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;\r | |
| 659 | \r | |
| 660 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);\r | |
| 661 | @endcode\r | |
| e108c3f6 | 662 | @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r |
| 7ae88a62 MK |
663 | **/\r |
| 664 | #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r | |
| 665 | \r | |
| 666 | /**\r | |
| 667 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1\r | |
| 668 | **/\r | |
| 669 | typedef union {\r | |
| 670 | ///\r | |
| 671 | /// Individual bit fields\r | |
| 672 | ///\r | |
| 673 | struct {\r | |
| 674 | ///\r | |
| 675 | /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r | |
| 676 | ///\r | |
| 677 | UINT32 PKG_TDP_LVL1:15;\r | |
| 678 | UINT32 Reserved1:1;\r | |
| 679 | ///\r | |
| 680 | /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r | |
| 681 | /// for this specific processor.\r | |
| 682 | ///\r | |
| 683 | UINT32 Config_TDP_LVL1_Ratio:8;\r | |
| 684 | UINT32 Reserved2:8;\r | |
| 685 | ///\r | |
| 686 | /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r | |
| 687 | /// Level 1.\r | |
| 688 | ///\r | |
| 689 | UINT32 PKG_MAX_PWR_LVL1:15;\r | |
| 690 | ///\r | |
| 691 | /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r | |
| 692 | /// Level 1.\r | |
| 693 | ///\r | |
| 694 | UINT32 PKG_MIN_PWR_LVL1:16;\r | |
| 695 | UINT32 Reserved3:1;\r | |
| 696 | } Bits;\r | |
| 697 | ///\r | |
| 698 | /// All bit fields as a 64-bit value\r | |
| 699 | ///\r | |
| 700 | UINT64 Uint64;\r | |
| 701 | } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;\r | |
| 702 | \r | |
| 703 | \r | |
| 704 | /**\r | |
| 705 | Package. ConfigTDP Level 2 ratio and power level (R/O).\r | |
| 706 | \r | |
| 707 | @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)\r | |
| 708 | @param EAX Lower 32-bits of MSR value.\r | |
| 709 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 710 | @param EDX Upper 32-bits of MSR value.\r | |
| 711 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 712 | \r | |
| 713 | <b>Example usage</b>\r | |
| 714 | @code\r | |
| 715 | MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;\r | |
| 716 | \r | |
| 717 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);\r | |
| 718 | @endcode\r | |
| e108c3f6 | 719 | @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r |
| 7ae88a62 MK |
720 | **/\r |
| 721 | #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r | |
| 722 | \r | |
| 723 | /**\r | |
| 724 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2\r | |
| 725 | **/\r | |
| 726 | typedef union {\r | |
| 727 | ///\r | |
| 728 | /// Individual bit fields\r | |
| 729 | ///\r | |
| 730 | struct {\r | |
| 731 | ///\r | |
| 732 | /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r | |
| 733 | ///\r | |
| 734 | UINT32 PKG_TDP_LVL2:15;\r | |
| 735 | UINT32 Reserved1:1;\r | |
| 736 | ///\r | |
| 737 | /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r | |
| 738 | /// for this specific processor.\r | |
| 739 | ///\r | |
| 740 | UINT32 Config_TDP_LVL2_Ratio:8;\r | |
| 741 | UINT32 Reserved2:8;\r | |
| 742 | ///\r | |
| 743 | /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r | |
| 744 | /// Level 2.\r | |
| 745 | ///\r | |
| 746 | UINT32 PKG_MAX_PWR_LVL2:15;\r | |
| 747 | ///\r | |
| 748 | /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r | |
| 749 | /// Level 2.\r | |
| 750 | ///\r | |
| 751 | UINT32 PKG_MIN_PWR_LVL2:16;\r | |
| 752 | UINT32 Reserved3:1;\r | |
| 753 | } Bits;\r | |
| 754 | ///\r | |
| 755 | /// All bit fields as a 64-bit value\r | |
| 756 | ///\r | |
| 757 | UINT64 Uint64;\r | |
| 758 | } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;\r | |
| 759 | \r | |
| 760 | \r | |
| 761 | /**\r | |
| 762 | Package. ConfigTDP Control (R/W).\r | |
| 763 | \r | |
| 764 | @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)\r | |
| 765 | @param EAX Lower 32-bits of MSR value.\r | |
| 766 | Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 767 | @param EDX Upper 32-bits of MSR value.\r | |
| 768 | Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 769 | \r | |
| 770 | <b>Example usage</b>\r | |
| 771 | @code\r | |
| 772 | MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;\r | |
| 773 | \r | |
| 774 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);\r | |
| 775 | AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);\r | |
| 776 | @endcode\r | |
| e108c3f6 | 777 | @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r |
| 7ae88a62 MK |
778 | **/\r |
| 779 | #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r | |
| 780 | \r | |
| 781 | /**\r | |
| 782 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL\r | |
| 783 | **/\r | |
| 784 | typedef union {\r | |
| 785 | ///\r | |
| 786 | /// Individual bit fields\r | |
| 787 | ///\r | |
| 788 | struct {\r | |
| 789 | ///\r | |
| 790 | /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r | |
| 791 | ///\r | |
| 792 | UINT32 TDP_LEVEL:2;\r | |
| 793 | UINT32 Reserved1:29;\r | |
| 794 | ///\r | |
| 795 | /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r | |
| 796 | /// this register is locked until a reset.\r | |
| 797 | ///\r | |
| 798 | UINT32 Config_TDP_Lock:1;\r | |
| 799 | UINT32 Reserved2:32;\r | |
| 800 | } Bits;\r | |
| 801 | ///\r | |
| 802 | /// All bit fields as a 32-bit value\r | |
| 803 | ///\r | |
| 804 | UINT32 Uint32;\r | |
| 805 | ///\r | |
| 806 | /// All bit fields as a 64-bit value\r | |
| 807 | ///\r | |
| 808 | UINT64 Uint64;\r | |
| 809 | } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;\r | |
| 810 | \r | |
| 811 | \r | |
| 812 | /**\r | |
| 813 | Package. ConfigTDP Control (R/W).\r | |
| 814 | \r | |
| 815 | @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
| 816 | @param EAX Lower 32-bits of MSR value.\r | |
| 817 | Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 818 | @param EDX Upper 32-bits of MSR value.\r | |
| 819 | Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 820 | \r | |
| 821 | <b>Example usage</b>\r | |
| 822 | @code\r | |
| 823 | MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r | |
| 824 | \r | |
| 825 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);\r | |
| 826 | AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r | |
| 827 | @endcode\r | |
| e108c3f6 | 828 | @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r |
| 7ae88a62 MK |
829 | **/\r |
| 830 | #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
| 831 | \r | |
| 832 | /**\r | |
| 833 | MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO\r | |
| 834 | **/\r | |
| 835 | typedef union {\r | |
| 836 | ///\r | |
| 837 | /// Individual bit fields\r | |
| 838 | ///\r | |
| 839 | struct {\r | |
| 840 | ///\r | |
| 841 | /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r | |
| 842 | /// field.\r | |
| 843 | ///\r | |
| 844 | UINT32 MAX_NON_TURBO_RATIO:8;\r | |
| 845 | UINT32 Reserved1:23;\r | |
| 846 | ///\r | |
| 847 | /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r | |
| 848 | /// content of this register is locked until a reset.\r | |
| 849 | ///\r | |
| 850 | UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r | |
| 851 | UINT32 Reserved2:32;\r | |
| 852 | } Bits;\r | |
| 853 | ///\r | |
| 854 | /// All bit fields as a 32-bit value\r | |
| 855 | ///\r | |
| 856 | UINT32 Uint32;\r | |
| 857 | ///\r | |
| 858 | /// All bit fields as a 64-bit value\r | |
| 859 | ///\r | |
| 860 | UINT64 Uint64;\r | |
| 861 | } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r | |
| 862 | \r | |
| 863 | \r | |
| 7ae88a62 MK |
864 | /**\r |
| 865 | Core. C-State Configuration Control (R/W) Note: C-state values are processor\r | |
| 866 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
| 867 | or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.\r | |
| 868 | \r | |
| 869 | @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 870 | @param EAX Lower 32-bits of MSR value.\r | |
| 871 | Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 872 | @param EDX Upper 32-bits of MSR value.\r | |
| 873 | Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 874 | \r | |
| 875 | <b>Example usage</b>\r | |
| 876 | @code\r | |
| 877 | MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 878 | \r | |
| 879 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);\r | |
| 880 | AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 881 | @endcode\r | |
| e108c3f6 | 882 | @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| 7ae88a62 MK |
883 | **/\r |
| 884 | #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 885 | \r | |
| 886 | /**\r | |
| 887 | MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL\r | |
| 888 | **/\r | |
| 889 | typedef union {\r | |
| 890 | ///\r | |
| 891 | /// Individual bit fields\r | |
| 892 | ///\r | |
| 893 | struct {\r | |
| 894 | ///\r | |
| 895 | /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 896 | /// processor-specific C-state code name (consuming the least power) for\r | |
| 897 | /// the package. The default is set as factory-configured package C-state\r | |
| 898 | /// limit. The following C-state code name encodings are supported: 0000b:\r | |
| 899 | /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r | |
| 900 | /// 0100b: C7 0101b: C7s Package C states C7 are not available to\r | |
| 901 | /// processor with signature 06_3CH.\r | |
| 902 | ///\r | |
| 903 | UINT32 Limit:4;\r | |
| 904 | UINT32 Reserved1:6;\r | |
| 905 | ///\r | |
| 906 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
| 907 | ///\r | |
| 908 | UINT32 IO_MWAIT:1;\r | |
| 909 | UINT32 Reserved2:4;\r | |
| 910 | ///\r | |
| 911 | /// [Bit 15] CFG Lock (R/WO).\r | |
| 912 | ///\r | |
| 913 | UINT32 CFGLock:1;\r | |
| 914 | UINT32 Reserved3:9;\r | |
| 915 | ///\r | |
| 916 | /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r | |
| 917 | ///\r | |
| 918 | UINT32 C3AutoDemotion:1;\r | |
| 919 | ///\r | |
| 920 | /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r | |
| 921 | ///\r | |
| 922 | UINT32 C1AutoDemotion:1;\r | |
| 923 | ///\r | |
| 924 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
| 925 | ///\r | |
| 926 | UINT32 C3Undemotion:1;\r | |
| 927 | ///\r | |
| 928 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
| 929 | ///\r | |
| 930 | UINT32 C1Undemotion:1;\r | |
| 931 | UINT32 Reserved4:3;\r | |
| 932 | UINT32 Reserved5:32;\r | |
| 933 | } Bits;\r | |
| 934 | ///\r | |
| 935 | /// All bit fields as a 32-bit value\r | |
| 936 | ///\r | |
| 937 | UINT32 Uint32;\r | |
| 938 | ///\r | |
| 939 | /// All bit fields as a 64-bit value\r | |
| 940 | ///\r | |
| 941 | UINT64 Uint64;\r | |
| 942 | } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 943 | \r | |
| 944 | \r | |
| 945 | /**\r | |
| 946 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
| 947 | Enhancement. Accessible only while in SMM.\r | |
| 948 | \r | |
| 949 | @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)\r | |
| 950 | @param EAX Lower 32-bits of MSR value.\r | |
| 951 | Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r | |
| 952 | @param EDX Upper 32-bits of MSR value.\r | |
| 953 | Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r | |
| 954 | \r | |
| 955 | <b>Example usage</b>\r | |
| 956 | @code\r | |
| 957 | MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;\r | |
| 958 | \r | |
| 959 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);\r | |
| 960 | AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);\r | |
| 961 | @endcode\r | |
| e108c3f6 | 962 | @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r |
| 7ae88a62 MK |
963 | **/\r |
| 964 | #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r | |
| 965 | \r | |
| 966 | /**\r | |
| 967 | MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP\r | |
| 968 | **/\r | |
| 969 | typedef union {\r | |
| 970 | ///\r | |
| 971 | /// Individual bit fields\r | |
| 972 | ///\r | |
| 973 | struct {\r | |
| 974 | UINT32 Reserved1:32;\r | |
| 975 | UINT32 Reserved2:26;\r | |
| 976 | ///\r | |
| 977 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
| 978 | /// SMM code access restriction is supported and the\r | |
| 979 | /// MSR_SMM_FEATURE_CONTROL is supported.\r | |
| 980 | ///\r | |
| 981 | UINT32 SMM_Code_Access_Chk:1;\r | |
| 982 | ///\r | |
| 983 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
| 984 | /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r | |
| 985 | /// supported.\r | |
| 986 | ///\r | |
| 987 | UINT32 Long_Flow_Indication:1;\r | |
| 988 | UINT32 Reserved3:4;\r | |
| 989 | } Bits;\r | |
| 990 | ///\r | |
| 991 | /// All bit fields as a 64-bit value\r | |
| 992 | ///\r | |
| 993 | UINT64 Uint64;\r | |
| 994 | } MSR_HASWELL_SMM_MCA_CAP_REGISTER;\r | |
| 995 | \r | |
| 996 | \r | |
| 997 | /**\r | |
| 998 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 999 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 1000 | \r | |
| 1001 | @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 1002 | @param EAX Lower 32-bits of MSR value.\r | |
| 1003 | Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 1004 | @param EDX Upper 32-bits of MSR value.\r | |
| 1005 | Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 1006 | \r | |
| 1007 | <b>Example usage</b>\r | |
| 1008 | @code\r | |
| 1009 | MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 1010 | \r | |
| 1011 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);\r | |
| 1012 | @endcode\r | |
| e108c3f6 | 1013 | @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
| 7ae88a62 MK |
1014 | **/\r |
| 1015 | #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r | |
| 1016 | \r | |
| 1017 | /**\r | |
| 1018 | MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT\r | |
| 1019 | **/\r | |
| 1020 | typedef union {\r | |
| 1021 | ///\r | |
| 1022 | /// Individual bit fields\r | |
| 1023 | ///\r | |
| 1024 | struct {\r | |
| 1025 | ///\r | |
| 1026 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
| 1027 | /// limit of 1 core active.\r | |
| 1028 | ///\r | |
| 1029 | UINT32 Maximum1C:8;\r | |
| 1030 | ///\r | |
| 1031 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
| 1032 | /// limit of 2 core active.\r | |
| 1033 | ///\r | |
| 1034 | UINT32 Maximum2C:8;\r | |
| 1035 | ///\r | |
| 1036 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
| 1037 | /// limit of 3 core active.\r | |
| 1038 | ///\r | |
| 1039 | UINT32 Maximum3C:8;\r | |
| 1040 | ///\r | |
| 1041 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
| 1042 | /// limit of 4 core active.\r | |
| 1043 | ///\r | |
| 1044 | UINT32 Maximum4C:8;\r | |
| 1045 | UINT32 Reserved:32;\r | |
| 1046 | } Bits;\r | |
| 1047 | ///\r | |
| 1048 | /// All bit fields as a 32-bit value\r | |
| 1049 | ///\r | |
| 1050 | UINT32 Uint32;\r | |
| 1051 | ///\r | |
| 1052 | /// All bit fields as a 64-bit value\r | |
| 1053 | ///\r | |
| 1054 | UINT64 Uint64;\r | |
| 1055 | } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;\r | |
| 1056 | \r | |
| 1057 | \r | |
| 1058 | /**\r | |
| 1059 | Package. Uncore PMU global control.\r | |
| 1060 | \r | |
| 1061 | @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)\r | |
| 1062 | @param EAX Lower 32-bits of MSR value.\r | |
| 1063 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 1064 | @param EDX Upper 32-bits of MSR value.\r | |
| 1065 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 1066 | \r | |
| 1067 | <b>Example usage</b>\r | |
| 1068 | @code\r | |
| 1069 | MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
| 1070 | \r | |
| 1071 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);\r | |
| 1072 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
| 1073 | @endcode\r | |
| e108c3f6 | 1074 | @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r |
| 7ae88a62 MK |
1075 | **/\r |
| 1076 | #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r | |
| 1077 | \r | |
| 1078 | /**\r | |
| 1079 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL\r | |
| 1080 | **/\r | |
| 1081 | typedef union {\r | |
| 1082 | ///\r | |
| 1083 | /// Individual bit fields\r | |
| 1084 | ///\r | |
| 1085 | struct {\r | |
| 1086 | ///\r | |
| 1087 | /// [Bit 0] Core 0 select.\r | |
| 1088 | ///\r | |
| 1089 | UINT32 PMI_Sel_Core0:1;\r | |
| 1090 | ///\r | |
| 1091 | /// [Bit 1] Core 1 select.\r | |
| 1092 | ///\r | |
| 1093 | UINT32 PMI_Sel_Core1:1;\r | |
| 1094 | ///\r | |
| 1095 | /// [Bit 2] Core 2 select.\r | |
| 1096 | ///\r | |
| 1097 | UINT32 PMI_Sel_Core2:1;\r | |
| 1098 | ///\r | |
| 1099 | /// [Bit 3] Core 3 select.\r | |
| 1100 | ///\r | |
| 1101 | UINT32 PMI_Sel_Core3:1;\r | |
| 1102 | UINT32 Reserved1:15;\r | |
| 1103 | UINT32 Reserved2:10;\r | |
| 1104 | ///\r | |
| 1105 | /// [Bit 29] Enable all uncore counters.\r | |
| 1106 | ///\r | |
| 1107 | UINT32 EN:1;\r | |
| 1108 | ///\r | |
| 1109 | /// [Bit 30] Enable wake on PMI.\r | |
| 1110 | ///\r | |
| 1111 | UINT32 WakePMI:1;\r | |
| 1112 | ///\r | |
| 1113 | /// [Bit 31] Enable Freezing counter when overflow.\r | |
| 1114 | ///\r | |
| 1115 | UINT32 FREEZE:1;\r | |
| 1116 | UINT32 Reserved3:32;\r | |
| 1117 | } Bits;\r | |
| 1118 | ///\r | |
| 1119 | /// All bit fields as a 32-bit value\r | |
| 1120 | ///\r | |
| 1121 | UINT32 Uint32;\r | |
| 1122 | ///\r | |
| 1123 | /// All bit fields as a 64-bit value\r | |
| 1124 | ///\r | |
| 1125 | UINT64 Uint64;\r | |
| 1126 | } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;\r | |
| 1127 | \r | |
| 1128 | \r | |
| 1129 | /**\r | |
| 1130 | Package. Uncore PMU main status.\r | |
| 1131 | \r | |
| 1132 | @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)\r | |
| 1133 | @param EAX Lower 32-bits of MSR value.\r | |
| 1134 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 1135 | @param EDX Upper 32-bits of MSR value.\r | |
| 1136 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 1137 | \r | |
| 1138 | <b>Example usage</b>\r | |
| 1139 | @code\r | |
| 1140 | MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
| 1141 | \r | |
| 1142 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);\r | |
| 1143 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r | |
| 1144 | @endcode\r | |
| e108c3f6 | 1145 | @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r |
| 7ae88a62 MK |
1146 | **/\r |
| 1147 | #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r | |
| 1148 | \r | |
| 1149 | /**\r | |
| 1150 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS\r | |
| 1151 | **/\r | |
| 1152 | typedef union {\r | |
| 1153 | ///\r | |
| 1154 | /// Individual bit fields\r | |
| 1155 | ///\r | |
| 1156 | struct {\r | |
| 1157 | ///\r | |
| 1158 | /// [Bit 0] Fixed counter overflowed.\r | |
| 1159 | ///\r | |
| 1160 | UINT32 Fixed:1;\r | |
| 1161 | ///\r | |
| 1162 | /// [Bit 1] An ARB counter overflowed.\r | |
| 1163 | ///\r | |
| 1164 | UINT32 ARB:1;\r | |
| 1165 | UINT32 Reserved1:1;\r | |
| 1166 | ///\r | |
| 1167 | /// [Bit 3] A CBox counter overflowed (on any slice).\r | |
| 1168 | ///\r | |
| 1169 | UINT32 CBox:1;\r | |
| 1170 | UINT32 Reserved2:28;\r | |
| 1171 | UINT32 Reserved3:32;\r | |
| 1172 | } Bits;\r | |
| 1173 | ///\r | |
| 1174 | /// All bit fields as a 32-bit value\r | |
| 1175 | ///\r | |
| 1176 | UINT32 Uint32;\r | |
| 1177 | ///\r | |
| 1178 | /// All bit fields as a 64-bit value\r | |
| 1179 | ///\r | |
| 1180 | UINT64 Uint64;\r | |
| 1181 | } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;\r | |
| 1182 | \r | |
| 1183 | \r | |
| 1184 | /**\r | |
| 1185 | Package. Uncore fixed counter control (R/W).\r | |
| 1186 | \r | |
| 1187 | @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)\r | |
| 1188 | @param EAX Lower 32-bits of MSR value.\r | |
| 1189 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
| 1190 | @param EDX Upper 32-bits of MSR value.\r | |
| 1191 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
| 1192 | \r | |
| 1193 | <b>Example usage</b>\r | |
| 1194 | @code\r | |
| 1195 | MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r | |
| 1196 | \r | |
| 1197 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);\r | |
| 1198 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r | |
| 1199 | @endcode\r | |
| e108c3f6 | 1200 | @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r |
| 7ae88a62 MK |
1201 | **/\r |
| 1202 | #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r | |
| 1203 | \r | |
| 1204 | /**\r | |
| 1205 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL\r | |
| 1206 | **/\r | |
| 1207 | typedef union {\r | |
| 1208 | ///\r | |
| 1209 | /// Individual bit fields\r | |
| 1210 | ///\r | |
| 1211 | struct {\r | |
| 1212 | UINT32 Reserved1:20;\r | |
| 1213 | ///\r | |
| 1214 | /// [Bit 20] Enable overflow propagation.\r | |
| 1215 | ///\r | |
| 1216 | UINT32 EnableOverflow:1;\r | |
| 1217 | UINT32 Reserved2:1;\r | |
| 1218 | ///\r | |
| 1219 | /// [Bit 22] Enable counting.\r | |
| 1220 | ///\r | |
| 1221 | UINT32 EnableCounting:1;\r | |
| 1222 | UINT32 Reserved3:9;\r | |
| 1223 | UINT32 Reserved4:32;\r | |
| 1224 | } Bits;\r | |
| 1225 | ///\r | |
| 1226 | /// All bit fields as a 32-bit value\r | |
| 1227 | ///\r | |
| 1228 | UINT32 Uint32;\r | |
| 1229 | ///\r | |
| 1230 | /// All bit fields as a 64-bit value\r | |
| 1231 | ///\r | |
| 1232 | UINT64 Uint64;\r | |
| 1233 | } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;\r | |
| 1234 | \r | |
| 1235 | \r | |
| 1236 | /**\r | |
| 1237 | Package. Uncore fixed counter.\r | |
| 1238 | \r | |
| 1239 | @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)\r | |
| 1240 | @param EAX Lower 32-bits of MSR value.\r | |
| 1241 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r | |
| 1242 | @param EDX Upper 32-bits of MSR value.\r | |
| 1243 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r | |
| 1244 | \r | |
| 1245 | <b>Example usage</b>\r | |
| 1246 | @code\r | |
| 1247 | MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;\r | |
| 1248 | \r | |
| 1249 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);\r | |
| 1250 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);\r | |
| 1251 | @endcode\r | |
| e108c3f6 | 1252 | @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r |
| 7ae88a62 MK |
1253 | **/\r |
| 1254 | #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r | |
| 1255 | \r | |
| 1256 | /**\r | |
| 1257 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR\r | |
| 1258 | **/\r | |
| 1259 | typedef union {\r | |
| 1260 | ///\r | |
| 1261 | /// Individual bit fields\r | |
| 1262 | ///\r | |
| 1263 | struct {\r | |
| 1264 | ///\r | |
| 1265 | /// [Bits 31:0] Current count.\r | |
| 1266 | ///\r | |
| 1267 | UINT32 CurrentCount:32;\r | |
| 1268 | ///\r | |
| 1269 | /// [Bits 47:32] Current count.\r | |
| 1270 | ///\r | |
| 1271 | UINT32 CurrentCountHi:16;\r | |
| 1272 | UINT32 Reserved:16;\r | |
| 1273 | } Bits;\r | |
| 1274 | ///\r | |
| 1275 | /// All bit fields as a 64-bit value\r | |
| 1276 | ///\r | |
| 1277 | UINT64 Uint64;\r | |
| 1278 | } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;\r | |
| 1279 | \r | |
| 1280 | \r | |
| 1281 | /**\r | |
| 1282 | Package. Uncore C-Box configuration information (R/O).\r | |
| 1283 | \r | |
| 1284 | @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)\r | |
| 1285 | @param EAX Lower 32-bits of MSR value.\r | |
| 1286 | Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r | |
| 1287 | @param EDX Upper 32-bits of MSR value.\r | |
| 1288 | Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r | |
| 1289 | \r | |
| 1290 | <b>Example usage</b>\r | |
| 1291 | @code\r | |
| 1292 | MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;\r | |
| 1293 | \r | |
| 1294 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);\r | |
| 1295 | @endcode\r | |
| e108c3f6 | 1296 | @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r |
| 7ae88a62 MK |
1297 | **/\r |
| 1298 | #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r | |
| 1299 | \r | |
| 1300 | /**\r | |
| 1301 | MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG\r | |
| 1302 | **/\r | |
| 1303 | typedef union {\r | |
| 1304 | ///\r | |
| 1305 | /// Individual bit fields\r | |
| 1306 | ///\r | |
| 1307 | struct {\r | |
| 1308 | ///\r | |
| 1309 | /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r | |
| 1310 | ///\r | |
| 1311 | UINT32 CBox:4;\r | |
| 1312 | UINT32 Reserved1:28;\r | |
| 1313 | UINT32 Reserved2:32;\r | |
| 1314 | } Bits;\r | |
| 1315 | ///\r | |
| 1316 | /// All bit fields as a 32-bit value\r | |
| 1317 | ///\r | |
| 1318 | UINT32 Uint32;\r | |
| 1319 | ///\r | |
| 1320 | /// All bit fields as a 64-bit value\r | |
| 1321 | ///\r | |
| 1322 | UINT64 Uint64;\r | |
| 1323 | } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;\r | |
| 1324 | \r | |
| 1325 | \r | |
| 1326 | /**\r | |
| 1327 | Package. Uncore Arb unit, performance counter 0.\r | |
| 1328 | \r | |
| 1329 | @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)\r | |
| 1330 | @param EAX Lower 32-bits of MSR value.\r | |
| 1331 | @param EDX Upper 32-bits of MSR value.\r | |
| 1332 | \r | |
| 1333 | <b>Example usage</b>\r | |
| 1334 | @code\r | |
| 1335 | UINT64 Msr;\r | |
| 1336 | \r | |
| 1337 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);\r | |
| 1338 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);\r | |
| 1339 | @endcode\r | |
| e108c3f6 | 1340 | @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
1341 | **/\r |
| 1342 | #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r | |
| 1343 | \r | |
| 1344 | \r | |
| 1345 | /**\r | |
| 1346 | Package. Uncore Arb unit, performance counter 1.\r | |
| 1347 | \r | |
| 1348 | @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)\r | |
| 1349 | @param EAX Lower 32-bits of MSR value.\r | |
| 1350 | @param EDX Upper 32-bits of MSR value.\r | |
| 1351 | \r | |
| 1352 | <b>Example usage</b>\r | |
| 1353 | @code\r | |
| 1354 | UINT64 Msr;\r | |
| 1355 | \r | |
| 1356 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);\r | |
| 1357 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);\r | |
| 1358 | @endcode\r | |
| e108c3f6 | 1359 | @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
1360 | **/\r |
| 1361 | #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r | |
| 1362 | \r | |
| 1363 | \r | |
| 1364 | /**\r | |
| 1365 | Package. Uncore Arb unit, counter 0 event select MSR.\r | |
| 1366 | \r | |
| 1367 | @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r | |
| 1368 | @param EAX Lower 32-bits of MSR value.\r | |
| 1369 | @param EDX Upper 32-bits of MSR value.\r | |
| 1370 | \r | |
| 1371 | <b>Example usage</b>\r | |
| 1372 | @code\r | |
| 1373 | UINT64 Msr;\r | |
| 1374 | \r | |
| 1375 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);\r | |
| 1376 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);\r | |
| 1377 | @endcode\r | |
| e108c3f6 | 1378 | @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
1379 | **/\r |
| 1380 | #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r | |
| 1381 | \r | |
| 1382 | \r | |
| 1383 | /**\r | |
| 1384 | Package. Uncore Arb unit, counter 1 event select MSR.\r | |
| 1385 | \r | |
| 1386 | @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r | |
| 1387 | @param EAX Lower 32-bits of MSR value.\r | |
| 1388 | @param EDX Upper 32-bits of MSR value.\r | |
| 1389 | \r | |
| 1390 | <b>Example usage</b>\r | |
| 1391 | @code\r | |
| 1392 | UINT64 Msr;\r | |
| 1393 | \r | |
| 1394 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);\r | |
| 1395 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);\r | |
| 1396 | @endcode\r | |
| e108c3f6 | 1397 | @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
1398 | **/\r |
| 1399 | #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r | |
| 1400 | \r | |
| 1401 | \r | |
| 1402 | /**\r | |
| 1403 | Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r | |
| 1404 | Enhancement. Accessible only while in SMM.\r | |
| 1405 | \r | |
| 1406 | @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)\r | |
| 1407 | @param EAX Lower 32-bits of MSR value.\r | |
| 1408 | Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r | |
| 1409 | @param EDX Upper 32-bits of MSR value.\r | |
| 1410 | Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r | |
| 1411 | \r | |
| 1412 | <b>Example usage</b>\r | |
| 1413 | @code\r | |
| 1414 | MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;\r | |
| 1415 | \r | |
| 1416 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);\r | |
| 1417 | AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);\r | |
| 1418 | @endcode\r | |
| e108c3f6 | 1419 | @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r |
| 7ae88a62 MK |
1420 | **/\r |
| 1421 | #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r | |
| 1422 | \r | |
| 1423 | /**\r | |
| 1424 | MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL\r | |
| 1425 | **/\r | |
| 1426 | typedef union {\r | |
| 1427 | ///\r | |
| 1428 | /// Individual bit fields\r | |
| 1429 | ///\r | |
| 1430 | struct {\r | |
| 1431 | ///\r | |
| 1432 | /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r | |
| 1433 | /// further changes.\r | |
| 1434 | ///\r | |
| 1435 | UINT32 Lock:1;\r | |
| 1436 | UINT32 Reserved1:1;\r | |
| 1437 | ///\r | |
| 1438 | /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r | |
| 1439 | /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r | |
| 1440 | /// logical processors are prevented from executing SMM code outside the\r | |
| 1441 | /// ranges defined by the SMRR. When set to '1' any logical processor in\r | |
| 1442 | /// the package that attempts to execute SMM code not within the ranges\r | |
| 1443 | /// defined by the SMRR will assert an unrecoverable MCE.\r | |
| 1444 | ///\r | |
| 1445 | UINT32 SMM_Code_Chk_En:1;\r | |
| 1446 | UINT32 Reserved2:29;\r | |
| 1447 | UINT32 Reserved3:32;\r | |
| 1448 | } Bits;\r | |
| 1449 | ///\r | |
| 1450 | /// All bit fields as a 32-bit value\r | |
| 1451 | ///\r | |
| 1452 | UINT32 Uint32;\r | |
| 1453 | ///\r | |
| 1454 | /// All bit fields as a 64-bit value\r | |
| 1455 | ///\r | |
| 1456 | UINT64 Uint64;\r | |
| 1457 | } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;\r | |
| 1458 | \r | |
| 1459 | \r | |
| 1460 | /**\r | |
| 1461 | Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r | |
| 1462 | processors in the package. Available only while in SMM and\r | |
| 1463 | MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r | |
| 1464 | \r | |
| 1465 | [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1466 | processor of its state in a long flow of internal operation which\r | |
| 1467 | delays servicing an interrupt. The corresponding bit will be set at\r | |
| 1468 | the start of long events such as: Microcode Update Load, C6, WBINVD,\r | |
| 1469 | Ratio Change, Throttle. The bit is automatically cleared at the end of\r | |
| 1470 | each long event. The reset value of this field is 0. Only bit\r | |
| 1471 | positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r | |
| 1472 | updated.\r | |
| 1473 | \r | |
| 1474 | [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1475 | processor of its state in a long flow of internal operation which\r | |
| 1476 | delays servicing an interrupt. The corresponding bit will be set at\r | |
| 1477 | the start of long events such as: Microcode Update Load, C6, WBINVD,\r | |
| 1478 | Ratio Change, Throttle. The bit is automatically cleared at the end of\r | |
| 1479 | each long event. The reset value of this field is 0. Only bit\r | |
| 1480 | positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r | |
| 1481 | updated.\r | |
| 1482 | \r | |
| 1483 | @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)\r | |
| 1484 | @param EAX Lower 32-bits of MSR value.\r | |
| 1485 | @param EDX Upper 32-bits of MSR value.\r | |
| 1486 | \r | |
| 1487 | <b>Example usage</b>\r | |
| 1488 | @code\r | |
| 1489 | UINT64 Msr;\r | |
| 1490 | \r | |
| 1491 | Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);\r | |
| 1492 | @endcode\r | |
| e108c3f6 | 1493 | @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r |
| 7ae88a62 MK |
1494 | **/\r |
| 1495 | #define MSR_HASWELL_SMM_DELAYED 0x000004E2\r | |
| 1496 | \r | |
| 1497 | \r | |
| 1498 | /**\r | |
| 1499 | Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r | |
| 1500 | processors in the package. Available only while in SMM.\r | |
| 1501 | \r | |
| 1502 | [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1503 | processor of its blocked state to service an SMI. The corresponding\r | |
| 1504 | bit will be set if the logical processor is in one of the following\r | |
| 1505 | states: Wait For SIPI or SENTER Sleep. The reset value of this field\r | |
| 1506 | is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r | |
| 1507 | ECX=PKG_LVL):EBX[15:0] can be updated.\r | |
| 1508 | \r | |
| 1509 | \r | |
| 1510 | [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1511 | processor of its blocked state to service an SMI. The corresponding\r | |
| 1512 | bit will be set if the logical processor is in one of the following\r | |
| 1513 | states: Wait For SIPI or SENTER Sleep. The reset value of this field\r | |
| 1514 | is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r | |
| 1515 | ECX=PKG_LVL):EBX[15:0] can be updated.\r | |
| 1516 | \r | |
| 1517 | @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)\r | |
| 1518 | @param EAX Lower 32-bits of MSR value.\r | |
| 1519 | @param EDX Upper 32-bits of MSR value.\r | |
| 1520 | \r | |
| 1521 | <b>Example usage</b>\r | |
| 1522 | @code\r | |
| 1523 | UINT64 Msr;\r | |
| 1524 | \r | |
| 1525 | Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);\r | |
| 1526 | @endcode\r | |
| e108c3f6 | 1527 | @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r |
| 7ae88a62 MK |
1528 | **/\r |
| 1529 | #define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r | |
| 1530 | \r | |
| 1531 | \r | |
| 1532 | /**\r | |
| 1533 | Package. Unit Multipliers used in RAPL Interfaces (R/O).\r | |
| 1534 | \r | |
| 1535 | @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)\r | |
| 1536 | @param EAX Lower 32-bits of MSR value.\r | |
| 1537 | Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r | |
| 1538 | @param EDX Upper 32-bits of MSR value.\r | |
| 1539 | Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r | |
| 1540 | \r | |
| 1541 | <b>Example usage</b>\r | |
| 1542 | @code\r | |
| 1543 | MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;\r | |
| 1544 | \r | |
| 1545 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);\r | |
| 1546 | @endcode\r | |
| e108c3f6 | 1547 | @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
| 7ae88a62 MK |
1548 | **/\r |
| 1549 | #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r | |
| 1550 | \r | |
| 1551 | /**\r | |
| 1552 | MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT\r | |
| 1553 | **/\r | |
| 1554 | typedef union {\r | |
| 1555 | ///\r | |
| 1556 | /// Individual bit fields\r | |
| 1557 | ///\r | |
| 1558 | struct {\r | |
| 1559 | ///\r | |
| 1560 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
| 1561 | ///\r | |
| 1562 | UINT32 PowerUnits:4;\r | |
| 1563 | UINT32 Reserved1:4;\r | |
| 1564 | ///\r | |
| 1565 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
| 1566 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
| 1567 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
| 1568 | /// micro-joules).\r | |
| 1569 | ///\r | |
| 1570 | UINT32 EnergyStatusUnits:5;\r | |
| 1571 | UINT32 Reserved2:3;\r | |
| 1572 | ///\r | |
| 1573 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
| 1574 | /// Interfaces.".\r | |
| 1575 | ///\r | |
| 1576 | UINT32 TimeUnits:4;\r | |
| 1577 | UINT32 Reserved3:12;\r | |
| 1578 | UINT32 Reserved4:32;\r | |
| 1579 | } Bits;\r | |
| 1580 | ///\r | |
| 1581 | /// All bit fields as a 32-bit value\r | |
| 1582 | ///\r | |
| 1583 | UINT32 Uint32;\r | |
| 1584 | ///\r | |
| 1585 | /// All bit fields as a 64-bit value\r | |
| 1586 | ///\r | |
| 1587 | UINT64 Uint64;\r | |
| 1588 | } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r | |
| 1589 | \r | |
| 1590 | \r | |
| 0f16be6d HW |
1591 | /**\r |
| 1592 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1593 | Domains.".\r | |
| 1594 | \r | |
| 1595 | @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)\r | |
| 1596 | @param EAX Lower 32-bits of MSR value.\r | |
| 1597 | @param EDX Upper 32-bits of MSR value.\r | |
| 1598 | \r | |
| 1599 | <b>Example usage</b>\r | |
| 1600 | @code\r | |
| 1601 | UINT64 Msr;\r | |
| 1602 | \r | |
| 1603 | Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);\r | |
| 1604 | @endcode\r | |
| 1605 | @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 1606 | **/\r | |
| 1607 | #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r | |
| 1608 | \r | |
| 1609 | \r | |
| 7ae88a62 MK |
1610 | /**\r |
| 1611 | Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r | |
| 1612 | RAPL Domains.".\r | |
| 1613 | \r | |
| 1614 | @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)\r | |
| 1615 | @param EAX Lower 32-bits of MSR value.\r | |
| 1616 | @param EDX Upper 32-bits of MSR value.\r | |
| 1617 | \r | |
| 1618 | <b>Example usage</b>\r | |
| 1619 | @code\r | |
| 1620 | UINT64 Msr;\r | |
| 1621 | \r | |
| 1622 | Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);\r | |
| 1623 | AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);\r | |
| 1624 | @endcode\r | |
| e108c3f6 | 1625 | @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r |
| 7ae88a62 MK |
1626 | **/\r |
| 1627 | #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r | |
| 1628 | \r | |
| 1629 | \r | |
| 1630 | /**\r | |
| 1631 | Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1632 | Domains.".\r | |
| 1633 | \r | |
| 1634 | @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)\r | |
| 1635 | @param EAX Lower 32-bits of MSR value.\r | |
| 1636 | @param EDX Upper 32-bits of MSR value.\r | |
| 1637 | \r | |
| 1638 | <b>Example usage</b>\r | |
| 1639 | @code\r | |
| 1640 | UINT64 Msr;\r | |
| 1641 | \r | |
| 1642 | Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);\r | |
| 1643 | @endcode\r | |
| e108c3f6 | 1644 | @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r |
| 7ae88a62 MK |
1645 | **/\r |
| 1646 | #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r | |
| 1647 | \r | |
| 1648 | \r | |
| 1649 | /**\r | |
| 1650 | Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1651 | Domains.".\r | |
| 1652 | \r | |
| 1653 | @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)\r | |
| 1654 | @param EAX Lower 32-bits of MSR value.\r | |
| 1655 | @param EDX Upper 32-bits of MSR value.\r | |
| 1656 | \r | |
| 1657 | <b>Example usage</b>\r | |
| 1658 | @code\r | |
| 1659 | UINT64 Msr;\r | |
| 1660 | \r | |
| 1661 | Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);\r | |
| 1662 | AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);\r | |
| 1663 | @endcode\r | |
| e108c3f6 | 1664 | @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r |
| 7ae88a62 MK |
1665 | **/\r |
| 1666 | #define MSR_HASWELL_PP1_POLICY 0x00000642\r | |
| 1667 | \r | |
| 1668 | \r | |
| 1669 | /**\r | |
| 1670 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
| 1671 | refers to processor core frequency).\r | |
| 1672 | \r | |
| 1673 | @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)\r | |
| 1674 | @param EAX Lower 32-bits of MSR value.\r | |
| 1675 | Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1676 | @param EDX Upper 32-bits of MSR value.\r | |
| 1677 | Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1678 | \r | |
| 1679 | <b>Example usage</b>\r | |
| 1680 | @code\r | |
| 1681 | MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 1682 | \r | |
| 1683 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);\r | |
| 1684 | AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 1685 | @endcode\r | |
| e108c3f6 | 1686 | @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r |
| 7ae88a62 MK |
1687 | **/\r |
| 1688 | #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r | |
| 1689 | \r | |
| 1690 | /**\r | |
| 1691 | MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS\r | |
| 1692 | **/\r | |
| 1693 | typedef union {\r | |
| 1694 | ///\r | |
| 1695 | /// Individual bit fields\r | |
| 1696 | ///\r | |
| 1697 | struct {\r | |
| 1698 | ///\r | |
| 1699 | /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r | |
| 1700 | /// reduced below the operating system request due to assertion of\r | |
| 1701 | /// external PROCHOT.\r | |
| 1702 | ///\r | |
| 1703 | UINT32 PROCHOT_Status:1;\r | |
| 1704 | ///\r | |
| 1705 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 1706 | /// operating system request due to a thermal event.\r | |
| 1707 | ///\r | |
| 1708 | UINT32 ThermalStatus:1;\r | |
| 1709 | UINT32 Reserved1:2;\r | |
| 1710 | ///\r | |
| 1711 | /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r | |
| 1712 | /// below the operating system request due to Processor Graphics driver\r | |
| 1713 | /// override.\r | |
| 1714 | ///\r | |
| 1715 | UINT32 GraphicsDriverStatus:1;\r | |
| 1716 | ///\r | |
| 1717 | /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r | |
| 1718 | /// When set, frequency is reduced below the operating system request\r | |
| 1719 | /// because the processor has detected that utilization is low.\r | |
| 1720 | ///\r | |
| 1721 | UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r | |
| 1722 | ///\r | |
| 1723 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 1724 | /// below the operating system request due to a thermal alert from the\r | |
| 1725 | /// Voltage Regulator.\r | |
| 1726 | ///\r | |
| 1727 | UINT32 VRThermAlertStatus:1;\r | |
| 1728 | UINT32 Reserved2:1;\r | |
| 1729 | ///\r | |
| 1730 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 1731 | /// reduced below the operating system request due to electrical design\r | |
| 1732 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 1733 | ///\r | |
| 1734 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 1735 | ///\r | |
| 1736 | /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r | |
| 1737 | /// below the operating system request due to domain-level power limiting.\r | |
| 1738 | ///\r | |
| 1739 | UINT32 PLStatus:1;\r | |
| 1740 | ///\r | |
| 1741 | /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
| 1742 | /// frequency is reduced below the operating system request due to\r | |
| 1743 | /// package-level power limiting PL1.\r | |
| 1744 | ///\r | |
| 1745 | UINT32 PL1Status:1;\r | |
| 1746 | ///\r | |
| 1747 | /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
| 1748 | /// frequency is reduced below the operating system request due to\r | |
| 1749 | /// package-level power limiting PL2.\r | |
| 1750 | ///\r | |
| 1751 | UINT32 PL2Status:1;\r | |
| 1752 | ///\r | |
| 1753 | /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r | |
| 1754 | /// below the operating system request due to multi-core turbo limits.\r | |
| 1755 | ///\r | |
| 1756 | UINT32 MaxTurboLimitStatus:1;\r | |
| 1757 | ///\r | |
| 1758 | /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r | |
| 1759 | /// is reduced below the operating system request due to Turbo transition\r | |
| 1760 | /// attenuation. This prevents performance degradation due to frequent\r | |
| 1761 | /// operating ratio changes.\r | |
| 1762 | ///\r | |
| 1763 | UINT32 TurboTransitionAttenuationStatus:1;\r | |
| 1764 | UINT32 Reserved3:2;\r | |
| 1765 | ///\r | |
| 1766 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 1767 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1768 | /// remain set until cleared by software writing 0.\r | |
| 1769 | ///\r | |
| 1770 | UINT32 PROCHOT_Log:1;\r | |
| 1771 | ///\r | |
| 1772 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 1773 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1774 | /// remain set until cleared by software writing 0.\r | |
| 1775 | ///\r | |
| 1776 | UINT32 ThermalLog:1;\r | |
| 1777 | UINT32 Reserved4:2;\r | |
| 1778 | ///\r | |
| 1779 | /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r | |
| 1780 | /// Driver Status bit has asserted since the log bit was last cleared.\r | |
| 1781 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 1782 | ///\r | |
| 1783 | UINT32 GraphicsDriverLog:1;\r | |
| 1784 | ///\r | |
| 1785 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 1786 | /// indicates that the Autonomous Utilization-Based Frequency Control\r | |
| 1787 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1788 | /// bit will remain set until cleared by software writing 0.\r | |
| 1789 | ///\r | |
| 1790 | UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r | |
| 1791 | ///\r | |
| 1792 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 1793 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 1794 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1795 | ///\r | |
| 1796 | UINT32 VRThermAlertLog:1;\r | |
| 1797 | UINT32 Reserved5:1;\r | |
| 1798 | ///\r | |
| 1799 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 1800 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1801 | /// bit will remain set until cleared by software writing 0.\r | |
| 1802 | ///\r | |
| 1803 | UINT32 ElectricalDesignPointLog:1;\r | |
| 1804 | ///\r | |
| 1805 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
| 1806 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
| 1807 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1808 | /// writing 0.\r | |
| 1809 | ///\r | |
| 1810 | UINT32 PLLog:1;\r | |
| 1811 | ///\r | |
| 1812 | /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r | |
| 1813 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
| 1814 | /// since the log bit was last cleared. This log bit will remain set until\r | |
| 1815 | /// cleared by software writing 0.\r | |
| 1816 | ///\r | |
| 1817 | UINT32 PL1Log:1;\r | |
| 1818 | ///\r | |
| 1819 | /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
| 1820 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
| 1821 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
| 1822 | /// by software writing 0.\r | |
| 1823 | ///\r | |
| 1824 | UINT32 PL2Log:1;\r | |
| 1825 | ///\r | |
| 1826 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 1827 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 1828 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1829 | ///\r | |
| 1830 | UINT32 MaxTurboLimitLog:1;\r | |
| 1831 | ///\r | |
| 1832 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 1833 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 1834 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 1835 | /// software writing 0.\r | |
| 1836 | ///\r | |
| 1837 | UINT32 TurboTransitionAttenuationLog:1;\r | |
| 1838 | UINT32 Reserved6:2;\r | |
| 1839 | UINT32 Reserved7:32;\r | |
| 1840 | } Bits;\r | |
| 1841 | ///\r | |
| 1842 | /// All bit fields as a 32-bit value\r | |
| 1843 | ///\r | |
| 1844 | UINT32 Uint32;\r | |
| 1845 | ///\r | |
| 1846 | /// All bit fields as a 64-bit value\r | |
| 1847 | ///\r | |
| 1848 | UINT64 Uint64;\r | |
| 1849 | } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;\r | |
| 1850 | \r | |
| 1851 | \r | |
| 1852 | /**\r | |
| 1853 | Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r | |
| 1854 | (frequency refers to processor graphics frequency).\r | |
| 1855 | \r | |
| 1856 | @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r | |
| 1857 | @param EAX Lower 32-bits of MSR value.\r | |
| 1858 | Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1859 | @param EDX Upper 32-bits of MSR value.\r | |
| 1860 | Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1861 | \r | |
| 1862 | <b>Example usage</b>\r | |
| 1863 | @code\r | |
| 1864 | MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 1865 | \r | |
| 1866 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);\r | |
| 1867 | AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 1868 | @endcode\r | |
| e108c3f6 | 1869 | @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r |
| 7ae88a62 MK |
1870 | **/\r |
| 1871 | #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r | |
| 1872 | \r | |
| 1873 | /**\r | |
| 1874 | MSR information returned for MSR index\r | |
| 1875 | #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS\r | |
| 1876 | **/\r | |
| 1877 | typedef union {\r | |
| 1878 | ///\r | |
| 1879 | /// Individual bit fields\r | |
| 1880 | ///\r | |
| 1881 | struct {\r | |
| 1882 | ///\r | |
| 1883 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r | |
| 1884 | /// operating system request due to assertion of external PROCHOT.\r | |
| 1885 | ///\r | |
| 1886 | UINT32 PROCHOT_Status:1;\r | |
| 1887 | ///\r | |
| 1888 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 1889 | /// operating system request due to a thermal event.\r | |
| 1890 | ///\r | |
| 1891 | UINT32 ThermalStatus:1;\r | |
| 1892 | UINT32 Reserved1:2;\r | |
| 1893 | ///\r | |
| 1894 | /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r | |
| 1895 | /// below the operating system request due to Processor Graphics driver\r | |
| 1896 | /// override.\r | |
| 1897 | ///\r | |
| 1898 | UINT32 GraphicsDriverStatus:1;\r | |
| 1899 | ///\r | |
| 1900 | /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r | |
| 1901 | /// When set, frequency is reduced below the operating system request\r | |
| 1902 | /// because the processor has detected that utilization is low.\r | |
| 1903 | ///\r | |
| 1904 | UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r | |
| 1905 | ///\r | |
| 1906 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 1907 | /// below the operating system request due to a thermal alert from the\r | |
| 1908 | /// Voltage Regulator.\r | |
| 1909 | ///\r | |
| 1910 | UINT32 VRThermAlertStatus:1;\r | |
| 1911 | UINT32 Reserved2:1;\r | |
| 1912 | ///\r | |
| 1913 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 1914 | /// reduced below the operating system request due to electrical design\r | |
| 1915 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 1916 | ///\r | |
| 1917 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 1918 | ///\r | |
| 1919 | /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is\r | |
| 1920 | /// reduced below the operating system request due to domain-level power\r | |
| 1921 | /// limiting.\r | |
| 1922 | ///\r | |
| 1923 | UINT32 GraphicsPowerLimitingStatus:1;\r | |
| 1924 | ///\r | |
| 1925 | /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
| 1926 | /// frequency is reduced below the operating system request due to\r | |
| 1927 | /// package-level power limiting PL1.\r | |
| 1928 | ///\r | |
| 1929 | UINT32 PL1STatus:1;\r | |
| 1930 | ///\r | |
| 1931 | /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
| 1932 | /// frequency is reduced below the operating system request due to\r | |
| 1933 | /// package-level power limiting PL2.\r | |
| 1934 | ///\r | |
| 1935 | UINT32 PL2Status:1;\r | |
| 1936 | UINT32 Reserved3:4;\r | |
| 1937 | ///\r | |
| 1938 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 1939 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1940 | /// remain set until cleared by software writing 0.\r | |
| 1941 | ///\r | |
| 1942 | UINT32 PROCHOT_Log:1;\r | |
| 1943 | ///\r | |
| 1944 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 1945 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1946 | /// remain set until cleared by software writing 0.\r | |
| 1947 | ///\r | |
| 1948 | UINT32 ThermalLog:1;\r | |
| 1949 | UINT32 Reserved4:2;\r | |
| 1950 | ///\r | |
| 1951 | /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r | |
| 1952 | /// Driver Status bit has asserted since the log bit was last cleared.\r | |
| 1953 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 1954 | ///\r | |
| 1955 | UINT32 GraphicsDriverLog:1;\r | |
| 1956 | ///\r | |
| 1957 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 1958 | /// indicates that the Autonomous Utilization-Based Frequency Control\r | |
| 1959 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1960 | /// bit will remain set until cleared by software writing 0.\r | |
| 1961 | ///\r | |
| 1962 | UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r | |
| 1963 | ///\r | |
| 1964 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 1965 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 1966 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1967 | ///\r | |
| 1968 | UINT32 VRThermAlertLog:1;\r | |
| 1969 | UINT32 Reserved5:1;\r | |
| 1970 | ///\r | |
| 1971 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 1972 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1973 | /// bit will remain set until cleared by software writing 0.\r | |
| 1974 | ///\r | |
| 1975 | UINT32 ElectricalDesignPointLog:1;\r | |
| 1976 | ///\r | |
| 1977 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
| 1978 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
| 1979 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1980 | /// writing 0.\r | |
| 1981 | ///\r | |
| 1982 | UINT32 CorePowerLimitingLog:1;\r | |
| 1983 | ///\r | |
| 1984 | /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r | |
| 1985 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
| 1986 | /// since the log bit was last cleared. This log bit will remain set until\r | |
| 1987 | /// cleared by software writing 0.\r | |
| 1988 | ///\r | |
| 1989 | UINT32 PL1Log:1;\r | |
| 1990 | ///\r | |
| 1991 | /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
| 1992 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
| 1993 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
| 1994 | /// by software writing 0.\r | |
| 1995 | ///\r | |
| 1996 | UINT32 PL2Log:1;\r | |
| 1997 | ///\r | |
| 1998 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 1999 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 2000 | /// log bit will remain set until cleared by software writing 0.\r | |
| 2001 | ///\r | |
| 2002 | UINT32 MaxTurboLimitLog:1;\r | |
| 2003 | ///\r | |
| 2004 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 2005 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 2006 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 2007 | /// software writing 0.\r | |
| 2008 | ///\r | |
| 2009 | UINT32 TurboTransitionAttenuationLog:1;\r | |
| 2010 | UINT32 Reserved6:2;\r | |
| 2011 | UINT32 Reserved7:32;\r | |
| 2012 | } Bits;\r | |
| 2013 | ///\r | |
| 2014 | /// All bit fields as a 32-bit value\r | |
| 2015 | ///\r | |
| 2016 | UINT32 Uint32;\r | |
| 2017 | ///\r | |
| 2018 | /// All bit fields as a 64-bit value\r | |
| 2019 | ///\r | |
| 2020 | UINT64 Uint64;\r | |
| 2021 | } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r | |
| 2022 | \r | |
| 2023 | \r | |
| 2024 | /**\r | |
| 2025 | Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r | |
| 2026 | (frequency refers to ring interconnect in the uncore).\r | |
| 2027 | \r | |
| 2028 | @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)\r | |
| 2029 | @param EAX Lower 32-bits of MSR value.\r | |
| 2030 | Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r | |
| 2031 | @param EDX Upper 32-bits of MSR value.\r | |
| 2032 | Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r | |
| 2033 | \r | |
| 2034 | <b>Example usage</b>\r | |
| 2035 | @code\r | |
| 2036 | MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 2037 | \r | |
| 2038 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);\r | |
| 2039 | AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 2040 | @endcode\r | |
| e108c3f6 | 2041 | @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r |
| 7ae88a62 MK |
2042 | **/\r |
| 2043 | #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r | |
| 2044 | \r | |
| 2045 | /**\r | |
| 2046 | MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS\r | |
| 2047 | **/\r | |
| 2048 | typedef union {\r | |
| 2049 | ///\r | |
| 2050 | /// Individual bit fields\r | |
| 2051 | ///\r | |
| 2052 | struct {\r | |
| 2053 | ///\r | |
| 2054 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r | |
| 2055 | /// operating system request due to assertion of external PROCHOT.\r | |
| 2056 | ///\r | |
| 2057 | UINT32 PROCHOT_Status:1;\r | |
| 2058 | ///\r | |
| 2059 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 2060 | /// operating system request due to a thermal event.\r | |
| 2061 | ///\r | |
| 2062 | UINT32 ThermalStatus:1;\r | |
| 2063 | UINT32 Reserved1:4;\r | |
| 2064 | ///\r | |
| 2065 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 2066 | /// below the operating system request due to a thermal alert from the\r | |
| 2067 | /// Voltage Regulator.\r | |
| 2068 | ///\r | |
| 2069 | UINT32 VRThermAlertStatus:1;\r | |
| 2070 | UINT32 Reserved2:1;\r | |
| 2071 | ///\r | |
| 2072 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 2073 | /// reduced below the operating system request due to electrical design\r | |
| 2074 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 2075 | ///\r | |
| 2076 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 2077 | UINT32 Reserved3:1;\r | |
| 2078 | ///\r | |
| 2079 | /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
| 2080 | /// frequency is reduced below the operating system request due to\r | |
| 2081 | /// package-level power limiting PL1.\r | |
| 2082 | ///\r | |
| 2083 | UINT32 PL1STatus:1;\r | |
| 2084 | ///\r | |
| 2085 | /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
| 2086 | /// frequency is reduced below the operating system request due to\r | |
| 2087 | /// package-level power limiting PL2.\r | |
| 2088 | ///\r | |
| 2089 | UINT32 PL2Status:1;\r | |
| 2090 | UINT32 Reserved4:4;\r | |
| 2091 | ///\r | |
| 2092 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 2093 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 2094 | /// remain set until cleared by software writing 0.\r | |
| 2095 | ///\r | |
| 2096 | UINT32 PROCHOT_Log:1;\r | |
| 2097 | ///\r | |
| 2098 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 2099 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 2100 | /// remain set until cleared by software writing 0.\r | |
| 2101 | ///\r | |
| 2102 | UINT32 ThermalLog:1;\r | |
| 2103 | UINT32 Reserved5:2;\r | |
| 2104 | ///\r | |
| 2105 | /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r | |
| 2106 | /// Driver Status bit has asserted since the log bit was last cleared.\r | |
| 2107 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 2108 | ///\r | |
| 2109 | UINT32 GraphicsDriverLog:1;\r | |
| 2110 | ///\r | |
| 2111 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 2112 | /// indicates that the Autonomous Utilization-Based Frequency Control\r | |
| 2113 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 2114 | /// bit will remain set until cleared by software writing 0.\r | |
| 2115 | ///\r | |
| 2116 | UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r | |
| 2117 | ///\r | |
| 2118 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 2119 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 2120 | /// log bit will remain set until cleared by software writing 0.\r | |
| 2121 | ///\r | |
| 2122 | UINT32 VRThermAlertLog:1;\r | |
| 2123 | UINT32 Reserved6:1;\r | |
| 2124 | ///\r | |
| 2125 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 2126 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 2127 | /// bit will remain set until cleared by software writing 0.\r | |
| 2128 | ///\r | |
| 2129 | UINT32 ElectricalDesignPointLog:1;\r | |
| 2130 | ///\r | |
| 2131 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
| 2132 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
| 2133 | /// cleared. This log bit will remain set until cleared by software\r | |
| 2134 | /// writing 0.\r | |
| 2135 | ///\r | |
| 2136 | UINT32 CorePowerLimitingLog:1;\r | |
| 2137 | ///\r | |
| 2138 | /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r | |
| 2139 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
| 2140 | /// since the log bit was last cleared. This log bit will remain set until\r | |
| 2141 | /// cleared by software writing 0.\r | |
| 2142 | ///\r | |
| 2143 | UINT32 PL1Log:1;\r | |
| 2144 | ///\r | |
| 2145 | /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
| 2146 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
| 2147 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
| 2148 | /// by software writing 0.\r | |
| 2149 | ///\r | |
| 2150 | UINT32 PL2Log:1;\r | |
| 2151 | ///\r | |
| 2152 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 2153 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 2154 | /// log bit will remain set until cleared by software writing 0.\r | |
| 2155 | ///\r | |
| 2156 | UINT32 MaxTurboLimitLog:1;\r | |
| 2157 | ///\r | |
| 2158 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 2159 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 2160 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 2161 | /// software writing 0.\r | |
| 2162 | ///\r | |
| 2163 | UINT32 TurboTransitionAttenuationLog:1;\r | |
| 2164 | UINT32 Reserved7:2;\r | |
| 2165 | UINT32 Reserved8:32;\r | |
| 2166 | } Bits;\r | |
| 2167 | ///\r | |
| 2168 | /// All bit fields as a 32-bit value\r | |
| 2169 | ///\r | |
| 2170 | UINT32 Uint32;\r | |
| 2171 | ///\r | |
| 2172 | /// All bit fields as a 64-bit value\r | |
| 2173 | ///\r | |
| 2174 | UINT64 Uint64;\r | |
| 2175 | } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;\r | |
| 2176 | \r | |
| 2177 | \r | |
| 2178 | /**\r | |
| 2179 | Package. Uncore C-Box 0, counter 0 event select MSR.\r | |
| 2180 | \r | |
| 2181 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r | |
| 2182 | @param EAX Lower 32-bits of MSR value.\r | |
| 2183 | @param EDX Upper 32-bits of MSR value.\r | |
| 2184 | \r | |
| 2185 | <b>Example usage</b>\r | |
| 2186 | @code\r | |
| 2187 | UINT64 Msr;\r | |
| 2188 | \r | |
| 2189 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);\r | |
| 2190 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);\r | |
| 2191 | @endcode\r | |
| e108c3f6 | 2192 | @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2193 | **/\r |
| 2194 | #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r | |
| 2195 | \r | |
| 2196 | \r | |
| 2197 | /**\r | |
| 2198 | Package. Uncore C-Box 0, counter 1 event select MSR.\r | |
| 2199 | \r | |
| 2200 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r | |
| 2201 | @param EAX Lower 32-bits of MSR value.\r | |
| 2202 | @param EDX Upper 32-bits of MSR value.\r | |
| 2203 | \r | |
| 2204 | <b>Example usage</b>\r | |
| 2205 | @code\r | |
| 2206 | UINT64 Msr;\r | |
| 2207 | \r | |
| 2208 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);\r | |
| 2209 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);\r | |
| 2210 | @endcode\r | |
| e108c3f6 | 2211 | @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2212 | **/\r |
| 2213 | #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r | |
| 2214 | \r | |
| 2215 | \r | |
| 2216 | /**\r | |
| 2217 | Package. Uncore C-Box 0, performance counter 0.\r | |
| 2218 | \r | |
| 2219 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)\r | |
| 2220 | @param EAX Lower 32-bits of MSR value.\r | |
| 2221 | @param EDX Upper 32-bits of MSR value.\r | |
| 2222 | \r | |
| 2223 | <b>Example usage</b>\r | |
| 2224 | @code\r | |
| 2225 | UINT64 Msr;\r | |
| 2226 | \r | |
| 2227 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);\r | |
| 2228 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);\r | |
| 2229 | @endcode\r | |
| e108c3f6 | 2230 | @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2231 | **/\r |
| 2232 | #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r | |
| 2233 | \r | |
| 2234 | \r | |
| 2235 | /**\r | |
| 2236 | Package. Uncore C-Box 0, performance counter 1.\r | |
| 2237 | \r | |
| 2238 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)\r | |
| 2239 | @param EAX Lower 32-bits of MSR value.\r | |
| 2240 | @param EDX Upper 32-bits of MSR value.\r | |
| 2241 | \r | |
| 2242 | <b>Example usage</b>\r | |
| 2243 | @code\r | |
| 2244 | UINT64 Msr;\r | |
| 2245 | \r | |
| 2246 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);\r | |
| 2247 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);\r | |
| 2248 | @endcode\r | |
| e108c3f6 | 2249 | @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2250 | **/\r |
| 2251 | #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r | |
| 2252 | \r | |
| 2253 | \r | |
| 2254 | /**\r | |
| 2255 | Package. Uncore C-Box 1, counter 0 event select MSR.\r | |
| 2256 | \r | |
| 2257 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r | |
| 2258 | @param EAX Lower 32-bits of MSR value.\r | |
| 2259 | @param EDX Upper 32-bits of MSR value.\r | |
| 2260 | \r | |
| 2261 | <b>Example usage</b>\r | |
| 2262 | @code\r | |
| 2263 | UINT64 Msr;\r | |
| 2264 | \r | |
| 2265 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);\r | |
| 2266 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);\r | |
| 2267 | @endcode\r | |
| e108c3f6 | 2268 | @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2269 | **/\r |
| 2270 | #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r | |
| 2271 | \r | |
| 2272 | \r | |
| 2273 | /**\r | |
| 2274 | Package. Uncore C-Box 1, counter 1 event select MSR.\r | |
| 2275 | \r | |
| 2276 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r | |
| 2277 | @param EAX Lower 32-bits of MSR value.\r | |
| 2278 | @param EDX Upper 32-bits of MSR value.\r | |
| 2279 | \r | |
| 2280 | <b>Example usage</b>\r | |
| 2281 | @code\r | |
| 2282 | UINT64 Msr;\r | |
| 2283 | \r | |
| 2284 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);\r | |
| 2285 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);\r | |
| 2286 | @endcode\r | |
| e108c3f6 | 2287 | @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2288 | **/\r |
| 2289 | #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r | |
| 2290 | \r | |
| 2291 | \r | |
| 2292 | /**\r | |
| 2293 | Package. Uncore C-Box 1, performance counter 0.\r | |
| 2294 | \r | |
| 2295 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)\r | |
| 2296 | @param EAX Lower 32-bits of MSR value.\r | |
| 2297 | @param EDX Upper 32-bits of MSR value.\r | |
| 2298 | \r | |
| 2299 | <b>Example usage</b>\r | |
| 2300 | @code\r | |
| 2301 | UINT64 Msr;\r | |
| 2302 | \r | |
| 2303 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);\r | |
| 2304 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);\r | |
| 2305 | @endcode\r | |
| e108c3f6 | 2306 | @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2307 | **/\r |
| 2308 | #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r | |
| 2309 | \r | |
| 2310 | \r | |
| 2311 | /**\r | |
| 2312 | Package. Uncore C-Box 1, performance counter 1.\r | |
| 2313 | \r | |
| 2314 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)\r | |
| 2315 | @param EAX Lower 32-bits of MSR value.\r | |
| 2316 | @param EDX Upper 32-bits of MSR value.\r | |
| 2317 | \r | |
| 2318 | <b>Example usage</b>\r | |
| 2319 | @code\r | |
| 2320 | UINT64 Msr;\r | |
| 2321 | \r | |
| 2322 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);\r | |
| 2323 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);\r | |
| 2324 | @endcode\r | |
| e108c3f6 | 2325 | @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2326 | **/\r |
| 2327 | #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r | |
| 2328 | \r | |
| 2329 | \r | |
| 2330 | /**\r | |
| 2331 | Package. Uncore C-Box 2, counter 0 event select MSR.\r | |
| 2332 | \r | |
| 2333 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r | |
| 2334 | @param EAX Lower 32-bits of MSR value.\r | |
| 2335 | @param EDX Upper 32-bits of MSR value.\r | |
| 2336 | \r | |
| 2337 | <b>Example usage</b>\r | |
| 2338 | @code\r | |
| 2339 | UINT64 Msr;\r | |
| 2340 | \r | |
| 2341 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);\r | |
| 2342 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);\r | |
| 2343 | @endcode\r | |
| e108c3f6 | 2344 | @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2345 | **/\r |
| 2346 | #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r | |
| 2347 | \r | |
| 2348 | \r | |
| 2349 | /**\r | |
| 2350 | Package. Uncore C-Box 2, counter 1 event select MSR.\r | |
| 2351 | \r | |
| 2352 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r | |
| 2353 | @param EAX Lower 32-bits of MSR value.\r | |
| 2354 | @param EDX Upper 32-bits of MSR value.\r | |
| 2355 | \r | |
| 2356 | <b>Example usage</b>\r | |
| 2357 | @code\r | |
| 2358 | UINT64 Msr;\r | |
| 2359 | \r | |
| 2360 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);\r | |
| 2361 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);\r | |
| 2362 | @endcode\r | |
| e108c3f6 | 2363 | @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2364 | **/\r |
| 2365 | #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r | |
| 2366 | \r | |
| 2367 | \r | |
| 2368 | /**\r | |
| 2369 | Package. Uncore C-Box 2, performance counter 0.\r | |
| 2370 | \r | |
| 2371 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)\r | |
| 2372 | @param EAX Lower 32-bits of MSR value.\r | |
| 2373 | @param EDX Upper 32-bits of MSR value.\r | |
| 2374 | \r | |
| 2375 | <b>Example usage</b>\r | |
| 2376 | @code\r | |
| 2377 | UINT64 Msr;\r | |
| 2378 | \r | |
| 2379 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);\r | |
| 2380 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);\r | |
| 2381 | @endcode\r | |
| e108c3f6 | 2382 | @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2383 | **/\r |
| 2384 | #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r | |
| 2385 | \r | |
| 2386 | \r | |
| 2387 | /**\r | |
| 2388 | Package. Uncore C-Box 2, performance counter 1.\r | |
| 2389 | \r | |
| 2390 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)\r | |
| 2391 | @param EAX Lower 32-bits of MSR value.\r | |
| 2392 | @param EDX Upper 32-bits of MSR value.\r | |
| 2393 | \r | |
| 2394 | <b>Example usage</b>\r | |
| 2395 | @code\r | |
| 2396 | UINT64 Msr;\r | |
| 2397 | \r | |
| 2398 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);\r | |
| 2399 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);\r | |
| 2400 | @endcode\r | |
| e108c3f6 | 2401 | @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2402 | **/\r |
| 2403 | #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r | |
| 2404 | \r | |
| 2405 | \r | |
| 2406 | /**\r | |
| 2407 | Package. Uncore C-Box 3, counter 0 event select MSR.\r | |
| 2408 | \r | |
| 2409 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r | |
| 2410 | @param EAX Lower 32-bits of MSR value.\r | |
| 2411 | @param EDX Upper 32-bits of MSR value.\r | |
| 2412 | \r | |
| 2413 | <b>Example usage</b>\r | |
| 2414 | @code\r | |
| 2415 | UINT64 Msr;\r | |
| 2416 | \r | |
| 2417 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);\r | |
| 2418 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);\r | |
| 2419 | @endcode\r | |
| e108c3f6 | 2420 | @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2421 | **/\r |
| 2422 | #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r | |
| 2423 | \r | |
| 2424 | \r | |
| 2425 | /**\r | |
| 2426 | Package. Uncore C-Box 3, counter 1 event select MSR.\r | |
| 2427 | \r | |
| 2428 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r | |
| 2429 | @param EAX Lower 32-bits of MSR value.\r | |
| 2430 | @param EDX Upper 32-bits of MSR value.\r | |
| 2431 | \r | |
| 2432 | <b>Example usage</b>\r | |
| 2433 | @code\r | |
| 2434 | UINT64 Msr;\r | |
| 2435 | \r | |
| 2436 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);\r | |
| 2437 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);\r | |
| 2438 | @endcode\r | |
| e108c3f6 | 2439 | @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2440 | **/\r |
| 2441 | #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r | |
| 2442 | \r | |
| 2443 | \r | |
| 2444 | /**\r | |
| 2445 | Package. Uncore C-Box 3, performance counter 0.\r | |
| 2446 | \r | |
| 2447 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)\r | |
| 2448 | @param EAX Lower 32-bits of MSR value.\r | |
| 2449 | @param EDX Upper 32-bits of MSR value.\r | |
| 2450 | \r | |
| 2451 | <b>Example usage</b>\r | |
| 2452 | @code\r | |
| 2453 | UINT64 Msr;\r | |
| 2454 | \r | |
| 2455 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);\r | |
| 2456 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);\r | |
| 2457 | @endcode\r | |
| e108c3f6 | 2458 | @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2459 | **/\r |
| 2460 | #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r | |
| 2461 | \r | |
| 2462 | \r | |
| 2463 | /**\r | |
| 2464 | Package. Uncore C-Box 3, performance counter 1.\r | |
| 2465 | \r | |
| 2466 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)\r | |
| 2467 | @param EAX Lower 32-bits of MSR value.\r | |
| 2468 | @param EDX Upper 32-bits of MSR value.\r | |
| 2469 | \r | |
| 2470 | <b>Example usage</b>\r | |
| 2471 | @code\r | |
| 2472 | UINT64 Msr;\r | |
| 2473 | \r | |
| 2474 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);\r | |
| 2475 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);\r | |
| 2476 | @endcode\r | |
| e108c3f6 | 2477 | @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2478 | **/\r |
| 2479 | #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r | |
| 2480 | \r | |
| 2481 | \r | |
| 2482 | /**\r | |
| 2483 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 2484 | unrelated to MWAIT extension C-state parameters or ACPI C-States.\r | |
| 2485 | \r | |
| 2486 | @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)\r | |
| 2487 | @param EAX Lower 32-bits of MSR value.\r | |
| 2488 | Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r | |
| 2489 | @param EDX Upper 32-bits of MSR value.\r | |
| 2490 | Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r | |
| 2491 | \r | |
| 2492 | <b>Example usage</b>\r | |
| 2493 | @code\r | |
| 2494 | MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;\r | |
| 2495 | \r | |
| 2496 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);\r | |
| 2497 | AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);\r | |
| 2498 | @endcode\r | |
| e108c3f6 | 2499 | @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r |
| 7ae88a62 MK |
2500 | **/\r |
| 2501 | #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r | |
| 2502 | \r | |
| 2503 | /**\r | |
| 2504 | MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY\r | |
| 2505 | **/\r | |
| 2506 | typedef union {\r | |
| 2507 | ///\r | |
| 2508 | /// Individual bit fields\r | |
| 2509 | ///\r | |
| 2510 | struct {\r | |
| 2511 | ///\r | |
| 2512 | /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r | |
| 2513 | /// that this package is in processor-specific C8 states. Count at the\r | |
| 2514 | /// same frequency as the TSC.\r | |
| 2515 | ///\r | |
| 2516 | UINT32 C8ResidencyCounter:32;\r | |
| 2517 | ///\r | |
| 2518 | /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r | |
| 2519 | /// reset that this package is in processor-specific C8 states. Count at\r | |
| 2520 | /// the same frequency as the TSC.\r | |
| 2521 | ///\r | |
| 2522 | UINT32 C8ResidencyCounterHi:28;\r | |
| 2523 | UINT32 Reserved:4;\r | |
| 2524 | } Bits;\r | |
| 2525 | ///\r | |
| 2526 | /// All bit fields as a 64-bit value\r | |
| 2527 | ///\r | |
| 2528 | UINT64 Uint64;\r | |
| 2529 | } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;\r | |
| 2530 | \r | |
| 2531 | \r | |
| 2532 | /**\r | |
| 2533 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 2534 | unrelated to MWAIT extension C-state parameters or ACPI C-States.\r | |
| 2535 | \r | |
| 2536 | @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)\r | |
| 2537 | @param EAX Lower 32-bits of MSR value.\r | |
| 2538 | Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r | |
| 2539 | @param EDX Upper 32-bits of MSR value.\r | |
| 2540 | Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r | |
| 2541 | \r | |
| 2542 | <b>Example usage</b>\r | |
| 2543 | @code\r | |
| 2544 | MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;\r | |
| 2545 | \r | |
| 2546 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);\r | |
| 2547 | AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);\r | |
| 2548 | @endcode\r | |
| e108c3f6 | 2549 | @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r |
| 7ae88a62 MK |
2550 | **/\r |
| 2551 | #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r | |
| 2552 | \r | |
| 2553 | /**\r | |
| 2554 | MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY\r | |
| 2555 | **/\r | |
| 2556 | typedef union {\r | |
| 2557 | ///\r | |
| 2558 | /// Individual bit fields\r | |
| 2559 | ///\r | |
| 2560 | struct {\r | |
| 2561 | ///\r | |
| 2562 | /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r | |
| 2563 | /// that this package is in processor-specific C9 states. Count at the\r | |
| 2564 | /// same frequency as the TSC.\r | |
| 2565 | ///\r | |
| 2566 | UINT32 C9ResidencyCounter:32;\r | |
| 2567 | ///\r | |
| 2568 | /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r | |
| 2569 | /// reset that this package is in processor-specific C9 states. Count at\r | |
| 2570 | /// the same frequency as the TSC.\r | |
| 2571 | ///\r | |
| 2572 | UINT32 C9ResidencyCounterHi:28;\r | |
| 2573 | UINT32 Reserved:4;\r | |
| 2574 | } Bits;\r | |
| 2575 | ///\r | |
| 2576 | /// All bit fields as a 64-bit value\r | |
| 2577 | ///\r | |
| 2578 | UINT64 Uint64;\r | |
| 2579 | } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;\r | |
| 2580 | \r | |
| 2581 | \r | |
| 2582 | /**\r | |
| 2583 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 2584 | unrelated to MWAIT extension C-state parameters or ACPI C-States.\r | |
| 2585 | \r | |
| 2586 | @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)\r | |
| 2587 | @param EAX Lower 32-bits of MSR value.\r | |
| 2588 | Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r | |
| 2589 | @param EDX Upper 32-bits of MSR value.\r | |
| 2590 | Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r | |
| 2591 | \r | |
| 2592 | <b>Example usage</b>\r | |
| 2593 | @code\r | |
| 2594 | MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;\r | |
| 2595 | \r | |
| 2596 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);\r | |
| 2597 | AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);\r | |
| 2598 | @endcode\r | |
| e108c3f6 | 2599 | @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r |
| 7ae88a62 MK |
2600 | **/\r |
| 2601 | #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r | |
| 2602 | \r | |
| 2603 | /**\r | |
| 2604 | MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY\r | |
| 2605 | **/\r | |
| 2606 | typedef union {\r | |
| 2607 | ///\r | |
| 2608 | /// Individual bit fields\r | |
| 2609 | ///\r | |
| 2610 | struct {\r | |
| 2611 | ///\r | |
| 2612 | /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r | |
| 2613 | /// reset that this package is in processor-specific C10 states. Count at\r | |
| 2614 | /// the same frequency as the TSC.\r | |
| 2615 | ///\r | |
| 2616 | UINT32 C10ResidencyCounter:32;\r | |
| 2617 | ///\r | |
| 2618 | /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r | |
| 2619 | /// reset that this package is in processor-specific C10 states. Count at\r | |
| 2620 | /// the same frequency as the TSC.\r | |
| 2621 | ///\r | |
| 2622 | UINT32 C10ResidencyCounterHi:28;\r | |
| 2623 | UINT32 Reserved:4;\r | |
| 2624 | } Bits;\r | |
| 2625 | ///\r | |
| 2626 | /// All bit fields as a 64-bit value\r | |
| 2627 | ///\r | |
| 2628 | UINT64 Uint64;\r | |
| 2629 | } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;\r | |
| 2630 | \r | |
| 2631 | #endif\r |