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[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / NehalemMsr.h
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bd946618
MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Nehalem microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
f4c982bf 9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
bd946618
MK		 10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
0f16be6d 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6.\r
bd946618
MK		 21\r
22**/\r
23\r
24#ifndef __NEHALEM_MSR_H__\r
25#define __NEHALEM_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
f4c982bf
JF		 29/**\r
30 Is Intel processors based on the Nehalem microarchitecture?\r
31\r
32 @param DisplayFamily Display Family ID\r
33 @param DisplayModel Display Model ID\r
34\r
35 @retval TRUE Yes, it is.\r
36 @retval FALSE No, it isn't.\r
37**/\r
38#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \\r
39 (DisplayFamily == 0x06 && \\r
40 ( \\r
41 DisplayModel == 0x1A || \\r
42 DisplayModel == 0x1E || \\r
43 DisplayModel == 0x1F || \\r
44 DisplayModel == 0x2E \\r
45 ) \\r
46 )\r
47\r
bd946618
MK		 48/**\r
49 Package. Model Specific Platform ID (R).\r
50\r
51 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)\r
52 @param EAX Lower 32-bits of MSR value.\r
53 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
54 @param EDX Upper 32-bits of MSR value.\r
55 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
56\r
57 <b>Example usage</b>\r
58 @code\r
59 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;\r
60\r
61 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);\r
62 @endcode\r
c2aa191b 63 @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
bd946618
MK		 64**/\r
65#define MSR_NEHALEM_PLATFORM_ID 0x00000017\r
66\r
67/**\r
68 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID\r
69**/\r
70typedef union {\r
71 ///\r
72 /// Individual bit fields\r
73 ///\r
74 struct {\r
75 UINT32 Reserved1:32;\r
76 UINT32 Reserved2:18;\r
77 ///\r
78 /// [Bits 52:50] See Table 35-2.\r
79 ///\r
80 UINT32 PlatformId:3;\r
81 UINT32 Reserved3:11;\r
82 } Bits;\r
83 ///\r
84 /// All bit fields as a 64-bit value\r
85 ///\r
86 UINT64 Uint64;\r
87} MSR_NEHALEM_PLATFORM_ID_REGISTER;\r
88\r
89\r
90/**\r
91 Thread. SMI Counter (R/O).\r
92\r
93 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)\r
94 @param EAX Lower 32-bits of MSR value.\r
95 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
96 @param EDX Upper 32-bits of MSR value.\r
97 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
98\r
99 <b>Example usage</b>\r
100 @code\r
101 MSR_NEHALEM_SMI_COUNT_REGISTER Msr;\r
102\r
103 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);\r
104 @endcode\r
c2aa191b 105 @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
bd946618
MK		 106**/\r
107#define MSR_NEHALEM_SMI_COUNT 0x00000034\r
108\r
109/**\r
110 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT\r
111**/\r
112typedef union {\r
113 ///\r
114 /// Individual bit fields\r
115 ///\r
116 struct {\r
117 ///\r
118 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
119 /// RESET.\r
120 ///\r
121 UINT32 SMICount:32;\r
122 UINT32 Reserved:32;\r
123 } Bits;\r
124 ///\r
125 /// All bit fields as a 32-bit value\r
126 ///\r
127 UINT32 Uint32;\r
128 ///\r
129 /// All bit fields as a 64-bit value\r
130 ///\r
131 UINT64 Uint64;\r
132} MSR_NEHALEM_SMI_COUNT_REGISTER;\r
133\r
134\r
135/**\r
136 Package. see http://biosbits.org.\r
137\r
138 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)\r
139 @param EAX Lower 32-bits of MSR value.\r
140 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
141 @param EDX Upper 32-bits of MSR value.\r
142 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
143\r
144 <b>Example usage</b>\r
145 @code\r
146 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;\r
147\r
148 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);\r
149 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);\r
150 @endcode\r
c2aa191b 151 @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
bd946618
MK		 152**/\r
153#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE\r
154\r
155/**\r
156 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO\r
157**/\r
158typedef union {\r
159 ///\r
160 /// Individual bit fields\r
161 ///\r
162 struct {\r
163 UINT32 Reserved1:8;\r
164 ///\r
165 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
166 /// of the frequency that invariant TSC runs at. The invariant TSC\r
167 /// frequency can be computed by multiplying this ratio by 133.33 MHz.\r
168 ///\r
169 UINT32 MaximumNonTurboRatio:8;\r
170 UINT32 Reserved2:12;\r
171 ///\r
172 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
173 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
174 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
175 /// Turbo mode is disabled.\r
176 ///\r
177 UINT32 RatioLimit:1;\r
178 ///\r
179 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)\r
180 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are\r
181 /// programmable, and when set to 0, indicates TDC and TDP Limits for\r
182 /// Turbo mode are not programmable.\r
183 ///\r
184 UINT32 TDC_TDPLimit:1;\r
185 UINT32 Reserved3:2;\r
186 UINT32 Reserved4:8;\r
187 ///\r
188 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
189 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
190 /// units of 133.33MHz.\r
191 ///\r
192 UINT32 MaximumEfficiencyRatio:8;\r
193 UINT32 Reserved5:16;\r
194 } Bits;\r
195 ///\r
196 /// All bit fields as a 64-bit value\r
197 ///\r
198 UINT64 Uint64;\r
199} MSR_NEHALEM_PLATFORM_INFO_REGISTER;\r
200\r
201\r
202/**\r
203 Core. C-State Configuration Control (R/W) Note: C-state values are\r
204 processor specific C-state code names, unrelated to MWAIT extension C-state\r
205 parameters or ACPI CStates. See http://biosbits.org.\r
206\r
207 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
208 @param EAX Lower 32-bits of MSR value.\r
209 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
210 @param EDX Upper 32-bits of MSR value.\r
211 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
212\r
213 <b>Example usage</b>\r
214 @code\r
215 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
216\r
217 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);\r
218 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
219 @endcode\r
c2aa191b 220 @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
bd946618
MK		 221**/\r
222#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2\r
223\r
224/**\r
225 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL\r
226**/\r
227typedef union {\r
228 ///\r
229 /// Individual bit fields\r
230 ///\r
231 struct {\r
232 ///\r
233 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
234 /// processor-specific C-state code name (consuming the least power). for\r
235 /// the package. The default is set as factory-configured package C-state\r
236 /// limit. The following C-state code name encodings are supported: 000b:\r
237 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
238 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package\r
239 /// C-state limit. Note: This field cannot be used to limit package\r
240 /// C-state to C3.\r
241 ///\r
242 UINT32 Limit:3;\r
243 UINT32 Reserved1:7;\r
244 ///\r
245 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
246 /// IO_read instructions sent to IO register specified by\r
247 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
248 ///\r
249 UINT32 IO_MWAIT:1;\r
250 UINT32 Reserved2:4;\r
251 ///\r
252 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
253 /// until next reset.\r
254 ///\r
255 UINT32 CFGLock:1;\r
256 UINT32 Reserved3:8;\r
257 ///\r
258 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores\r
259 /// in a deep C-State will wake only when the event message is destined\r
260 /// for that core. When 0, all processor cores in a deep C-State will wake\r
261 /// for an event message.\r
262 ///\r
263 UINT32 InterruptFiltering:1;\r
264 ///\r
265 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
266 /// will conditionally demote C6/C7 requests to C3 based on uncore\r
267 /// auto-demote information.\r
268 ///\r
269 UINT32 C3AutoDemotion:1;\r
270 ///\r
271 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
272 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
273 /// auto-demote information.\r
274 ///\r
275 UINT32 C1AutoDemotion:1;\r
0f16be6d
HW		 276 ///\r
277 /// [Bit 27] Enable C3 Undemotion (R/W).\r
278 ///\r
279 UINT32 C3Undemotion:1;\r
280 ///\r
281 /// [Bit 28] Enable C1 Undemotion (R/W).\r
282 ///\r
283 UINT32 C1Undemotion:1;\r
284 ///\r
285 /// [Bit 29] Package C State Demotion Enable (R/W).\r
286 ///\r
287 UINT32 CStateDemotion:1;\r
288 ///\r
289 /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
290 ///\r
291 UINT32 CStateUndemotion:1;\r
292 UINT32 Reserved4:1;\r
bd946618
MK		 293 UINT32 Reserved5:32;\r
294 } Bits;\r
295 ///\r
296 /// All bit fields as a 32-bit value\r
297 ///\r
298 UINT32 Uint32;\r
299 ///\r
300 /// All bit fields as a 64-bit value\r
301 ///\r
302 UINT64 Uint64;\r
303} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;\r
304\r
305\r
306/**\r
307 Core. Power Management IO Redirection in C-state (R/W) See\r
308 http://biosbits.org.\r
309\r
310 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)\r
311 @param EAX Lower 32-bits of MSR value.\r
312 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
313 @param EDX Upper 32-bits of MSR value.\r
314 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
315\r
316 <b>Example usage</b>\r
317 @code\r
318 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
319\r
320 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);\r
321 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
322 @endcode\r
c2aa191b 323 @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
bd946618
MK		 324**/\r
325#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4\r
326\r
327/**\r
328 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE\r
329**/\r
330typedef union {\r
331 ///\r
332 /// Individual bit fields\r
333 ///\r
334 struct {\r
335 ///\r
336 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
337 /// visible to software for IO redirection. If IO MWAIT Redirection is\r
338 /// enabled, reads to this address will be consumed by the power\r
339 /// management logic and decoded to MWAIT instructions. When IO port\r
340 /// address redirection is enabled, this is the IO port address reported\r
341 /// to the OS/software.\r
342 ///\r
343 UINT32 Lvl2Base:16;\r
344 ///\r
345 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
346 /// maximum C-State code name to be included when IO read to MWAIT\r
347 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
348 /// is the max C-State to include 001b - C6 is the max C-State to include\r
349 /// 010b - C7 is the max C-State to include.\r
350 ///\r
351 UINT32 CStateRange:3;\r
352 UINT32 Reserved1:13;\r
353 UINT32 Reserved2:32;\r
354 } Bits;\r
355 ///\r
356 /// All bit fields as a 32-bit value\r
357 ///\r
358 UINT32 Uint32;\r
359 ///\r
360 /// All bit fields as a 64-bit value\r
361 ///\r
362 UINT64 Uint64;\r
363} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;\r
364\r
365\r
366/**\r
367 Enable Misc. Processor Features (R/W) Allows a variety of processor\r
368 functions to be enabled and disabled.\r
369\r
370 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)\r
371 @param EAX Lower 32-bits of MSR value.\r
372 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
373 @param EDX Upper 32-bits of MSR value.\r
374 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
375\r
376 <b>Example usage</b>\r
377 @code\r
378 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;\r
379\r
380 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);\r
381 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);\r
382 @endcode\r
c2aa191b 383 @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
bd946618
MK		 384**/\r
385#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0\r
386\r
387/**\r
388 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE\r
389**/\r
390typedef union {\r
391 ///\r
392 /// Individual bit fields\r
393 ///\r
394 struct {\r
395 ///\r
396 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.\r
397 ///\r
398 UINT32 FastStrings:1;\r
399 UINT32 Reserved1:2;\r
400 ///\r
401 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
0f16be6d 402 /// Table 35-2. Default value is 1.\r
bd946618
MK		 403 ///\r
404 UINT32 AutomaticThermalControlCircuit:1;\r
405 UINT32 Reserved2:3;\r
406 ///\r
407 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.\r
408 ///\r
409 UINT32 PerformanceMonitoring:1;\r
410 UINT32 Reserved3:3;\r
411 ///\r
412 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
413 ///\r
414 UINT32 BTS:1;\r
415 ///\r
0f16be6d 416 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
bd946618
MK		 417 /// Table 35-2.\r
418 ///\r
419 UINT32 PEBS:1;\r
420 UINT32 Reserved4:3;\r
421 ///\r
422 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
423 /// Table 35-2.\r
424 ///\r
425 UINT32 EIST:1;\r
426 UINT32 Reserved5:1;\r
427 ///\r
428 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.\r
429 ///\r
430 UINT32 MONITOR:1;\r
431 UINT32 Reserved6:3;\r
432 ///\r
433 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.\r
434 ///\r
435 UINT32 LimitCpuidMaxval:1;\r
436 ///\r
437 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.\r
438 ///\r
439 UINT32 xTPR_Message_Disable:1;\r
440 UINT32 Reserved7:8;\r
441 UINT32 Reserved8:2;\r
442 ///\r
443 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.\r
444 ///\r
445 UINT32 XD:1;\r
446 UINT32 Reserved9:3;\r
447 ///\r
448 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
449 /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
450 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
451 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
452 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
453 /// the power-on default value is used by BIOS to detect hardware support\r
454 /// of turbo mode. If power-on default value is 1, turbo mode is available\r
455 /// in the processor. If power-on default value is 0, turbo mode is not\r
456 /// available.\r
457 ///\r
458 UINT32 TurboModeDisable:1;\r
459 UINT32 Reserved10:25;\r
460 } Bits;\r
461 ///\r
462 /// All bit fields as a 64-bit value\r
463 ///\r
464 UINT64 Uint64;\r
465} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;\r
466\r
467\r
468/**\r
469 Thread.\r
470\r
471 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)\r
472 @param EAX Lower 32-bits of MSR value.\r
473 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
474 @param EDX Upper 32-bits of MSR value.\r
475 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
476\r
477 <b>Example usage</b>\r
478 @code\r
479 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;\r
480\r
481 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);\r
482 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);\r
483 @endcode\r
c2aa191b 484 @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
bd946618
MK		 485**/\r
486#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2\r
487\r
488/**\r
489 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET\r
490**/\r
491typedef union {\r
492 ///\r
493 /// Individual bit fields\r
494 ///\r
495 struct {\r
496 UINT32 Reserved1:16;\r
497 ///\r
498 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
499 /// PROCHOT# will be asserted. The value is degree C.\r
500 ///\r
501 UINT32 TemperatureTarget:8;\r
502 UINT32 Reserved2:8;\r
503 UINT32 Reserved3:32;\r
504 } Bits;\r
505 ///\r
506 /// All bit fields as a 32-bit value\r
507 ///\r
508 UINT32 Uint32;\r
509 ///\r
510 /// All bit fields as a 64-bit value\r
511 ///\r
512 UINT64 Uint64;\r
513} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;\r
514\r
515\r
516/**\r
517 Miscellaneous Feature Control (R/W).\r
518\r
519 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)\r
520 @param EAX Lower 32-bits of MSR value.\r
521 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
522 @param EDX Upper 32-bits of MSR value.\r
523 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
524\r
525 <b>Example usage</b>\r
526 @code\r
527 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;\r
528\r
529 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);\r
530 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);\r
531 @endcode\r
c2aa191b 532 @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
bd946618
MK		 533**/\r
534#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4\r
535\r
536/**\r
537 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL\r
538**/\r
539typedef union {\r
540 ///\r
541 /// Individual bit fields\r
542 ///\r
543 struct {\r
544 ///\r
545 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
546 /// L2 hardware prefetcher, which fetches additional lines of code or data\r
547 /// into the L2 cache.\r
548 ///\r
549 UINT32 L2HardwarePrefetcherDisable:1;\r
550 ///\r
551 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
552 /// disables the adjacent cache line prefetcher, which fetches the cache\r
553 /// line that comprises a cache line pair (128 bytes).\r
554 ///\r
555 UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
556 ///\r
557 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
558 /// the L1 data cache prefetcher, which fetches the next cache line into\r
559 /// L1 data cache.\r
560 ///\r
561 UINT32 DCUHardwarePrefetcherDisable:1;\r
562 ///\r
563 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
564 /// data cache IP prefetcher, which uses sequential load history (based on\r
565 /// instruction Pointer of previous loads) to determine whether to\r
566 /// prefetch additional lines.\r
567 ///\r
568 UINT32 DCUIPPrefetcherDisable:1;\r
569 UINT32 Reserved1:28;\r
570 UINT32 Reserved2:32;\r
571 } Bits;\r
572 ///\r
573 /// All bit fields as a 32-bit value\r
574 ///\r
575 UINT32 Uint32;\r
576 ///\r
577 /// All bit fields as a 64-bit value\r
578 ///\r
579 UINT64 Uint64;\r
580} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;\r
581\r
582\r
583/**\r
584 Thread. Offcore Response Event Select Register (R/W).\r
585\r
586 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)\r
587 @param EAX Lower 32-bits of MSR value.\r
588 @param EDX Upper 32-bits of MSR value.\r
589\r
590 <b>Example usage</b>\r
591 @code\r
592 UINT64 Msr;\r
593\r
594 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);\r
595 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);\r
596 @endcode\r
c2aa191b 597 @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
bd946618
MK		 598**/\r
599#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6\r
600\r
601\r
602/**\r
603 See http://biosbits.org.\r
604\r
605 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)\r
606 @param EAX Lower 32-bits of MSR value.\r
607 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
608 @param EDX Upper 32-bits of MSR value.\r
609 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
610\r
611 <b>Example usage</b>\r
612 @code\r
613 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;\r
614\r
615 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);\r
616 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);\r
617 @endcode\r
c2aa191b 618 @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
bd946618
MK		 619**/\r
620#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA\r
621\r
622/**\r
623 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT\r
624**/\r
625typedef union {\r
626 ///\r
627 /// Individual bit fields\r
628 ///\r
629 struct {\r
630 ///\r
631 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,\r
632 /// enables hardware coordination of Enhanced Intel Speedstep Technology\r
633 /// request from processor cores; When 1, disables hardware coordination\r
634 /// of Enhanced Intel Speedstep Technology requests.\r
635 ///\r
636 UINT32 EISTHardwareCoordinationDisable:1;\r
637 ///\r
638 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes\r
639 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with\r
640 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by\r
641 /// CPUID.(EAX=06h):ECX[3].\r
642 ///\r
643 UINT32 EnergyPerformanceBiasEnable:1;\r
644 UINT32 Reserved1:30;\r
645 UINT32 Reserved2:32;\r
646 } Bits;\r
647 ///\r
648 /// All bit fields as a 32-bit value\r
649 ///\r
650 UINT32 Uint32;\r
651 ///\r
652 /// All bit fields as a 64-bit value\r
653 ///\r
654 UINT64 Uint64;\r
655} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;\r
656\r
657\r
658/**\r
659 See http://biosbits.org.\r
660\r
661 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)\r
662 @param EAX Lower 32-bits of MSR value.\r
663 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
664 @param EDX Upper 32-bits of MSR value.\r
665 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
666\r
667 <b>Example usage</b>\r
668 @code\r
669 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;\r
670\r
671 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);\r
672 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);\r
673 @endcode\r
c2aa191b 674 @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.\r
bd946618
MK		 675**/\r
676#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC\r
677\r
678/**\r
679 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT\r
680**/\r
681typedef union {\r
682 ///\r
683 /// Individual bit fields\r
684 ///\r
685 struct {\r
686 ///\r
687 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt\r
688 /// granularity.\r
689 ///\r
690 UINT32 TDPLimit:15;\r
691 ///\r
692 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0\r
693 /// indicates override is not active, and a value = 1 indicates active.\r
694 ///\r
695 UINT32 TDPLimitOverrideEnable:1;\r
696 ///\r
697 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp\r
698 /// granularity.\r
699 ///\r
700 UINT32 TDCLimit:15;\r
701 ///\r
702 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0\r
703 /// indicates override is not active, and a value = 1 indicates active.\r
704 ///\r
705 UINT32 TDCLimitOverrideEnable:1;\r
706 UINT32 Reserved:32;\r
707 } Bits;\r
708 ///\r
709 /// All bit fields as a 32-bit value\r
710 ///\r
711 UINT32 Uint32;\r
712 ///\r
713 /// All bit fields as a 64-bit value\r
714 ///\r
715 UINT64 Uint64;\r
716} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;\r
717\r
718\r
719/**\r
720 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
721 RW if MSR_PLATFORM_INFO.[28] = 1.\r
722\r
723 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)\r
724 @param EAX Lower 32-bits of MSR value.\r
725 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
726 @param EDX Upper 32-bits of MSR value.\r
727 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
728\r
729 <b>Example usage</b>\r
730 @code\r
731 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;\r
732\r
733 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);\r
734 @endcode\r
c2aa191b 735 @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
bd946618
MK		 736**/\r
737#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD\r
738\r
739/**\r
740 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT\r
741**/\r
742typedef union {\r
743 ///\r
744 /// Individual bit fields\r
745 ///\r
746 struct {\r
747 ///\r
748 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
749 /// limit of 1 core active.\r
750 ///\r
751 UINT32 Maximum1C:8;\r
752 ///\r
753 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
754 /// limit of 2 core active.\r
755 ///\r
756 UINT32 Maximum2C:8;\r
757 ///\r
758 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
759 /// limit of 3 core active.\r
760 ///\r
761 UINT32 Maximum3C:8;\r
762 ///\r
763 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
764 /// limit of 4 core active.\r
765 ///\r
766 UINT32 Maximum4C:8;\r
767 UINT32 Reserved:32;\r
768 } Bits;\r
769 ///\r
770 /// All bit fields as a 32-bit value\r
771 ///\r
772 UINT32 Uint32;\r
773 ///\r
774 /// All bit fields as a 64-bit value\r
775 ///\r
776 UINT64 Uint64;\r
777} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;\r
778\r
779\r
780/**\r
781 Core. Last Branch Record Filtering Select Register (R/W) See Section\r
0f16be6d 782 17.7.2, "Filtering of Last Branch Records.".\r
bd946618
MK		 783\r
784 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)\r
785 @param EAX Lower 32-bits of MSR value.\r
786 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
787 @param EDX Upper 32-bits of MSR value.\r
788 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
789\r
790 <b>Example usage</b>\r
791 @code\r
792 MSR_NEHALEM_LBR_SELECT_REGISTER Msr;\r
793\r
794 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);\r
795 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);\r
796 @endcode\r
c2aa191b 797 @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
bd946618
MK		 798**/\r
799#define MSR_NEHALEM_LBR_SELECT 0x000001C8\r
800\r
801/**\r
802 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT\r
803**/\r
804typedef union {\r
805 ///\r
806 /// Individual bit fields\r
807 ///\r
808 struct {\r
809 ///\r
810 /// [Bit 0] CPL_EQ_0.\r
811 ///\r
812 UINT32 CPL_EQ_0:1;\r
813 ///\r
814 /// [Bit 1] CPL_NEQ_0.\r
815 ///\r
816 UINT32 CPL_NEQ_0:1;\r
817 ///\r
818 /// [Bit 2] JCC.\r
819 ///\r
820 UINT32 JCC:1;\r
821 ///\r
822 /// [Bit 3] NEAR_REL_CALL.\r
823 ///\r
824 UINT32 NEAR_REL_CALL:1;\r
825 ///\r
826 /// [Bit 4] NEAR_IND_CALL.\r
827 ///\r
828 UINT32 NEAR_IND_CALL:1;\r
829 ///\r
830 /// [Bit 5] NEAR_RET.\r
831 ///\r
832 UINT32 NEAR_RET:1;\r
833 ///\r
834 /// [Bit 6] NEAR_IND_JMP.\r
835 ///\r
836 UINT32 NEAR_IND_JMP:1;\r
837 ///\r
838 /// [Bit 7] NEAR_REL_JMP.\r
839 ///\r
840 UINT32 NEAR_REL_JMP:1;\r
841 ///\r
842 /// [Bit 8] FAR_BRANCH.\r
843 ///\r
844 UINT32 FAR_BRANCH:1;\r
845 UINT32 Reserved1:23;\r
846 UINT32 Reserved2:32;\r
847 } Bits;\r
848 ///\r
849 /// All bit fields as a 32-bit value\r
850 ///\r
851 UINT32 Uint32;\r
852 ///\r
853 /// All bit fields as a 64-bit value\r
854 ///\r
855 UINT64 Uint64;\r
856} MSR_NEHALEM_LBR_SELECT_REGISTER;\r
857\r
858\r
859/**\r
860 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
861 that points to the MSR containing the most recent branch record. See\r
862 MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
863\r
864 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)\r
865 @param EAX Lower 32-bits of MSR value.\r
866 @param EDX Upper 32-bits of MSR value.\r
867\r
868 <b>Example usage</b>\r
869 @code\r
870 UINT64 Msr;\r
871\r
872 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);\r
873 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);\r
874 @endcode\r
c2aa191b 875 @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
bd946618
MK		 876**/\r
877#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9\r
878\r
879\r
880/**\r
881 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
882 last branch instruction that the processor executed prior to the last\r
883 exception that was generated or the last interrupt that was handled.\r
884\r
885 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)\r
886 @param EAX Lower 32-bits of MSR value.\r
887 @param EDX Upper 32-bits of MSR value.\r
888\r
889 <b>Example usage</b>\r
890 @code\r
891 UINT64 Msr;\r
892\r
893 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);\r
894 @endcode\r
c2aa191b 895 @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
bd946618
MK		 896**/\r
897#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD\r
898\r
899\r
900/**\r
901 Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
902 to the target of the last branch instruction that the processor executed\r
903 prior to the last exception that was generated or the last interrupt that\r
904 was handled.\r
905\r
906 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)\r
907 @param EAX Lower 32-bits of MSR value.\r
908 @param EDX Upper 32-bits of MSR value.\r
909\r
910 <b>Example usage</b>\r
911 @code\r
912 UINT64 Msr;\r
913\r
914 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);\r
915 @endcode\r
c2aa191b 916 @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
bd946618
MK		 917**/\r
918#define MSR_NEHALEM_LER_TO_LIP 0x000001DE\r
919\r
920\r
921/**\r
922 Core. Power Control Register. See http://biosbits.org.\r
923\r
924 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)\r
925 @param EAX Lower 32-bits of MSR value.\r
926 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
927 @param EDX Upper 32-bits of MSR value.\r
928 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
929\r
930 <b>Example usage</b>\r
931 @code\r
932 MSR_NEHALEM_POWER_CTL_REGISTER Msr;\r
933\r
934 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);\r
935 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);\r
936 @endcode\r
c2aa191b 937 @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
bd946618
MK		 938**/\r
939#define MSR_NEHALEM_POWER_CTL 0x000001FC\r
940\r
941/**\r
942 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL\r
943**/\r
944typedef union {\r
945 ///\r
946 /// Individual bit fields\r
947 ///\r
948 struct {\r
949 UINT32 Reserved1:1;\r
950 ///\r
951 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
952 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
953 /// operating point when all execution cores enter MWAIT (C1).\r
954 ///\r
955 UINT32 C1EEnable:1;\r
956 UINT32 Reserved2:30;\r
957 UINT32 Reserved3:32;\r
958 } Bits;\r
959 ///\r
960 /// All bit fields as a 32-bit value\r
961 ///\r
962 UINT32 Uint32;\r
963 ///\r
964 /// All bit fields as a 64-bit value\r
965 ///\r
966 UINT64 Uint64;\r
967} MSR_NEHALEM_POWER_CTL_REGISTER;\r
968\r
969\r
bd946618
MK		 970/**\r
971 Thread. (RO).\r
972\r
0f16be6d 973 @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)\r
bd946618 974 @param EAX Lower 32-bits of MSR value.\r
0f16be6d 975 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
bd946618 976 @param EDX Upper 32-bits of MSR value.\r
0f16be6d 977 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
bd946618
MK		 978\r
979 <b>Example usage</b>\r
980 @code\r
0f16be6d 981 MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;\r
bd946618 982\r
0f16be6d 983 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);\r
bd946618 984 @endcode\r
0f16be6d 985 @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
bd946618 986**/\r
0f16be6d 987#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r
bd946618
MK		 988\r
989/**\r
0f16be6d 990 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r
bd946618
MK		 991**/\r
992typedef union {\r
993 ///\r
994 /// Individual bit fields\r
995 ///\r
996 struct {\r
997 UINT32 Reserved1:32;\r
998 UINT32 Reserved2:29;\r
999 ///\r
1000 /// [Bit 61] UNC_Ovf Uncore overflowed if 1.\r
1001 ///\r
1002 UINT32 Ovf_Uncore:1;\r
1003 UINT32 Reserved3:2;\r
1004 } Bits;\r
1005 ///\r
1006 /// All bit fields as a 64-bit value\r
1007 ///\r
1008 UINT64 Uint64;\r
0f16be6d 1009} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r
bd946618
MK		 1010\r
1011\r
1012/**\r
1013 Thread. (R/W).\r
1014\r
1015 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
1016 @param EAX Lower 32-bits of MSR value.\r
1017 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
1018 @param EDX Upper 32-bits of MSR value.\r
1019 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
1020\r
1021 <b>Example usage</b>\r
1022 @code\r
1023 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
1024\r
1025 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);\r
1026 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
1027 @endcode\r
c2aa191b 1028 @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
bd946618
MK		 1029**/\r
1030#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390\r
1031\r
1032/**\r
1033 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL\r
1034**/\r
1035typedef union {\r
1036 ///\r
1037 /// Individual bit fields\r
1038 ///\r
1039 struct {\r
1040 UINT32 Reserved1:32;\r
1041 UINT32 Reserved2:29;\r
1042 ///\r
1043 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.\r
1044 ///\r
1045 UINT32 Ovf_Uncore:1;\r
1046 UINT32 Reserved3:2;\r
1047 } Bits;\r
1048 ///\r
1049 /// All bit fields as a 64-bit value\r
1050 ///\r
1051 UINT64 Uint64;\r
1052} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
1053\r
1054\r
1055/**\r
0f16be6d 1056 Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".\r
bd946618
MK		 1057\r
1058 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r
1059 @param EAX Lower 32-bits of MSR value.\r
1060 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
1061 @param EDX Upper 32-bits of MSR value.\r
1062 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
1063\r
1064 <b>Example usage</b>\r
1065 @code\r
1066 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;\r
1067\r
1068 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);\r
1069 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);\r
1070 @endcode\r
c2aa191b 1071 @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
bd946618
MK		 1072**/\r
1073#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1\r
1074\r
1075/**\r
1076 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE\r
1077**/\r
1078typedef union {\r
1079 ///\r
1080 /// Individual bit fields\r
1081 ///\r
1082 struct {\r
1083 ///\r
1084 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
1085 ///\r
1086 UINT32 PEBS_EN_PMC0:1;\r
1087 ///\r
1088 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
1089 ///\r
1090 UINT32 PEBS_EN_PMC1:1;\r
1091 ///\r
1092 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
1093 ///\r
1094 UINT32 PEBS_EN_PMC2:1;\r
1095 ///\r
1096 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
1097 ///\r
1098 UINT32 PEBS_EN_PMC3:1;\r
1099 UINT32 Reserved1:28;\r
1100 ///\r
1101 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
1102 ///\r
1103 UINT32 LL_EN_PMC0:1;\r
1104 ///\r
1105 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
1106 ///\r
1107 UINT32 LL_EN_PMC1:1;\r
1108 ///\r
1109 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
1110 ///\r
1111 UINT32 LL_EN_PMC2:1;\r
1112 ///\r
1113 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
1114 ///\r
1115 UINT32 LL_EN_PMC3:1;\r
1116 UINT32 Reserved2:28;\r
1117 } Bits;\r
1118 ///\r
1119 /// All bit fields as a 64-bit value\r
1120 ///\r
1121 UINT64 Uint64;\r
1122} MSR_NEHALEM_PEBS_ENABLE_REGISTER;\r
1123\r
1124\r
1125/**\r
0f16be6d 1126 Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring\r
bd946618
MK		 1127 Facility.".\r
1128\r
1129 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r
1130 @param EAX Lower 32-bits of MSR value.\r
1131 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
1132 @param EDX Upper 32-bits of MSR value.\r
1133 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
1134\r
1135 <b>Example usage</b>\r
1136 @code\r
1137 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;\r
1138\r
1139 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);\r
1140 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);\r
1141 @endcode\r
c2aa191b 1142 @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
bd946618
MK		 1143**/\r
1144#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6\r
1145\r
1146/**\r
1147 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT\r
1148**/\r
1149typedef union {\r
1150 ///\r
1151 /// Individual bit fields\r
1152 ///\r
1153 struct {\r
1154 ///\r
1155 /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
1156 /// that will be counted. (R/W).\r
1157 ///\r
1158 UINT32 MinimumThreshold:16;\r
1159 UINT32 Reserved1:16;\r
1160 UINT32 Reserved2:32;\r
1161 } Bits;\r
1162 ///\r
1163 /// All bit fields as a 32-bit value\r
1164 ///\r
1165 UINT32 Uint32;\r
1166 ///\r
1167 /// All bit fields as a 64-bit value\r
1168 ///\r
1169 UINT64 Uint64;\r
1170} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;\r
1171\r
1172\r
1173/**\r
1174 Package. Note: C-state values are processor specific C-state code names,\r
1175 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
1176 Residency Counter. (R/O) Value since last reset that this package is in\r
1177 processor-specific C3 states. Count at the same frequency as the TSC.\r
1178\r
1179 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)\r
1180 @param EAX Lower 32-bits of MSR value.\r
1181 @param EDX Upper 32-bits of MSR value.\r
1182\r
1183 <b>Example usage</b>\r
1184 @code\r
1185 UINT64 Msr;\r
1186\r
1187 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);\r
1188 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);\r
1189 @endcode\r
c2aa191b 1190 @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
bd946618
MK		 1191**/\r
1192#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8\r
1193\r
1194\r
1195/**\r
1196 Package. Note: C-state values are processor specific C-state code names,\r
1197 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
1198 Residency Counter. (R/O) Value since last reset that this package is in\r
1199 processor-specific C6 states. Count at the same frequency as the TSC.\r
1200\r
1201 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)\r
1202 @param EAX Lower 32-bits of MSR value.\r
1203 @param EDX Upper 32-bits of MSR value.\r
1204\r
1205 <b>Example usage</b>\r
1206 @code\r
1207 UINT64 Msr;\r
1208\r
1209 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);\r
1210 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);\r
1211 @endcode\r
c2aa191b 1212 @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
bd946618
MK		 1213**/\r
1214#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9\r
1215\r
1216\r
1217/**\r
1218 Package. Note: C-state values are processor specific C-state code names,\r
1219 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
1220 Residency Counter. (R/O) Value since last reset that this package is in\r
1221 processor-specific C7 states. Count at the same frequency as the TSC.\r
1222\r
1223 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)\r
1224 @param EAX Lower 32-bits of MSR value.\r
1225 @param EDX Upper 32-bits of MSR value.\r
1226\r
1227 <b>Example usage</b>\r
1228 @code\r
1229 UINT64 Msr;\r
1230\r
1231 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);\r
1232 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);\r
1233 @endcode\r
c2aa191b 1234 @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
bd946618
MK		 1235**/\r
1236#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA\r
1237\r
1238\r
1239/**\r
1240 Core. Note: C-state values are processor specific C-state code names,\r
1241 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
1242 Residency Counter. (R/O) Value since last reset that this core is in\r
1243 processor-specific C3 states. Count at the same frequency as the TSC.\r
1244\r
1245 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)\r
1246 @param EAX Lower 32-bits of MSR value.\r
1247 @param EDX Upper 32-bits of MSR value.\r
1248\r
1249 <b>Example usage</b>\r
1250 @code\r
1251 UINT64 Msr;\r
1252\r
1253 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);\r
1254 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);\r
1255 @endcode\r
c2aa191b 1256 @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
bd946618
MK		 1257**/\r
1258#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC\r
1259\r
1260\r
1261/**\r
1262 Core. Note: C-state values are processor specific C-state code names,\r
1263 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
1264 Residency Counter. (R/O) Value since last reset that this core is in\r
1265 processor-specific C6 states. Count at the same frequency as the TSC.\r
1266\r
1267 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)\r
1268 @param EAX Lower 32-bits of MSR value.\r
1269 @param EDX Upper 32-bits of MSR value.\r
1270\r
1271 <b>Example usage</b>\r
1272 @code\r
1273 UINT64 Msr;\r
1274\r
1275 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);\r
1276 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);\r
1277 @endcode\r
c2aa191b 1278 @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
bd946618
MK		 1279**/\r
1280#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
1281\r
1282\r
bd946618
MK		 1283/**\r
1284 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
0f16be6d
HW		 1285 branch record registers on the last branch record stack. The From_IP part of\r
1286 the stack contains pointers to the source instruction. See also: - Last\r
1287 Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in\r
1288 Section 17.4.8.1.\r
bd946618
MK		 1289\r
1290 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r
1291 @param EAX Lower 32-bits of MSR value.\r
1292 @param EDX Upper 32-bits of MSR value.\r
1293\r
1294 <b>Example usage</b>\r
1295 @code\r
1296 UINT64 Msr;\r
1297\r
1298 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);\r
1299 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);\r
1300 @endcode\r
c2aa191b
JF		 1301 @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
1302 MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
1303 MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
1304 MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
1305 MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
1306 MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
1307 MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
1308 MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
1309 MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
1310 MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
1311 MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
1312 MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
1313 MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
1314 MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
1315 MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
1316 MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
bd946618
MK		 1317 @{\r
1318**/\r
1319#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680\r
1320#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681\r
1321#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682\r
1322#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683\r
1323#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684\r
1324#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685\r
1325#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686\r
1326#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687\r
1327#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688\r
1328#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689\r
1329#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A\r
1330#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B\r
1331#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C\r
1332#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D\r
1333#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E\r
1334#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F\r
1335/// @}\r
1336\r
1337\r
1338/**\r
1339 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
1340 record registers on the last branch record stack. This part of the stack\r
0f16be6d 1341 contains pointers to the destination instruction.\r
bd946618
MK		 1342\r
1343 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP\r
1344 @param EAX Lower 32-bits of MSR value.\r
1345 @param EDX Upper 32-bits of MSR value.\r
1346\r
1347 <b>Example usage</b>\r
1348 @code\r
1349 UINT64 Msr;\r
1350\r
1351 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);\r
1352 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);\r
1353 @endcode\r
c2aa191b
JF		 1354 @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
1355 MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
1356 MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
1357 MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
1358 MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
1359 MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
1360 MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
1361 MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
1362 MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
1363 MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
1364 MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
1365 MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
1366 MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
1367 MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
1368 MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
1369 MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
bd946618
MK		 1370 @{\r
1371**/\r
1372#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0\r
1373#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1\r
1374#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2\r
1375#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3\r
1376#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4\r
1377#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5\r
1378#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6\r
1379#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7\r
1380#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8\r
1381#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9\r
1382#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA\r
1383#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB\r
1384#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC\r
1385#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD\r
1386#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE\r
1387#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF\r
1388/// @}\r
1389\r
1390\r
1391/**\r
1392 Package.\r
1393\r
1394 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)\r
1395 @param EAX Lower 32-bits of MSR value.\r
1396 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
1397 @param EDX Upper 32-bits of MSR value.\r
1398 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
1399\r
1400 <b>Example usage</b>\r
1401 @code\r
1402 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;\r
1403\r
1404 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);\r
1405 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);\r
1406 @endcode\r
c2aa191b 1407 @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.\r
bd946618
MK		 1408**/\r
1409#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301\r
1410\r
1411/**\r
1412 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF\r
1413**/\r
1414typedef union {\r
1415 ///\r
1416 /// Individual bit fields\r
1417 ///\r
1418 struct {\r
1419 ///\r
1420 /// [Bit 0] From M to S (R/W).\r
1421 ///\r
1422 UINT32 FromMtoS:1;\r
1423 ///\r
1424 /// [Bit 1] From E to S (R/W).\r
1425 ///\r
1426 UINT32 FromEtoS:1;\r
1427 ///\r
1428 /// [Bit 2] From S to S (R/W).\r
1429 ///\r
1430 UINT32 FromStoS:1;\r
1431 ///\r
1432 /// [Bit 3] From F to S (R/W).\r
1433 ///\r
1434 UINT32 FromFtoS:1;\r
1435 ///\r
1436 /// [Bit 4] From M to I (R/W).\r
1437 ///\r
1438 UINT32 FromMtoI:1;\r
1439 ///\r
1440 /// [Bit 5] From E to I (R/W).\r
1441 ///\r
1442 UINT32 FromEtoI:1;\r
1443 ///\r
1444 /// [Bit 6] From S to I (R/W).\r
1445 ///\r
1446 UINT32 FromStoI:1;\r
1447 ///\r
1448 /// [Bit 7] From F to I (R/W).\r
1449 ///\r
1450 UINT32 FromFtoI:1;\r
1451 UINT32 Reserved1:24;\r
1452 UINT32 Reserved2:32;\r
1453 } Bits;\r
1454 ///\r
1455 /// All bit fields as a 32-bit value\r
1456 ///\r
1457 UINT32 Uint32;\r
1458 ///\r
1459 /// All bit fields as a 64-bit value\r
1460 ///\r
1461 UINT64 Uint64;\r
1462} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;\r
1463\r
1464\r
1465/**\r
0f16be6d 1466 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
bd946618
MK		 1467 Facility.".\r
1468\r
1469 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r
1470 @param EAX Lower 32-bits of MSR value.\r
1471 @param EDX Upper 32-bits of MSR value.\r
1472\r
1473 <b>Example usage</b>\r
1474 @code\r
1475 UINT64 Msr;\r
1476\r
1477 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);\r
1478 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);\r
1479 @endcode\r
c2aa191b 1480 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.\r
bd946618
MK		 1481**/\r
1482#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391\r
1483\r
1484\r
1485/**\r
0f16be6d 1486 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
bd946618
MK		 1487 Facility.".\r
1488\r
1489 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r
1490 @param EAX Lower 32-bits of MSR value.\r
1491 @param EDX Upper 32-bits of MSR value.\r
1492\r
1493 <b>Example usage</b>\r
1494 @code\r
1495 UINT64 Msr;\r
1496\r
1497 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);\r
1498 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);\r
1499 @endcode\r
c2aa191b 1500 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.\r
bd946618
MK		 1501**/\r
1502#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392\r
1503\r
1504\r
1505/**\r
0f16be6d 1506 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
bd946618
MK		 1507 Facility.".\r
1508\r
1509 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r
1510 @param EAX Lower 32-bits of MSR value.\r
1511 @param EDX Upper 32-bits of MSR value.\r
1512\r
1513 <b>Example usage</b>\r
1514 @code\r
1515 UINT64 Msr;\r
1516\r
1517 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);\r
1518 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);\r
1519 @endcode\r
c2aa191b 1520 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.\r
bd946618
MK		 1521**/\r
1522#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393\r
1523\r
1524\r
1525/**\r
0f16be6d 1526 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
bd946618
MK		 1527 Facility.".\r
1528\r
1529 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r
1530 @param EAX Lower 32-bits of MSR value.\r
1531 @param EDX Upper 32-bits of MSR value.\r
1532\r
1533 <b>Example usage</b>\r
1534 @code\r
1535 UINT64 Msr;\r
1536\r
1537 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);\r
1538 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);\r
1539 @endcode\r
c2aa191b 1540 @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.\r
bd946618
MK		 1541**/\r
1542#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394\r
1543\r
1544\r
1545/**\r
0f16be6d 1546 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
bd946618
MK		 1547 Facility.".\r
1548\r
1549 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r
1550 @param EAX Lower 32-bits of MSR value.\r
1551 @param EDX Upper 32-bits of MSR value.\r
1552\r
1553 <b>Example usage</b>\r
1554 @code\r
1555 UINT64 Msr;\r
1556\r
1557 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);\r
1558 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);\r
1559 @endcode\r
c2aa191b 1560 @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.\r
bd946618
MK		 1561**/\r
1562#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395\r
1563\r
1564\r
1565/**\r
0f16be6d 1566 Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.".\r
bd946618
MK		 1567\r
1568 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r
1569 @param EAX Lower 32-bits of MSR value.\r
1570 @param EDX Upper 32-bits of MSR value.\r
1571\r
1572 <b>Example usage</b>\r
1573 @code\r
1574 UINT64 Msr;\r
1575\r
1576 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);\r
1577 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);\r
1578 @endcode\r
c2aa191b 1579 @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.\r
bd946618
MK		 1580**/\r
1581#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396\r
1582\r
1583\r
1584/**\r
0f16be6d 1585 Package. See Section 18.8.2.2, "Uncore Performance Event Configuration\r
bd946618
MK		 1586 Facility.".\r
1587\r
1588 @param ECX MSR_NEHALEM_UNCORE_PMCi\r
1589 @param EAX Lower 32-bits of MSR value.\r
1590 @param EDX Upper 32-bits of MSR value.\r
1591\r
1592 <b>Example usage</b>\r
1593 @code\r
1594 UINT64 Msr;\r
1595\r
1596 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);\r
1597 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);\r
1598 @endcode\r
c2aa191b
JF		 1599 @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.\r
1600 MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.\r
1601 MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.\r
1602 MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.\r
1603 MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.\r
1604 MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.\r
1605 MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.\r
1606 MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.\r
bd946618
MK		 1607 @{\r
1608**/\r
1609#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0\r
1610#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1\r
1611#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2\r
1612#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3\r
1613#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4\r
1614#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5\r
1615#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6\r
1616#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7\r
1617/// @}\r
1618\r
1619/**\r
0f16be6d 1620 Package. See Section 18.8.2.2, "Uncore Performance Event Configuration\r
bd946618
MK		 1621 Facility.".\r
1622\r
1623 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi\r
1624 @param EAX Lower 32-bits of MSR value.\r
1625 @param EDX Upper 32-bits of MSR value.\r
1626\r
1627 <b>Example usage</b>\r
1628 @code\r
1629 UINT64 Msr;\r
1630\r
1631 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);\r
1632 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);\r
1633 @endcode\r
c2aa191b
JF		 1634 @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.\r
1635 MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.\r
1636 MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.\r
1637 MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.\r
1638 MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.\r
1639 MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.\r
1640 MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.\r
1641 MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.\r
bd946618
MK		 1642 @{\r
1643**/\r
1644#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0\r
1645#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1\r
1646#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2\r
1647#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3\r
1648#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4\r
1649#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5\r
1650#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6\r
1651#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7\r
1652/// @}\r
1653\r
1654\r
1655/**\r
1656 Package. Uncore W-box perfmon fixed counter.\r
1657\r
1658 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)\r
1659 @param EAX Lower 32-bits of MSR value.\r
1660 @param EDX Upper 32-bits of MSR value.\r
1661\r
1662 <b>Example usage</b>\r
1663 @code\r
1664 UINT64 Msr;\r
1665\r
1666 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);\r
1667 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);\r
1668 @endcode\r
c2aa191b 1669 @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.\r
bd946618
MK		 1670**/\r
1671#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394\r
1672\r
1673\r
1674/**\r
1675 Package. Uncore U-box perfmon fixed counter control MSR.\r
1676\r
1677 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)\r
1678 @param EAX Lower 32-bits of MSR value.\r
1679 @param EDX Upper 32-bits of MSR value.\r
1680\r
1681 <b>Example usage</b>\r
1682 @code\r
1683 UINT64 Msr;\r
1684\r
1685 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);\r
1686 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);\r
1687 @endcode\r
c2aa191b 1688 @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.\r
bd946618
MK		 1689**/\r
1690#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395\r
1691\r
1692\r
1693/**\r
1694 Package. Uncore U-box perfmon global control MSR.\r
1695\r
1696 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)\r
1697 @param EAX Lower 32-bits of MSR value.\r
1698 @param EDX Upper 32-bits of MSR value.\r
1699\r
1700 <b>Example usage</b>\r
1701 @code\r
1702 UINT64 Msr;\r
1703\r
1704 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);\r
1705 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);\r
1706 @endcode\r
c2aa191b 1707 @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.\r
bd946618
MK		 1708**/\r
1709#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00\r
1710\r
1711\r
1712/**\r
1713 Package. Uncore U-box perfmon global status MSR.\r
1714\r
1715 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)\r
1716 @param EAX Lower 32-bits of MSR value.\r
1717 @param EDX Upper 32-bits of MSR value.\r
1718\r
1719 <b>Example usage</b>\r
1720 @code\r
1721 UINT64 Msr;\r
1722\r
1723 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);\r
1724 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);\r
1725 @endcode\r
c2aa191b 1726 @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.\r
bd946618
MK		 1727**/\r
1728#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01\r
1729\r
1730\r
1731/**\r
1732 Package. Uncore U-box perfmon global overflow control MSR.\r
1733\r
1734 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)\r
1735 @param EAX Lower 32-bits of MSR value.\r
1736 @param EDX Upper 32-bits of MSR value.\r
1737\r
1738 <b>Example usage</b>\r
1739 @code\r
1740 UINT64 Msr;\r
1741\r
1742 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);\r
1743 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);\r
1744 @endcode\r
c2aa191b 1745 @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.\r
bd946618
MK		 1746**/\r
1747#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02\r
1748\r
1749\r
1750/**\r
1751 Package. Uncore U-box perfmon event select MSR.\r
1752\r
1753 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)\r
1754 @param EAX Lower 32-bits of MSR value.\r
1755 @param EDX Upper 32-bits of MSR value.\r
1756\r
1757 <b>Example usage</b>\r
1758 @code\r
1759 UINT64 Msr;\r
1760\r
1761 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);\r
1762 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);\r
1763 @endcode\r
c2aa191b 1764 @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.\r
bd946618
MK		 1765**/\r
1766#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10\r
1767\r
1768\r
1769/**\r
1770 Package. Uncore U-box perfmon counter MSR.\r
1771\r
1772 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)\r
1773 @param EAX Lower 32-bits of MSR value.\r
1774 @param EDX Upper 32-bits of MSR value.\r
1775\r
1776 <b>Example usage</b>\r
1777 @code\r
1778 UINT64 Msr;\r
1779\r
1780 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);\r
1781 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);\r
1782 @endcode\r
c2aa191b 1783 @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.\r
bd946618
MK		 1784**/\r
1785#define MSR_NEHALEM_U_PMON_CTR 0x00000C11\r
1786\r
1787\r
1788/**\r
1789 Package. Uncore B-box 0 perfmon local box control MSR.\r
1790\r
1791 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)\r
1792 @param EAX Lower 32-bits of MSR value.\r
1793 @param EDX Upper 32-bits of MSR value.\r
1794\r
1795 <b>Example usage</b>\r
1796 @code\r
1797 UINT64 Msr;\r
1798\r
1799 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);\r
1800 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);\r
1801 @endcode\r
c2aa191b 1802 @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 1803**/\r
1804#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20\r
1805\r
1806\r
1807/**\r
1808 Package. Uncore B-box 0 perfmon local box status MSR.\r
1809\r
1810 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)\r
1811 @param EAX Lower 32-bits of MSR value.\r
1812 @param EDX Upper 32-bits of MSR value.\r
1813\r
1814 <b>Example usage</b>\r
1815 @code\r
1816 UINT64 Msr;\r
1817\r
1818 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);\r
1819 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);\r
1820 @endcode\r
c2aa191b 1821 @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 1822**/\r
1823#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21\r
1824\r
1825\r
1826/**\r
1827 Package. Uncore B-box 0 perfmon local box overflow control MSR.\r
1828\r
1829 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)\r
1830 @param EAX Lower 32-bits of MSR value.\r
1831 @param EDX Upper 32-bits of MSR value.\r
1832\r
1833 <b>Example usage</b>\r
1834 @code\r
1835 UINT64 Msr;\r
1836\r
1837 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);\r
1838 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);\r
1839 @endcode\r
c2aa191b 1840 @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 1841**/\r
1842#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22\r
1843\r
1844\r
1845/**\r
1846 Package. Uncore B-box 0 perfmon event select MSR.\r
1847\r
1848 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)\r
1849 @param EAX Lower 32-bits of MSR value.\r
1850 @param EDX Upper 32-bits of MSR value.\r
1851\r
1852 <b>Example usage</b>\r
1853 @code\r
1854 UINT64 Msr;\r
1855\r
1856 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);\r
1857 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);\r
1858 @endcode\r
c2aa191b 1859 @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 1860**/\r
1861#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30\r
1862\r
1863\r
1864/**\r
1865 Package. Uncore B-box 0 perfmon counter MSR.\r
1866\r
1867 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)\r
1868 @param EAX Lower 32-bits of MSR value.\r
1869 @param EDX Upper 32-bits of MSR value.\r
1870\r
1871 <b>Example usage</b>\r
1872 @code\r
1873 UINT64 Msr;\r
1874\r
1875 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);\r
1876 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);\r
1877 @endcode\r
c2aa191b 1878 @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.\r
bd946618
MK		 1879**/\r
1880#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31\r
1881\r
1882\r
1883/**\r
1884 Package. Uncore B-box 0 perfmon event select MSR.\r
1885\r
1886 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)\r
1887 @param EAX Lower 32-bits of MSR value.\r
1888 @param EDX Upper 32-bits of MSR value.\r
1889\r
1890 <b>Example usage</b>\r
1891 @code\r
1892 UINT64 Msr;\r
1893\r
1894 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);\r
1895 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);\r
1896 @endcode\r
c2aa191b 1897 @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 1898**/\r
1899#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32\r
1900\r
1901\r
1902/**\r
1903 Package. Uncore B-box 0 perfmon counter MSR.\r
1904\r
1905 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)\r
1906 @param EAX Lower 32-bits of MSR value.\r
1907 @param EDX Upper 32-bits of MSR value.\r
1908\r
1909 <b>Example usage</b>\r
1910 @code\r
1911 UINT64 Msr;\r
1912\r
1913 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);\r
1914 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);\r
1915 @endcode\r
c2aa191b 1916 @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.\r
bd946618
MK		 1917**/\r
1918#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33\r
1919\r
1920\r
1921/**\r
1922 Package. Uncore B-box 0 perfmon event select MSR.\r
1923\r
1924 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)\r
1925 @param EAX Lower 32-bits of MSR value.\r
1926 @param EDX Upper 32-bits of MSR value.\r
1927\r
1928 <b>Example usage</b>\r
1929 @code\r
1930 UINT64 Msr;\r
1931\r
1932 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);\r
1933 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);\r
1934 @endcode\r
c2aa191b 1935 @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 1936**/\r
1937#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34\r
1938\r
1939\r
1940/**\r
1941 Package. Uncore B-box 0 perfmon counter MSR.\r
1942\r
1943 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)\r
1944 @param EAX Lower 32-bits of MSR value.\r
1945 @param EDX Upper 32-bits of MSR value.\r
1946\r
1947 <b>Example usage</b>\r
1948 @code\r
1949 UINT64 Msr;\r
1950\r
1951 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);\r
1952 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);\r
1953 @endcode\r
c2aa191b 1954 @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.\r
bd946618
MK		 1955**/\r
1956#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35\r
1957\r
1958\r
1959/**\r
1960 Package. Uncore B-box 0 perfmon event select MSR.\r
1961\r
1962 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)\r
1963 @param EAX Lower 32-bits of MSR value.\r
1964 @param EDX Upper 32-bits of MSR value.\r
1965\r
1966 <b>Example usage</b>\r
1967 @code\r
1968 UINT64 Msr;\r
1969\r
1970 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);\r
1971 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);\r
1972 @endcode\r
c2aa191b 1973 @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 1974**/\r
1975#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36\r
1976\r
1977\r
1978/**\r
1979 Package. Uncore B-box 0 perfmon counter MSR.\r
1980\r
1981 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)\r
1982 @param EAX Lower 32-bits of MSR value.\r
1983 @param EDX Upper 32-bits of MSR value.\r
1984\r
1985 <b>Example usage</b>\r
1986 @code\r
1987 UINT64 Msr;\r
1988\r
1989 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);\r
1990 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);\r
1991 @endcode\r
c2aa191b 1992 @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.\r
bd946618
MK		 1993**/\r
1994#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37\r
1995\r
1996\r
1997/**\r
1998 Package. Uncore S-box 0 perfmon local box control MSR.\r
1999\r
2000 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)\r
2001 @param EAX Lower 32-bits of MSR value.\r
2002 @param EDX Upper 32-bits of MSR value.\r
2003\r
2004 <b>Example usage</b>\r
2005 @code\r
2006 UINT64 Msr;\r
2007\r
2008 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);\r
2009 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);\r
2010 @endcode\r
c2aa191b 2011 @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 2012**/\r
2013#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40\r
2014\r
2015\r
2016/**\r
2017 Package. Uncore S-box 0 perfmon local box status MSR.\r
2018\r
2019 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)\r
2020 @param EAX Lower 32-bits of MSR value.\r
2021 @param EDX Upper 32-bits of MSR value.\r
2022\r
2023 <b>Example usage</b>\r
2024 @code\r
2025 UINT64 Msr;\r
2026\r
2027 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);\r
2028 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);\r
2029 @endcode\r
c2aa191b 2030 @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 2031**/\r
2032#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41\r
2033\r
2034\r
2035/**\r
2036 Package. Uncore S-box 0 perfmon local box overflow control MSR.\r
2037\r
2038 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)\r
2039 @param EAX Lower 32-bits of MSR value.\r
2040 @param EDX Upper 32-bits of MSR value.\r
2041\r
2042 <b>Example usage</b>\r
2043 @code\r
2044 UINT64 Msr;\r
2045\r
2046 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);\r
2047 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);\r
2048 @endcode\r
c2aa191b 2049 @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 2050**/\r
2051#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42\r
2052\r
2053\r
2054/**\r
2055 Package. Uncore S-box 0 perfmon event select MSR.\r
2056\r
2057 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)\r
2058 @param EAX Lower 32-bits of MSR value.\r
2059 @param EDX Upper 32-bits of MSR value.\r
2060\r
2061 <b>Example usage</b>\r
2062 @code\r
2063 UINT64 Msr;\r
2064\r
2065 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);\r
2066 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);\r
2067 @endcode\r
c2aa191b 2068 @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 2069**/\r
2070#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50\r
2071\r
2072\r
2073/**\r
2074 Package. Uncore S-box 0 perfmon counter MSR.\r
2075\r
2076 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)\r
2077 @param EAX Lower 32-bits of MSR value.\r
2078 @param EDX Upper 32-bits of MSR value.\r
2079\r
2080 <b>Example usage</b>\r
2081 @code\r
2082 UINT64 Msr;\r
2083\r
2084 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);\r
2085 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);\r
2086 @endcode\r
c2aa191b 2087 @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
bd946618
MK		 2088**/\r
2089#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51\r
2090\r
2091\r
2092/**\r
2093 Package. Uncore S-box 0 perfmon event select MSR.\r
2094\r
2095 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)\r
2096 @param EAX Lower 32-bits of MSR value.\r
2097 @param EDX Upper 32-bits of MSR value.\r
2098\r
2099 <b>Example usage</b>\r
2100 @code\r
2101 UINT64 Msr;\r
2102\r
2103 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);\r
2104 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);\r
2105 @endcode\r
c2aa191b 2106 @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 2107**/\r
2108#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52\r
2109\r
2110\r
2111/**\r
2112 Package. Uncore S-box 0 perfmon counter MSR.\r
2113\r
2114 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)\r
2115 @param EAX Lower 32-bits of MSR value.\r
2116 @param EDX Upper 32-bits of MSR value.\r
2117\r
2118 <b>Example usage</b>\r
2119 @code\r
2120 UINT64 Msr;\r
2121\r
2122 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);\r
2123 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);\r
2124 @endcode\r
c2aa191b 2125 @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
bd946618
MK		 2126**/\r
2127#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53\r
2128\r
2129\r
2130/**\r
2131 Package. Uncore S-box 0 perfmon event select MSR.\r
2132\r
2133 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)\r
2134 @param EAX Lower 32-bits of MSR value.\r
2135 @param EDX Upper 32-bits of MSR value.\r
2136\r
2137 <b>Example usage</b>\r
2138 @code\r
2139 UINT64 Msr;\r
2140\r
2141 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);\r
2142 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);\r
2143 @endcode\r
c2aa191b 2144 @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 2145**/\r
2146#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54\r
2147\r
2148\r
2149/**\r
2150 Package. Uncore S-box 0 perfmon counter MSR.\r
2151\r
2152 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)\r
2153 @param EAX Lower 32-bits of MSR value.\r
2154 @param EDX Upper 32-bits of MSR value.\r
2155\r
2156 <b>Example usage</b>\r
2157 @code\r
2158 UINT64 Msr;\r
2159\r
2160 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);\r
2161 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);\r
2162 @endcode\r
c2aa191b 2163 @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
bd946618
MK		 2164**/\r
2165#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55\r
2166\r
2167\r
2168/**\r
2169 Package. Uncore S-box 0 perfmon event select MSR.\r
2170\r
2171 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)\r
2172 @param EAX Lower 32-bits of MSR value.\r
2173 @param EDX Upper 32-bits of MSR value.\r
2174\r
2175 <b>Example usage</b>\r
2176 @code\r
2177 UINT64 Msr;\r
2178\r
2179 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);\r
2180 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);\r
2181 @endcode\r
c2aa191b 2182 @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 2183**/\r
2184#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56\r
2185\r
2186\r
2187/**\r
2188 Package. Uncore S-box 0 perfmon counter MSR.\r
2189\r
2190 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)\r
2191 @param EAX Lower 32-bits of MSR value.\r
2192 @param EDX Upper 32-bits of MSR value.\r
2193\r
2194 <b>Example usage</b>\r
2195 @code\r
2196 UINT64 Msr;\r
2197\r
2198 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);\r
2199 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);\r
2200 @endcode\r
c2aa191b 2201 @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
bd946618
MK		 2202**/\r
2203#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57\r
2204\r
2205\r
2206/**\r
2207 Package. Uncore B-box 1 perfmon local box control MSR.\r
2208\r
2209 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)\r
2210 @param EAX Lower 32-bits of MSR value.\r
2211 @param EDX Upper 32-bits of MSR value.\r
2212\r
2213 <b>Example usage</b>\r
2214 @code\r
2215 UINT64 Msr;\r
2216\r
2217 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);\r
2218 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);\r
2219 @endcode\r
c2aa191b 2220 @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 2221**/\r
2222#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60\r
2223\r
2224\r
2225/**\r
2226 Package. Uncore B-box 1 perfmon local box status MSR.\r
2227\r
2228 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)\r
2229 @param EAX Lower 32-bits of MSR value.\r
2230 @param EDX Upper 32-bits of MSR value.\r
2231\r
2232 <b>Example usage</b>\r
2233 @code\r
2234 UINT64 Msr;\r
2235\r
2236 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);\r
2237 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);\r
2238 @endcode\r
c2aa191b 2239 @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 2240**/\r
2241#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61\r
2242\r
2243\r
2244/**\r
2245 Package. Uncore B-box 1 perfmon local box overflow control MSR.\r
2246\r
2247 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)\r
2248 @param EAX Lower 32-bits of MSR value.\r
2249 @param EDX Upper 32-bits of MSR value.\r
2250\r
2251 <b>Example usage</b>\r
2252 @code\r
2253 UINT64 Msr;\r
2254\r
2255 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);\r
2256 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);\r
2257 @endcode\r
c2aa191b 2258 @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 2259**/\r
2260#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62\r
2261\r
2262\r
2263/**\r
2264 Package. Uncore B-box 1 perfmon event select MSR.\r
2265\r
2266 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)\r
2267 @param EAX Lower 32-bits of MSR value.\r
2268 @param EDX Upper 32-bits of MSR value.\r
2269\r
2270 <b>Example usage</b>\r
2271 @code\r
2272 UINT64 Msr;\r
2273\r
2274 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);\r
2275 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);\r
2276 @endcode\r
c2aa191b 2277 @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 2278**/\r
2279#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70\r
2280\r
2281\r
2282/**\r
2283 Package. Uncore B-box 1 perfmon counter MSR.\r
2284\r
2285 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)\r
2286 @param EAX Lower 32-bits of MSR value.\r
2287 @param EDX Upper 32-bits of MSR value.\r
2288\r
2289 <b>Example usage</b>\r
2290 @code\r
2291 UINT64 Msr;\r
2292\r
2293 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);\r
2294 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);\r
2295 @endcode\r
c2aa191b 2296 @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.\r
bd946618
MK		 2297**/\r
2298#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71\r
2299\r
2300\r
2301/**\r
2302 Package. Uncore B-box 1 perfmon event select MSR.\r
2303\r
2304 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)\r
2305 @param EAX Lower 32-bits of MSR value.\r
2306 @param EDX Upper 32-bits of MSR value.\r
2307\r
2308 <b>Example usage</b>\r
2309 @code\r
2310 UINT64 Msr;\r
2311\r
2312 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);\r
2313 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);\r
2314 @endcode\r
c2aa191b 2315 @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 2316**/\r
2317#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72\r
2318\r
2319\r
2320/**\r
2321 Package. Uncore B-box 1 perfmon counter MSR.\r
2322\r
2323 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)\r
2324 @param EAX Lower 32-bits of MSR value.\r
2325 @param EDX Upper 32-bits of MSR value.\r
2326\r
2327 <b>Example usage</b>\r
2328 @code\r
2329 UINT64 Msr;\r
2330\r
2331 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);\r
2332 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);\r
2333 @endcode\r
c2aa191b 2334 @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.\r
bd946618
MK		 2335**/\r
2336#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73\r
2337\r
2338\r
2339/**\r
2340 Package. Uncore B-box 1 perfmon event select MSR.\r
2341\r
2342 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)\r
2343 @param EAX Lower 32-bits of MSR value.\r
2344 @param EDX Upper 32-bits of MSR value.\r
2345\r
2346 <b>Example usage</b>\r
2347 @code\r
2348 UINT64 Msr;\r
2349\r
2350 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);\r
2351 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);\r
2352 @endcode\r
c2aa191b 2353 @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 2354**/\r
2355#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74\r
2356\r
2357\r
2358/**\r
2359 Package. Uncore B-box 1 perfmon counter MSR.\r
2360\r
2361 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)\r
2362 @param EAX Lower 32-bits of MSR value.\r
2363 @param EDX Upper 32-bits of MSR value.\r
2364\r
2365 <b>Example usage</b>\r
2366 @code\r
2367 UINT64 Msr;\r
2368\r
2369 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);\r
2370 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);\r
2371 @endcode\r
c2aa191b 2372 @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.\r
bd946618
MK		 2373**/\r
2374#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75\r
2375\r
2376\r
2377/**\r
2378 Package. Uncore B-box 1vperfmon event select MSR.\r
2379\r
2380 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)\r
2381 @param EAX Lower 32-bits of MSR value.\r
2382 @param EDX Upper 32-bits of MSR value.\r
2383\r
2384 <b>Example usage</b>\r
2385 @code\r
2386 UINT64 Msr;\r
2387\r
2388 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);\r
2389 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);\r
2390 @endcode\r
c2aa191b 2391 @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 2392**/\r
2393#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76\r
2394\r
2395\r
2396/**\r
2397 Package. Uncore B-box 1 perfmon counter MSR.\r
2398\r
2399 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)\r
2400 @param EAX Lower 32-bits of MSR value.\r
2401 @param EDX Upper 32-bits of MSR value.\r
2402\r
2403 <b>Example usage</b>\r
2404 @code\r
2405 UINT64 Msr;\r
2406\r
2407 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);\r
2408 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);\r
2409 @endcode\r
c2aa191b 2410 @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.\r
bd946618
MK		 2411**/\r
2412#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77\r
2413\r
2414\r
2415/**\r
2416 Package. Uncore W-box perfmon local box control MSR.\r
2417\r
2418 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)\r
2419 @param EAX Lower 32-bits of MSR value.\r
2420 @param EDX Upper 32-bits of MSR value.\r
2421\r
2422 <b>Example usage</b>\r
2423 @code\r
2424 UINT64 Msr;\r
2425\r
2426 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);\r
2427 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);\r
2428 @endcode\r
c2aa191b 2429 @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 2430**/\r
2431#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80\r
2432\r
2433\r
2434/**\r
2435 Package. Uncore W-box perfmon local box status MSR.\r
2436\r
2437 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)\r
2438 @param EAX Lower 32-bits of MSR value.\r
2439 @param EDX Upper 32-bits of MSR value.\r
2440\r
2441 <b>Example usage</b>\r
2442 @code\r
2443 UINT64 Msr;\r
2444\r
2445 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);\r
2446 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);\r
2447 @endcode\r
c2aa191b 2448 @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 2449**/\r
2450#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81\r
2451\r
2452\r
2453/**\r
2454 Package. Uncore W-box perfmon local box overflow control MSR.\r
2455\r
2456 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)\r
2457 @param EAX Lower 32-bits of MSR value.\r
2458 @param EDX Upper 32-bits of MSR value.\r
2459\r
2460 <b>Example usage</b>\r
2461 @code\r
2462 UINT64 Msr;\r
2463\r
2464 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);\r
2465 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);\r
2466 @endcode\r
c2aa191b 2467 @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 2468**/\r
2469#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82\r
2470\r
2471\r
2472/**\r
2473 Package. Uncore W-box perfmon event select MSR.\r
2474\r
2475 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)\r
2476 @param EAX Lower 32-bits of MSR value.\r
2477 @param EDX Upper 32-bits of MSR value.\r
2478\r
2479 <b>Example usage</b>\r
2480 @code\r
2481 UINT64 Msr;\r
2482\r
2483 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);\r
2484 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);\r
2485 @endcode\r
c2aa191b 2486 @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 2487**/\r
2488#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90\r
2489\r
2490\r
2491/**\r
2492 Package. Uncore W-box perfmon counter MSR.\r
2493\r
2494 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)\r
2495 @param EAX Lower 32-bits of MSR value.\r
2496 @param EDX Upper 32-bits of MSR value.\r
2497\r
2498 <b>Example usage</b>\r
2499 @code\r
2500 UINT64 Msr;\r
2501\r
2502 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);\r
2503 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);\r
2504 @endcode\r
c2aa191b 2505 @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.\r
bd946618
MK		 2506**/\r
2507#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91\r
2508\r
2509\r
2510/**\r
2511 Package. Uncore W-box perfmon event select MSR.\r
2512\r
2513 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)\r
2514 @param EAX Lower 32-bits of MSR value.\r
2515 @param EDX Upper 32-bits of MSR value.\r
2516\r
2517 <b>Example usage</b>\r
2518 @code\r
2519 UINT64 Msr;\r
2520\r
2521 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);\r
2522 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);\r
2523 @endcode\r
c2aa191b 2524 @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 2525**/\r
2526#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92\r
2527\r
2528\r
2529/**\r
2530 Package. Uncore W-box perfmon counter MSR.\r
2531\r
2532 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)\r
2533 @param EAX Lower 32-bits of MSR value.\r
2534 @param EDX Upper 32-bits of MSR value.\r
2535\r
2536 <b>Example usage</b>\r
2537 @code\r
2538 UINT64 Msr;\r
2539\r
2540 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);\r
2541 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);\r
2542 @endcode\r
c2aa191b 2543 @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.\r
bd946618
MK		 2544**/\r
2545#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93\r
2546\r
2547\r
2548/**\r
2549 Package. Uncore W-box perfmon event select MSR.\r
2550\r
2551 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)\r
2552 @param EAX Lower 32-bits of MSR value.\r
2553 @param EDX Upper 32-bits of MSR value.\r
2554\r
2555 <b>Example usage</b>\r
2556 @code\r
2557 UINT64 Msr;\r
2558\r
2559 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);\r
2560 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);\r
2561 @endcode\r
c2aa191b 2562 @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 2563**/\r
2564#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94\r
2565\r
2566\r
2567/**\r
2568 Package. Uncore W-box perfmon counter MSR.\r
2569\r
2570 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)\r
2571 @param EAX Lower 32-bits of MSR value.\r
2572 @param EDX Upper 32-bits of MSR value.\r
2573\r
2574 <b>Example usage</b>\r
2575 @code\r
2576 UINT64 Msr;\r
2577\r
2578 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);\r
2579 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);\r
2580 @endcode\r
c2aa191b 2581 @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.\r
bd946618
MK		 2582**/\r
2583#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95\r
2584\r
2585\r
2586/**\r
2587 Package. Uncore W-box perfmon event select MSR.\r
2588\r
2589 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)\r
2590 @param EAX Lower 32-bits of MSR value.\r
2591 @param EDX Upper 32-bits of MSR value.\r
2592\r
2593 <b>Example usage</b>\r
2594 @code\r
2595 UINT64 Msr;\r
2596\r
2597 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);\r
2598 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);\r
2599 @endcode\r
c2aa191b 2600 @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 2601**/\r
2602#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96\r
2603\r
2604\r
2605/**\r
2606 Package. Uncore W-box perfmon counter MSR.\r
2607\r
2608 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)\r
2609 @param EAX Lower 32-bits of MSR value.\r
2610 @param EDX Upper 32-bits of MSR value.\r
2611\r
2612 <b>Example usage</b>\r
2613 @code\r
2614 UINT64 Msr;\r
2615\r
2616 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);\r
2617 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);\r
2618 @endcode\r
c2aa191b 2619 @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.\r
bd946618
MK		 2620**/\r
2621#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97\r
2622\r
2623\r
2624/**\r
2625 Package. Uncore M-box 0 perfmon local box control MSR.\r
2626\r
2627 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)\r
2628 @param EAX Lower 32-bits of MSR value.\r
2629 @param EDX Upper 32-bits of MSR value.\r
2630\r
2631 <b>Example usage</b>\r
2632 @code\r
2633 UINT64 Msr;\r
2634\r
2635 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);\r
2636 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);\r
2637 @endcode\r
c2aa191b 2638 @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 2639**/\r
2640#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0\r
2641\r
2642\r
2643/**\r
2644 Package. Uncore M-box 0 perfmon local box status MSR.\r
2645\r
2646 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)\r
2647 @param EAX Lower 32-bits of MSR value.\r
2648 @param EDX Upper 32-bits of MSR value.\r
2649\r
2650 <b>Example usage</b>\r
2651 @code\r
2652 UINT64 Msr;\r
2653\r
2654 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);\r
2655 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);\r
2656 @endcode\r
c2aa191b 2657 @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 2658**/\r
2659#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1\r
2660\r
2661\r
2662/**\r
2663 Package. Uncore M-box 0 perfmon local box overflow control MSR.\r
2664\r
2665 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)\r
2666 @param EAX Lower 32-bits of MSR value.\r
2667 @param EDX Upper 32-bits of MSR value.\r
2668\r
2669 <b>Example usage</b>\r
2670 @code\r
2671 UINT64 Msr;\r
2672\r
2673 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);\r
2674 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);\r
2675 @endcode\r
c2aa191b 2676 @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 2677**/\r
2678#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2\r
2679\r
2680\r
2681/**\r
2682 Package. Uncore M-box 0 perfmon time stamp unit select MSR.\r
2683\r
2684 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)\r
2685 @param EAX Lower 32-bits of MSR value.\r
2686 @param EDX Upper 32-bits of MSR value.\r
2687\r
2688 <b>Example usage</b>\r
2689 @code\r
2690 UINT64 Msr;\r
2691\r
2692 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);\r
2693 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);\r
2694 @endcode\r
c2aa191b 2695 @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.\r
bd946618
MK		 2696**/\r
2697#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4\r
2698\r
2699\r
2700/**\r
2701 Package. Uncore M-box 0 perfmon DSP unit select MSR.\r
2702\r
2703 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)\r
2704 @param EAX Lower 32-bits of MSR value.\r
2705 @param EDX Upper 32-bits of MSR value.\r
2706\r
2707 <b>Example usage</b>\r
2708 @code\r
2709 UINT64 Msr;\r
2710\r
2711 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);\r
2712 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);\r
2713 @endcode\r
c2aa191b 2714 @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.\r
bd946618
MK		 2715**/\r
2716#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5\r
2717\r
2718\r
2719/**\r
2720 Package. Uncore M-box 0 perfmon ISS unit select MSR.\r
2721\r
2722 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)\r
2723 @param EAX Lower 32-bits of MSR value.\r
2724 @param EDX Upper 32-bits of MSR value.\r
2725\r
2726 <b>Example usage</b>\r
2727 @code\r
2728 UINT64 Msr;\r
2729\r
2730 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);\r
2731 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);\r
2732 @endcode\r
c2aa191b 2733 @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.\r
bd946618
MK		 2734**/\r
2735#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6\r
2736\r
2737\r
2738/**\r
2739 Package. Uncore M-box 0 perfmon MAP unit select MSR.\r
2740\r
2741 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)\r
2742 @param EAX Lower 32-bits of MSR value.\r
2743 @param EDX Upper 32-bits of MSR value.\r
2744\r
2745 <b>Example usage</b>\r
2746 @code\r
2747 UINT64 Msr;\r
2748\r
2749 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);\r
2750 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);\r
2751 @endcode\r
c2aa191b 2752 @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.\r
bd946618
MK		 2753**/\r
2754#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7\r
2755\r
2756\r
2757/**\r
2758 Package. Uncore M-box 0 perfmon MIC THR select MSR.\r
2759\r
2760 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)\r
2761 @param EAX Lower 32-bits of MSR value.\r
2762 @param EDX Upper 32-bits of MSR value.\r
2763\r
2764 <b>Example usage</b>\r
2765 @code\r
2766 UINT64 Msr;\r
2767\r
2768 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);\r
2769 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);\r
2770 @endcode\r
c2aa191b 2771 @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.\r
bd946618
MK		 2772**/\r
2773#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8\r
2774\r
2775\r
2776/**\r
2777 Package. Uncore M-box 0 perfmon PGT unit select MSR.\r
2778\r
2779 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)\r
2780 @param EAX Lower 32-bits of MSR value.\r
2781 @param EDX Upper 32-bits of MSR value.\r
2782\r
2783 <b>Example usage</b>\r
2784 @code\r
2785 UINT64 Msr;\r
2786\r
2787 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);\r
2788 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);\r
2789 @endcode\r
c2aa191b 2790 @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.\r
bd946618
MK		 2791**/\r
2792#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9\r
2793\r
2794\r
2795/**\r
2796 Package. Uncore M-box 0 perfmon PLD unit select MSR.\r
2797\r
2798 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)\r
2799 @param EAX Lower 32-bits of MSR value.\r
2800 @param EDX Upper 32-bits of MSR value.\r
2801\r
2802 <b>Example usage</b>\r
2803 @code\r
2804 UINT64 Msr;\r
2805\r
2806 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);\r
2807 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);\r
2808 @endcode\r
c2aa191b 2809 @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.\r
bd946618
MK		 2810**/\r
2811#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA\r
2812\r
2813\r
2814/**\r
2815 Package. Uncore M-box 0 perfmon ZDP unit select MSR.\r
2816\r
2817 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)\r
2818 @param EAX Lower 32-bits of MSR value.\r
2819 @param EDX Upper 32-bits of MSR value.\r
2820\r
2821 <b>Example usage</b>\r
2822 @code\r
2823 UINT64 Msr;\r
2824\r
2825 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);\r
2826 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);\r
2827 @endcode\r
c2aa191b 2828 @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.\r
bd946618
MK		 2829**/\r
2830#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB\r
2831\r
2832\r
2833/**\r
2834 Package. Uncore M-box 0 perfmon event select MSR.\r
2835\r
2836 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)\r
2837 @param EAX Lower 32-bits of MSR value.\r
2838 @param EDX Upper 32-bits of MSR value.\r
2839\r
2840 <b>Example usage</b>\r
2841 @code\r
2842 UINT64 Msr;\r
2843\r
2844 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);\r
2845 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);\r
2846 @endcode\r
c2aa191b 2847 @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 2848**/\r
2849#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0\r
2850\r
2851\r
2852/**\r
2853 Package. Uncore M-box 0 perfmon counter MSR.\r
2854\r
2855 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)\r
2856 @param EAX Lower 32-bits of MSR value.\r
2857 @param EDX Upper 32-bits of MSR value.\r
2858\r
2859 <b>Example usage</b>\r
2860 @code\r
2861 UINT64 Msr;\r
2862\r
2863 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);\r
2864 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);\r
2865 @endcode\r
c2aa191b 2866 @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.\r
bd946618
MK		 2867**/\r
2868#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1\r
2869\r
2870\r
2871/**\r
2872 Package. Uncore M-box 0 perfmon event select MSR.\r
2873\r
2874 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)\r
2875 @param EAX Lower 32-bits of MSR value.\r
2876 @param EDX Upper 32-bits of MSR value.\r
2877\r
2878 <b>Example usage</b>\r
2879 @code\r
2880 UINT64 Msr;\r
2881\r
2882 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);\r
2883 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);\r
2884 @endcode\r
c2aa191b 2885 @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 2886**/\r
2887#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2\r
2888\r
2889\r
2890/**\r
2891 Package. Uncore M-box 0 perfmon counter MSR.\r
2892\r
2893 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)\r
2894 @param EAX Lower 32-bits of MSR value.\r
2895 @param EDX Upper 32-bits of MSR value.\r
2896\r
2897 <b>Example usage</b>\r
2898 @code\r
2899 UINT64 Msr;\r
2900\r
2901 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);\r
2902 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);\r
2903 @endcode\r
c2aa191b 2904 @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.\r
bd946618
MK		 2905**/\r
2906#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3\r
2907\r
2908\r
2909/**\r
2910 Package. Uncore M-box 0 perfmon event select MSR.\r
2911\r
2912 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)\r
2913 @param EAX Lower 32-bits of MSR value.\r
2914 @param EDX Upper 32-bits of MSR value.\r
2915\r
2916 <b>Example usage</b>\r
2917 @code\r
2918 UINT64 Msr;\r
2919\r
2920 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);\r
2921 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);\r
2922 @endcode\r
c2aa191b 2923 @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 2924**/\r
2925#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4\r
2926\r
2927\r
2928/**\r
2929 Package. Uncore M-box 0 perfmon counter MSR.\r
2930\r
2931 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)\r
2932 @param EAX Lower 32-bits of MSR value.\r
2933 @param EDX Upper 32-bits of MSR value.\r
2934\r
2935 <b>Example usage</b>\r
2936 @code\r
2937 UINT64 Msr;\r
2938\r
2939 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);\r
2940 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);\r
2941 @endcode\r
c2aa191b 2942 @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.\r
bd946618
MK		 2943**/\r
2944#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5\r
2945\r
2946\r
2947/**\r
2948 Package. Uncore M-box 0 perfmon event select MSR.\r
2949\r
2950 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)\r
2951 @param EAX Lower 32-bits of MSR value.\r
2952 @param EDX Upper 32-bits of MSR value.\r
2953\r
2954 <b>Example usage</b>\r
2955 @code\r
2956 UINT64 Msr;\r
2957\r
2958 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);\r
2959 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);\r
2960 @endcode\r
c2aa191b 2961 @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 2962**/\r
2963#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6\r
2964\r
2965\r
2966/**\r
2967 Package. Uncore M-box 0 perfmon counter MSR.\r
2968\r
2969 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)\r
2970 @param EAX Lower 32-bits of MSR value.\r
2971 @param EDX Upper 32-bits of MSR value.\r
2972\r
2973 <b>Example usage</b>\r
2974 @code\r
2975 UINT64 Msr;\r
2976\r
2977 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);\r
2978 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);\r
2979 @endcode\r
c2aa191b 2980 @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.\r
bd946618
MK		 2981**/\r
2982#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7\r
2983\r
2984\r
2985/**\r
2986 Package. Uncore M-box 0 perfmon event select MSR.\r
2987\r
2988 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)\r
2989 @param EAX Lower 32-bits of MSR value.\r
2990 @param EDX Upper 32-bits of MSR value.\r
2991\r
2992 <b>Example usage</b>\r
2993 @code\r
2994 UINT64 Msr;\r
2995\r
2996 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);\r
2997 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);\r
2998 @endcode\r
c2aa191b 2999 @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 3000**/\r
3001#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8\r
3002\r
3003\r
3004/**\r
3005 Package. Uncore M-box 0 perfmon counter MSR.\r
3006\r
3007 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)\r
3008 @param EAX Lower 32-bits of MSR value.\r
3009 @param EDX Upper 32-bits of MSR value.\r
3010\r
3011 <b>Example usage</b>\r
3012 @code\r
3013 UINT64 Msr;\r
3014\r
3015 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);\r
3016 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);\r
3017 @endcode\r
c2aa191b 3018 @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.\r
bd946618
MK		 3019**/\r
3020#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9\r
3021\r
3022\r
3023/**\r
3024 Package. Uncore M-box 0 perfmon event select MSR.\r
3025\r
3026 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)\r
3027 @param EAX Lower 32-bits of MSR value.\r
3028 @param EDX Upper 32-bits of MSR value.\r
3029\r
3030 <b>Example usage</b>\r
3031 @code\r
3032 UINT64 Msr;\r
3033\r
3034 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);\r
3035 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);\r
3036 @endcode\r
c2aa191b 3037 @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 3038**/\r
3039#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA\r
3040\r
3041\r
3042/**\r
3043 Package. Uncore M-box 0 perfmon counter MSR.\r
3044\r
3045 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)\r
3046 @param EAX Lower 32-bits of MSR value.\r
3047 @param EDX Upper 32-bits of MSR value.\r
3048\r
3049 <b>Example usage</b>\r
3050 @code\r
3051 UINT64 Msr;\r
3052\r
3053 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);\r
3054 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);\r
3055 @endcode\r
c2aa191b 3056 @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.\r
bd946618
MK		 3057**/\r
3058#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB\r
3059\r
3060\r
3061/**\r
3062 Package. Uncore S-box 1 perfmon local box control MSR.\r
3063\r
3064 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)\r
3065 @param EAX Lower 32-bits of MSR value.\r
3066 @param EDX Upper 32-bits of MSR value.\r
3067\r
3068 <b>Example usage</b>\r
3069 @code\r
3070 UINT64 Msr;\r
3071\r
3072 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);\r
3073 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);\r
3074 @endcode\r
c2aa191b 3075 @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 3076**/\r
3077#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0\r
3078\r
3079\r
3080/**\r
3081 Package. Uncore S-box 1 perfmon local box status MSR.\r
3082\r
3083 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)\r
3084 @param EAX Lower 32-bits of MSR value.\r
3085 @param EDX Upper 32-bits of MSR value.\r
3086\r
3087 <b>Example usage</b>\r
3088 @code\r
3089 UINT64 Msr;\r
3090\r
3091 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);\r
3092 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);\r
3093 @endcode\r
c2aa191b 3094 @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 3095**/\r
3096#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1\r
3097\r
3098\r
3099/**\r
3100 Package. Uncore S-box 1 perfmon local box overflow control MSR.\r
3101\r
3102 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)\r
3103 @param EAX Lower 32-bits of MSR value.\r
3104 @param EDX Upper 32-bits of MSR value.\r
3105\r
3106 <b>Example usage</b>\r
3107 @code\r
3108 UINT64 Msr;\r
3109\r
3110 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);\r
3111 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);\r
3112 @endcode\r
c2aa191b 3113 @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 3114**/\r
3115#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2\r
3116\r
3117\r
3118/**\r
3119 Package. Uncore S-box 1 perfmon event select MSR.\r
3120\r
3121 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)\r
3122 @param EAX Lower 32-bits of MSR value.\r
3123 @param EDX Upper 32-bits of MSR value.\r
3124\r
3125 <b>Example usage</b>\r
3126 @code\r
3127 UINT64 Msr;\r
3128\r
3129 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);\r
3130 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);\r
3131 @endcode\r
c2aa191b 3132 @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 3133**/\r
3134#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0\r
3135\r
3136\r
3137/**\r
3138 Package. Uncore S-box 1 perfmon counter MSR.\r
3139\r
3140 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)\r
3141 @param EAX Lower 32-bits of MSR value.\r
3142 @param EDX Upper 32-bits of MSR value.\r
3143\r
3144 <b>Example usage</b>\r
3145 @code\r
3146 UINT64 Msr;\r
3147\r
3148 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);\r
3149 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);\r
3150 @endcode\r
c2aa191b 3151 @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
bd946618
MK		 3152**/\r
3153#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1\r
3154\r
3155\r
3156/**\r
3157 Package. Uncore S-box 1 perfmon event select MSR.\r
3158\r
3159 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)\r
3160 @param EAX Lower 32-bits of MSR value.\r
3161 @param EDX Upper 32-bits of MSR value.\r
3162\r
3163 <b>Example usage</b>\r
3164 @code\r
3165 UINT64 Msr;\r
3166\r
3167 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);\r
3168 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);\r
3169 @endcode\r
c2aa191b 3170 @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 3171**/\r
3172#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2\r
3173\r
3174\r
3175/**\r
3176 Package. Uncore S-box 1 perfmon counter MSR.\r
3177\r
3178 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)\r
3179 @param EAX Lower 32-bits of MSR value.\r
3180 @param EDX Upper 32-bits of MSR value.\r
3181\r
3182 <b>Example usage</b>\r
3183 @code\r
3184 UINT64 Msr;\r
3185\r
3186 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);\r
3187 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);\r
3188 @endcode\r
c2aa191b 3189 @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
bd946618
MK		 3190**/\r
3191#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3\r
3192\r
3193\r
3194/**\r
3195 Package. Uncore S-box 1 perfmon event select MSR.\r
3196\r
3197 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)\r
3198 @param EAX Lower 32-bits of MSR value.\r
3199 @param EDX Upper 32-bits of MSR value.\r
3200\r
3201 <b>Example usage</b>\r
3202 @code\r
3203 UINT64 Msr;\r
3204\r
3205 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);\r
3206 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);\r
3207 @endcode\r
c2aa191b 3208 @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 3209**/\r
3210#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4\r
3211\r
3212\r
3213/**\r
3214 Package. Uncore S-box 1 perfmon counter MSR.\r
3215\r
3216 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)\r
3217 @param EAX Lower 32-bits of MSR value.\r
3218 @param EDX Upper 32-bits of MSR value.\r
3219\r
3220 <b>Example usage</b>\r
3221 @code\r
3222 UINT64 Msr;\r
3223\r
3224 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);\r
3225 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);\r
3226 @endcode\r
c2aa191b 3227 @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
bd946618
MK		 3228**/\r
3229#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5\r
3230\r
3231\r
3232/**\r
3233 Package. Uncore S-box 1 perfmon event select MSR.\r
3234\r
3235 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)\r
3236 @param EAX Lower 32-bits of MSR value.\r
3237 @param EDX Upper 32-bits of MSR value.\r
3238\r
3239 <b>Example usage</b>\r
3240 @code\r
3241 UINT64 Msr;\r
3242\r
3243 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);\r
3244 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);\r
3245 @endcode\r
c2aa191b 3246 @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 3247**/\r
3248#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6\r
3249\r
3250\r
3251/**\r
3252 Package. Uncore S-box 1 perfmon counter MSR.\r
3253\r
3254 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)\r
3255 @param EAX Lower 32-bits of MSR value.\r
3256 @param EDX Upper 32-bits of MSR value.\r
3257\r
3258 <b>Example usage</b>\r
3259 @code\r
3260 UINT64 Msr;\r
3261\r
3262 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);\r
3263 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);\r
3264 @endcode\r
c2aa191b 3265 @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
bd946618
MK		 3266**/\r
3267#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7\r
3268\r
3269\r
3270/**\r
3271 Package. Uncore M-box 1 perfmon local box control MSR.\r
3272\r
3273 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)\r
3274 @param EAX Lower 32-bits of MSR value.\r
3275 @param EDX Upper 32-bits of MSR value.\r
3276\r
3277 <b>Example usage</b>\r
3278 @code\r
3279 UINT64 Msr;\r
3280\r
3281 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);\r
3282 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);\r
3283 @endcode\r
c2aa191b 3284 @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 3285**/\r
3286#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0\r
3287\r
3288\r
3289/**\r
3290 Package. Uncore M-box 1 perfmon local box status MSR.\r
3291\r
3292 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)\r
3293 @param EAX Lower 32-bits of MSR value.\r
3294 @param EDX Upper 32-bits of MSR value.\r
3295\r
3296 <b>Example usage</b>\r
3297 @code\r
3298 UINT64 Msr;\r
3299\r
3300 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);\r
3301 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);\r
3302 @endcode\r
c2aa191b 3303 @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 3304**/\r
3305#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1\r
3306\r
3307\r
3308/**\r
3309 Package. Uncore M-box 1 perfmon local box overflow control MSR.\r
3310\r
3311 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)\r
3312 @param EAX Lower 32-bits of MSR value.\r
3313 @param EDX Upper 32-bits of MSR value.\r
3314\r
3315 <b>Example usage</b>\r
3316 @code\r
3317 UINT64 Msr;\r
3318\r
3319 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);\r
3320 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);\r
3321 @endcode\r
c2aa191b 3322 @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 3323**/\r
3324#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2\r
3325\r
3326\r
3327/**\r
3328 Package. Uncore M-box 1 perfmon time stamp unit select MSR.\r
3329\r
3330 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)\r
3331 @param EAX Lower 32-bits of MSR value.\r
3332 @param EDX Upper 32-bits of MSR value.\r
3333\r
3334 <b>Example usage</b>\r
3335 @code\r
3336 UINT64 Msr;\r
3337\r
3338 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);\r
3339 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);\r
3340 @endcode\r
c2aa191b 3341 @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.\r
bd946618
MK		 3342**/\r
3343#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4\r
3344\r
3345\r
3346/**\r
3347 Package. Uncore M-box 1 perfmon DSP unit select MSR.\r
3348\r
3349 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)\r
3350 @param EAX Lower 32-bits of MSR value.\r
3351 @param EDX Upper 32-bits of MSR value.\r
3352\r
3353 <b>Example usage</b>\r
3354 @code\r
3355 UINT64 Msr;\r
3356\r
3357 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);\r
3358 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);\r
3359 @endcode\r
c2aa191b 3360 @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.\r
bd946618
MK		 3361**/\r
3362#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5\r
3363\r
3364\r
3365/**\r
3366 Package. Uncore M-box 1 perfmon ISS unit select MSR.\r
3367\r
3368 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)\r
3369 @param EAX Lower 32-bits of MSR value.\r
3370 @param EDX Upper 32-bits of MSR value.\r
3371\r
3372 <b>Example usage</b>\r
3373 @code\r
3374 UINT64 Msr;\r
3375\r
3376 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);\r
3377 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);\r
3378 @endcode\r
c2aa191b 3379 @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.\r
bd946618
MK		 3380**/\r
3381#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6\r
3382\r
3383\r
3384/**\r
3385 Package. Uncore M-box 1 perfmon MAP unit select MSR.\r
3386\r
3387 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)\r
3388 @param EAX Lower 32-bits of MSR value.\r
3389 @param EDX Upper 32-bits of MSR value.\r
3390\r
3391 <b>Example usage</b>\r
3392 @code\r
3393 UINT64 Msr;\r
3394\r
3395 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);\r
3396 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);\r
3397 @endcode\r
c2aa191b 3398 @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.\r
bd946618
MK		 3399**/\r
3400#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7\r
3401\r
3402\r
3403/**\r
3404 Package. Uncore M-box 1 perfmon MIC THR select MSR.\r
3405\r
3406 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)\r
3407 @param EAX Lower 32-bits of MSR value.\r
3408 @param EDX Upper 32-bits of MSR value.\r
3409\r
3410 <b>Example usage</b>\r
3411 @code\r
3412 UINT64 Msr;\r
3413\r
3414 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);\r
3415 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);\r
3416 @endcode\r
c2aa191b 3417 @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.\r
bd946618
MK		 3418**/\r
3419#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8\r
3420\r
3421\r
3422/**\r
3423 Package. Uncore M-box 1 perfmon PGT unit select MSR.\r
3424\r
3425 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)\r
3426 @param EAX Lower 32-bits of MSR value.\r
3427 @param EDX Upper 32-bits of MSR value.\r
3428\r
3429 <b>Example usage</b>\r
3430 @code\r
3431 UINT64 Msr;\r
3432\r
3433 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);\r
3434 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);\r
3435 @endcode\r
c2aa191b 3436 @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.\r
bd946618
MK		 3437**/\r
3438#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9\r
3439\r
3440\r
3441/**\r
3442 Package. Uncore M-box 1 perfmon PLD unit select MSR.\r
3443\r
3444 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)\r
3445 @param EAX Lower 32-bits of MSR value.\r
3446 @param EDX Upper 32-bits of MSR value.\r
3447\r
3448 <b>Example usage</b>\r
3449 @code\r
3450 UINT64 Msr;\r
3451\r
3452 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);\r
3453 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);\r
3454 @endcode\r
c2aa191b 3455 @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.\r
bd946618
MK		 3456**/\r
3457#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA\r
3458\r
3459\r
3460/**\r
3461 Package. Uncore M-box 1 perfmon ZDP unit select MSR.\r
3462\r
3463 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)\r
3464 @param EAX Lower 32-bits of MSR value.\r
3465 @param EDX Upper 32-bits of MSR value.\r
3466\r
3467 <b>Example usage</b>\r
3468 @code\r
3469 UINT64 Msr;\r
3470\r
3471 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);\r
3472 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);\r
3473 @endcode\r
c2aa191b 3474 @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.\r
bd946618
MK		 3475**/\r
3476#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB\r
3477\r
3478\r
3479/**\r
3480 Package. Uncore M-box 1 perfmon event select MSR.\r
3481\r
3482 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)\r
3483 @param EAX Lower 32-bits of MSR value.\r
3484 @param EDX Upper 32-bits of MSR value.\r
3485\r
3486 <b>Example usage</b>\r
3487 @code\r
3488 UINT64 Msr;\r
3489\r
3490 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);\r
3491 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);\r
3492 @endcode\r
c2aa191b 3493 @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 3494**/\r
3495#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0\r
3496\r
3497\r
3498/**\r
3499 Package. Uncore M-box 1 perfmon counter MSR.\r
3500\r
3501 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)\r
3502 @param EAX Lower 32-bits of MSR value.\r
3503 @param EDX Upper 32-bits of MSR value.\r
3504\r
3505 <b>Example usage</b>\r
3506 @code\r
3507 UINT64 Msr;\r
3508\r
3509 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);\r
3510 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);\r
3511 @endcode\r
c2aa191b 3512 @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.\r
bd946618
MK		 3513**/\r
3514#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1\r
3515\r
3516\r
3517/**\r
3518 Package. Uncore M-box 1 perfmon event select MSR.\r
3519\r
3520 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)\r
3521 @param EAX Lower 32-bits of MSR value.\r
3522 @param EDX Upper 32-bits of MSR value.\r
3523\r
3524 <b>Example usage</b>\r
3525 @code\r
3526 UINT64 Msr;\r
3527\r
3528 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);\r
3529 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);\r
3530 @endcode\r
c2aa191b 3531 @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 3532**/\r
3533#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2\r
3534\r
3535\r
3536/**\r
3537 Package. Uncore M-box 1 perfmon counter MSR.\r
3538\r
3539 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)\r
3540 @param EAX Lower 32-bits of MSR value.\r
3541 @param EDX Upper 32-bits of MSR value.\r
3542\r
3543 <b>Example usage</b>\r
3544 @code\r
3545 UINT64 Msr;\r
3546\r
3547 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);\r
3548 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);\r
3549 @endcode\r
c2aa191b 3550 @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.\r
bd946618
MK		 3551**/\r
3552#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3\r
3553\r
3554\r
3555/**\r
3556 Package. Uncore M-box 1 perfmon event select MSR.\r
3557\r
3558 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)\r
3559 @param EAX Lower 32-bits of MSR value.\r
3560 @param EDX Upper 32-bits of MSR value.\r
3561\r
3562 <b>Example usage</b>\r
3563 @code\r
3564 UINT64 Msr;\r
3565\r
3566 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);\r
3567 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);\r
3568 @endcode\r
c2aa191b 3569 @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 3570**/\r
3571#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4\r
3572\r
3573\r
3574/**\r
3575 Package. Uncore M-box 1 perfmon counter MSR.\r
3576\r
3577 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)\r
3578 @param EAX Lower 32-bits of MSR value.\r
3579 @param EDX Upper 32-bits of MSR value.\r
3580\r
3581 <b>Example usage</b>\r
3582 @code\r
3583 UINT64 Msr;\r
3584\r
3585 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);\r
3586 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);\r
3587 @endcode\r
c2aa191b 3588 @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.\r
bd946618
MK		 3589**/\r
3590#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5\r
3591\r
3592\r
3593/**\r
3594 Package. Uncore M-box 1 perfmon event select MSR.\r
3595\r
3596 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)\r
3597 @param EAX Lower 32-bits of MSR value.\r
3598 @param EDX Upper 32-bits of MSR value.\r
3599\r
3600 <b>Example usage</b>\r
3601 @code\r
3602 UINT64 Msr;\r
3603\r
3604 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);\r
3605 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);\r
3606 @endcode\r
c2aa191b 3607 @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 3608**/\r
3609#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6\r
3610\r
3611\r
3612/**\r
3613 Package. Uncore M-box 1 perfmon counter MSR.\r
3614\r
3615 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)\r
3616 @param EAX Lower 32-bits of MSR value.\r
3617 @param EDX Upper 32-bits of MSR value.\r
3618\r
3619 <b>Example usage</b>\r
3620 @code\r
3621 UINT64 Msr;\r
3622\r
3623 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);\r
3624 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);\r
3625 @endcode\r
c2aa191b 3626 @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.\r
bd946618
MK		 3627**/\r
3628#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7\r
3629\r
3630\r
3631/**\r
3632 Package. Uncore M-box 1 perfmon event select MSR.\r
3633\r
3634 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)\r
3635 @param EAX Lower 32-bits of MSR value.\r
3636 @param EDX Upper 32-bits of MSR value.\r
3637\r
3638 <b>Example usage</b>\r
3639 @code\r
3640 UINT64 Msr;\r
3641\r
3642 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);\r
3643 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);\r
3644 @endcode\r
c2aa191b 3645 @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 3646**/\r
3647#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8\r
3648\r
3649\r
3650/**\r
3651 Package. Uncore M-box 1 perfmon counter MSR.\r
3652\r
3653 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)\r
3654 @param EAX Lower 32-bits of MSR value.\r
3655 @param EDX Upper 32-bits of MSR value.\r
3656\r
3657 <b>Example usage</b>\r
3658 @code\r
3659 UINT64 Msr;\r
3660\r
3661 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);\r
3662 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);\r
3663 @endcode\r
c2aa191b 3664 @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.\r
bd946618
MK		 3665**/\r
3666#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9\r
3667\r
3668\r
3669/**\r
3670 Package. Uncore M-box 1 perfmon event select MSR.\r
3671\r
3672 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)\r
3673 @param EAX Lower 32-bits of MSR value.\r
3674 @param EDX Upper 32-bits of MSR value.\r
3675\r
3676 <b>Example usage</b>\r
3677 @code\r
3678 UINT64 Msr;\r
3679\r
3680 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);\r
3681 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);\r
3682 @endcode\r
c2aa191b 3683 @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 3684**/\r
3685#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA\r
3686\r
3687\r
3688/**\r
3689 Package. Uncore M-box 1 perfmon counter MSR.\r
3690\r
3691 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)\r
3692 @param EAX Lower 32-bits of MSR value.\r
3693 @param EDX Upper 32-bits of MSR value.\r
3694\r
3695 <b>Example usage</b>\r
3696 @code\r
3697 UINT64 Msr;\r
3698\r
3699 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);\r
3700 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);\r
3701 @endcode\r
c2aa191b 3702 @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.\r
bd946618
MK		 3703**/\r
3704#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB\r
3705\r
3706\r
3707/**\r
3708 Package. Uncore C-box 0 perfmon local box control MSR.\r
3709\r
3710 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)\r
3711 @param EAX Lower 32-bits of MSR value.\r
3712 @param EDX Upper 32-bits of MSR value.\r
3713\r
3714 <b>Example usage</b>\r
3715 @code\r
3716 UINT64 Msr;\r
3717\r
3718 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);\r
3719 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);\r
3720 @endcode\r
c2aa191b 3721 @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 3722**/\r
3723#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00\r
3724\r
3725\r
3726/**\r
3727 Package. Uncore C-box 0 perfmon local box status MSR.\r
3728\r
3729 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)\r
3730 @param EAX Lower 32-bits of MSR value.\r
3731 @param EDX Upper 32-bits of MSR value.\r
3732\r
3733 <b>Example usage</b>\r
3734 @code\r
3735 UINT64 Msr;\r
3736\r
3737 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);\r
3738 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);\r
3739 @endcode\r
c2aa191b 3740 @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 3741**/\r
3742#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01\r
3743\r
3744\r
3745/**\r
3746 Package. Uncore C-box 0 perfmon local box overflow control MSR.\r
3747\r
3748 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)\r
3749 @param EAX Lower 32-bits of MSR value.\r
3750 @param EDX Upper 32-bits of MSR value.\r
3751\r
3752 <b>Example usage</b>\r
3753 @code\r
3754 UINT64 Msr;\r
3755\r
3756 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);\r
3757 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);\r
3758 @endcode\r
c2aa191b 3759 @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 3760**/\r
3761#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02\r
3762\r
3763\r
3764/**\r
3765 Package. Uncore C-box 0 perfmon event select MSR.\r
3766\r
3767 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)\r
3768 @param EAX Lower 32-bits of MSR value.\r
3769 @param EDX Upper 32-bits of MSR value.\r
3770\r
3771 <b>Example usage</b>\r
3772 @code\r
3773 UINT64 Msr;\r
3774\r
3775 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);\r
3776 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);\r
3777 @endcode\r
c2aa191b 3778 @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 3779**/\r
3780#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10\r
3781\r
3782\r
3783/**\r
3784 Package. Uncore C-box 0 perfmon counter MSR.\r
3785\r
3786 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)\r
3787 @param EAX Lower 32-bits of MSR value.\r
3788 @param EDX Upper 32-bits of MSR value.\r
3789\r
3790 <b>Example usage</b>\r
3791 @code\r
3792 UINT64 Msr;\r
3793\r
3794 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);\r
3795 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);\r
3796 @endcode\r
c2aa191b 3797 @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
bd946618
MK		 3798**/\r
3799#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11\r
3800\r
3801\r
3802/**\r
3803 Package. Uncore C-box 0 perfmon event select MSR.\r
3804\r
3805 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)\r
3806 @param EAX Lower 32-bits of MSR value.\r
3807 @param EDX Upper 32-bits of MSR value.\r
3808\r
3809 <b>Example usage</b>\r
3810 @code\r
3811 UINT64 Msr;\r
3812\r
3813 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);\r
3814 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);\r
3815 @endcode\r
c2aa191b 3816 @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 3817**/\r
3818#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12\r
3819\r
3820\r
3821/**\r
3822 Package. Uncore C-box 0 perfmon counter MSR.\r
3823\r
3824 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)\r
3825 @param EAX Lower 32-bits of MSR value.\r
3826 @param EDX Upper 32-bits of MSR value.\r
3827\r
3828 <b>Example usage</b>\r
3829 @code\r
3830 UINT64 Msr;\r
3831\r
3832 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);\r
3833 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);\r
3834 @endcode\r
c2aa191b 3835 @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
bd946618
MK		 3836**/\r
3837#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13\r
3838\r
3839\r
3840/**\r
3841 Package. Uncore C-box 0 perfmon event select MSR.\r
3842\r
3843 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)\r
3844 @param EAX Lower 32-bits of MSR value.\r
3845 @param EDX Upper 32-bits of MSR value.\r
3846\r
3847 <b>Example usage</b>\r
3848 @code\r
3849 UINT64 Msr;\r
3850\r
3851 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);\r
3852 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);\r
3853 @endcode\r
c2aa191b 3854 @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 3855**/\r
3856#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14\r
3857\r
3858\r
3859/**\r
3860 Package. Uncore C-box 0 perfmon counter MSR.\r
3861\r
3862 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)\r
3863 @param EAX Lower 32-bits of MSR value.\r
3864 @param EDX Upper 32-bits of MSR value.\r
3865\r
3866 <b>Example usage</b>\r
3867 @code\r
3868 UINT64 Msr;\r
3869\r
3870 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);\r
3871 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);\r
3872 @endcode\r
c2aa191b 3873 @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
bd946618
MK		 3874**/\r
3875#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15\r
3876\r
3877\r
3878/**\r
3879 Package. Uncore C-box 0 perfmon event select MSR.\r
3880\r
3881 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)\r
3882 @param EAX Lower 32-bits of MSR value.\r
3883 @param EDX Upper 32-bits of MSR value.\r
3884\r
3885 <b>Example usage</b>\r
3886 @code\r
3887 UINT64 Msr;\r
3888\r
3889 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);\r
3890 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);\r
3891 @endcode\r
c2aa191b 3892 @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 3893**/\r
3894#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16\r
3895\r
3896\r
3897/**\r
3898 Package. Uncore C-box 0 perfmon counter MSR.\r
3899\r
3900 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)\r
3901 @param EAX Lower 32-bits of MSR value.\r
3902 @param EDX Upper 32-bits of MSR value.\r
3903\r
3904 <b>Example usage</b>\r
3905 @code\r
3906 UINT64 Msr;\r
3907\r
3908 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);\r
3909 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);\r
3910 @endcode\r
c2aa191b 3911 @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
bd946618
MK		 3912**/\r
3913#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17\r
3914\r
3915\r
3916/**\r
3917 Package. Uncore C-box 0 perfmon event select MSR.\r
3918\r
3919 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)\r
3920 @param EAX Lower 32-bits of MSR value.\r
3921 @param EDX Upper 32-bits of MSR value.\r
3922\r
3923 <b>Example usage</b>\r
3924 @code\r
3925 UINT64 Msr;\r
3926\r
3927 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);\r
3928 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);\r
3929 @endcode\r
c2aa191b 3930 @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 3931**/\r
3932#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18\r
3933\r
3934\r
3935/**\r
3936 Package. Uncore C-box 0 perfmon counter MSR.\r
3937\r
3938 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)\r
3939 @param EAX Lower 32-bits of MSR value.\r
3940 @param EDX Upper 32-bits of MSR value.\r
3941\r
3942 <b>Example usage</b>\r
3943 @code\r
3944 UINT64 Msr;\r
3945\r
3946 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);\r
3947 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);\r
3948 @endcode\r
c2aa191b 3949 @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.\r
bd946618
MK		 3950**/\r
3951#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19\r
3952\r
3953\r
3954/**\r
3955 Package. Uncore C-box 0 perfmon event select MSR.\r
3956\r
3957 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)\r
3958 @param EAX Lower 32-bits of MSR value.\r
3959 @param EDX Upper 32-bits of MSR value.\r
3960\r
3961 <b>Example usage</b>\r
3962 @code\r
3963 UINT64 Msr;\r
3964\r
3965 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);\r
3966 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);\r
3967 @endcode\r
c2aa191b 3968 @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 3969**/\r
3970#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A\r
3971\r
3972\r
3973/**\r
3974 Package. Uncore C-box 0 perfmon counter MSR.\r
3975\r
3976 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)\r
3977 @param EAX Lower 32-bits of MSR value.\r
3978 @param EDX Upper 32-bits of MSR value.\r
3979\r
3980 <b>Example usage</b>\r
3981 @code\r
3982 UINT64 Msr;\r
3983\r
3984 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);\r
3985 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);\r
3986 @endcode\r
c2aa191b 3987 @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.\r
bd946618
MK		 3988**/\r
3989#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B\r
3990\r
3991\r
3992/**\r
3993 Package. Uncore C-box 4 perfmon local box control MSR.\r
3994\r
3995 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)\r
3996 @param EAX Lower 32-bits of MSR value.\r
3997 @param EDX Upper 32-bits of MSR value.\r
3998\r
3999 <b>Example usage</b>\r
4000 @code\r
4001 UINT64 Msr;\r
4002\r
4003 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);\r
4004 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);\r
4005 @endcode\r
c2aa191b 4006 @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 4007**/\r
4008#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20\r
4009\r
4010\r
4011/**\r
4012 Package. Uncore C-box 4 perfmon local box status MSR.\r
4013\r
4014 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)\r
4015 @param EAX Lower 32-bits of MSR value.\r
4016 @param EDX Upper 32-bits of MSR value.\r
4017\r
4018 <b>Example usage</b>\r
4019 @code\r
4020 UINT64 Msr;\r
4021\r
4022 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);\r
4023 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);\r
4024 @endcode\r
c2aa191b 4025 @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 4026**/\r
4027#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21\r
4028\r
4029\r
4030/**\r
4031 Package. Uncore C-box 4 perfmon local box overflow control MSR.\r
4032\r
4033 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)\r
4034 @param EAX Lower 32-bits of MSR value.\r
4035 @param EDX Upper 32-bits of MSR value.\r
4036\r
4037 <b>Example usage</b>\r
4038 @code\r
4039 UINT64 Msr;\r
4040\r
4041 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);\r
4042 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);\r
4043 @endcode\r
c2aa191b 4044 @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 4045**/\r
4046#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22\r
4047\r
4048\r
4049/**\r
4050 Package. Uncore C-box 4 perfmon event select MSR.\r
4051\r
4052 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)\r
4053 @param EAX Lower 32-bits of MSR value.\r
4054 @param EDX Upper 32-bits of MSR value.\r
4055\r
4056 <b>Example usage</b>\r
4057 @code\r
4058 UINT64 Msr;\r
4059\r
4060 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);\r
4061 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);\r
4062 @endcode\r
c2aa191b 4063 @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 4064**/\r
4065#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30\r
4066\r
4067\r
4068/**\r
4069 Package. Uncore C-box 4 perfmon counter MSR.\r
4070\r
4071 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)\r
4072 @param EAX Lower 32-bits of MSR value.\r
4073 @param EDX Upper 32-bits of MSR value.\r
4074\r
4075 <b>Example usage</b>\r
4076 @code\r
4077 UINT64 Msr;\r
4078\r
4079 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);\r
4080 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);\r
4081 @endcode\r
c2aa191b 4082 @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
bd946618
MK		 4083**/\r
4084#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31\r
4085\r
4086\r
4087/**\r
4088 Package. Uncore C-box 4 perfmon event select MSR.\r
4089\r
4090 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)\r
4091 @param EAX Lower 32-bits of MSR value.\r
4092 @param EDX Upper 32-bits of MSR value.\r
4093\r
4094 <b>Example usage</b>\r
4095 @code\r
4096 UINT64 Msr;\r
4097\r
4098 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);\r
4099 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);\r
4100 @endcode\r
c2aa191b 4101 @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 4102**/\r
4103#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32\r
4104\r
4105\r
4106/**\r
4107 Package. Uncore C-box 4 perfmon counter MSR.\r
4108\r
4109 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)\r
4110 @param EAX Lower 32-bits of MSR value.\r
4111 @param EDX Upper 32-bits of MSR value.\r
4112\r
4113 <b>Example usage</b>\r
4114 @code\r
4115 UINT64 Msr;\r
4116\r
4117 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);\r
4118 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);\r
4119 @endcode\r
c2aa191b 4120 @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
bd946618
MK		 4121**/\r
4122#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33\r
4123\r
4124\r
4125/**\r
4126 Package. Uncore C-box 4 perfmon event select MSR.\r
4127\r
4128 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)\r
4129 @param EAX Lower 32-bits of MSR value.\r
4130 @param EDX Upper 32-bits of MSR value.\r
4131\r
4132 <b>Example usage</b>\r
4133 @code\r
4134 UINT64 Msr;\r
4135\r
4136 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);\r
4137 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);\r
4138 @endcode\r
c2aa191b 4139 @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 4140**/\r
4141#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34\r
4142\r
4143\r
4144/**\r
4145 Package. Uncore C-box 4 perfmon counter MSR.\r
4146\r
4147 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)\r
4148 @param EAX Lower 32-bits of MSR value.\r
4149 @param EDX Upper 32-bits of MSR value.\r
4150\r
4151 <b>Example usage</b>\r
4152 @code\r
4153 UINT64 Msr;\r
4154\r
4155 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);\r
4156 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);\r
4157 @endcode\r
c2aa191b 4158 @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
bd946618
MK		 4159**/\r
4160#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35\r
4161\r
4162\r
4163/**\r
4164 Package. Uncore C-box 4 perfmon event select MSR.\r
4165\r
4166 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)\r
4167 @param EAX Lower 32-bits of MSR value.\r
4168 @param EDX Upper 32-bits of MSR value.\r
4169\r
4170 <b>Example usage</b>\r
4171 @code\r
4172 UINT64 Msr;\r
4173\r
4174 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);\r
4175 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);\r
4176 @endcode\r
c2aa191b 4177 @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 4178**/\r
4179#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36\r
4180\r
4181\r
4182/**\r
4183 Package. Uncore C-box 4 perfmon counter MSR.\r
4184\r
4185 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)\r
4186 @param EAX Lower 32-bits of MSR value.\r
4187 @param EDX Upper 32-bits of MSR value.\r
4188\r
4189 <b>Example usage</b>\r
4190 @code\r
4191 UINT64 Msr;\r
4192\r
4193 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);\r
4194 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);\r
4195 @endcode\r
c2aa191b 4196 @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
bd946618
MK		 4197**/\r
4198#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37\r
4199\r
4200\r
4201/**\r
4202 Package. Uncore C-box 4 perfmon event select MSR.\r
4203\r
4204 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)\r
4205 @param EAX Lower 32-bits of MSR value.\r
4206 @param EDX Upper 32-bits of MSR value.\r
4207\r
4208 <b>Example usage</b>\r
4209 @code\r
4210 UINT64 Msr;\r
4211\r
4212 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);\r
4213 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);\r
4214 @endcode\r
c2aa191b 4215 @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 4216**/\r
4217#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38\r
4218\r
4219\r
4220/**\r
4221 Package. Uncore C-box 4 perfmon counter MSR.\r
4222\r
4223 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)\r
4224 @param EAX Lower 32-bits of MSR value.\r
4225 @param EDX Upper 32-bits of MSR value.\r
4226\r
4227 <b>Example usage</b>\r
4228 @code\r
4229 UINT64 Msr;\r
4230\r
4231 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);\r
4232 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);\r
4233 @endcode\r
c2aa191b 4234 @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.\r
bd946618
MK		 4235**/\r
4236#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39\r
4237\r
4238\r
4239/**\r
4240 Package. Uncore C-box 4 perfmon event select MSR.\r
4241\r
4242 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)\r
4243 @param EAX Lower 32-bits of MSR value.\r
4244 @param EDX Upper 32-bits of MSR value.\r
4245\r
4246 <b>Example usage</b>\r
4247 @code\r
4248 UINT64 Msr;\r
4249\r
4250 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);\r
4251 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);\r
4252 @endcode\r
c2aa191b 4253 @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 4254**/\r
4255#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A\r
4256\r
4257\r
4258/**\r
4259 Package. Uncore C-box 4 perfmon counter MSR.\r
4260\r
4261 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)\r
4262 @param EAX Lower 32-bits of MSR value.\r
4263 @param EDX Upper 32-bits of MSR value.\r
4264\r
4265 <b>Example usage</b>\r
4266 @code\r
4267 UINT64 Msr;\r
4268\r
4269 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);\r
4270 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);\r
4271 @endcode\r
c2aa191b 4272 @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.\r
bd946618
MK		 4273**/\r
4274#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B\r
4275\r
4276\r
4277/**\r
4278 Package. Uncore C-box 2 perfmon local box control MSR.\r
4279\r
4280 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)\r
4281 @param EAX Lower 32-bits of MSR value.\r
4282 @param EDX Upper 32-bits of MSR value.\r
4283\r
4284 <b>Example usage</b>\r
4285 @code\r
4286 UINT64 Msr;\r
4287\r
4288 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);\r
4289 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);\r
4290 @endcode\r
c2aa191b 4291 @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 4292**/\r
4293#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40\r
4294\r
4295\r
4296/**\r
4297 Package. Uncore C-box 2 perfmon local box status MSR.\r
4298\r
4299 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)\r
4300 @param EAX Lower 32-bits of MSR value.\r
4301 @param EDX Upper 32-bits of MSR value.\r
4302\r
4303 <b>Example usage</b>\r
4304 @code\r
4305 UINT64 Msr;\r
4306\r
4307 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);\r
4308 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);\r
4309 @endcode\r
c2aa191b 4310 @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 4311**/\r
4312#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41\r
4313\r
4314\r
4315/**\r
4316 Package. Uncore C-box 2 perfmon local box overflow control MSR.\r
4317\r
4318 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)\r
4319 @param EAX Lower 32-bits of MSR value.\r
4320 @param EDX Upper 32-bits of MSR value.\r
4321\r
4322 <b>Example usage</b>\r
4323 @code\r
4324 UINT64 Msr;\r
4325\r
4326 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);\r
4327 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);\r
4328 @endcode\r
c2aa191b 4329 @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 4330**/\r
4331#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42\r
4332\r
4333\r
4334/**\r
4335 Package. Uncore C-box 2 perfmon event select MSR.\r
4336\r
4337 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)\r
4338 @param EAX Lower 32-bits of MSR value.\r
4339 @param EDX Upper 32-bits of MSR value.\r
4340\r
4341 <b>Example usage</b>\r
4342 @code\r
4343 UINT64 Msr;\r
4344\r
4345 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);\r
4346 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);\r
4347 @endcode\r
c2aa191b 4348 @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 4349**/\r
4350#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50\r
4351\r
4352\r
4353/**\r
4354 Package. Uncore C-box 2 perfmon counter MSR.\r
4355\r
4356 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)\r
4357 @param EAX Lower 32-bits of MSR value.\r
4358 @param EDX Upper 32-bits of MSR value.\r
4359\r
4360 <b>Example usage</b>\r
4361 @code\r
4362 UINT64 Msr;\r
4363\r
4364 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);\r
4365 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);\r
4366 @endcode\r
c2aa191b 4367 @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
bd946618
MK		 4368**/\r
4369#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51\r
4370\r
4371\r
4372/**\r
4373 Package. Uncore C-box 2 perfmon event select MSR.\r
4374\r
4375 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)\r
4376 @param EAX Lower 32-bits of MSR value.\r
4377 @param EDX Upper 32-bits of MSR value.\r
4378\r
4379 <b>Example usage</b>\r
4380 @code\r
4381 UINT64 Msr;\r
4382\r
4383 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);\r
4384 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);\r
4385 @endcode\r
c2aa191b 4386 @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 4387**/\r
4388#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52\r
4389\r
4390\r
4391/**\r
4392 Package. Uncore C-box 2 perfmon counter MSR.\r
4393\r
4394 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)\r
4395 @param EAX Lower 32-bits of MSR value.\r
4396 @param EDX Upper 32-bits of MSR value.\r
4397\r
4398 <b>Example usage</b>\r
4399 @code\r
4400 UINT64 Msr;\r
4401\r
4402 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);\r
4403 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);\r
4404 @endcode\r
c2aa191b 4405 @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
bd946618
MK		 4406**/\r
4407#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53\r
4408\r
4409\r
4410/**\r
4411 Package. Uncore C-box 2 perfmon event select MSR.\r
4412\r
4413 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)\r
4414 @param EAX Lower 32-bits of MSR value.\r
4415 @param EDX Upper 32-bits of MSR value.\r
4416\r
4417 <b>Example usage</b>\r
4418 @code\r
4419 UINT64 Msr;\r
4420\r
4421 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);\r
4422 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);\r
4423 @endcode\r
c2aa191b 4424 @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 4425**/\r
4426#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54\r
4427\r
4428\r
4429/**\r
4430 Package. Uncore C-box 2 perfmon counter MSR.\r
4431\r
4432 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)\r
4433 @param EAX Lower 32-bits of MSR value.\r
4434 @param EDX Upper 32-bits of MSR value.\r
4435\r
4436 <b>Example usage</b>\r
4437 @code\r
4438 UINT64 Msr;\r
4439\r
4440 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);\r
4441 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);\r
4442 @endcode\r
c2aa191b 4443 @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
bd946618
MK		 4444**/\r
4445#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55\r
4446\r
4447\r
4448/**\r
4449 Package. Uncore C-box 2 perfmon event select MSR.\r
4450\r
4451 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)\r
4452 @param EAX Lower 32-bits of MSR value.\r
4453 @param EDX Upper 32-bits of MSR value.\r
4454\r
4455 <b>Example usage</b>\r
4456 @code\r
4457 UINT64 Msr;\r
4458\r
4459 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);\r
4460 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);\r
4461 @endcode\r
c2aa191b 4462 @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 4463**/\r
4464#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56\r
4465\r
4466\r
4467/**\r
4468 Package. Uncore C-box 2 perfmon counter MSR.\r
4469\r
4470 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)\r
4471 @param EAX Lower 32-bits of MSR value.\r
4472 @param EDX Upper 32-bits of MSR value.\r
4473\r
4474 <b>Example usage</b>\r
4475 @code\r
4476 UINT64 Msr;\r
4477\r
4478 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);\r
4479 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);\r
4480 @endcode\r
c2aa191b 4481 @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
bd946618
MK		 4482**/\r
4483#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57\r
4484\r
4485\r
4486/**\r
4487 Package. Uncore C-box 2 perfmon event select MSR.\r
4488\r
4489 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)\r
4490 @param EAX Lower 32-bits of MSR value.\r
4491 @param EDX Upper 32-bits of MSR value.\r
4492\r
4493 <b>Example usage</b>\r
4494 @code\r
4495 UINT64 Msr;\r
4496\r
4497 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);\r
4498 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);\r
4499 @endcode\r
c2aa191b 4500 @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 4501**/\r
4502#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58\r
4503\r
4504\r
4505/**\r
4506 Package. Uncore C-box 2 perfmon counter MSR.\r
4507\r
4508 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)\r
4509 @param EAX Lower 32-bits of MSR value.\r
4510 @param EDX Upper 32-bits of MSR value.\r
4511\r
4512 <b>Example usage</b>\r
4513 @code\r
4514 UINT64 Msr;\r
4515\r
4516 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);\r
4517 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);\r
4518 @endcode\r
c2aa191b 4519 @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.\r
bd946618
MK		 4520**/\r
4521#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59\r
4522\r
4523\r
4524/**\r
4525 Package. Uncore C-box 2 perfmon event select MSR.\r
4526\r
4527 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)\r
4528 @param EAX Lower 32-bits of MSR value.\r
4529 @param EDX Upper 32-bits of MSR value.\r
4530\r
4531 <b>Example usage</b>\r
4532 @code\r
4533 UINT64 Msr;\r
4534\r
4535 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);\r
4536 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);\r
4537 @endcode\r
c2aa191b 4538 @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 4539**/\r
4540#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A\r
4541\r
4542\r
4543/**\r
4544 Package. Uncore C-box 2 perfmon counter MSR.\r
4545\r
4546 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)\r
4547 @param EAX Lower 32-bits of MSR value.\r
4548 @param EDX Upper 32-bits of MSR value.\r
4549\r
4550 <b>Example usage</b>\r
4551 @code\r
4552 UINT64 Msr;\r
4553\r
4554 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);\r
4555 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);\r
4556 @endcode\r
c2aa191b 4557 @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.\r
bd946618
MK		 4558**/\r
4559#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B\r
4560\r
4561\r
4562/**\r
4563 Package. Uncore C-box 6 perfmon local box control MSR.\r
4564\r
4565 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)\r
4566 @param EAX Lower 32-bits of MSR value.\r
4567 @param EDX Upper 32-bits of MSR value.\r
4568\r
4569 <b>Example usage</b>\r
4570 @code\r
4571 UINT64 Msr;\r
4572\r
4573 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);\r
4574 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);\r
4575 @endcode\r
c2aa191b 4576 @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 4577**/\r
4578#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60\r
4579\r
4580\r
4581/**\r
4582 Package. Uncore C-box 6 perfmon local box status MSR.\r
4583\r
4584 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)\r
4585 @param EAX Lower 32-bits of MSR value.\r
4586 @param EDX Upper 32-bits of MSR value.\r
4587\r
4588 <b>Example usage</b>\r
4589 @code\r
4590 UINT64 Msr;\r
4591\r
4592 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);\r
4593 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);\r
4594 @endcode\r
c2aa191b 4595 @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 4596**/\r
4597#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61\r
4598\r
4599\r
4600/**\r
4601 Package. Uncore C-box 6 perfmon local box overflow control MSR.\r
4602\r
4603 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)\r
4604 @param EAX Lower 32-bits of MSR value.\r
4605 @param EDX Upper 32-bits of MSR value.\r
4606\r
4607 <b>Example usage</b>\r
4608 @code\r
4609 UINT64 Msr;\r
4610\r
4611 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);\r
4612 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);\r
4613 @endcode\r
c2aa191b 4614 @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 4615**/\r
4616#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62\r
4617\r
4618\r
4619/**\r
4620 Package. Uncore C-box 6 perfmon event select MSR.\r
4621\r
4622 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)\r
4623 @param EAX Lower 32-bits of MSR value.\r
4624 @param EDX Upper 32-bits of MSR value.\r
4625\r
4626 <b>Example usage</b>\r
4627 @code\r
4628 UINT64 Msr;\r
4629\r
4630 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);\r
4631 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);\r
4632 @endcode\r
c2aa191b 4633 @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 4634**/\r
4635#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70\r
4636\r
4637\r
4638/**\r
4639 Package. Uncore C-box 6 perfmon counter MSR.\r
4640\r
4641 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)\r
4642 @param EAX Lower 32-bits of MSR value.\r
4643 @param EDX Upper 32-bits of MSR value.\r
4644\r
4645 <b>Example usage</b>\r
4646 @code\r
4647 UINT64 Msr;\r
4648\r
4649 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);\r
4650 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);\r
4651 @endcode\r
c2aa191b 4652 @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
bd946618
MK		 4653**/\r
4654#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71\r
4655\r
4656\r
4657/**\r
4658 Package. Uncore C-box 6 perfmon event select MSR.\r
4659\r
4660 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)\r
4661 @param EAX Lower 32-bits of MSR value.\r
4662 @param EDX Upper 32-bits of MSR value.\r
4663\r
4664 <b>Example usage</b>\r
4665 @code\r
4666 UINT64 Msr;\r
4667\r
4668 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);\r
4669 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);\r
4670 @endcode\r
c2aa191b 4671 @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 4672**/\r
4673#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72\r
4674\r
4675\r
4676/**\r
4677 Package. Uncore C-box 6 perfmon counter MSR.\r
4678\r
4679 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)\r
4680 @param EAX Lower 32-bits of MSR value.\r
4681 @param EDX Upper 32-bits of MSR value.\r
4682\r
4683 <b>Example usage</b>\r
4684 @code\r
4685 UINT64 Msr;\r
4686\r
4687 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);\r
4688 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);\r
4689 @endcode\r
c2aa191b 4690 @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
bd946618
MK		 4691**/\r
4692#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73\r
4693\r
4694\r
4695/**\r
4696 Package. Uncore C-box 6 perfmon event select MSR.\r
4697\r
4698 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)\r
4699 @param EAX Lower 32-bits of MSR value.\r
4700 @param EDX Upper 32-bits of MSR value.\r
4701\r
4702 <b>Example usage</b>\r
4703 @code\r
4704 UINT64 Msr;\r
4705\r
4706 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);\r
4707 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);\r
4708 @endcode\r
c2aa191b 4709 @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 4710**/\r
4711#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74\r
4712\r
4713\r
4714/**\r
4715 Package. Uncore C-box 6 perfmon counter MSR.\r
4716\r
4717 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)\r
4718 @param EAX Lower 32-bits of MSR value.\r
4719 @param EDX Upper 32-bits of MSR value.\r
4720\r
4721 <b>Example usage</b>\r
4722 @code\r
4723 UINT64 Msr;\r
4724\r
4725 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);\r
4726 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);\r
4727 @endcode\r
c2aa191b 4728 @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
bd946618
MK		 4729**/\r
4730#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75\r
4731\r
4732\r
4733/**\r
4734 Package. Uncore C-box 6 perfmon event select MSR.\r
4735\r
4736 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)\r
4737 @param EAX Lower 32-bits of MSR value.\r
4738 @param EDX Upper 32-bits of MSR value.\r
4739\r
4740 <b>Example usage</b>\r
4741 @code\r
4742 UINT64 Msr;\r
4743\r
4744 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);\r
4745 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);\r
4746 @endcode\r
c2aa191b 4747 @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 4748**/\r
4749#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76\r
4750\r
4751\r
4752/**\r
4753 Package. Uncore C-box 6 perfmon counter MSR.\r
4754\r
4755 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)\r
4756 @param EAX Lower 32-bits of MSR value.\r
4757 @param EDX Upper 32-bits of MSR value.\r
4758\r
4759 <b>Example usage</b>\r
4760 @code\r
4761 UINT64 Msr;\r
4762\r
4763 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);\r
4764 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);\r
4765 @endcode\r
c2aa191b 4766 @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
bd946618
MK		 4767**/\r
4768#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77\r
4769\r
4770\r
4771/**\r
4772 Package. Uncore C-box 6 perfmon event select MSR.\r
4773\r
4774 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)\r
4775 @param EAX Lower 32-bits of MSR value.\r
4776 @param EDX Upper 32-bits of MSR value.\r
4777\r
4778 <b>Example usage</b>\r
4779 @code\r
4780 UINT64 Msr;\r
4781\r
4782 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);\r
4783 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);\r
4784 @endcode\r
c2aa191b 4785 @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 4786**/\r
4787#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78\r
4788\r
4789\r
4790/**\r
4791 Package. Uncore C-box 6 perfmon counter MSR.\r
4792\r
4793 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)\r
4794 @param EAX Lower 32-bits of MSR value.\r
4795 @param EDX Upper 32-bits of MSR value.\r
4796\r
4797 <b>Example usage</b>\r
4798 @code\r
4799 UINT64 Msr;\r
4800\r
4801 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);\r
4802 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);\r
4803 @endcode\r
c2aa191b 4804 @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.\r
bd946618
MK		 4805**/\r
4806#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79\r
4807\r
4808\r
4809/**\r
4810 Package. Uncore C-box 6 perfmon event select MSR.\r
4811\r
4812 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)\r
4813 @param EAX Lower 32-bits of MSR value.\r
4814 @param EDX Upper 32-bits of MSR value.\r
4815\r
4816 <b>Example usage</b>\r
4817 @code\r
4818 UINT64 Msr;\r
4819\r
4820 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);\r
4821 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);\r
4822 @endcode\r
c2aa191b 4823 @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 4824**/\r
4825#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A\r
4826\r
4827\r
4828/**\r
4829 Package. Uncore C-box 6 perfmon counter MSR.\r
4830\r
4831 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)\r
4832 @param EAX Lower 32-bits of MSR value.\r
4833 @param EDX Upper 32-bits of MSR value.\r
4834\r
4835 <b>Example usage</b>\r
4836 @code\r
4837 UINT64 Msr;\r
4838\r
4839 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);\r
4840 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);\r
4841 @endcode\r
c2aa191b 4842 @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.\r
bd946618
MK		 4843**/\r
4844#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B\r
4845\r
4846\r
4847/**\r
4848 Package. Uncore C-box 1 perfmon local box control MSR.\r
4849\r
4850 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)\r
4851 @param EAX Lower 32-bits of MSR value.\r
4852 @param EDX Upper 32-bits of MSR value.\r
4853\r
4854 <b>Example usage</b>\r
4855 @code\r
4856 UINT64 Msr;\r
4857\r
4858 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);\r
4859 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);\r
4860 @endcode\r
c2aa191b 4861 @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 4862**/\r
4863#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80\r
4864\r
4865\r
4866/**\r
4867 Package. Uncore C-box 1 perfmon local box status MSR.\r
4868\r
4869 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)\r
4870 @param EAX Lower 32-bits of MSR value.\r
4871 @param EDX Upper 32-bits of MSR value.\r
4872\r
4873 <b>Example usage</b>\r
4874 @code\r
4875 UINT64 Msr;\r
4876\r
4877 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);\r
4878 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);\r
4879 @endcode\r
c2aa191b 4880 @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 4881**/\r
4882#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81\r
4883\r
4884\r
4885/**\r
4886 Package. Uncore C-box 1 perfmon local box overflow control MSR.\r
4887\r
4888 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)\r
4889 @param EAX Lower 32-bits of MSR value.\r
4890 @param EDX Upper 32-bits of MSR value.\r
4891\r
4892 <b>Example usage</b>\r
4893 @code\r
4894 UINT64 Msr;\r
4895\r
4896 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);\r
4897 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);\r
4898 @endcode\r
c2aa191b 4899 @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 4900**/\r
4901#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82\r
4902\r
4903\r
4904/**\r
4905 Package. Uncore C-box 1 perfmon event select MSR.\r
4906\r
4907 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)\r
4908 @param EAX Lower 32-bits of MSR value.\r
4909 @param EDX Upper 32-bits of MSR value.\r
4910\r
4911 <b>Example usage</b>\r
4912 @code\r
4913 UINT64 Msr;\r
4914\r
4915 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);\r
4916 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);\r
4917 @endcode\r
c2aa191b 4918 @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 4919**/\r
4920#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90\r
4921\r
4922\r
4923/**\r
4924 Package. Uncore C-box 1 perfmon counter MSR.\r
4925\r
4926 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)\r
4927 @param EAX Lower 32-bits of MSR value.\r
4928 @param EDX Upper 32-bits of MSR value.\r
4929\r
4930 <b>Example usage</b>\r
4931 @code\r
4932 UINT64 Msr;\r
4933\r
4934 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);\r
4935 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);\r
4936 @endcode\r
c2aa191b 4937 @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
bd946618
MK		 4938**/\r
4939#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91\r
4940\r
4941\r
4942/**\r
4943 Package. Uncore C-box 1 perfmon event select MSR.\r
4944\r
4945 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)\r
4946 @param EAX Lower 32-bits of MSR value.\r
4947 @param EDX Upper 32-bits of MSR value.\r
4948\r
4949 <b>Example usage</b>\r
4950 @code\r
4951 UINT64 Msr;\r
4952\r
4953 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);\r
4954 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);\r
4955 @endcode\r
c2aa191b 4956 @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 4957**/\r
4958#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92\r
4959\r
4960\r
4961/**\r
4962 Package. Uncore C-box 1 perfmon counter MSR.\r
4963\r
4964 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)\r
4965 @param EAX Lower 32-bits of MSR value.\r
4966 @param EDX Upper 32-bits of MSR value.\r
4967\r
4968 <b>Example usage</b>\r
4969 @code\r
4970 UINT64 Msr;\r
4971\r
4972 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);\r
4973 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);\r
4974 @endcode\r
c2aa191b 4975 @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
bd946618
MK		 4976**/\r
4977#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93\r
4978\r
4979\r
4980/**\r
4981 Package. Uncore C-box 1 perfmon event select MSR.\r
4982\r
4983 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)\r
4984 @param EAX Lower 32-bits of MSR value.\r
4985 @param EDX Upper 32-bits of MSR value.\r
4986\r
4987 <b>Example usage</b>\r
4988 @code\r
4989 UINT64 Msr;\r
4990\r
4991 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);\r
4992 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);\r
4993 @endcode\r
c2aa191b 4994 @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 4995**/\r
4996#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94\r
4997\r
4998\r
4999/**\r
5000 Package. Uncore C-box 1 perfmon counter MSR.\r
5001\r
5002 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)\r
5003 @param EAX Lower 32-bits of MSR value.\r
5004 @param EDX Upper 32-bits of MSR value.\r
5005\r
5006 <b>Example usage</b>\r
5007 @code\r
5008 UINT64 Msr;\r
5009\r
5010 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);\r
5011 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);\r
5012 @endcode\r
c2aa191b 5013 @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
bd946618
MK		 5014**/\r
5015#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95\r
5016\r
5017\r
5018/**\r
5019 Package. Uncore C-box 1 perfmon event select MSR.\r
5020\r
5021 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)\r
5022 @param EAX Lower 32-bits of MSR value.\r
5023 @param EDX Upper 32-bits of MSR value.\r
5024\r
5025 <b>Example usage</b>\r
5026 @code\r
5027 UINT64 Msr;\r
5028\r
5029 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);\r
5030 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);\r
5031 @endcode\r
c2aa191b 5032 @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 5033**/\r
5034#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96\r
5035\r
5036\r
5037/**\r
5038 Package. Uncore C-box 1 perfmon counter MSR.\r
5039\r
5040 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)\r
5041 @param EAX Lower 32-bits of MSR value.\r
5042 @param EDX Upper 32-bits of MSR value.\r
5043\r
5044 <b>Example usage</b>\r
5045 @code\r
5046 UINT64 Msr;\r
5047\r
5048 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);\r
5049 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);\r
5050 @endcode\r
c2aa191b 5051 @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
bd946618
MK		 5052**/\r
5053#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97\r
5054\r
5055\r
5056/**\r
5057 Package. Uncore C-box 1 perfmon event select MSR.\r
5058\r
5059 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)\r
5060 @param EAX Lower 32-bits of MSR value.\r
5061 @param EDX Upper 32-bits of MSR value.\r
5062\r
5063 <b>Example usage</b>\r
5064 @code\r
5065 UINT64 Msr;\r
5066\r
5067 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);\r
5068 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);\r
5069 @endcode\r
c2aa191b 5070 @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 5071**/\r
5072#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98\r
5073\r
5074\r
5075/**\r
5076 Package. Uncore C-box 1 perfmon counter MSR.\r
5077\r
5078 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)\r
5079 @param EAX Lower 32-bits of MSR value.\r
5080 @param EDX Upper 32-bits of MSR value.\r
5081\r
5082 <b>Example usage</b>\r
5083 @code\r
5084 UINT64 Msr;\r
5085\r
5086 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);\r
5087 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);\r
5088 @endcode\r
c2aa191b 5089 @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.\r
bd946618
MK		 5090**/\r
5091#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99\r
5092\r
5093\r
5094/**\r
5095 Package. Uncore C-box 1 perfmon event select MSR.\r
5096\r
5097 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)\r
5098 @param EAX Lower 32-bits of MSR value.\r
5099 @param EDX Upper 32-bits of MSR value.\r
5100\r
5101 <b>Example usage</b>\r
5102 @code\r
5103 UINT64 Msr;\r
5104\r
5105 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);\r
5106 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);\r
5107 @endcode\r
c2aa191b 5108 @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 5109**/\r
5110#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A\r
5111\r
5112\r
5113/**\r
5114 Package. Uncore C-box 1 perfmon counter MSR.\r
5115\r
5116 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)\r
5117 @param EAX Lower 32-bits of MSR value.\r
5118 @param EDX Upper 32-bits of MSR value.\r
5119\r
5120 <b>Example usage</b>\r
5121 @code\r
5122 UINT64 Msr;\r
5123\r
5124 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);\r
5125 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);\r
5126 @endcode\r
c2aa191b 5127 @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.\r
bd946618
MK		 5128**/\r
5129#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B\r
5130\r
5131\r
5132/**\r
5133 Package. Uncore C-box 5 perfmon local box control MSR.\r
5134\r
5135 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)\r
5136 @param EAX Lower 32-bits of MSR value.\r
5137 @param EDX Upper 32-bits of MSR value.\r
5138\r
5139 <b>Example usage</b>\r
5140 @code\r
5141 UINT64 Msr;\r
5142\r
5143 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);\r
5144 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);\r
5145 @endcode\r
c2aa191b 5146 @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 5147**/\r
5148#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0\r
5149\r
5150\r
5151/**\r
5152 Package. Uncore C-box 5 perfmon local box status MSR.\r
5153\r
5154 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)\r
5155 @param EAX Lower 32-bits of MSR value.\r
5156 @param EDX Upper 32-bits of MSR value.\r
5157\r
5158 <b>Example usage</b>\r
5159 @code\r
5160 UINT64 Msr;\r
5161\r
5162 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);\r
5163 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);\r
5164 @endcode\r
c2aa191b 5165 @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 5166**/\r
5167#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1\r
5168\r
5169\r
5170/**\r
5171 Package. Uncore C-box 5 perfmon local box overflow control MSR.\r
5172\r
5173 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)\r
5174 @param EAX Lower 32-bits of MSR value.\r
5175 @param EDX Upper 32-bits of MSR value.\r
5176\r
5177 <b>Example usage</b>\r
5178 @code\r
5179 UINT64 Msr;\r
5180\r
5181 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);\r
5182 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);\r
5183 @endcode\r
c2aa191b 5184 @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 5185**/\r
5186#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2\r
5187\r
5188\r
5189/**\r
5190 Package. Uncore C-box 5 perfmon event select MSR.\r
5191\r
5192 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)\r
5193 @param EAX Lower 32-bits of MSR value.\r
5194 @param EDX Upper 32-bits of MSR value.\r
5195\r
5196 <b>Example usage</b>\r
5197 @code\r
5198 UINT64 Msr;\r
5199\r
5200 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);\r
5201 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);\r
5202 @endcode\r
c2aa191b 5203 @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 5204**/\r
5205#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0\r
5206\r
5207\r
5208/**\r
5209 Package. Uncore C-box 5 perfmon counter MSR.\r
5210\r
5211 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)\r
5212 @param EAX Lower 32-bits of MSR value.\r
5213 @param EDX Upper 32-bits of MSR value.\r
5214\r
5215 <b>Example usage</b>\r
5216 @code\r
5217 UINT64 Msr;\r
5218\r
5219 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);\r
5220 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);\r
5221 @endcode\r
c2aa191b 5222 @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
bd946618
MK		 5223**/\r
5224#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1\r
5225\r
5226\r
5227/**\r
5228 Package. Uncore C-box 5 perfmon event select MSR.\r
5229\r
5230 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)\r
5231 @param EAX Lower 32-bits of MSR value.\r
5232 @param EDX Upper 32-bits of MSR value.\r
5233\r
5234 <b>Example usage</b>\r
5235 @code\r
5236 UINT64 Msr;\r
5237\r
5238 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);\r
5239 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);\r
5240 @endcode\r
c2aa191b 5241 @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 5242**/\r
5243#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2\r
5244\r
5245\r
5246/**\r
5247 Package. Uncore C-box 5 perfmon counter MSR.\r
5248\r
5249 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)\r
5250 @param EAX Lower 32-bits of MSR value.\r
5251 @param EDX Upper 32-bits of MSR value.\r
5252\r
5253 <b>Example usage</b>\r
5254 @code\r
5255 UINT64 Msr;\r
5256\r
5257 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);\r
5258 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);\r
5259 @endcode\r
c2aa191b 5260 @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
bd946618
MK		 5261**/\r
5262#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3\r
5263\r
5264\r
5265/**\r
5266 Package. Uncore C-box 5 perfmon event select MSR.\r
5267\r
5268 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)\r
5269 @param EAX Lower 32-bits of MSR value.\r
5270 @param EDX Upper 32-bits of MSR value.\r
5271\r
5272 <b>Example usage</b>\r
5273 @code\r
5274 UINT64 Msr;\r
5275\r
5276 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);\r
5277 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);\r
5278 @endcode\r
c2aa191b 5279 @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 5280**/\r
5281#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4\r
5282\r
5283\r
5284/**\r
5285 Package. Uncore C-box 5 perfmon counter MSR.\r
5286\r
5287 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)\r
5288 @param EAX Lower 32-bits of MSR value.\r
5289 @param EDX Upper 32-bits of MSR value.\r
5290\r
5291 <b>Example usage</b>\r
5292 @code\r
5293 UINT64 Msr;\r
5294\r
5295 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);\r
5296 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);\r
5297 @endcode\r
c2aa191b 5298 @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
bd946618
MK		 5299**/\r
5300#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5\r
5301\r
5302\r
5303/**\r
5304 Package. Uncore C-box 5 perfmon event select MSR.\r
5305\r
5306 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)\r
5307 @param EAX Lower 32-bits of MSR value.\r
5308 @param EDX Upper 32-bits of MSR value.\r
5309\r
5310 <b>Example usage</b>\r
5311 @code\r
5312 UINT64 Msr;\r
5313\r
5314 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);\r
5315 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);\r
5316 @endcode\r
c2aa191b 5317 @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 5318**/\r
5319#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6\r
5320\r
5321\r
5322/**\r
5323 Package. Uncore C-box 5 perfmon counter MSR.\r
5324\r
5325 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)\r
5326 @param EAX Lower 32-bits of MSR value.\r
5327 @param EDX Upper 32-bits of MSR value.\r
5328\r
5329 <b>Example usage</b>\r
5330 @code\r
5331 UINT64 Msr;\r
5332\r
5333 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);\r
5334 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);\r
5335 @endcode\r
c2aa191b 5336 @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
bd946618
MK		 5337**/\r
5338#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7\r
5339\r
5340\r
5341/**\r
5342 Package. Uncore C-box 5 perfmon event select MSR.\r
5343\r
5344 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)\r
5345 @param EAX Lower 32-bits of MSR value.\r
5346 @param EDX Upper 32-bits of MSR value.\r
5347\r
5348 <b>Example usage</b>\r
5349 @code\r
5350 UINT64 Msr;\r
5351\r
5352 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);\r
5353 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);\r
5354 @endcode\r
c2aa191b 5355 @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 5356**/\r
5357#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8\r
5358\r
5359\r
5360/**\r
5361 Package. Uncore C-box 5 perfmon counter MSR.\r
5362\r
5363 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)\r
5364 @param EAX Lower 32-bits of MSR value.\r
5365 @param EDX Upper 32-bits of MSR value.\r
5366\r
5367 <b>Example usage</b>\r
5368 @code\r
5369 UINT64 Msr;\r
5370\r
5371 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);\r
5372 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);\r
5373 @endcode\r
c2aa191b 5374 @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.\r
bd946618
MK		 5375**/\r
5376#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9\r
5377\r
5378\r
5379/**\r
5380 Package. Uncore C-box 5 perfmon event select MSR.\r
5381\r
5382 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)\r
5383 @param EAX Lower 32-bits of MSR value.\r
5384 @param EDX Upper 32-bits of MSR value.\r
5385\r
5386 <b>Example usage</b>\r
5387 @code\r
5388 UINT64 Msr;\r
5389\r
5390 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);\r
5391 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);\r
5392 @endcode\r
c2aa191b 5393 @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 5394**/\r
5395#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA\r
5396\r
5397\r
5398/**\r
5399 Package. Uncore C-box 5 perfmon counter MSR.\r
5400\r
5401 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)\r
5402 @param EAX Lower 32-bits of MSR value.\r
5403 @param EDX Upper 32-bits of MSR value.\r
5404\r
5405 <b>Example usage</b>\r
5406 @code\r
5407 UINT64 Msr;\r
5408\r
5409 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);\r
5410 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);\r
5411 @endcode\r
c2aa191b 5412 @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.\r
bd946618
MK		 5413**/\r
5414#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB\r
5415\r
5416\r
5417/**\r
5418 Package. Uncore C-box 3 perfmon local box control MSR.\r
5419\r
5420 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)\r
5421 @param EAX Lower 32-bits of MSR value.\r
5422 @param EDX Upper 32-bits of MSR value.\r
5423\r
5424 <b>Example usage</b>\r
5425 @code\r
5426 UINT64 Msr;\r
5427\r
5428 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);\r
5429 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);\r
5430 @endcode\r
c2aa191b 5431 @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 5432**/\r
5433#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0\r
5434\r
5435\r
5436/**\r
5437 Package. Uncore C-box 3 perfmon local box status MSR.\r
5438\r
5439 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)\r
5440 @param EAX Lower 32-bits of MSR value.\r
5441 @param EDX Upper 32-bits of MSR value.\r
5442\r
5443 <b>Example usage</b>\r
5444 @code\r
5445 UINT64 Msr;\r
5446\r
5447 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);\r
5448 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);\r
5449 @endcode\r
c2aa191b 5450 @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 5451**/\r
5452#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1\r
5453\r
5454\r
5455/**\r
5456 Package. Uncore C-box 3 perfmon local box overflow control MSR.\r
5457\r
5458 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)\r
5459 @param EAX Lower 32-bits of MSR value.\r
5460 @param EDX Upper 32-bits of MSR value.\r
5461\r
5462 <b>Example usage</b>\r
5463 @code\r
5464 UINT64 Msr;\r
5465\r
5466 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);\r
5467 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);\r
5468 @endcode\r
c2aa191b 5469 @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 5470**/\r
5471#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2\r
5472\r
5473\r
5474/**\r
5475 Package. Uncore C-box 3 perfmon event select MSR.\r
5476\r
5477 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)\r
5478 @param EAX Lower 32-bits of MSR value.\r
5479 @param EDX Upper 32-bits of MSR value.\r
5480\r
5481 <b>Example usage</b>\r
5482 @code\r
5483 UINT64 Msr;\r
5484\r
5485 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);\r
5486 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);\r
5487 @endcode\r
c2aa191b 5488 @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 5489**/\r
5490#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0\r
5491\r
5492\r
5493/**\r
5494 Package. Uncore C-box 3 perfmon counter MSR.\r
5495\r
5496 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)\r
5497 @param EAX Lower 32-bits of MSR value.\r
5498 @param EDX Upper 32-bits of MSR value.\r
5499\r
5500 <b>Example usage</b>\r
5501 @code\r
5502 UINT64 Msr;\r
5503\r
5504 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);\r
5505 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);\r
5506 @endcode\r
c2aa191b 5507 @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
bd946618
MK		 5508**/\r
5509#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1\r
5510\r
5511\r
5512/**\r
5513 Package. Uncore C-box 3 perfmon event select MSR.\r
5514\r
5515 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)\r
5516 @param EAX Lower 32-bits of MSR value.\r
5517 @param EDX Upper 32-bits of MSR value.\r
5518\r
5519 <b>Example usage</b>\r
5520 @code\r
5521 UINT64 Msr;\r
5522\r
5523 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);\r
5524 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);\r
5525 @endcode\r
c2aa191b 5526 @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 5527**/\r
5528#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2\r
5529\r
5530\r
5531/**\r
5532 Package. Uncore C-box 3 perfmon counter MSR.\r
5533\r
5534 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)\r
5535 @param EAX Lower 32-bits of MSR value.\r
5536 @param EDX Upper 32-bits of MSR value.\r
5537\r
5538 <b>Example usage</b>\r
5539 @code\r
5540 UINT64 Msr;\r
5541\r
5542 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);\r
5543 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);\r
5544 @endcode\r
c2aa191b 5545 @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
bd946618
MK		 5546**/\r
5547#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3\r
5548\r
5549\r
5550/**\r
5551 Package. Uncore C-box 3 perfmon event select MSR.\r
5552\r
5553 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)\r
5554 @param EAX Lower 32-bits of MSR value.\r
5555 @param EDX Upper 32-bits of MSR value.\r
5556\r
5557 <b>Example usage</b>\r
5558 @code\r
5559 UINT64 Msr;\r
5560\r
5561 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);\r
5562 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);\r
5563 @endcode\r
c2aa191b 5564 @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 5565**/\r
5566#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4\r
5567\r
5568\r
5569/**\r
5570 Package. Uncore C-box 3 perfmon counter MSR.\r
5571\r
5572 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)\r
5573 @param EAX Lower 32-bits of MSR value.\r
5574 @param EDX Upper 32-bits of MSR value.\r
5575\r
5576 <b>Example usage</b>\r
5577 @code\r
5578 UINT64 Msr;\r
5579\r
5580 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);\r
5581 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);\r
5582 @endcode\r
c2aa191b 5583 @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
bd946618
MK		 5584**/\r
5585#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5\r
5586\r
5587\r
5588/**\r
5589 Package. Uncore C-box 3 perfmon event select MSR.\r
5590\r
5591 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)\r
5592 @param EAX Lower 32-bits of MSR value.\r
5593 @param EDX Upper 32-bits of MSR value.\r
5594\r
5595 <b>Example usage</b>\r
5596 @code\r
5597 UINT64 Msr;\r
5598\r
5599 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);\r
5600 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);\r
5601 @endcode\r
c2aa191b 5602 @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 5603**/\r
5604#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6\r
5605\r
5606\r
5607/**\r
5608 Package. Uncore C-box 3 perfmon counter MSR.\r
5609\r
5610 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)\r
5611 @param EAX Lower 32-bits of MSR value.\r
5612 @param EDX Upper 32-bits of MSR value.\r
5613\r
5614 <b>Example usage</b>\r
5615 @code\r
5616 UINT64 Msr;\r
5617\r
5618 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);\r
5619 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);\r
5620 @endcode\r
c2aa191b 5621 @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
bd946618
MK		 5622**/\r
5623#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7\r
5624\r
5625\r
5626/**\r
5627 Package. Uncore C-box 3 perfmon event select MSR.\r
5628\r
5629 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)\r
5630 @param EAX Lower 32-bits of MSR value.\r
5631 @param EDX Upper 32-bits of MSR value.\r
5632\r
5633 <b>Example usage</b>\r
5634 @code\r
5635 UINT64 Msr;\r
5636\r
5637 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);\r
5638 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);\r
5639 @endcode\r
c2aa191b 5640 @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 5641**/\r
5642#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8\r
5643\r
5644\r
5645/**\r
5646 Package. Uncore C-box 3 perfmon counter MSR.\r
5647\r
5648 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)\r
5649 @param EAX Lower 32-bits of MSR value.\r
5650 @param EDX Upper 32-bits of MSR value.\r
5651\r
5652 <b>Example usage</b>\r
5653 @code\r
5654 UINT64 Msr;\r
5655\r
5656 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);\r
5657 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);\r
5658 @endcode\r
c2aa191b 5659 @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.\r
bd946618
MK		 5660**/\r
5661#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9\r
5662\r
5663\r
5664/**\r
5665 Package. Uncore C-box 3 perfmon event select MSR.\r
5666\r
5667 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)\r
5668 @param EAX Lower 32-bits of MSR value.\r
5669 @param EDX Upper 32-bits of MSR value.\r
5670\r
5671 <b>Example usage</b>\r
5672 @code\r
5673 UINT64 Msr;\r
5674\r
5675 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);\r
5676 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);\r
5677 @endcode\r
c2aa191b 5678 @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 5679**/\r
5680#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA\r
5681\r
5682\r
5683/**\r
5684 Package. Uncore C-box 3 perfmon counter MSR.\r
5685\r
5686 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)\r
5687 @param EAX Lower 32-bits of MSR value.\r
5688 @param EDX Upper 32-bits of MSR value.\r
5689\r
5690 <b>Example usage</b>\r
5691 @code\r
5692 UINT64 Msr;\r
5693\r
5694 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);\r
5695 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);\r
5696 @endcode\r
c2aa191b 5697 @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.\r
bd946618
MK		 5698**/\r
5699#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB\r
5700\r
5701\r
5702/**\r
5703 Package. Uncore C-box 7 perfmon local box control MSR.\r
5704\r
5705 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)\r
5706 @param EAX Lower 32-bits of MSR value.\r
5707 @param EDX Upper 32-bits of MSR value.\r
5708\r
5709 <b>Example usage</b>\r
5710 @code\r
5711 UINT64 Msr;\r
5712\r
5713 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);\r
5714 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);\r
5715 @endcode\r
c2aa191b 5716 @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 5717**/\r
5718#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0\r
5719\r
5720\r
5721/**\r
5722 Package. Uncore C-box 7 perfmon local box status MSR.\r
5723\r
5724 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)\r
5725 @param EAX Lower 32-bits of MSR value.\r
5726 @param EDX Upper 32-bits of MSR value.\r
5727\r
5728 <b>Example usage</b>\r
5729 @code\r
5730 UINT64 Msr;\r
5731\r
5732 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);\r
5733 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);\r
5734 @endcode\r
c2aa191b 5735 @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 5736**/\r
5737#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1\r
5738\r
5739\r
5740/**\r
5741 Package. Uncore C-box 7 perfmon local box overflow control MSR.\r
5742\r
5743 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)\r
5744 @param EAX Lower 32-bits of MSR value.\r
5745 @param EDX Upper 32-bits of MSR value.\r
5746\r
5747 <b>Example usage</b>\r
5748 @code\r
5749 UINT64 Msr;\r
5750\r
5751 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);\r
5752 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);\r
5753 @endcode\r
c2aa191b 5754 @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 5755**/\r
5756#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2\r
5757\r
5758\r
5759/**\r
5760 Package. Uncore C-box 7 perfmon event select MSR.\r
5761\r
5762 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)\r
5763 @param EAX Lower 32-bits of MSR value.\r
5764 @param EDX Upper 32-bits of MSR value.\r
5765\r
5766 <b>Example usage</b>\r
5767 @code\r
5768 UINT64 Msr;\r
5769\r
5770 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);\r
5771 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);\r
5772 @endcode\r
c2aa191b 5773 @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 5774**/\r
5775#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0\r
5776\r
5777\r
5778/**\r
5779 Package. Uncore C-box 7 perfmon counter MSR.\r
5780\r
5781 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)\r
5782 @param EAX Lower 32-bits of MSR value.\r
5783 @param EDX Upper 32-bits of MSR value.\r
5784\r
5785 <b>Example usage</b>\r
5786 @code\r
5787 UINT64 Msr;\r
5788\r
5789 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);\r
5790 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);\r
5791 @endcode\r
c2aa191b 5792 @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
bd946618
MK		 5793**/\r
5794#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1\r
5795\r
5796\r
5797/**\r
5798 Package. Uncore C-box 7 perfmon event select MSR.\r
5799\r
5800 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)\r
5801 @param EAX Lower 32-bits of MSR value.\r
5802 @param EDX Upper 32-bits of MSR value.\r
5803\r
5804 <b>Example usage</b>\r
5805 @code\r
5806 UINT64 Msr;\r
5807\r
5808 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);\r
5809 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);\r
5810 @endcode\r
c2aa191b 5811 @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 5812**/\r
5813#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2\r
5814\r
5815\r
5816/**\r
5817 Package. Uncore C-box 7 perfmon counter MSR.\r
5818\r
5819 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)\r
5820 @param EAX Lower 32-bits of MSR value.\r
5821 @param EDX Upper 32-bits of MSR value.\r
5822\r
5823 <b>Example usage</b>\r
5824 @code\r
5825 UINT64 Msr;\r
5826\r
5827 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);\r
5828 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);\r
5829 @endcode\r
c2aa191b 5830 @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
bd946618
MK		 5831**/\r
5832#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3\r
5833\r
5834\r
5835/**\r
5836 Package. Uncore C-box 7 perfmon event select MSR.\r
5837\r
5838 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)\r
5839 @param EAX Lower 32-bits of MSR value.\r
5840 @param EDX Upper 32-bits of MSR value.\r
5841\r
5842 <b>Example usage</b>\r
5843 @code\r
5844 UINT64 Msr;\r
5845\r
5846 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);\r
5847 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);\r
5848 @endcode\r
c2aa191b 5849 @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 5850**/\r
5851#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4\r
5852\r
5853\r
5854/**\r
5855 Package. Uncore C-box 7 perfmon counter MSR.\r
5856\r
5857 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)\r
5858 @param EAX Lower 32-bits of MSR value.\r
5859 @param EDX Upper 32-bits of MSR value.\r
5860\r
5861 <b>Example usage</b>\r
5862 @code\r
5863 UINT64 Msr;\r
5864\r
5865 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);\r
5866 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);\r
5867 @endcode\r
c2aa191b 5868 @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
bd946618
MK		 5869**/\r
5870#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5\r
5871\r
5872\r
5873/**\r
5874 Package. Uncore C-box 7 perfmon event select MSR.\r
5875\r
5876 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)\r
5877 @param EAX Lower 32-bits of MSR value.\r
5878 @param EDX Upper 32-bits of MSR value.\r
5879\r
5880 <b>Example usage</b>\r
5881 @code\r
5882 UINT64 Msr;\r
5883\r
5884 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);\r
5885 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);\r
5886 @endcode\r
c2aa191b 5887 @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 5888**/\r
5889#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6\r
5890\r
5891\r
5892/**\r
5893 Package. Uncore C-box 7 perfmon counter MSR.\r
5894\r
5895 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)\r
5896 @param EAX Lower 32-bits of MSR value.\r
5897 @param EDX Upper 32-bits of MSR value.\r
5898\r
5899 <b>Example usage</b>\r
5900 @code\r
5901 UINT64 Msr;\r
5902\r
5903 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);\r
5904 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);\r
5905 @endcode\r
c2aa191b 5906 @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
bd946618
MK		 5907**/\r
5908#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7\r
5909\r
5910\r
5911/**\r
5912 Package. Uncore C-box 7 perfmon event select MSR.\r
5913\r
5914 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)\r
5915 @param EAX Lower 32-bits of MSR value.\r
5916 @param EDX Upper 32-bits of MSR value.\r
5917\r
5918 <b>Example usage</b>\r
5919 @code\r
5920 UINT64 Msr;\r
5921\r
5922 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);\r
5923 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);\r
5924 @endcode\r
c2aa191b 5925 @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 5926**/\r
5927#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8\r
5928\r
5929\r
5930/**\r
5931 Package. Uncore C-box 7 perfmon counter MSR.\r
5932\r
5933 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)\r
5934 @param EAX Lower 32-bits of MSR value.\r
5935 @param EDX Upper 32-bits of MSR value.\r
5936\r
5937 <b>Example usage</b>\r
5938 @code\r
5939 UINT64 Msr;\r
5940\r
5941 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);\r
5942 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);\r
5943 @endcode\r
c2aa191b 5944 @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.\r
bd946618
MK		 5945**/\r
5946#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9\r
5947\r
5948\r
5949/**\r
5950 Package. Uncore C-box 7 perfmon event select MSR.\r
5951\r
5952 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)\r
5953 @param EAX Lower 32-bits of MSR value.\r
5954 @param EDX Upper 32-bits of MSR value.\r
5955\r
5956 <b>Example usage</b>\r
5957 @code\r
5958 UINT64 Msr;\r
5959\r
5960 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);\r
5961 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);\r
5962 @endcode\r
c2aa191b 5963 @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 5964**/\r
5965#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA\r
5966\r
5967\r
5968/**\r
5969 Package. Uncore C-box 7 perfmon counter MSR.\r
5970\r
5971 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)\r
5972 @param EAX Lower 32-bits of MSR value.\r
5973 @param EDX Upper 32-bits of MSR value.\r
5974\r
5975 <b>Example usage</b>\r
5976 @code\r
5977 UINT64 Msr;\r
5978\r
5979 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);\r
5980 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);\r
5981 @endcode\r
c2aa191b 5982 @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.\r
bd946618
MK		 5983**/\r
5984#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB\r
5985\r
5986\r
5987/**\r
5988 Package. Uncore R-box 0 perfmon local box control MSR.\r
5989\r
5990 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)\r
5991 @param EAX Lower 32-bits of MSR value.\r
5992 @param EDX Upper 32-bits of MSR value.\r
5993\r
5994 <b>Example usage</b>\r
5995 @code\r
5996 UINT64 Msr;\r
5997\r
5998 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);\r
5999 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);\r
6000 @endcode\r
c2aa191b 6001 @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 6002**/\r
6003#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00\r
6004\r
6005\r
6006/**\r
6007 Package. Uncore R-box 0 perfmon local box status MSR.\r
6008\r
6009 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)\r
6010 @param EAX Lower 32-bits of MSR value.\r
6011 @param EDX Upper 32-bits of MSR value.\r
6012\r
6013 <b>Example usage</b>\r
6014 @code\r
6015 UINT64 Msr;\r
6016\r
6017 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);\r
6018 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);\r
6019 @endcode\r
c2aa191b 6020 @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 6021**/\r
6022#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01\r
6023\r
6024\r
6025/**\r
6026 Package. Uncore R-box 0 perfmon local box overflow control MSR.\r
6027\r
6028 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)\r
6029 @param EAX Lower 32-bits of MSR value.\r
6030 @param EDX Upper 32-bits of MSR value.\r
6031\r
6032 <b>Example usage</b>\r
6033 @code\r
6034 UINT64 Msr;\r
6035\r
6036 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);\r
6037 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);\r
6038 @endcode\r
c2aa191b 6039 @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 6040**/\r
6041#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02\r
6042\r
6043\r
6044/**\r
6045 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.\r
6046\r
6047 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)\r
6048 @param EAX Lower 32-bits of MSR value.\r
6049 @param EDX Upper 32-bits of MSR value.\r
6050\r
6051 <b>Example usage</b>\r
6052 @code\r
6053 UINT64 Msr;\r
6054\r
6055 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);\r
6056 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);\r
6057 @endcode\r
c2aa191b 6058 @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.\r
bd946618
MK		 6059**/\r
6060#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04\r
6061\r
6062\r
6063/**\r
6064 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.\r
6065\r
6066 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)\r
6067 @param EAX Lower 32-bits of MSR value.\r
6068 @param EDX Upper 32-bits of MSR value.\r
6069\r
6070 <b>Example usage</b>\r
6071 @code\r
6072 UINT64 Msr;\r
6073\r
6074 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);\r
6075 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);\r
6076 @endcode\r
c2aa191b 6077 @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.\r
bd946618
MK		 6078**/\r
6079#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05\r
6080\r
6081\r
6082/**\r
6083 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.\r
6084\r
6085 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)\r
6086 @param EAX Lower 32-bits of MSR value.\r
6087 @param EDX Upper 32-bits of MSR value.\r
6088\r
6089 <b>Example usage</b>\r
6090 @code\r
6091 UINT64 Msr;\r
6092\r
6093 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);\r
6094 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);\r
6095 @endcode\r
c2aa191b 6096 @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.\r
bd946618
MK		 6097**/\r
6098#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06\r
6099\r
6100\r
6101/**\r
6102 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.\r
6103\r
6104 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)\r
6105 @param EAX Lower 32-bits of MSR value.\r
6106 @param EDX Upper 32-bits of MSR value.\r
6107\r
6108 <b>Example usage</b>\r
6109 @code\r
6110 UINT64 Msr;\r
6111\r
6112 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);\r
6113 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);\r
6114 @endcode\r
c2aa191b 6115 @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.\r
bd946618
MK		 6116**/\r
6117#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07\r
6118\r
6119\r
6120/**\r
6121 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.\r
6122\r
6123 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)\r
6124 @param EAX Lower 32-bits of MSR value.\r
6125 @param EDX Upper 32-bits of MSR value.\r
6126\r
6127 <b>Example usage</b>\r
6128 @code\r
6129 UINT64 Msr;\r
6130\r
6131 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);\r
6132 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);\r
6133 @endcode\r
c2aa191b 6134 @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.\r
bd946618
MK		 6135**/\r
6136#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08\r
6137\r
6138\r
6139/**\r
6140 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.\r
6141\r
6142 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)\r
6143 @param EAX Lower 32-bits of MSR value.\r
6144 @param EDX Upper 32-bits of MSR value.\r
6145\r
6146 <b>Example usage</b>\r
6147 @code\r
6148 UINT64 Msr;\r
6149\r
6150 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);\r
6151 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);\r
6152 @endcode\r
c2aa191b 6153 @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.\r
bd946618
MK		 6154**/\r
6155#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09\r
6156\r
6157\r
6158/**\r
6159 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.\r
6160\r
6161 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)\r
6162 @param EAX Lower 32-bits of MSR value.\r
6163 @param EDX Upper 32-bits of MSR value.\r
6164\r
6165 <b>Example usage</b>\r
6166 @code\r
6167 UINT64 Msr;\r
6168\r
6169 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);\r
6170 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);\r
6171 @endcode\r
c2aa191b 6172 @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.\r
bd946618
MK		 6173**/\r
6174#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A\r
6175\r
6176\r
6177/**\r
6178 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.\r
6179\r
6180 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)\r
6181 @param EAX Lower 32-bits of MSR value.\r
6182 @param EDX Upper 32-bits of MSR value.\r
6183\r
6184 <b>Example usage</b>\r
6185 @code\r
6186 UINT64 Msr;\r
6187\r
6188 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);\r
6189 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);\r
6190 @endcode\r
c2aa191b 6191 @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.\r
bd946618
MK		 6192**/\r
6193#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B\r
6194\r
6195\r
6196/**\r
6197 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.\r
6198\r
6199 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)\r
6200 @param EAX Lower 32-bits of MSR value.\r
6201 @param EDX Upper 32-bits of MSR value.\r
6202\r
6203 <b>Example usage</b>\r
6204 @code\r
6205 UINT64 Msr;\r
6206\r
6207 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);\r
6208 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);\r
6209 @endcode\r
c2aa191b 6210 @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.\r
bd946618
MK		 6211**/\r
6212#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C\r
6213\r
6214\r
6215/**\r
6216 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.\r
6217\r
6218 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)\r
6219 @param EAX Lower 32-bits of MSR value.\r
6220 @param EDX Upper 32-bits of MSR value.\r
6221\r
6222 <b>Example usage</b>\r
6223 @code\r
6224 UINT64 Msr;\r
6225\r
6226 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);\r
6227 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);\r
6228 @endcode\r
c2aa191b 6229 @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.\r
bd946618
MK		 6230**/\r
6231#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D\r
6232\r
6233\r
6234/**\r
6235 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.\r
6236\r
6237 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)\r
6238 @param EAX Lower 32-bits of MSR value.\r
6239 @param EDX Upper 32-bits of MSR value.\r
6240\r
6241 <b>Example usage</b>\r
6242 @code\r
6243 UINT64 Msr;\r
6244\r
6245 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);\r
6246 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);\r
6247 @endcode\r
c2aa191b 6248 @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.\r
bd946618
MK		 6249**/\r
6250#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E\r
6251\r
6252\r
6253/**\r
6254 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.\r
6255\r
6256 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)\r
6257 @param EAX Lower 32-bits of MSR value.\r
6258 @param EDX Upper 32-bits of MSR value.\r
6259\r
6260 <b>Example usage</b>\r
6261 @code\r
6262 UINT64 Msr;\r
6263\r
6264 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);\r
6265 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);\r
6266 @endcode\r
c2aa191b 6267 @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.\r
bd946618
MK		 6268**/\r
6269#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F\r
6270\r
6271\r
6272/**\r
6273 Package. Uncore R-box 0 perfmon event select MSR.\r
6274\r
6275 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)\r
6276 @param EAX Lower 32-bits of MSR value.\r
6277 @param EDX Upper 32-bits of MSR value.\r
6278\r
6279 <b>Example usage</b>\r
6280 @code\r
6281 UINT64 Msr;\r
6282\r
6283 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);\r
6284 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);\r
6285 @endcode\r
c2aa191b 6286 @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.\r
bd946618
MK		 6287**/\r
6288#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10\r
6289\r
6290\r
6291/**\r
6292 Package. Uncore R-box 0 perfmon counter MSR.\r
6293\r
6294 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)\r
6295 @param EAX Lower 32-bits of MSR value.\r
6296 @param EDX Upper 32-bits of MSR value.\r
6297\r
6298 <b>Example usage</b>\r
6299 @code\r
6300 UINT64 Msr;\r
6301\r
6302 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);\r
6303 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);\r
6304 @endcode\r
c2aa191b 6305 @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.\r
bd946618
MK		 6306**/\r
6307#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11\r
6308\r
6309\r
6310/**\r
6311 Package. Uncore R-box 0 perfmon event select MSR.\r
6312\r
6313 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)\r
6314 @param EAX Lower 32-bits of MSR value.\r
6315 @param EDX Upper 32-bits of MSR value.\r
6316\r
6317 <b>Example usage</b>\r
6318 @code\r
6319 UINT64 Msr;\r
6320\r
6321 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);\r
6322 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);\r
6323 @endcode\r
c2aa191b 6324 @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.\r
bd946618
MK		 6325**/\r
6326#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12\r
6327\r
6328\r
6329/**\r
6330 Package. Uncore R-box 0 perfmon counter MSR.\r
6331\r
6332 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)\r
6333 @param EAX Lower 32-bits of MSR value.\r
6334 @param EDX Upper 32-bits of MSR value.\r
6335\r
6336 <b>Example usage</b>\r
6337 @code\r
6338 UINT64 Msr;\r
6339\r
6340 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);\r
6341 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);\r
6342 @endcode\r
c2aa191b 6343 @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.\r
bd946618
MK		 6344**/\r
6345#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13\r
6346\r
6347\r
6348/**\r
6349 Package. Uncore R-box 0 perfmon event select MSR.\r
6350\r
6351 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)\r
6352 @param EAX Lower 32-bits of MSR value.\r
6353 @param EDX Upper 32-bits of MSR value.\r
6354\r
6355 <b>Example usage</b>\r
6356 @code\r
6357 UINT64 Msr;\r
6358\r
6359 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);\r
6360 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);\r
6361 @endcode\r
c2aa191b 6362 @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.\r
bd946618
MK		 6363**/\r
6364#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14\r
6365\r
6366\r
6367/**\r
6368 Package. Uncore R-box 0 perfmon counter MSR.\r
6369\r
6370 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)\r
6371 @param EAX Lower 32-bits of MSR value.\r
6372 @param EDX Upper 32-bits of MSR value.\r
6373\r
6374 <b>Example usage</b>\r
6375 @code\r
6376 UINT64 Msr;\r
6377\r
6378 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);\r
6379 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);\r
6380 @endcode\r
c2aa191b 6381 @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.\r
bd946618
MK		 6382**/\r
6383#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15\r
6384\r
6385\r
6386/**\r
6387 Package. Uncore R-box 0 perfmon event select MSR.\r
6388\r
6389 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)\r
6390 @param EAX Lower 32-bits of MSR value.\r
6391 @param EDX Upper 32-bits of MSR value.\r
6392\r
6393 <b>Example usage</b>\r
6394 @code\r
6395 UINT64 Msr;\r
6396\r
6397 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);\r
6398 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);\r
6399 @endcode\r
c2aa191b 6400 @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.\r
bd946618
MK		 6401**/\r
6402#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16\r
6403\r
6404\r
6405/**\r
6406 Package. Uncore R-box 0 perfmon counter MSR.\r
6407\r
6408 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)\r
6409 @param EAX Lower 32-bits of MSR value.\r
6410 @param EDX Upper 32-bits of MSR value.\r
6411\r
6412 <b>Example usage</b>\r
6413 @code\r
6414 UINT64 Msr;\r
6415\r
6416 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);\r
6417 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);\r
6418 @endcode\r
c2aa191b 6419 @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.\r
bd946618
MK		 6420**/\r
6421#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17\r
6422\r
6423\r
6424/**\r
6425 Package. Uncore R-box 0 perfmon event select MSR.\r
6426\r
6427 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)\r
6428 @param EAX Lower 32-bits of MSR value.\r
6429 @param EDX Upper 32-bits of MSR value.\r
6430\r
6431 <b>Example usage</b>\r
6432 @code\r
6433 UINT64 Msr;\r
6434\r
6435 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);\r
6436 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);\r
6437 @endcode\r
c2aa191b 6438 @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.\r
bd946618
MK		 6439**/\r
6440#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18\r
6441\r
6442\r
6443/**\r
6444 Package. Uncore R-box 0 perfmon counter MSR.\r
6445\r
6446 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)\r
6447 @param EAX Lower 32-bits of MSR value.\r
6448 @param EDX Upper 32-bits of MSR value.\r
6449\r
6450 <b>Example usage</b>\r
6451 @code\r
6452 UINT64 Msr;\r
6453\r
6454 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);\r
6455 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);\r
6456 @endcode\r
c2aa191b 6457 @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.\r
bd946618
MK		 6458**/\r
6459#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19\r
6460\r
6461\r
6462/**\r
6463 Package. Uncore R-box 0 perfmon event select MSR.\r
6464\r
6465 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)\r
6466 @param EAX Lower 32-bits of MSR value.\r
6467 @param EDX Upper 32-bits of MSR value.\r
6468\r
6469 <b>Example usage</b>\r
6470 @code\r
6471 UINT64 Msr;\r
6472\r
6473 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);\r
6474 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);\r
6475 @endcode\r
c2aa191b 6476 @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.\r
bd946618
MK		 6477**/\r
6478#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A\r
6479\r
6480\r
6481/**\r
6482 Package. Uncore R-box 0 perfmon counter MSR.\r
6483\r
6484 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)\r
6485 @param EAX Lower 32-bits of MSR value.\r
6486 @param EDX Upper 32-bits of MSR value.\r
6487\r
6488 <b>Example usage</b>\r
6489 @code\r
6490 UINT64 Msr;\r
6491\r
6492 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);\r
6493 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);\r
6494 @endcode\r
c2aa191b 6495 @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.\r
bd946618
MK		 6496**/\r
6497#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B\r
6498\r
6499\r
6500/**\r
6501 Package. Uncore R-box 0 perfmon event select MSR.\r
6502\r
6503 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)\r
6504 @param EAX Lower 32-bits of MSR value.\r
6505 @param EDX Upper 32-bits of MSR value.\r
6506\r
6507 <b>Example usage</b>\r
6508 @code\r
6509 UINT64 Msr;\r
6510\r
6511 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);\r
6512 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);\r
6513 @endcode\r
c2aa191b 6514 @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.\r
bd946618
MK		 6515**/\r
6516#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C\r
6517\r
6518\r
6519/**\r
6520 Package. Uncore R-box 0 perfmon counter MSR.\r
6521\r
6522 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)\r
6523 @param EAX Lower 32-bits of MSR value.\r
6524 @param EDX Upper 32-bits of MSR value.\r
6525\r
6526 <b>Example usage</b>\r
6527 @code\r
6528 UINT64 Msr;\r
6529\r
6530 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);\r
6531 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);\r
6532 @endcode\r
c2aa191b 6533 @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.\r
bd946618
MK		 6534**/\r
6535#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D\r
6536\r
6537\r
6538/**\r
6539 Package. Uncore R-box 0 perfmon event select MSR.\r
6540\r
6541 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)\r
6542 @param EAX Lower 32-bits of MSR value.\r
6543 @param EDX Upper 32-bits of MSR value.\r
6544\r
6545 <b>Example usage</b>\r
6546 @code\r
6547 UINT64 Msr;\r
6548\r
6549 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);\r
6550 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);\r
6551 @endcode\r
c2aa191b 6552 @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.\r
bd946618
MK		 6553**/\r
6554#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E\r
6555\r
6556\r
6557/**\r
6558 Package. Uncore R-box 0 perfmon counter MSR.\r
6559\r
6560 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)\r
6561 @param EAX Lower 32-bits of MSR value.\r
6562 @param EDX Upper 32-bits of MSR value.\r
6563\r
6564 <b>Example usage</b>\r
6565 @code\r
6566 UINT64 Msr;\r
6567\r
6568 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);\r
6569 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);\r
6570 @endcode\r
c2aa191b 6571 @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.\r
bd946618
MK		 6572**/\r
6573#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F\r
6574\r
6575\r
6576/**\r
6577 Package. Uncore R-box 1 perfmon local box control MSR.\r
6578\r
6579 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)\r
6580 @param EAX Lower 32-bits of MSR value.\r
6581 @param EDX Upper 32-bits of MSR value.\r
6582\r
6583 <b>Example usage</b>\r
6584 @code\r
6585 UINT64 Msr;\r
6586\r
6587 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);\r
6588 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);\r
6589 @endcode\r
c2aa191b 6590 @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.\r
bd946618
MK		 6591**/\r
6592#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20\r
6593\r
6594\r
6595/**\r
6596 Package. Uncore R-box 1 perfmon local box status MSR.\r
6597\r
6598 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)\r
6599 @param EAX Lower 32-bits of MSR value.\r
6600 @param EDX Upper 32-bits of MSR value.\r
6601\r
6602 <b>Example usage</b>\r
6603 @code\r
6604 UINT64 Msr;\r
6605\r
6606 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);\r
6607 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);\r
6608 @endcode\r
c2aa191b 6609 @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.\r
bd946618
MK		 6610**/\r
6611#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21\r
6612\r
6613\r
6614/**\r
6615 Package. Uncore R-box 1 perfmon local box overflow control MSR.\r
6616\r
6617 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)\r
6618 @param EAX Lower 32-bits of MSR value.\r
6619 @param EDX Upper 32-bits of MSR value.\r
6620\r
6621 <b>Example usage</b>\r
6622 @code\r
6623 UINT64 Msr;\r
6624\r
6625 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);\r
6626 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);\r
6627 @endcode\r
c2aa191b 6628 @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.\r
bd946618
MK		 6629**/\r
6630#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22\r
6631\r
6632\r
6633/**\r
6634 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.\r
6635\r
6636 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)\r
6637 @param EAX Lower 32-bits of MSR value.\r
6638 @param EDX Upper 32-bits of MSR value.\r
6639\r
6640 <b>Example usage</b>\r
6641 @code\r
6642 UINT64 Msr;\r
6643\r
6644 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);\r
6645 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);\r
6646 @endcode\r
c2aa191b 6647 @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.\r
bd946618
MK		 6648**/\r
6649#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24\r
6650\r
6651\r
6652/**\r
6653 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.\r
6654\r
6655 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)\r
6656 @param EAX Lower 32-bits of MSR value.\r
6657 @param EDX Upper 32-bits of MSR value.\r
6658\r
6659 <b>Example usage</b>\r
6660 @code\r
6661 UINT64 Msr;\r
6662\r
6663 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);\r
6664 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);\r
6665 @endcode\r
c2aa191b 6666 @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.\r
bd946618
MK		 6667**/\r
6668#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25\r
6669\r
6670\r
6671/**\r
6672 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.\r
6673\r
6674 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)\r
6675 @param EAX Lower 32-bits of MSR value.\r
6676 @param EDX Upper 32-bits of MSR value.\r
6677\r
6678 <b>Example usage</b>\r
6679 @code\r
6680 UINT64 Msr;\r
6681\r
6682 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);\r
6683 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);\r
6684 @endcode\r
c2aa191b 6685 @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.\r
bd946618
MK		 6686**/\r
6687#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26\r
6688\r
6689\r
6690/**\r
6691 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.\r
6692\r
6693 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)\r
6694 @param EAX Lower 32-bits of MSR value.\r
6695 @param EDX Upper 32-bits of MSR value.\r
6696\r
6697 <b>Example usage</b>\r
6698 @code\r
6699 UINT64 Msr;\r
6700\r
6701 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);\r
6702 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);\r
6703 @endcode\r
c2aa191b 6704 @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.\r
bd946618
MK		 6705**/\r
6706#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27\r
6707\r
6708\r
6709/**\r
6710 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.\r
6711\r
6712 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)\r
6713 @param EAX Lower 32-bits of MSR value.\r
6714 @param EDX Upper 32-bits of MSR value.\r
6715\r
6716 <b>Example usage</b>\r
6717 @code\r
6718 UINT64 Msr;\r
6719\r
6720 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);\r
6721 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);\r
6722 @endcode\r
c2aa191b 6723 @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.\r
bd946618
MK		 6724**/\r
6725#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28\r
6726\r
6727\r
6728/**\r
6729 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.\r
6730\r
6731 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)\r
6732 @param EAX Lower 32-bits of MSR value.\r
6733 @param EDX Upper 32-bits of MSR value.\r
6734\r
6735 <b>Example usage</b>\r
6736 @code\r
6737 UINT64 Msr;\r
6738\r
6739 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);\r
6740 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);\r
6741 @endcode\r
c2aa191b 6742 @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.\r
bd946618
MK		 6743**/\r
6744#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29\r
6745\r
6746\r
6747/**\r
6748 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.\r
6749\r
6750 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)\r
6751 @param EAX Lower 32-bits of MSR value.\r
6752 @param EDX Upper 32-bits of MSR value.\r
6753\r
6754 <b>Example usage</b>\r
6755 @code\r
6756 UINT64 Msr;\r
6757\r
6758 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);\r
6759 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);\r
6760 @endcode\r
c2aa191b 6761 @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.\r
bd946618
MK		 6762**/\r
6763#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A\r
6764\r
6765\r
6766/**\r
6767 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.\r
6768\r
6769 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)\r
6770 @param EAX Lower 32-bits of MSR value.\r
6771 @param EDX Upper 32-bits of MSR value.\r
6772\r
6773 <b>Example usage</b>\r
6774 @code\r
6775 UINT64 Msr;\r
6776\r
6777 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);\r
6778 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);\r
6779 @endcode\r
c2aa191b 6780 @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.\r
bd946618
MK		 6781**/\r
6782#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B\r
6783\r
6784\r
6785/**\r
6786 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.\r
6787\r
6788 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)\r
6789 @param EAX Lower 32-bits of MSR value.\r
6790 @param EDX Upper 32-bits of MSR value.\r
6791\r
6792 <b>Example usage</b>\r
6793 @code\r
6794 UINT64 Msr;\r
6795\r
6796 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);\r
6797 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);\r
6798 @endcode\r
c2aa191b 6799 @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.\r
bd946618
MK		 6800**/\r
6801#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C\r
6802\r
6803\r
6804/**\r
6805 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.\r
6806\r
6807 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)\r
6808 @param EAX Lower 32-bits of MSR value.\r
6809 @param EDX Upper 32-bits of MSR value.\r
6810\r
6811 <b>Example usage</b>\r
6812 @code\r
6813 UINT64 Msr;\r
6814\r
6815 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);\r
6816 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);\r
6817 @endcode\r
c2aa191b 6818 @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.\r
bd946618
MK		 6819**/\r
6820#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D\r
6821\r
6822\r
6823/**\r
6824 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.\r
6825\r
6826 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)\r
6827 @param EAX Lower 32-bits of MSR value.\r
6828 @param EDX Upper 32-bits of MSR value.\r
6829\r
6830 <b>Example usage</b>\r
6831 @code\r
6832 UINT64 Msr;\r
6833\r
6834 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);\r
6835 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);\r
6836 @endcode\r
c2aa191b 6837 @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.\r
bd946618
MK		 6838**/\r
6839#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E\r
6840\r
6841\r
6842/**\r
6843 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.\r
6844\r
6845 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)\r
6846 @param EAX Lower 32-bits of MSR value.\r
6847 @param EDX Upper 32-bits of MSR value.\r
6848\r
6849 <b>Example usage</b>\r
6850 @code\r
6851 UINT64 Msr;\r
6852\r
6853 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);\r
6854 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);\r
6855 @endcode\r
c2aa191b 6856 @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.\r
bd946618
MK		 6857**/\r
6858#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F\r
6859\r
6860\r
6861/**\r
6862 Package. Uncore R-box 1 perfmon event select MSR.\r
6863\r
6864 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)\r
6865 @param EAX Lower 32-bits of MSR value.\r
6866 @param EDX Upper 32-bits of MSR value.\r
6867\r
6868 <b>Example usage</b>\r
6869 @code\r
6870 UINT64 Msr;\r
6871\r
6872 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);\r
6873 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);\r
6874 @endcode\r
c2aa191b 6875 @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.\r
bd946618
MK		 6876**/\r
6877#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30\r
6878\r
6879\r
6880/**\r
6881 Package. Uncore R-box 1 perfmon counter MSR.\r
6882\r
6883 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)\r
6884 @param EAX Lower 32-bits of MSR value.\r
6885 @param EDX Upper 32-bits of MSR value.\r
6886\r
6887 <b>Example usage</b>\r
6888 @code\r
6889 UINT64 Msr;\r
6890\r
6891 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);\r
6892 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);\r
6893 @endcode\r
c2aa191b 6894 @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.\r
bd946618
MK		 6895**/\r
6896#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31\r
6897\r
6898\r
6899/**\r
6900 Package. Uncore R-box 1 perfmon event select MSR.\r
6901\r
6902 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)\r
6903 @param EAX Lower 32-bits of MSR value.\r
6904 @param EDX Upper 32-bits of MSR value.\r
6905\r
6906 <b>Example usage</b>\r
6907 @code\r
6908 UINT64 Msr;\r
6909\r
6910 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);\r
6911 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);\r
6912 @endcode\r
c2aa191b 6913 @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.\r
bd946618
MK		 6914**/\r
6915#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32\r
6916\r
6917\r
6918/**\r
6919 Package. Uncore R-box 1 perfmon counter MSR.\r
6920\r
6921 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)\r
6922 @param EAX Lower 32-bits of MSR value.\r
6923 @param EDX Upper 32-bits of MSR value.\r
6924\r
6925 <b>Example usage</b>\r
6926 @code\r
6927 UINT64 Msr;\r
6928\r
6929 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);\r
6930 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);\r
6931 @endcode\r
c2aa191b 6932 @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.\r
bd946618
MK		 6933**/\r
6934#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33\r
6935\r
6936\r
6937/**\r
6938 Package. Uncore R-box 1 perfmon event select MSR.\r
6939\r
6940 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)\r
6941 @param EAX Lower 32-bits of MSR value.\r
6942 @param EDX Upper 32-bits of MSR value.\r
6943\r
6944 <b>Example usage</b>\r
6945 @code\r
6946 UINT64 Msr;\r
6947\r
6948 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);\r
6949 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);\r
6950 @endcode\r
c2aa191b 6951 @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.\r
bd946618
MK		 6952**/\r
6953#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34\r
6954\r
6955\r
6956/**\r
6957 Package. Uncore R-box 1 perfmon counter MSR.\r
6958\r
6959 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)\r
6960 @param EAX Lower 32-bits of MSR value.\r
6961 @param EDX Upper 32-bits of MSR value.\r
6962\r
6963 <b>Example usage</b>\r
6964 @code\r
6965 UINT64 Msr;\r
6966\r
6967 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);\r
6968 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);\r
6969 @endcode\r
c2aa191b 6970 @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.\r
bd946618
MK		 6971**/\r
6972#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35\r
6973\r
6974\r
6975/**\r
6976 Package. Uncore R-box 1 perfmon event select MSR.\r
6977\r
6978 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)\r
6979 @param EAX Lower 32-bits of MSR value.\r
6980 @param EDX Upper 32-bits of MSR value.\r
6981\r
6982 <b>Example usage</b>\r
6983 @code\r
6984 UINT64 Msr;\r
6985\r
6986 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);\r
6987 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);\r
6988 @endcode\r
c2aa191b 6989 @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.\r
bd946618
MK		 6990**/\r
6991#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36\r
6992\r
6993\r
6994/**\r
6995 Package. Uncore R-box 1 perfmon counter MSR.\r
6996\r
6997 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)\r
6998 @param EAX Lower 32-bits of MSR value.\r
6999 @param EDX Upper 32-bits of MSR value.\r
7000\r
7001 <b>Example usage</b>\r
7002 @code\r
7003 UINT64 Msr;\r
7004\r
7005 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);\r
7006 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);\r
7007 @endcode\r
c2aa191b 7008 @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.\r
bd946618
MK		 7009**/\r
7010#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37\r
7011\r
7012\r
7013/**\r
7014 Package. Uncore R-box 1 perfmon event select MSR.\r
7015\r
7016 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)\r
7017 @param EAX Lower 32-bits of MSR value.\r
7018 @param EDX Upper 32-bits of MSR value.\r
7019\r
7020 <b>Example usage</b>\r
7021 @code\r
7022 UINT64 Msr;\r
7023\r
7024 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);\r
7025 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);\r
7026 @endcode\r
c2aa191b 7027 @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.\r
bd946618
MK		 7028**/\r
7029#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38\r
7030\r
7031\r
7032/**\r
7033 Package. Uncore R-box 1 perfmon counter MSR.\r
7034\r
7035 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)\r
7036 @param EAX Lower 32-bits of MSR value.\r
7037 @param EDX Upper 32-bits of MSR value.\r
7038\r
7039 <b>Example usage</b>\r
7040 @code\r
7041 UINT64 Msr;\r
7042\r
7043 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);\r
7044 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);\r
7045 @endcode\r
c2aa191b 7046 @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.\r
bd946618
MK		 7047**/\r
7048#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39\r
7049\r
7050\r
7051/**\r
7052 Package. Uncore R-box 1 perfmon event select MSR.\r
7053\r
7054 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)\r
7055 @param EAX Lower 32-bits of MSR value.\r
7056 @param EDX Upper 32-bits of MSR value.\r
7057\r
7058 <b>Example usage</b>\r
7059 @code\r
7060 UINT64 Msr;\r
7061\r
7062 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);\r
7063 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);\r
7064 @endcode\r
c2aa191b 7065 @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.\r
bd946618
MK		 7066**/\r
7067#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A\r
7068\r
7069\r
7070/**\r
7071 Package. Uncore R-box 1perfmon counter MSR.\r
7072\r
7073 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)\r
7074 @param EAX Lower 32-bits of MSR value.\r
7075 @param EDX Upper 32-bits of MSR value.\r
7076\r
7077 <b>Example usage</b>\r
7078 @code\r
7079 UINT64 Msr;\r
7080\r
7081 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);\r
7082 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);\r
7083 @endcode\r
c2aa191b 7084 @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.\r
bd946618
MK		 7085**/\r
7086#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B\r
7087\r
7088\r
7089/**\r
7090 Package. Uncore R-box 1 perfmon event select MSR.\r
7091\r
7092 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)\r
7093 @param EAX Lower 32-bits of MSR value.\r
7094 @param EDX Upper 32-bits of MSR value.\r
7095\r
7096 <b>Example usage</b>\r
7097 @code\r
7098 UINT64 Msr;\r
7099\r
7100 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);\r
7101 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);\r
7102 @endcode\r
c2aa191b 7103 @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.\r
bd946618
MK		 7104**/\r
7105#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C\r
7106\r
7107\r
7108/**\r
7109 Package. Uncore R-box 1 perfmon counter MSR.\r
7110\r
7111 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)\r
7112 @param EAX Lower 32-bits of MSR value.\r
7113 @param EDX Upper 32-bits of MSR value.\r
7114\r
7115 <b>Example usage</b>\r
7116 @code\r
7117 UINT64 Msr;\r
7118\r
7119 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);\r
7120 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);\r
7121 @endcode\r
c2aa191b 7122 @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.\r
bd946618
MK		 7123**/\r
7124#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D\r
7125\r
7126\r
7127/**\r
7128 Package. Uncore R-box 1 perfmon event select MSR.\r
7129\r
7130 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)\r
7131 @param EAX Lower 32-bits of MSR value.\r
7132 @param EDX Upper 32-bits of MSR value.\r
7133\r
7134 <b>Example usage</b>\r
7135 @code\r
7136 UINT64 Msr;\r
7137\r
7138 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);\r
7139 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);\r
7140 @endcode\r
c2aa191b 7141 @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.\r
bd946618
MK		 7142**/\r
7143#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E\r
7144\r
7145\r
7146/**\r
7147 Package. Uncore R-box 1 perfmon counter MSR.\r
7148\r
7149 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)\r
7150 @param EAX Lower 32-bits of MSR value.\r
7151 @param EDX Upper 32-bits of MSR value.\r
7152\r
7153 <b>Example usage</b>\r
7154 @code\r
7155 UINT64 Msr;\r
7156\r
7157 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);\r
7158 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);\r
7159 @endcode\r
c2aa191b 7160 @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.\r
bd946618
MK		 7161**/\r
7162#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F\r
7163\r
7164\r
7165/**\r
7166 Package. Uncore B-box 0 perfmon local box match MSR.\r
7167\r
7168 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)\r
7169 @param EAX Lower 32-bits of MSR value.\r
7170 @param EDX Upper 32-bits of MSR value.\r
7171\r
7172 <b>Example usage</b>\r
7173 @code\r
7174 UINT64 Msr;\r
7175\r
7176 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);\r
7177 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);\r
7178 @endcode\r
c2aa191b 7179 @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.\r
bd946618
MK		 7180**/\r
7181#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45\r
7182\r
7183\r
7184/**\r
7185 Package. Uncore B-box 0 perfmon local box mask MSR.\r
7186\r
7187 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)\r
7188 @param EAX Lower 32-bits of MSR value.\r
7189 @param EDX Upper 32-bits of MSR value.\r
7190\r
7191 <b>Example usage</b>\r
7192 @code\r
7193 UINT64 Msr;\r
7194\r
7195 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);\r
7196 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);\r
7197 @endcode\r
c2aa191b 7198 @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.\r
bd946618
MK		 7199**/\r
7200#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46\r
7201\r
7202\r
7203/**\r
7204 Package. Uncore S-box 0 perfmon local box match MSR.\r
7205\r
7206 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)\r
7207 @param EAX Lower 32-bits of MSR value.\r
7208 @param EDX Upper 32-bits of MSR value.\r
7209\r
7210 <b>Example usage</b>\r
7211 @code\r
7212 UINT64 Msr;\r
7213\r
7214 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);\r
7215 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);\r
7216 @endcode\r
c2aa191b 7217 @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.\r
bd946618
MK		 7218**/\r
7219#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49\r
7220\r
7221\r
7222/**\r
7223 Package. Uncore S-box 0 perfmon local box mask MSR.\r
7224\r
7225 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)\r
7226 @param EAX Lower 32-bits of MSR value.\r
7227 @param EDX Upper 32-bits of MSR value.\r
7228\r
7229 <b>Example usage</b>\r
7230 @code\r
7231 UINT64 Msr;\r
7232\r
7233 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);\r
7234 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);\r
7235 @endcode\r
c2aa191b 7236 @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.\r
bd946618
MK		 7237**/\r
7238#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A\r
7239\r
7240\r
7241/**\r
7242 Package. Uncore B-box 1 perfmon local box match MSR.\r
7243\r
7244 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)\r
7245 @param EAX Lower 32-bits of MSR value.\r
7246 @param EDX Upper 32-bits of MSR value.\r
7247\r
7248 <b>Example usage</b>\r
7249 @code\r
7250 UINT64 Msr;\r
7251\r
7252 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);\r
7253 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);\r
7254 @endcode\r
c2aa191b 7255 @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.\r
bd946618
MK		 7256**/\r
7257#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D\r
7258\r
7259\r
7260/**\r
7261 Package. Uncore B-box 1 perfmon local box mask MSR.\r
7262\r
7263 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)\r
7264 @param EAX Lower 32-bits of MSR value.\r
7265 @param EDX Upper 32-bits of MSR value.\r
7266\r
7267 <b>Example usage</b>\r
7268 @code\r
7269 UINT64 Msr;\r
7270\r
7271 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);\r
7272 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);\r
7273 @endcode\r
c2aa191b 7274 @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.\r
bd946618
MK		 7275**/\r
7276#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E\r
7277\r
7278\r
7279/**\r
7280 Package. Uncore M-box 0 perfmon local box address match/mask config MSR.\r
7281\r
7282 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)\r
7283 @param EAX Lower 32-bits of MSR value.\r
7284 @param EDX Upper 32-bits of MSR value.\r
7285\r
7286 <b>Example usage</b>\r
7287 @code\r
7288 UINT64 Msr;\r
7289\r
7290 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);\r
7291 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);\r
7292 @endcode\r
c2aa191b 7293 @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.\r
bd946618
MK		 7294**/\r
7295#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54\r
7296\r
7297\r
7298/**\r
7299 Package. Uncore M-box 0 perfmon local box address match MSR.\r
7300\r
7301 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)\r
7302 @param EAX Lower 32-bits of MSR value.\r
7303 @param EDX Upper 32-bits of MSR value.\r
7304\r
7305 <b>Example usage</b>\r
7306 @code\r
7307 UINT64 Msr;\r
7308\r
7309 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);\r
7310 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);\r
7311 @endcode\r
c2aa191b 7312 @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.\r
bd946618
MK		 7313**/\r
7314#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55\r
7315\r
7316\r
7317/**\r
7318 Package. Uncore M-box 0 perfmon local box address mask MSR.\r
7319\r
7320 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)\r
7321 @param EAX Lower 32-bits of MSR value.\r
7322 @param EDX Upper 32-bits of MSR value.\r
7323\r
7324 <b>Example usage</b>\r
7325 @code\r
7326 UINT64 Msr;\r
7327\r
7328 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);\r
7329 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);\r
7330 @endcode\r
c2aa191b 7331 @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.\r
bd946618
MK		 7332**/\r
7333#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56\r
7334\r
7335\r
7336/**\r
7337 Package. Uncore S-box 1 perfmon local box match MSR.\r
7338\r
7339 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)\r
7340 @param EAX Lower 32-bits of MSR value.\r
7341 @param EDX Upper 32-bits of MSR value.\r
7342\r
7343 <b>Example usage</b>\r
7344 @code\r
7345 UINT64 Msr;\r
7346\r
7347 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);\r
7348 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);\r
7349 @endcode\r
c2aa191b 7350 @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.\r
bd946618
MK		 7351**/\r
7352#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59\r
7353\r
7354\r
7355/**\r
7356 Package. Uncore S-box 1 perfmon local box mask MSR.\r
7357\r
7358 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)\r
7359 @param EAX Lower 32-bits of MSR value.\r
7360 @param EDX Upper 32-bits of MSR value.\r
7361\r
7362 <b>Example usage</b>\r
7363 @code\r
7364 UINT64 Msr;\r
7365\r
7366 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);\r
7367 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);\r
7368 @endcode\r
c2aa191b 7369 @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.\r
bd946618
MK		 7370**/\r
7371#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A\r
7372\r
7373\r
7374/**\r
7375 Package. Uncore M-box 1 perfmon local box address match/mask config MSR.\r
7376\r
7377 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)\r
7378 @param EAX Lower 32-bits of MSR value.\r
7379 @param EDX Upper 32-bits of MSR value.\r
7380\r
7381 <b>Example usage</b>\r
7382 @code\r
7383 UINT64 Msr;\r
7384\r
7385 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);\r
7386 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);\r
7387 @endcode\r
c2aa191b 7388 @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.\r
bd946618
MK		 7389**/\r
7390#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C\r
7391\r
7392\r
7393/**\r
7394 Package. Uncore M-box 1 perfmon local box address match MSR.\r
7395\r
7396 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)\r
7397 @param EAX Lower 32-bits of MSR value.\r
7398 @param EDX Upper 32-bits of MSR value.\r
7399\r
7400 <b>Example usage</b>\r
7401 @code\r
7402 UINT64 Msr;\r
7403\r
7404 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);\r
7405 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);\r
7406 @endcode\r
c2aa191b 7407 @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.\r
bd946618
MK		 7408**/\r
7409#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D\r
7410\r
7411\r
7412/**\r
7413 Package. Uncore M-box 1 perfmon local box address mask MSR.\r
7414\r
7415 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)\r
7416 @param EAX Lower 32-bits of MSR value.\r
7417 @param EDX Upper 32-bits of MSR value.\r
7418\r
7419 <b>Example usage</b>\r
7420 @code\r
7421 UINT64 Msr;\r
7422\r
7423 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);\r
7424 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);\r
7425 @endcode\r
c2aa191b 7426 @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.\r
bd946618
MK		 7427**/\r
7428#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E\r
7429\r
7430#endif\r
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