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[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / PentiumMMsr.h
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83d4e58c
MK		 1/** @file\r
2 MSR Definitions for Pentium M Processors.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
f4c982bf 9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
83d4e58c
MK		 10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
0f16be6d 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.\r
83d4e58c
MK		 21\r
22**/\r
23\r
24#ifndef __PENTIUM_M_MSR_H__\r
25#define __PENTIUM_M_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
f4c982bf
JF		 29/**\r
30 Is Pentium M Processors?\r
31\r
32 @param DisplayFamily Display Family ID\r
33 @param DisplayModel Display Model ID\r
34\r
35 @retval TRUE Yes, it is.\r
36 @retval FALSE No, it isn't.\r
37**/\r
38#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \\r
39 (DisplayFamily == 0x06 && \\r
40 ( \\r
41 DisplayModel == 0x0D \\r
42 ) \\r
43 )\r
44\r
83d4e58c 45/**\r
0f16be6d 46 See Section 35.22, "MSRs in Pentium Processors.".\r
83d4e58c
MK		 47\r
48 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)\r
49 @param EAX Lower 32-bits of MSR value.\r
50 @param EDX Upper 32-bits of MSR value.\r
51\r
52 <b>Example usage</b>\r
53 @code\r
54 UINT64 Msr;\r
55\r
56 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
57 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
58 @endcode\r
65ee84bd 59 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
83d4e58c
MK		 60**/\r
61#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
62\r
63\r
64/**\r
0f16be6d 65 See Section 35.22, "MSRs in Pentium Processors.".\r
83d4e58c
MK		 66\r
67 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)\r
68 @param EAX Lower 32-bits of MSR value.\r
69 @param EDX Upper 32-bits of MSR value.\r
70\r
71 <b>Example usage</b>\r
72 @code\r
73 UINT64 Msr;\r
74\r
75 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
76 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
77 @endcode\r
65ee84bd 78 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
83d4e58c
MK		 79**/\r
80#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
81\r
82\r
83/**\r
84 Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
85 features. (R) Indicates current processor configuration.\r
86\r
87 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)\r
88 @param EAX Lower 32-bits of MSR value.\r
89 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
90 @param EDX Upper 32-bits of MSR value.\r
91 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
92\r
93 <b>Example usage</b>\r
94 @code\r
95 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;\r
96\r
97 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
98 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
99 @endcode\r
65ee84bd 100 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
83d4e58c
MK		 101**/\r
102#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
103\r
104/**\r
105 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON\r
106**/\r
107typedef union {\r
108 ///\r
109 /// Individual bit fields\r
110 ///\r
111 struct {\r
112 UINT32 Reserved1:1;\r
113 ///\r
114 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the\r
115 /// Pentium M processor.\r
116 ///\r
117 UINT32 DataErrorCheckingEnable:1;\r
118 ///\r
119 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on\r
120 /// the Pentium M processor.\r
121 ///\r
122 UINT32 ResponseErrorCheckingEnable:1;\r
123 ///\r
124 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium\r
125 /// M processor.\r
126 ///\r
127 UINT32 MCERR_DriveEnable:1;\r
128 ///\r
129 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium\r
130 /// M processor.\r
131 ///\r
132 UINT32 AddressParityEnable:1;\r
133 UINT32 Reserved2:2;\r
134 ///\r
135 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on\r
136 /// the Pentium M processor.\r
137 ///\r
138 UINT32 BINIT_DriverEnable:1;\r
139 ///\r
140 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
141 ///\r
142 UINT32 OutputTriStateEnable:1;\r
143 ///\r
144 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
145 ///\r
146 UINT32 ExecuteBIST:1;\r
147 ///\r
148 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
149 /// Always 0 on the Pentium M processor.\r
150 ///\r
151 UINT32 MCERR_ObservationEnabled:1;\r
152 UINT32 Reserved3:1;\r
153 ///\r
154 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
155 /// Always 0 on the Pentium M processor.\r
156 ///\r
157 UINT32 BINIT_ObservationEnabled:1;\r
158 UINT32 Reserved4:1;\r
159 ///\r
160 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes\r
161 /// Always 0 on the Pentium M processor.\r
162 ///\r
163 UINT32 ResetVector:1;\r
164 UINT32 Reserved5:1;\r
165 ///\r
166 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M\r
167 /// processor.\r
168 ///\r
169 UINT32 APICClusterID:2;\r
170 ///\r
171 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always\r
172 /// 0 on the Pentium M processor.\r
173 ///\r
174 UINT32 SystemBusFrequency:1;\r
175 UINT32 Reserved6:1;\r
176 ///\r
177 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium\r
178 /// M processor.\r
179 ///\r
180 UINT32 SymmetricArbitrationID:2;\r
181 ///\r
182 /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
183 ///\r
184 UINT32 ClockFrequencyRatio:5;\r
185 UINT32 Reserved7:5;\r
186 UINT32 Reserved8:32;\r
187 } Bits;\r
188 ///\r
189 /// All bit fields as a 32-bit value\r
190 ///\r
191 UINT32 Uint32;\r
192 ///\r
193 /// All bit fields as a 64-bit value\r
194 ///\r
195 UINT64 Uint64;\r
196} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;\r
197\r
198\r
199/**\r
200 Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
201 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
202 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section\r
0f16be6d 203 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
83d4e58c
MK		 204 Processors)".\r
205\r
206 @param ECX MSR_PENTIUM_M_LASTBRANCH_n\r
207 @param EAX Lower 32-bits of MSR value.\r
208 @param EDX Upper 32-bits of MSR value.\r
209\r
210 <b>Example usage</b>\r
211 @code\r
212 UINT64 Msr;\r
213\r
214 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
215 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
216 @endcode\r
65ee84bd
JF		 217 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
218 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
219 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
220 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
221 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
222 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
223 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
224 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
83d4e58c
MK		 225 @{\r
226**/\r
227#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
228#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
229#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
230#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
231#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
232#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
233#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
234#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
235/// @}\r
236\r
237\r
238/**\r
239 Reserved.\r
240\r
241 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)\r
242 @param EAX Lower 32-bits of MSR value.\r
243 @param EDX Upper 32-bits of MSR value.\r
244\r
245 <b>Example usage</b>\r
246 @code\r
247 UINT64 Msr;\r
248\r
249 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
250 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
251 @endcode\r
65ee84bd 252 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
83d4e58c
MK		 253**/\r
254#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
255\r
256\r
257/**\r
258\r
259\r
260 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)\r
261 @param EAX Lower 32-bits of MSR value.\r
262 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
263 @param EDX Upper 32-bits of MSR value.\r
264 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
265\r
266 <b>Example usage</b>\r
267 @code\r
268 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;\r
269\r
270 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
271 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
272 @endcode\r
65ee84bd 273 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
83d4e58c
MK		 274**/\r
275#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
276\r
277/**\r
278 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3\r
279**/\r
280typedef union {\r
281 ///\r
282 /// Individual bit fields\r
283 ///\r
284 struct {\r
285 ///\r
286 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
287 /// Indicates if the L2 is hardware-disabled.\r
288 ///\r
289 UINT32 L2HardwareEnabled:1;\r
290 UINT32 Reserved1:4;\r
291 ///\r
292 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the\r
293 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled\r
294 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on\r
295 /// the cache data bus is always enabled.\r
296 ///\r
297 UINT32 ECCCheckEnable:1;\r
298 UINT32 Reserved2:2;\r
299 ///\r
300 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
301 /// Disabled (default) Until this bit is set the processor will not\r
302 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
303 ///\r
304 UINT32 L2Enabled:1;\r
305 UINT32 Reserved3:14;\r
306 ///\r
307 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
308 ///\r
309 UINT32 L2NotPresent:1;\r
310 UINT32 Reserved4:8;\r
311 UINT32 Reserved5:32;\r
312 } Bits;\r
313 ///\r
314 /// All bit fields as a 32-bit value\r
315 ///\r
316 UINT32 Uint32;\r
317 ///\r
318 /// All bit fields as a 64-bit value\r
319 ///\r
320 UINT64 Uint64;\r
321} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;\r
322\r
323\r
324/**\r
325\r
326\r
327 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)\r
328 @param EAX Lower 32-bits of MSR value.\r
329 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
330 @param EDX Upper 32-bits of MSR value.\r
331 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
332\r
333 <b>Example usage</b>\r
334 @code\r
335 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;\r
336\r
337 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
338 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
339 @endcode\r
65ee84bd 340 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
83d4e58c
MK		 341**/\r
342#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
343\r
344/**\r
345 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL\r
346**/\r
347typedef union {\r
348 ///\r
349 /// Individual bit fields\r
350 ///\r
351 struct {\r
352 UINT32 Reserved1:16;\r
353 ///\r
354 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
355 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
356 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
357 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
358 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
359 ///\r
360 UINT32 TM_SELECT:1;\r
361 UINT32 Reserved2:15;\r
362 UINT32 Reserved3:32;\r
363 } Bits;\r
364 ///\r
365 /// All bit fields as a 32-bit value\r
366 ///\r
367 UINT32 Uint32;\r
368 ///\r
369 /// All bit fields as a 64-bit value\r
370 ///\r
371 UINT64 Uint64;\r
372} MSR_PENTIUM_M_THERM2_CTL_REGISTER;\r
373\r
374\r
375/**\r
376 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
377 functions to be enabled and disabled.\r
378\r
379 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)\r
380 @param EAX Lower 32-bits of MSR value.\r
381 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
382 @param EDX Upper 32-bits of MSR value.\r
383 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
384\r
385 <b>Example usage</b>\r
386 @code\r
387 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;\r
388\r
389 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
390 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
391 @endcode\r
65ee84bd 392 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
83d4e58c
MK		 393**/\r
394#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
395\r
396/**\r
397 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE\r
398**/\r
399typedef union {\r
400 ///\r
401 /// Individual bit fields\r
402 ///\r
403 struct {\r
404 UINT32 Reserved1:3;\r
405 ///\r
406 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
407 /// this bit enables the thermal control circuit (TCC) portion of the\r
408 /// Intel Thermal Monitor feature. This allows processor clocks to be\r
409 /// automatically modulated based on the processor's thermal sensor\r
410 /// operation. 0 = Disabled (default). The automatic thermal control\r
411 /// circuit enable bit determines if the thermal control circuit (TCC)\r
412 /// will be activated when the processor's internal thermal sensor\r
413 /// determines the processor is about to exceed its maximum operating\r
414 /// temperature. When the TCC is activated and TM1 is enabled, the\r
415 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable\r
416 /// this feature. The bit should not be confused with the on-demand\r
417 /// thermal control circuit enable bit.\r
418 ///\r
419 UINT32 AutomaticThermalControlCircuit:1;\r
420 UINT32 Reserved2:3;\r
421 ///\r
422 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
423 /// monitoring enabled 0 = Performance monitoring disabled.\r
424 ///\r
425 UINT32 PerformanceMonitoring:1;\r
426 UINT32 Reserved3:2;\r
427 ///\r
428 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the\r
429 /// processor to indicate a pending break event within the processor 0 =\r
430 /// Indicates compatible FERR# signaling behavior This bit must be set to\r
431 /// 1 to support XAPIC interrupt model usage.\r
432 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't\r
433 /// support branch trace storage (BTS) 0 = BTS is supported\r
434 ///\r
435 UINT32 FERR:1;\r
436 ///\r
437 /// [Bit 11] Branch Trace Storage Unavailable (RO)\r
438 /// 1 = Processor doesn't support branch trace storage (BTS)\r
439 /// 0 = BTS is supported\r
440 ///\r
441 UINT32 BTS:1;\r
442 ///\r
0f16be6d
HW		 443 /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =\r
444 /// Processor does not support processor event based sampling (PEBS); 0 =\r
445 /// PEBS is supported. The Pentium M processor does not support PEBS.\r
83d4e58c
MK		 446 ///\r
447 UINT32 PEBS:1;\r
448 UINT32 Reserved5:3;\r
449 ///\r
450 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
451 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M\r
452 /// processor, this bit may be configured to be read-only.\r
453 ///\r
454 UINT32 EIST:1;\r
455 UINT32 Reserved6:6;\r
456 ///\r
457 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
458 /// disabled. xTPR messages are optional messages that allow the processor\r
459 /// to inform the chipset of its priority. The default is processor\r
460 /// specific.\r
461 ///\r
462 UINT32 xTPR_Message_Disable:1;\r
463 UINT32 Reserved7:8;\r
464 UINT32 Reserved8:32;\r
465 } Bits;\r
466 ///\r
467 /// All bit fields as a 32-bit value\r
468 ///\r
469 UINT32 Uint32;\r
470 ///\r
471 /// All bit fields as a 64-bit value\r
472 ///\r
473 UINT64 Uint64;\r
474} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;\r
475\r
476\r
477/**\r
478 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
479 to the MSR containing the most recent branch record. See also: -\r
0f16be6d 480 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,\r
83d4e58c
MK		 481 and Exception Recording (Pentium M Processors)".\r
482\r
483 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)\r
484 @param EAX Lower 32-bits of MSR value.\r
485 @param EDX Upper 32-bits of MSR value.\r
486\r
487 <b>Example usage</b>\r
488 @code\r
489 UINT64 Msr;\r
490\r
491 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
492 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
493 @endcode\r
65ee84bd 494 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
83d4e58c
MK		 495**/\r
496#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
497\r
498\r
499/**\r
500 Debug Control (R/W) Controls how several debug features are used. Bit\r
0f16be6d 501 definitions are discussed in the referenced section. See Section 17.13,\r
83d4e58c
MK		 502 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".\r
503\r
504 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)\r
505 @param EAX Lower 32-bits of MSR value.\r
506 @param EDX Upper 32-bits of MSR value.\r
507\r
508 <b>Example usage</b>\r
509 @code\r
510 UINT64 Msr;\r
511\r
512 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
513 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
514 @endcode\r
65ee84bd 515 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
83d4e58c
MK		 516**/\r
517#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
518\r
519\r
520/**\r
521 Last Exception Record To Linear IP (R) This area contains a pointer to the\r
522 target of the last branch instruction that the processor executed prior to\r
523 the last exception that was generated or the last interrupt that was\r
0f16be6d
HW		 524 handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording\r
525 (Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception\r
83d4e58c
MK		 526 MSRs.".\r
527\r
528 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)\r
529 @param EAX Lower 32-bits of MSR value.\r
530 @param EDX Upper 32-bits of MSR value.\r
531\r
532 <b>Example usage</b>\r
533 @code\r
534 UINT64 Msr;\r
535\r
536 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
537 @endcode\r
65ee84bd 538 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
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MK		 539**/\r
540#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
541\r
542\r
543/**\r
544 Last Exception Record From Linear IP (R) Contains a pointer to the last\r
545 branch instruction that the processor executed prior to the last exception\r
546 that was generated or the last interrupt that was handled. See Section\r
0f16be6d
HW		 547 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
548 Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".\r
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MK		 549\r
550 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)\r
551 @param EAX Lower 32-bits of MSR value.\r
552 @param EDX Upper 32-bits of MSR value.\r
553\r
554 <b>Example usage</b>\r
555 @code\r
556 UINT64 Msr;\r
557\r
558 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
559 @endcode\r
65ee84bd 560 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
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MK		 561**/\r
562#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
563\r
564\r
565/**\r
566 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
567\r
568 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)\r
569 @param EAX Lower 32-bits of MSR value.\r
570 @param EDX Upper 32-bits of MSR value.\r
571\r
572 <b>Example usage</b>\r
573 @code\r
574 UINT64 Msr;\r
575\r
576 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
577 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
578 @endcode\r
65ee84bd 579 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
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MK		 580**/\r
581#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
582\r
583\r
584/**\r
585 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
586\r
587 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)\r
588 @param EAX Lower 32-bits of MSR value.\r
589 @param EDX Upper 32-bits of MSR value.\r
590\r
591 <b>Example usage</b>\r
592 @code\r
593 UINT64 Msr;\r
594\r
595 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
596 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
597 @endcode\r
65ee84bd 598 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
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MK		 599**/\r
600#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
601\r
602\r
603/**\r
604 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is\r
605 either not implemented or contains no address if the ADDRV flag in the\r
606 MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
607 reads and writes to this MSR will cause a general-protection exception.\r
608\r
609 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)\r
610 @param EAX Lower 32-bits of MSR value.\r
611 @param EDX Upper 32-bits of MSR value.\r
612\r
613 <b>Example usage</b>\r
614 @code\r
615 UINT64 Msr;\r
616\r
617 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
618 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
619 @endcode\r
65ee84bd 620 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
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MK		 621**/\r
622#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
623\r
624\r
625/**\r
626 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
627\r
628 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)\r
629 @param EAX Lower 32-bits of MSR value.\r
630 @param EDX Upper 32-bits of MSR value.\r
631\r
632 <b>Example usage</b>\r
633 @code\r
634 UINT64 Msr;\r
635\r
636 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
637 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
638 @endcode\r
65ee84bd 639 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
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MK		 640**/\r
641#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
642\r
643\r
644/**\r
645 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
646\r
647 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)\r
648 @param EAX Lower 32-bits of MSR value.\r
649 @param EDX Upper 32-bits of MSR value.\r
650\r
651 <b>Example usage</b>\r
652 @code\r
653 UINT64 Msr;\r
654\r
655 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
656 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
657 @endcode\r
65ee84bd 658 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
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MK		 659**/\r
660#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
661\r
662\r
663/**\r
664 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is\r
665 either not implemented or contains no address if the ADDRV flag in the\r
666 MSR_MC3_STATUS register is clear. When not implemented in the processor, all\r
667 reads and writes to this MSR will cause a general-protection exception.\r
668\r
669 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)\r
670 @param EAX Lower 32-bits of MSR value.\r
671 @param EDX Upper 32-bits of MSR value.\r
672\r
673 <b>Example usage</b>\r
674 @code\r
675 UINT64 Msr;\r
676\r
677 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
678 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
679 @endcode\r
65ee84bd 680 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
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MK		 681**/\r
682#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
683\r
684#endif\r
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