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UefiCpuPkg/Msr: Add CPUID signature check MACROs
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / SkylakeMsr.h
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6b55a245
MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Skylake microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
f4c982bf 9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
6b55a245
MK		 10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
37cea63f 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.\r
6b55a245
MK		 21\r
22**/\r
23\r
24#ifndef __SKYLAKE_MSR_H__\r
25#define __SKYLAKE_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
f4c982bf
JF		 29/**\r
30 Is Intel processors based on the Skylake microarchitecture?\r
31\r
32 @param DisplayFamily Display Family ID\r
33 @param DisplayModel Display Model ID\r
34\r
35 @retval TRUE Yes, it is.\r
36 @retval FALSE No, it isn't.\r
37**/\r
38#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \\r
39 (DisplayFamily == 0x06 && \\r
40 ( \\r
41 DisplayModel == 0x4E || \\r
42 DisplayModel == 0x5E \\r
43 ) \\r
44 )\r
45\r
6b55a245
MK		 46/**\r
47 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
48 RW if MSR_PLATFORM_INFO.[28] = 1.\r
49\r
50 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)\r
51 @param EAX Lower 32-bits of MSR value.\r
52 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
53 @param EDX Upper 32-bits of MSR value.\r
54 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
55\r
56 <b>Example usage</b>\r
57 @code\r
58 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
59\r
60 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);\r
61 @endcode\r
04e7a465 62 @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
6b55a245
MK		 63**/\r
64#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
65\r
66/**\r
67 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r
68**/\r
69typedef union {\r
70 ///\r
71 /// Individual bit fields\r
72 ///\r
73 struct {\r
74 ///\r
75 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
76 /// limit of 1 core active.\r
77 ///\r
78 UINT32 Maximum1C:8;\r
79 ///\r
80 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
81 /// limit of 2 core active.\r
82 ///\r
83 UINT32 Maximum2C:8;\r
84 ///\r
85 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
86 /// limit of 3 core active.\r
87 ///\r
88 UINT32 Maximum3C:8;\r
89 ///\r
90 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
91 /// limit of 4 core active.\r
92 ///\r
93 UINT32 Maximum4C:8;\r
94 UINT32 Reserved:32;\r
95 } Bits;\r
96 ///\r
97 /// All bit fields as a 32-bit value\r
98 ///\r
99 UINT32 Uint32;\r
100 ///\r
101 /// All bit fields as a 64-bit value\r
102 ///\r
103 UINT64 Uint64;\r
104} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r
105\r
106\r
107/**\r
108 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)\r
109 that points to the MSR containing the most recent branch record.\r
110\r
111 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)\r
112 @param EAX Lower 32-bits of MSR value.\r
113 @param EDX Upper 32-bits of MSR value.\r
114\r
115 <b>Example usage</b>\r
116 @code\r
117 UINT64 Msr;\r
118\r
119 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);\r
120 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);\r
121 @endcode\r
04e7a465 122 @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
6b55a245
MK		 123**/\r
124#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
125\r
126\r
127/**\r
128 Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of\r
129 an 128-bit external entropy value for key derivation of an enclave.\r
130\r
131 @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300)\r
132 @param EAX Lower 32-bits of MSR value.\r
133 @param EDX Upper 32-bits of MSR value.\r
134\r
135 <b>Example usage</b>\r
136 @code\r
137 UINT64 Msr;\r
138\r
139 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);\r
140 @endcode\r
04e7a465 141 @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.\r
6b55a245
MK		 142**/\r
143#define MSR_SKYLAKE_SGXOWNER0 0x00000300\r
144\r
145\r
146/**\r
147 Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r
148 an 128-bit external entropy value for key derivation of an enclave.\r
149\r
150 @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301)\r
151 @param EAX Lower 32-bits of MSR value.\r
152 @param EDX Upper 32-bits of MSR value.\r
153\r
154 <b>Example usage</b>\r
155 @code\r
156 UINT64 Msr;\r
157\r
158 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);\r
159 @endcode\r
04e7a465 160 @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.\r
6b55a245
MK		 161**/\r
162#define MSR_SKYLAKE_SGXOWNER1 0x00000301\r
163\r
164\r
165/**\r
37cea63f
HW		 166 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring\r
167 Version 4.".\r
6b55a245 168\r
37cea63f 169 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
6b55a245 170 @param EAX Lower 32-bits of MSR value.\r
37cea63f 171 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
6b55a245 172 @param EDX Upper 32-bits of MSR value.\r
37cea63f 173 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
6b55a245
MK		 174\r
175 <b>Example usage</b>\r
176 @code\r
37cea63f 177 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
6b55a245 178\r
37cea63f
HW		 179 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);\r
180 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
6b55a245 181 @endcode\r
37cea63f 182 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
6b55a245 183**/\r
37cea63f 184#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
6b55a245
MK		 185\r
186/**\r
37cea63f 187 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r
6b55a245
MK		 188**/\r
189typedef union {\r
190 ///\r
191 /// Individual bit fields\r
192 ///\r
193 struct {\r
194 ///\r
195 /// [Bit 0] Thread. Ovf_PMC0.\r
196 ///\r
197 UINT32 Ovf_PMC0:1;\r
198 ///\r
199 /// [Bit 1] Thread. Ovf_PMC1.\r
200 ///\r
201 UINT32 Ovf_PMC1:1;\r
202 ///\r
203 /// [Bit 2] Thread. Ovf_PMC2.\r
204 ///\r
205 UINT32 Ovf_PMC2:1;\r
206 ///\r
207 /// [Bit 3] Thread. Ovf_PMC3.\r
208 ///\r
209 UINT32 Ovf_PMC3:1;\r
210 ///\r
211 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
212 ///\r
213 UINT32 Ovf_PMC4:1;\r
214 ///\r
215 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
216 ///\r
217 UINT32 Ovf_PMC5:1;\r
218 ///\r
219 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
220 ///\r
221 UINT32 Ovf_PMC6:1;\r
222 ///\r
223 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
224 ///\r
225 UINT32 Ovf_PMC7:1;\r
226 UINT32 Reserved1:24;\r
227 ///\r
228 /// [Bit 32] Thread. Ovf_FixedCtr0.\r
229 ///\r
230 UINT32 Ovf_FixedCtr0:1;\r
231 ///\r
232 /// [Bit 33] Thread. Ovf_FixedCtr1.\r
233 ///\r
234 UINT32 Ovf_FixedCtr1:1;\r
235 ///\r
236 /// [Bit 34] Thread. Ovf_FixedCtr2.\r
237 ///\r
238 UINT32 Ovf_FixedCtr2:1;\r
239 UINT32 Reserved2:20;\r
240 ///\r
241 /// [Bit 55] Thread. Trace_ToPA_PMI.\r
242 ///\r
243 UINT32 Trace_ToPA_PMI:1;\r
244 UINT32 Reserved3:2;\r
245 ///\r
246 /// [Bit 58] Thread. LBR_Frz.\r
247 ///\r
248 UINT32 LBR_Frz:1;\r
249 ///\r
250 /// [Bit 59] Thread. CTR_Frz.\r
251 ///\r
252 UINT32 CTR_Frz:1;\r
253 ///\r
254 /// [Bit 60] Thread. ASCI.\r
255 ///\r
256 UINT32 ASCI:1;\r
257 ///\r
258 /// [Bit 61] Thread. Ovf_Uncore.\r
259 ///\r
260 UINT32 Ovf_Uncore:1;\r
261 ///\r
262 /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
263 ///\r
264 UINT32 Ovf_BufDSSAVE:1;\r
265 ///\r
266 /// [Bit 63] Thread. CondChgd.\r
267 ///\r
268 UINT32 CondChgd:1;\r
269 } Bits;\r
270 ///\r
271 /// All bit fields as a 64-bit value\r
272 ///\r
273 UINT64 Uint64;\r
37cea63f 274} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
6b55a245
MK		 275\r
276\r
277/**\r
37cea63f
HW		 278 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring\r
279 Version 4.".\r
6b55a245
MK		 280\r
281 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
282 @param EAX Lower 32-bits of MSR value.\r
283 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
284 @param EDX Upper 32-bits of MSR value.\r
285 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
286\r
287 <b>Example usage</b>\r
288 @code\r
289 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
290\r
291 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);\r
292 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
293 @endcode\r
04e7a465 294 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
6b55a245
MK		 295**/\r
296#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
297\r
298/**\r
299 MSR information returned for MSR index\r
300 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET\r
301**/\r
302typedef union {\r
303 ///\r
304 /// Individual bit fields\r
305 ///\r
306 struct {\r
307 ///\r
308 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
309 ///\r
310 UINT32 Ovf_PMC0:1;\r
311 ///\r
312 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
313 ///\r
314 UINT32 Ovf_PMC1:1;\r
315 ///\r
316 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
317 ///\r
318 UINT32 Ovf_PMC2:1;\r
319 ///\r
320 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
321 ///\r
322 UINT32 Ovf_PMC3:1;\r
323 ///\r
324 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
325 ///\r
326 UINT32 Ovf_PMC4:1;\r
327 ///\r
328 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
329 ///\r
330 UINT32 Ovf_PMC5:1;\r
331 ///\r
332 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
333 ///\r
334 UINT32 Ovf_PMC6:1;\r
335 ///\r
336 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
337 ///\r
338 UINT32 Ovf_PMC7:1;\r
339 UINT32 Reserved1:24;\r
340 ///\r
341 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
342 ///\r
343 UINT32 Ovf_FixedCtr0:1;\r
344 ///\r
345 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
346 ///\r
347 UINT32 Ovf_FixedCtr1:1;\r
348 ///\r
349 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
350 ///\r
351 UINT32 Ovf_FixedCtr2:1;\r
352 UINT32 Reserved2:20;\r
353 ///\r
354 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r
355 ///\r
356 UINT32 Trace_ToPA_PMI:1;\r
357 UINT32 Reserved3:2;\r
358 ///\r
359 /// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r
360 ///\r
361 UINT32 LBR_Frz:1;\r
362 ///\r
363 /// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r
364 ///\r
365 UINT32 CTR_Frz:1;\r
366 ///\r
367 /// [Bit 60] Thread. Set 1 to clear ASCI.\r
368 ///\r
369 UINT32 ASCI:1;\r
370 ///\r
371 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
372 ///\r
373 UINT32 Ovf_Uncore:1;\r
374 ///\r
375 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
376 ///\r
377 UINT32 Ovf_BufDSSAVE:1;\r
378 ///\r
379 /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
380 ///\r
381 UINT32 CondChgd:1;\r
382 } Bits;\r
383 ///\r
384 /// All bit fields as a 64-bit value\r
385 ///\r
386 UINT64 Uint64;\r
387} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
388\r
389\r
390/**\r
37cea63f
HW		 391 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring\r
392 Version 4.".\r
6b55a245
MK		 393\r
394 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
395 @param EAX Lower 32-bits of MSR value.\r
396 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
397 @param EDX Upper 32-bits of MSR value.\r
398 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
399\r
400 <b>Example usage</b>\r
401 @code\r
402 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
403\r
404 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);\r
405 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
406 @endcode\r
04e7a465 407 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
6b55a245
MK		 408**/\r
409#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
410\r
411/**\r
412 MSR information returned for MSR index\r
413 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET\r
414**/\r
415typedef union {\r
416 ///\r
417 /// Individual bit fields\r
418 ///\r
419 struct {\r
420 ///\r
421 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r
422 ///\r
423 UINT32 Ovf_PMC0:1;\r
424 ///\r
425 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r
426 ///\r
427 UINT32 Ovf_PMC1:1;\r
428 ///\r
429 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r
430 ///\r
431 UINT32 Ovf_PMC2:1;\r
432 ///\r
433 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r
434 ///\r
435 UINT32 Ovf_PMC3:1;\r
436 ///\r
437 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r
438 ///\r
439 UINT32 Ovf_PMC4:1;\r
440 ///\r
441 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r
442 ///\r
443 UINT32 Ovf_PMC5:1;\r
444 ///\r
445 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r
446 ///\r
447 UINT32 Ovf_PMC6:1;\r
448 ///\r
449 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r
450 ///\r
451 UINT32 Ovf_PMC7:1;\r
452 UINT32 Reserved1:24;\r
453 ///\r
454 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r
455 ///\r
456 UINT32 Ovf_FixedCtr0:1;\r
457 ///\r
458 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r
459 ///\r
460 UINT32 Ovf_FixedCtr1:1;\r
461 ///\r
462 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r
463 ///\r
464 UINT32 Ovf_FixedCtr2:1;\r
465 UINT32 Reserved2:20;\r
466 ///\r
467 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r
468 ///\r
469 UINT32 Trace_ToPA_PMI:1;\r
470 UINT32 Reserved3:2;\r
471 ///\r
472 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r
473 ///\r
474 UINT32 LBR_Frz:1;\r
475 ///\r
476 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r
477 ///\r
478 UINT32 CTR_Frz:1;\r
479 ///\r
480 /// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r
481 ///\r
482 UINT32 ASCI:1;\r
483 ///\r
484 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r
485 ///\r
486 UINT32 Ovf_Uncore:1;\r
487 ///\r
488 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r
489 ///\r
490 UINT32 Ovf_BufDSSAVE:1;\r
491 UINT32 Reserved4:1;\r
492 } Bits;\r
493 ///\r
494 /// All bit fields as a 64-bit value\r
495 ///\r
496 UINT64 Uint64;\r
497} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
498\r
499\r
500/**\r
501 Thread. FrontEnd Precise Event Condition Select (R/W).\r
502\r
503 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)\r
504 @param EAX Lower 32-bits of MSR value.\r
505 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
506 @param EDX Upper 32-bits of MSR value.\r
507 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
508\r
509 <b>Example usage</b>\r
510 @code\r
511 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;\r
512\r
513 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);\r
514 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);\r
515 @endcode\r
04e7a465 516 @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r
6b55a245
MK		 517**/\r
518#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
519\r
520/**\r
521 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r
522**/\r
523typedef union {\r
524 ///\r
525 /// Individual bit fields\r
526 ///\r
527 struct {\r
528 ///\r
529 /// [Bits 2:0] Event Code Select.\r
530 ///\r
531 UINT32 EventCodeSelect:3;\r
532 UINT32 Reserved1:1;\r
533 ///\r
534 /// [Bit 4] Event Code Select High.\r
535 ///\r
536 UINT32 EventCodeSelectHigh:1;\r
537 UINT32 Reserved2:3;\r
538 ///\r
539 /// [Bits 19:8] IDQ_Bubble_Length Specifier.\r
540 ///\r
541 UINT32 IDQ_Bubble_Length:12;\r
542 ///\r
543 /// [Bits 22:20] IDQ_Bubble_Width Specifier.\r
544 ///\r
545 UINT32 IDQ_Bubble_Width:3;\r
546 UINT32 Reserved3:9;\r
547 UINT32 Reserved4:32;\r
548 } Bits;\r
549 ///\r
550 /// All bit fields as a 32-bit value\r
551 ///\r
552 UINT32 Uint32;\r
553 ///\r
554 /// All bit fields as a 64-bit value\r
555 ///\r
556 UINT64 Uint64;\r
557} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r
558\r
559\r
37cea63f
HW		 560/**\r
561 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
562 Domains.".\r
563\r
564 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
565 @param EAX Lower 32-bits of MSR value.\r
566 @param EDX Upper 32-bits of MSR value.\r
567\r
568 <b>Example usage</b>\r
569 @code\r
570 UINT64 Msr;\r
571\r
572 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
573 @endcode\r
574 @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
575**/\r
576#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
577\r
578\r
6b55a245
MK		 579/**\r
580 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r
581 platform vendor hardware implementation and BIOS enablement support it. This\r
582 MSR will read 0 if not valid.\r
583\r
584 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)\r
585 @param EAX Lower 32-bits of MSR value.\r
586 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
587 @param EDX Upper 32-bits of MSR value.\r
588 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
589\r
590 <b>Example usage</b>\r
591 @code\r
592 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;\r
593\r
594 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);\r
595 @endcode\r
04e7a465 596 @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r
6b55a245
MK		 597**/\r
598#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
599\r
600/**\r
601 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r
602**/\r
603typedef union {\r
604 ///\r
605 /// Individual bit fields\r
606 ///\r
607 struct {\r
608 ///\r
609 /// [Bits 31:0] Total energy consumed by all devices in the platform that\r
610 /// receive power from integrated power delivery mechanism, Included\r
611 /// platform devices are processor cores, SOC, memory, add-on or\r
612 /// peripheral devices that get powered directly from the platform power\r
613 /// delivery means. The energy units are specified in the\r
614 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r
615 ///\r
616 UINT32 TotalEnergy:32;\r
617 UINT32 Reserved:32;\r
618 } Bits;\r
619 ///\r
620 /// All bit fields as a 32-bit value\r
621 ///\r
622 UINT32 Uint32;\r
623 ///\r
624 /// All bit fields as a 64-bit value\r
625 ///\r
626 UINT64 Uint64;\r
627} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r
628\r
629\r
630/**\r
631 Thread. Productive Performance Count. (R/O). Hardware's view of workload\r
632 scalability. See Section 14.4.5.1.\r
633\r
634 @param ECX MSR_SKYLAKE_PPERF (0x0000064E)\r
635 @param EAX Lower 32-bits of MSR value.\r
636 @param EDX Upper 32-bits of MSR value.\r
637\r
638 <b>Example usage</b>\r
639 @code\r
640 UINT64 Msr;\r
641\r
642 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);\r
643 @endcode\r
04e7a465 644 @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r
6b55a245
MK		 645**/\r
646#define MSR_SKYLAKE_PPERF 0x0000064E\r
647\r
648\r
37cea63f
HW		 649/**\r
650 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
651 refers to processor core frequency).\r
652\r
653 @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)\r
654 @param EAX Lower 32-bits of MSR value.\r
655 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
656 @param EDX Upper 32-bits of MSR value.\r
657 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
658\r
659 <b>Example usage</b>\r
660 @code\r
661 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
662\r
663 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);\r
664 AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
665 @endcode\r
666 @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
667**/\r
668#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
669\r
670/**\r
671 MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r
672**/\r
673typedef union {\r
674 ///\r
675 /// Individual bit fields\r
676 ///\r
677 struct {\r
678 ///\r
679 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
680 /// operating system request due to assertion of external PROCHOT.\r
681 ///\r
682 UINT32 PROCHOT_Status:1;\r
683 ///\r
684 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
685 /// operating system request due to a thermal event.\r
686 ///\r
687 UINT32 ThermalStatus:1;\r
688 UINT32 Reserved1:2;\r
689 ///\r
690 /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r
691 /// reduced below the operating system request due to residency state\r
692 /// regulation limit.\r
693 ///\r
694 UINT32 ResidencyStateRegulationStatus:1;\r
695 ///\r
696 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
697 /// is reduced below the operating system request due to Running Average\r
698 /// Thermal Limit (RATL).\r
699 ///\r
700 UINT32 RunningAverageThermalLimitStatus:1;\r
701 ///\r
702 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
703 /// below the operating system request due to a thermal alert from a\r
704 /// processor Voltage Regulator (VR).\r
705 ///\r
706 UINT32 VRThermAlertStatus:1;\r
707 ///\r
708 /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r
709 /// reduced below the operating system request due to VR thermal design\r
710 /// current limit.\r
711 ///\r
712 UINT32 VRThermDesignCurrentStatus:1;\r
713 ///\r
714 /// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r
715 /// operating system request due to electrical or other constraints.\r
716 ///\r
717 UINT32 OtherStatus:1;\r
718 UINT32 Reserved2:1;\r
719 ///\r
720 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
721 /// set, frequency is reduced below the operating system request due to\r
722 /// package/platform-level power limiting PL1.\r
723 ///\r
724 UINT32 PL1Status:1;\r
725 ///\r
726 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
727 /// set, frequency is reduced below the operating system request due to\r
728 /// package/platform-level power limiting PL2/PL3.\r
729 ///\r
730 UINT32 PL2Status:1;\r
731 ///\r
732 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
733 /// below the operating system request due to multi-core turbo limits.\r
734 ///\r
735 UINT32 MaxTurboLimitStatus:1;\r
736 ///\r
737 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
738 /// is reduced below the operating system request due to Turbo transition\r
739 /// attenuation. This prevents performance degradation due to frequent\r
740 /// operating ratio changes.\r
741 ///\r
742 UINT32 TurboTransitionAttenuationStatus:1;\r
743 UINT32 Reserved3:2;\r
744 ///\r
745 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
746 /// has asserted since the log bit was last cleared. This log bit will\r
747 /// remain set until cleared by software writing 0.\r
748 ///\r
749 UINT32 PROCHOT_Log:1;\r
750 ///\r
751 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
752 /// has asserted since the log bit was last cleared. This log bit will\r
753 /// remain set until cleared by software writing 0.\r
754 ///\r
755 UINT32 ThermalLog:1;\r
756 UINT32 Reserved4:2;\r
757 ///\r
758 /// [Bit 20] Residency State Regulation Log When set, indicates that the\r
759 /// Residency State Regulation Status bit has asserted since the log bit\r
760 /// was last cleared. This log bit will remain set until cleared by\r
761 /// software writing 0.\r
762 ///\r
763 UINT32 ResidencyStateRegulationLog:1;\r
764 ///\r
765 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
766 /// the RATL Status bit has asserted since the log bit was last cleared.\r
767 /// This log bit will remain set until cleared by software writing 0.\r
768 ///\r
769 UINT32 RunningAverageThermalLimitLog:1;\r
770 ///\r
771 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
772 /// Alert Status bit has asserted since the log bit was last cleared. This\r
773 /// log bit will remain set until cleared by software writing 0.\r
774 ///\r
775 UINT32 VRThermAlertLog:1;\r
776 ///\r
777 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
778 /// VR TDC Status bit has asserted since the log bit was last cleared.\r
779 /// This log bit will remain set until cleared by software writing 0.\r
780 ///\r
781 UINT32 VRThermalDesignCurrentLog:1;\r
782 ///\r
783 /// [Bit 24] Other Log When set, indicates that the Other Status bit has\r
784 /// asserted since the log bit was last cleared. This log bit will remain\r
785 /// set until cleared by software writing 0.\r
786 ///\r
787 UINT32 OtherLog:1;\r
788 UINT32 Reserved5:1;\r
789 ///\r
790 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
791 /// indicates that the Package or Platform Level PL1 Power Limiting Status\r
792 /// bit has asserted since the log bit was last cleared. This log bit will\r
793 /// remain set until cleared by software writing 0.\r
794 ///\r
795 UINT32 PL1Log:1;\r
796 ///\r
797 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
798 /// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r
799 /// Status bit has asserted since the log bit was last cleared. This log\r
800 /// bit will remain set until cleared by software writing 0.\r
801 ///\r
802 UINT32 PL2Log:1;\r
803 ///\r
804 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
805 /// Limit Status bit has asserted since the log bit was last cleared. This\r
806 /// log bit will remain set until cleared by software writing 0.\r
807 ///\r
808 UINT32 MaxTurboLimitLog:1;\r
809 ///\r
810 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
811 /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
812 /// was last cleared. This log bit will remain set until cleared by\r
813 /// software writing 0.\r
814 ///\r
815 UINT32 TurboTransitionAttenuationLog:1;\r
816 UINT32 Reserved6:2;\r
817 UINT32 Reserved7:32;\r
818 } Bits;\r
819 ///\r
820 /// All bit fields as a 32-bit value\r
821 ///\r
822 UINT32 Uint32;\r
823 ///\r
824 /// All bit fields as a 64-bit value\r
825 ///\r
826 UINT64 Uint64;\r
827} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r
828\r
829\r
6b55a245
MK		 830/**\r
831 Package. HDC Configuration (R/W)..\r
832\r
833 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)\r
834 @param EAX Lower 32-bits of MSR value.\r
835 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
836 @param EDX Upper 32-bits of MSR value.\r
837 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
838\r
839 <b>Example usage</b>\r
840 @code\r
841 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;\r
842\r
843 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);\r
844 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);\r
845 @endcode\r
04e7a465 846 @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r
6b55a245
MK		 847**/\r
848#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
849\r
850/**\r
851 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r
852**/\r
853typedef union {\r
854 ///\r
855 /// Individual bit fields\r
856 ///\r
857 struct {\r
858 ///\r
859 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for\r
860 /// MSR_PKG_HDC_DEEP_RESIDENCY.\r
861 ///\r
862 UINT32 PKG_Cx_Monitor:3;\r
863 UINT32 Reserved1:29;\r
864 UINT32 Reserved2:32;\r
865 } Bits;\r
866 ///\r
867 /// All bit fields as a 32-bit value\r
868 ///\r
869 UINT32 Uint32;\r
870 ///\r
871 /// All bit fields as a 64-bit value\r
872 ///\r
873 UINT64 Uint64;\r
874} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r
875\r
876\r
877/**\r
878 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r
879\r
880 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)\r
881 @param EAX Lower 32-bits of MSR value.\r
882 @param EDX Upper 32-bits of MSR value.\r
883\r
884 <b>Example usage</b>\r
885 @code\r
886 UINT64 Msr;\r
887\r
888 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);\r
889 @endcode\r
04e7a465 890 @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r
6b55a245
MK		 891**/\r
892#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
893\r
894\r
895/**\r
896 Package. Accumulate the cycles the package was in C2 state and at least one\r
897 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.\r
898\r
899 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)\r
900 @param EAX Lower 32-bits of MSR value.\r
901 @param EDX Upper 32-bits of MSR value.\r
902\r
903 <b>Example usage</b>\r
904 @code\r
905 UINT64 Msr;\r
906\r
907 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);\r
908 @endcode\r
04e7a465 909 @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r
6b55a245
MK		 910**/\r
911#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
912\r
913\r
914/**\r
915 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r
916\r
917 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)\r
918 @param EAX Lower 32-bits of MSR value.\r
919 @param EDX Upper 32-bits of MSR value.\r
920\r
921 <b>Example usage</b>\r
922 @code\r
923 UINT64 Msr;\r
924\r
925 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);\r
926 @endcode\r
04e7a465 927 @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r
6b55a245
MK		 928**/\r
929#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
930\r
931\r
932/**\r
933 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r
934 as the TSC. The increment each cycle is weighted by the number of processor\r
935 cores in the package that reside in C0. If N cores are simultaneously in C0,\r
936 then each cycle the counter increments by N.\r
937\r
938 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)\r
939 @param EAX Lower 32-bits of MSR value.\r
940 @param EDX Upper 32-bits of MSR value.\r
941\r
942 <b>Example usage</b>\r
943 @code\r
944 UINT64 Msr;\r
945\r
946 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);\r
947 @endcode\r
04e7a465 948 @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r
6b55a245
MK		 949**/\r
950#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
951\r
952\r
953/**\r
954 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r
955 TSC. The increment each cycle is one if any processor core in the package is\r
956 in C0.\r
957\r
958 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)\r
959 @param EAX Lower 32-bits of MSR value.\r
960 @param EDX Upper 32-bits of MSR value.\r
961\r
962 <b>Example usage</b>\r
963 @code\r
964 UINT64 Msr;\r
965\r
966 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);\r
967 @endcode\r
04e7a465 968 @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r
6b55a245
MK		 969**/\r
970#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
971\r
972\r
973/**\r
974 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r
975 as the TSC. The increment each cycle is one if any processor graphic\r
976 device's compute engines are in C0.\r
977\r
978 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)\r
979 @param EAX Lower 32-bits of MSR value.\r
980 @param EDX Upper 32-bits of MSR value.\r
981\r
982 <b>Example usage</b>\r
983 @code\r
984 UINT64 Msr;\r
985\r
986 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);\r
987 @endcode\r
04e7a465 988 @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r
6b55a245
MK		 989**/\r
990#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
991\r
992\r
993/**\r
994 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r
995 at the same rate as the TSC. The increment each cycle is one if at least one\r
996 compute engine of the processor graphics is in C0 and at least one processor\r
997 core in the package is also in C0.\r
998\r
999 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)\r
1000 @param EAX Lower 32-bits of MSR value.\r
1001 @param EDX Upper 32-bits of MSR value.\r
1002\r
1003 <b>Example usage</b>\r
1004 @code\r
1005 UINT64 Msr;\r
1006\r
1007 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);\r
1008 @endcode\r
04e7a465 1009 @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r
6b55a245
MK		 1010**/\r
1011#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
1012\r
1013\r
1014/**\r
1015 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r
1016 limit power consumption of the platform devices to the specified values. The\r
1017 Long Duration power consumption is specified via Platform_Power_Limit_1 and\r
1018 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is\r
1019 specified via the Platform_Power_Limit_2 with duration chosen by the\r
1020 processor. The processor implements an exponential-weighted algorithm in the\r
1021 placement of the time windows.\r
1022\r
1023 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)\r
1024 @param EAX Lower 32-bits of MSR value.\r
1025 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
1026 @param EDX Upper 32-bits of MSR value.\r
1027 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
1028\r
1029 <b>Example usage</b>\r
1030 @code\r
1031 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;\r
1032\r
1033 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);\r
1034 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);\r
1035 @endcode\r
04e7a465 1036 @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r
6b55a245
MK		 1037**/\r
1038#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
1039\r
1040/**\r
1041 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r
1042**/\r
1043typedef union {\r
1044 ///\r
1045 /// Individual bit fields\r
1046 ///\r
1047 struct {\r
1048 ///\r
1049 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which\r
1050 /// the platform must not exceed over a time window as specified by\r
1051 /// Power_Limit_1_TIME field. The default value is the Thermal Design\r
1052 /// Power (TDP) and varies with product skus. The unit is specified in\r
1053 /// MSR_RAPLPOWER_UNIT.\r
1054 ///\r
1055 UINT32 PlatformPowerLimit1:15;\r
1056 ///\r
1057 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r
1058 /// processor to apply control policy such that the platform power does\r
1059 /// not exceed Platform Power limit #1 over the time window specified by\r
1060 /// Power Limit #1 Time Window.\r
1061 ///\r
1062 UINT32 EnablePlatformPowerLimit1:1;\r
1063 ///\r
1064 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r
1065 /// processor to go below the OS requested P states in order to maintain\r
1066 /// the power below specified Platform Power Limit #1 value. This bit is\r
1067 /// writeable only when CPUID (EAX=6):EAX[4] is set.\r
1068 ///\r
1069 UINT32 PlatformClampingLimitation1:1;\r
1070 ///\r
1071 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r
1072 /// duration of the time window over which Platform Power Limit 1 value\r
1073 /// should be maintained for sustained long duration. This field is made\r
1074 /// up of two numbers from the following equation: Time Window = (float)\r
1075 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =\r
1076 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is\r
1077 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r
1078 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r
1079 ///\r
1080 UINT32 Time:7;\r
1081 UINT32 Reserved1:8;\r
1082 ///\r
1083 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r
1084 /// the platform must not exceed over the Short Duration time window\r
1085 /// chosen by the processor. The recommended default value is 1.25 times\r
1086 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r
1087 ///\r
1088 UINT32 PlatformPowerLimit2:15;\r
1089 ///\r
1090 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r
1091 /// processor to apply control policy such that the platform power does\r
1092 /// not exceed Platform Power limit #2 over the Short Duration time window.\r
1093 ///\r
1094 UINT32 EnablePlatformPowerLimit2:1;\r
1095 ///\r
1096 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r
1097 /// processor to go below the OS requested P states in order to maintain\r
1098 /// the power below specified Platform Power Limit #2 value.\r
1099 ///\r
1100 UINT32 PlatformClampingLimitation2:1;\r
1101 UINT32 Reserved2:14;\r
1102 ///\r
1103 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r
1104 /// until system RESET.\r
1105 ///\r
1106 UINT32 Lock:1;\r
1107 } Bits;\r
1108 ///\r
1109 /// All bit fields as a 64-bit value\r
1110 ///\r
1111 UINT64 Uint64;\r
1112} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r
1113\r
1114\r
1115/**\r
1116 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r
1117 branch record registers on the last branch record stack. This part of the\r
1118 stack contains pointers to the source instruction. See also: - Last Branch\r
37cea63f 1119 Record Stack TOS at 1C9H - Section 17.10.\r
6b55a245
MK		 1120\r
1121 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP\r
1122 @param EAX Lower 32-bits of MSR value.\r
1123 @param EDX Upper 32-bits of MSR value.\r
1124\r
1125 <b>Example usage</b>\r
1126 @code\r
1127 UINT64 Msr;\r
1128\r
1129 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);\r
1130 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);\r
1131 @endcode\r
04e7a465
JF		 1132 @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r
1133 MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r
1134 MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r
1135 MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r
1136 MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r
1137 MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r
1138 MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r
1139 MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r
1140 MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r
1141 MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r
1142 MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r
1143 MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r
1144 MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r
1145 MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r
1146 MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r
1147 MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
6b55a245
MK		 1148 @{\r
1149**/\r
1150#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
1151#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
1152#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
1153#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
1154#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
1155#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
1156#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
1157#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
1158#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
1159#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
1160#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
1161#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
1162#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
1163#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
1164#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
1165#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
1166/// @}\r
1167\r
37cea63f
HW		 1168\r
1169/**\r
1170 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
1171 (frequency refers to processor graphics frequency).\r
1172\r
1173 @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
1174 @param EAX Lower 32-bits of MSR value.\r
1175 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
1176 @param EDX Upper 32-bits of MSR value.\r
1177 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
1178\r
1179 <b>Example usage</b>\r
1180 @code\r
1181 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r
1182\r
1183 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);\r
1184 AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
1185 @endcode\r
1186 @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
1187**/\r
1188#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
1189\r
1190/**\r
1191 MSR information returned for MSR index\r
1192 #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS\r
1193**/\r
1194typedef union {\r
1195 ///\r
1196 /// Individual bit fields\r
1197 ///\r
1198 struct {\r
1199 ///\r
1200 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
1201 /// assertion of external PROCHOT.\r
1202 ///\r
1203 UINT32 PROCHOT_Status:1;\r
1204 ///\r
1205 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
1206 /// thermal event.\r
1207 ///\r
1208 UINT32 ThermalStatus:1;\r
1209 UINT32 Reserved1:3;\r
1210 ///\r
1211 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
1212 /// is reduced due to running average thermal limit.\r
1213 ///\r
1214 UINT32 RunningAverageThermalLimitStatus:1;\r
1215 ///\r
1216 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
1217 /// to a thermal alert from a processor Voltage Regulator.\r
1218 ///\r
1219 UINT32 VRThermAlertStatus:1;\r
1220 ///\r
1221 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
1222 /// reduced due to VR TDC limit.\r
1223 ///\r
1224 UINT32 VRThermalDesignCurrentStatus:1;\r
1225 ///\r
1226 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
1227 /// electrical or other constraints.\r
1228 ///\r
1229 UINT32 OtherStatus:1;\r
1230 UINT32 Reserved2:1;\r
1231 ///\r
1232 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
1233 /// set, frequency is reduced due to package/platform-level power limiting\r
1234 /// PL1.\r
1235 ///\r
1236 UINT32 PL1Status:1;\r
1237 ///\r
1238 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
1239 /// set, frequency is reduced due to package/platform-level power limiting\r
1240 /// PL2/PL3.\r
1241 ///\r
1242 UINT32 PL2Status:1;\r
1243 ///\r
1244 /// [Bit 12] Inefficient Operation Status (R0) When set, processor\r
1245 /// graphics frequency is operating below target frequency.\r
1246 ///\r
1247 UINT32 InefficientOperationStatus:1;\r
1248 UINT32 Reserved3:3;\r
1249 ///\r
1250 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
1251 /// has asserted since the log bit was last cleared. This log bit will\r
1252 /// remain set until cleared by software writing 0.\r
1253 ///\r
1254 UINT32 PROCHOT_Log:1;\r
1255 ///\r
1256 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
1257 /// has asserted since the log bit was last cleared. This log bit will\r
1258 /// remain set until cleared by software writing 0.\r
1259 ///\r
1260 UINT32 ThermalLog:1;\r
1261 UINT32 Reserved4:3;\r
1262 ///\r
1263 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
1264 /// the RATL Status bit has asserted since the log bit was last cleared.\r
1265 /// This log bit will remain set until cleared by software writing 0.\r
1266 ///\r
1267 UINT32 RunningAverageThermalLimitLog:1;\r
1268 ///\r
1269 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
1270 /// Alert Status bit has asserted since the log bit was last cleared. This\r
1271 /// log bit will remain set until cleared by software writing 0.\r
1272 ///\r
1273 UINT32 VRThermAlertLog:1;\r
1274 ///\r
1275 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
1276 /// VR Therm Alert Status bit has asserted since the log bit was last\r
1277 /// cleared. This log bit will remain set until cleared by software\r
1278 /// writing 0.\r
1279 ///\r
1280 UINT32 VRThermalDesignCurrentLog:1;\r
1281 ///\r
1282 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
1283 /// asserted since the log bit was last cleared. This log bit will remain\r
1284 /// set until cleared by software writing 0.\r
1285 ///\r
1286 UINT32 OtherLog:1;\r
1287 UINT32 Reserved5:1;\r
1288 ///\r
1289 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
1290 /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
1291 /// bit has asserted since the log bit was last cleared. This log bit will\r
1292 /// remain set until cleared by software writing 0.\r
1293 ///\r
1294 UINT32 PL1Log:1;\r
1295 ///\r
1296 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
1297 /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
1298 /// bit has asserted since the log bit was last cleared. This log bit will\r
1299 /// remain set until cleared by software writing 0.\r
1300 ///\r
1301 UINT32 PL2Log:1;\r
1302 ///\r
1303 /// [Bit 28] Inefficient Operation Log When set, indicates that the\r
1304 /// Inefficient Operation Status bit has asserted since the log bit was\r
1305 /// last cleared. This log bit will remain set until cleared by software\r
1306 /// writing 0.\r
1307 ///\r
1308 UINT32 InefficientOperationLog:1;\r
1309 UINT32 Reserved6:3;\r
1310 UINT32 Reserved7:32;\r
1311 } Bits;\r
1312 ///\r
1313 /// All bit fields as a 32-bit value\r
1314 ///\r
1315 UINT32 Uint32;\r
1316 ///\r
1317 /// All bit fields as a 64-bit value\r
1318 ///\r
1319 UINT64 Uint64;\r
1320} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
1321\r
1322\r
1323/**\r
1324 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
1325 (frequency refers to ring interconnect in the uncore).\r
1326\r
1327 @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)\r
1328 @param EAX Lower 32-bits of MSR value.\r
1329 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
1330 @param EDX Upper 32-bits of MSR value.\r
1331 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
1332\r
1333 <b>Example usage</b>\r
1334 @code\r
1335 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r
1336\r
1337 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);\r
1338 AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
1339 @endcode\r
1340 @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
1341**/\r
1342#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
1343\r
1344/**\r
1345 MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r
1346**/\r
1347typedef union {\r
1348 ///\r
1349 /// Individual bit fields\r
1350 ///\r
1351 struct {\r
1352 ///\r
1353 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
1354 /// assertion of external PROCHOT.\r
1355 ///\r
1356 UINT32 PROCHOT_Status:1;\r
1357 ///\r
1358 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
1359 /// thermal event.\r
1360 ///\r
1361 UINT32 ThermalStatus:1;\r
1362 UINT32 Reserved1:3;\r
1363 ///\r
1364 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
1365 /// is reduced due to running average thermal limit.\r
1366 ///\r
1367 UINT32 RunningAverageThermalLimitStatus:1;\r
1368 ///\r
1369 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
1370 /// to a thermal alert from a processor Voltage Regulator.\r
1371 ///\r
1372 UINT32 VRThermAlertStatus:1;\r
1373 ///\r
1374 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
1375 /// reduced due to VR TDC limit.\r
1376 ///\r
1377 UINT32 VRThermalDesignCurrentStatus:1;\r
1378 ///\r
1379 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
1380 /// electrical or other constraints.\r
1381 ///\r
1382 UINT32 OtherStatus:1;\r
1383 UINT32 Reserved2:1;\r
1384 ///\r
1385 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
1386 /// set, frequency is reduced due to package/Platform-level power limiting\r
1387 /// PL1.\r
1388 ///\r
1389 UINT32 PL1Status:1;\r
1390 ///\r
1391 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
1392 /// set, frequency is reduced due to package/Platform-level power limiting\r
1393 /// PL2/PL3.\r
1394 ///\r
1395 UINT32 PL2Status:1;\r
1396 UINT32 Reserved3:4;\r
1397 ///\r
1398 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
1399 /// has asserted since the log bit was last cleared. This log bit will\r
1400 /// remain set until cleared by software writing 0.\r
1401 ///\r
1402 UINT32 PROCHOT_Log:1;\r
1403 ///\r
1404 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
1405 /// has asserted since the log bit was last cleared. This log bit will\r
1406 /// remain set until cleared by software writing 0.\r
1407 ///\r
1408 UINT32 ThermalLog:1;\r
1409 UINT32 Reserved4:3;\r
1410 ///\r
1411 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
1412 /// the RATL Status bit has asserted since the log bit was last cleared.\r
1413 /// This log bit will remain set until cleared by software writing 0.\r
1414 ///\r
1415 UINT32 RunningAverageThermalLimitLog:1;\r
1416 ///\r
1417 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
1418 /// Alert Status bit has asserted since the log bit was last cleared. This\r
1419 /// log bit will remain set until cleared by software writing 0.\r
1420 ///\r
1421 UINT32 VRThermAlertLog:1;\r
1422 ///\r
1423 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
1424 /// VR Therm Alert Status bit has asserted since the log bit was last\r
1425 /// cleared. This log bit will remain set until cleared by software\r
1426 /// writing 0.\r
1427 ///\r
1428 UINT32 VRThermalDesignCurrentLog:1;\r
1429 ///\r
1430 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
1431 /// asserted since the log bit was last cleared. This log bit will remain\r
1432 /// set until cleared by software writing 0.\r
1433 ///\r
1434 UINT32 OtherLog:1;\r
1435 UINT32 Reserved5:1;\r
1436 ///\r
1437 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
1438 /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
1439 /// bit has asserted since the log bit was last cleared. This log bit will\r
1440 /// remain set until cleared by software writing 0.\r
1441 ///\r
1442 UINT32 PL1Log:1;\r
1443 ///\r
1444 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
1445 /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
1446 /// bit has asserted since the log bit was last cleared. This log bit will\r
1447 /// remain set until cleared by software writing 0.\r
1448 ///\r
1449 UINT32 PL2Log:1;\r
1450 UINT32 Reserved6:4;\r
1451 UINT32 Reserved7:32;\r
1452 } Bits;\r
1453 ///\r
1454 /// All bit fields as a 32-bit value\r
1455 ///\r
1456 UINT32 Uint32;\r
1457 ///\r
1458 /// All bit fields as a 64-bit value\r
1459 ///\r
1460 UINT64 Uint64;\r
1461} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r
1462\r
1463\r
6b55a245
MK		 1464/**\r
1465 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r
1466 record registers on the last branch record stack. This part of the stack\r
1467 contains pointers to the destination instruction. See also: - Last Branch\r
37cea63f 1468 Record Stack TOS at 1C9H - Section 17.10.\r
6b55a245
MK		 1469\r
1470 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP\r
1471 @param EAX Lower 32-bits of MSR value.\r
1472 @param EDX Upper 32-bits of MSR value.\r
1473\r
1474 <b>Example usage</b>\r
1475 @code\r
1476 UINT64 Msr;\r
1477\r
1478 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);\r
1479 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);\r
1480 @endcode\r
04e7a465
JF		 1481 @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r
1482 MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r
1483 MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r
1484 MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r
1485 MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r
1486 MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r
1487 MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r
1488 MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r
1489 MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r
1490 MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r
1491 MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r
1492 MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r
1493 MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r
1494 MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r
1495 MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r
1496 MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
6b55a245
MK		 1497 @{\r
1498**/\r
1499#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
1500#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
1501#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
1502#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
1503#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
1504#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
1505#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
1506#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
1507#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
1508#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
1509#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
1510#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
1511#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
1512#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
1513#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
1514#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
1515/// @}\r
1516\r
1517\r
1518/**\r
1519 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r
1520 of last branch record registers on the last branch record stack. This part\r
1521 of the stack contains flag, TSX-related and elapsed cycle information. See\r
37cea63f 1522 also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR\r
6b55a245
MK		 1523 Stack.".\r
1524\r
1525 @param ECX MSR_SKYLAKE_LBR_INFO_n\r
1526 @param EAX Lower 32-bits of MSR value.\r
1527 @param EDX Upper 32-bits of MSR value.\r
1528\r
1529 <b>Example usage</b>\r
1530 @code\r
1531 UINT64 Msr;\r
1532\r
1533 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);\r
1534 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);\r
1535 @endcode\r
04e7a465
JF		 1536 @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.\r
1537 MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.\r
1538 MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.\r
1539 MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.\r
1540 MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.\r
1541 MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.\r
1542 MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.\r
1543 MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.\r
1544 MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.\r
1545 MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.\r
1546 MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.\r
1547 MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.\r
1548 MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.\r
1549 MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.\r
1550 MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.\r
1551 MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.\r
1552 MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.\r
1553 MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.\r
1554 MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.\r
1555 MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.\r
1556 MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.\r
1557 MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.\r
1558 MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.\r
1559 MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.\r
1560 MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.\r
1561 MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.\r
1562 MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.\r
1563 MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.\r
1564 MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.\r
1565 MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.\r
1566 MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.\r
1567 MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r
6b55a245
MK		 1568 @{\r
1569**/\r
1570#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
1571#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
1572#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
1573#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
1574#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
1575#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
1576#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
1577#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
1578#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
1579#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
1580#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
1581#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
1582#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
1583#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
1584#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
1585#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
1586#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
1587#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
1588#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
1589#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
1590#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
1591#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
1592#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
1593#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
1594#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
1595#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
1596#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
1597#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
1598#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
1599#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
1600#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
1601#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
1602/// @}\r
1603\r
37cea63f
HW		 1604\r
1605/**\r
1606 Package. Uncore fixed counter control (R/W).\r
1607\r
1608 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)\r
1609 @param EAX Lower 32-bits of MSR value.\r
1610 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
1611 @param EDX Upper 32-bits of MSR value.\r
1612 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
1613\r
1614 <b>Example usage</b>\r
1615 @code\r
1616 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
1617\r
1618 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);\r
1619 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
1620 @endcode\r
1621 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
1622**/\r
1623#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
1624\r
1625/**\r
1626 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r
1627**/\r
1628typedef union {\r
1629 ///\r
1630 /// Individual bit fields\r
1631 ///\r
1632 struct {\r
1633 UINT32 Reserved1:20;\r
1634 ///\r
1635 /// [Bit 20] Enable overflow propagation.\r
1636 ///\r
1637 UINT32 EnableOverflow:1;\r
1638 UINT32 Reserved2:1;\r
1639 ///\r
1640 /// [Bit 22] Enable counting.\r
1641 ///\r
1642 UINT32 EnableCounting:1;\r
1643 UINT32 Reserved3:9;\r
1644 UINT32 Reserved4:32;\r
1645 } Bits;\r
1646 ///\r
1647 /// All bit fields as a 32-bit value\r
1648 ///\r
1649 UINT32 Uint32;\r
1650 ///\r
1651 /// All bit fields as a 64-bit value\r
1652 ///\r
1653 UINT64 Uint64;\r
1654} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r
1655\r
1656\r
1657/**\r
1658 Package. Uncore fixed counter.\r
1659\r
1660 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)\r
1661 @param EAX Lower 32-bits of MSR value.\r
1662 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
1663 @param EDX Upper 32-bits of MSR value.\r
1664 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
1665\r
1666 <b>Example usage</b>\r
1667 @code\r
1668 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
1669\r
1670 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);\r
1671 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
1672 @endcode\r
1673 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
1674**/\r
1675#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
1676\r
1677/**\r
1678 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r
1679**/\r
1680typedef union {\r
1681 ///\r
1682 /// Individual bit fields\r
1683 ///\r
1684 struct {\r
1685 ///\r
1686 /// [Bits 31:0] Current count.\r
1687 ///\r
1688 UINT32 CurrentCount:32;\r
1689 ///\r
1690 /// [Bits 43:32] Current count.\r
1691 ///\r
1692 UINT32 CurrentCountHi:12;\r
1693 UINT32 Reserved:20;\r
1694 } Bits;\r
1695 ///\r
1696 /// All bit fields as a 64-bit value\r
1697 ///\r
1698 UINT64 Uint64;\r
1699} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r
1700\r
1701\r
1702/**\r
1703 Package. Uncore C-Box configuration information (R/O).\r
1704\r
1705 @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)\r
1706 @param EAX Lower 32-bits of MSR value.\r
1707 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
1708 @param EDX Upper 32-bits of MSR value.\r
1709 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
1710\r
1711 <b>Example usage</b>\r
1712 @code\r
1713 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;\r
1714\r
1715 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);\r
1716 @endcode\r
1717 @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
1718**/\r
1719#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
1720\r
1721/**\r
1722 MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r
1723**/\r
1724typedef union {\r
1725 ///\r
1726 /// Individual bit fields\r
1727 ///\r
1728 struct {\r
1729 ///\r
1730 /// [Bits 3:0] Specifies the number of C-Box units with programmable\r
1731 /// counters (including processor cores and processor graphics),.\r
1732 ///\r
1733 UINT32 CBox:4;\r
1734 UINT32 Reserved1:28;\r
1735 UINT32 Reserved2:32;\r
1736 } Bits;\r
1737 ///\r
1738 /// All bit fields as a 32-bit value\r
1739 ///\r
1740 UINT32 Uint32;\r
1741 ///\r
1742 /// All bit fields as a 64-bit value\r
1743 ///\r
1744 UINT64 Uint64;\r
1745} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r
1746\r
1747\r
1748/**\r
1749 Package. Uncore Arb unit, performance counter 0.\r
1750\r
1751 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)\r
1752 @param EAX Lower 32-bits of MSR value.\r
1753 @param EDX Upper 32-bits of MSR value.\r
1754\r
1755 <b>Example usage</b>\r
1756 @code\r
1757 UINT64 Msr;\r
1758\r
1759 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);\r
1760 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);\r
1761 @endcode\r
1762 @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
1763**/\r
1764#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
1765\r
1766\r
1767/**\r
1768 Package. Uncore Arb unit, performance counter 1.\r
1769\r
1770 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)\r
1771 @param EAX Lower 32-bits of MSR value.\r
1772 @param EDX Upper 32-bits of MSR value.\r
1773\r
1774 <b>Example usage</b>\r
1775 @code\r
1776 UINT64 Msr;\r
1777\r
1778 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);\r
1779 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);\r
1780 @endcode\r
1781 @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
1782**/\r
1783#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
1784\r
1785\r
1786/**\r
1787 Package. Uncore Arb unit, counter 0 event select MSR.\r
1788\r
1789 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
1790 @param EAX Lower 32-bits of MSR value.\r
1791 @param EDX Upper 32-bits of MSR value.\r
1792\r
1793 <b>Example usage</b>\r
1794 @code\r
1795 UINT64 Msr;\r
1796\r
1797 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);\r
1798 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);\r
1799 @endcode\r
1800 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
1801**/\r
1802#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
1803\r
1804\r
1805/**\r
1806 Package. Uncore Arb unit, counter 1 event select MSR.\r
1807\r
1808 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
1809 @param EAX Lower 32-bits of MSR value.\r
1810 @param EDX Upper 32-bits of MSR value.\r
1811\r
1812 <b>Example usage</b>\r
1813 @code\r
1814 UINT64 Msr;\r
1815\r
1816 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);\r
1817 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);\r
1818 @endcode\r
1819 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r
1820**/\r
1821#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
1822\r
1823\r
1824/**\r
1825 Package. Uncore C-Box 0, counter 0 event select MSR.\r
1826\r
1827 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
1828 @param EAX Lower 32-bits of MSR value.\r
1829 @param EDX Upper 32-bits of MSR value.\r
1830\r
1831 <b>Example usage</b>\r
1832 @code\r
1833 UINT64 Msr;\r
1834\r
1835 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);\r
1836 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
1837 @endcode\r
1838 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
1839**/\r
1840#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
1841\r
1842\r
1843/**\r
1844 Package. Uncore C-Box 0, counter 1 event select MSR.\r
1845\r
1846 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
1847 @param EAX Lower 32-bits of MSR value.\r
1848 @param EDX Upper 32-bits of MSR value.\r
1849\r
1850 <b>Example usage</b>\r
1851 @code\r
1852 UINT64 Msr;\r
1853\r
1854 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);\r
1855 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);\r
1856 @endcode\r
1857 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
1858**/\r
1859#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
1860\r
1861\r
1862/**\r
1863 Package. Uncore C-Box 0, performance counter 0.\r
1864\r
1865 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)\r
1866 @param EAX Lower 32-bits of MSR value.\r
1867 @param EDX Upper 32-bits of MSR value.\r
1868\r
1869 <b>Example usage</b>\r
1870 @code\r
1871 UINT64 Msr;\r
1872\r
1873 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);\r
1874 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);\r
1875 @endcode\r
1876 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
1877**/\r
1878#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
1879\r
1880\r
1881/**\r
1882 Package. Uncore C-Box 0, performance counter 1.\r
1883\r
1884 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)\r
1885 @param EAX Lower 32-bits of MSR value.\r
1886 @param EDX Upper 32-bits of MSR value.\r
1887\r
1888 <b>Example usage</b>\r
1889 @code\r
1890 UINT64 Msr;\r
1891\r
1892 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);\r
1893 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);\r
1894 @endcode\r
1895 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
1896**/\r
1897#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
1898\r
1899\r
1900/**\r
1901 Package. Uncore C-Box 1, counter 0 event select MSR.\r
1902\r
1903 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
1904 @param EAX Lower 32-bits of MSR value.\r
1905 @param EDX Upper 32-bits of MSR value.\r
1906\r
1907 <b>Example usage</b>\r
1908 @code\r
1909 UINT64 Msr;\r
1910\r
1911 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);\r
1912 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
1913 @endcode\r
1914 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
1915**/\r
1916#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
1917\r
1918\r
1919/**\r
1920 Package. Uncore C-Box 1, counter 1 event select MSR.\r
1921\r
1922 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
1923 @param EAX Lower 32-bits of MSR value.\r
1924 @param EDX Upper 32-bits of MSR value.\r
1925\r
1926 <b>Example usage</b>\r
1927 @code\r
1928 UINT64 Msr;\r
1929\r
1930 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);\r
1931 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);\r
1932 @endcode\r
1933 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
1934**/\r
1935#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
1936\r
1937\r
1938/**\r
1939 Package. Uncore C-Box 1, performance counter 0.\r
1940\r
1941 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)\r
1942 @param EAX Lower 32-bits of MSR value.\r
1943 @param EDX Upper 32-bits of MSR value.\r
1944\r
1945 <b>Example usage</b>\r
1946 @code\r
1947 UINT64 Msr;\r
1948\r
1949 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);\r
1950 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);\r
1951 @endcode\r
1952 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
1953**/\r
1954#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
1955\r
1956\r
1957/**\r
1958 Package. Uncore C-Box 1, performance counter 1.\r
1959\r
1960 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)\r
1961 @param EAX Lower 32-bits of MSR value.\r
1962 @param EDX Upper 32-bits of MSR value.\r
1963\r
1964 <b>Example usage</b>\r
1965 @code\r
1966 UINT64 Msr;\r
1967\r
1968 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);\r
1969 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);\r
1970 @endcode\r
1971 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
1972**/\r
1973#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
1974\r
1975\r
1976/**\r
1977 Package. Uncore C-Box 2, counter 0 event select MSR.\r
1978\r
1979 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
1980 @param EAX Lower 32-bits of MSR value.\r
1981 @param EDX Upper 32-bits of MSR value.\r
1982\r
1983 <b>Example usage</b>\r
1984 @code\r
1985 UINT64 Msr;\r
1986\r
1987 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);\r
1988 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
1989 @endcode\r
1990 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
1991**/\r
1992#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
1993\r
1994\r
1995/**\r
1996 Package. Uncore C-Box 2, counter 1 event select MSR.\r
1997\r
1998 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
1999 @param EAX Lower 32-bits of MSR value.\r
2000 @param EDX Upper 32-bits of MSR value.\r
2001\r
2002 <b>Example usage</b>\r
2003 @code\r
2004 UINT64 Msr;\r
2005\r
2006 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);\r
2007 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);\r
2008 @endcode\r
2009 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
2010**/\r
2011#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
2012\r
2013\r
2014/**\r
2015 Package. Uncore C-Box 2, performance counter 0.\r
2016\r
2017 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)\r
2018 @param EAX Lower 32-bits of MSR value.\r
2019 @param EDX Upper 32-bits of MSR value.\r
2020\r
2021 <b>Example usage</b>\r
2022 @code\r
2023 UINT64 Msr;\r
2024\r
2025 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);\r
2026 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);\r
2027 @endcode\r
2028 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
2029**/\r
2030#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
2031\r
2032\r
2033/**\r
2034 Package. Uncore C-Box 2, performance counter 1.\r
2035\r
2036 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)\r
2037 @param EAX Lower 32-bits of MSR value.\r
2038 @param EDX Upper 32-bits of MSR value.\r
2039\r
2040 <b>Example usage</b>\r
2041 @code\r
2042 UINT64 Msr;\r
2043\r
2044 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);\r
2045 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);\r
2046 @endcode\r
2047 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
2048**/\r
2049#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
2050\r
2051\r
2052/**\r
2053 Package. Uncore C-Box 3, counter 0 event select MSR.\r
2054\r
2055 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
2056 @param EAX Lower 32-bits of MSR value.\r
2057 @param EDX Upper 32-bits of MSR value.\r
2058\r
2059 <b>Example usage</b>\r
2060 @code\r
2061 UINT64 Msr;\r
2062\r
2063 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);\r
2064 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
2065 @endcode\r
2066 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
2067**/\r
2068#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
2069\r
2070\r
2071/**\r
2072 Package. Uncore C-Box 3, counter 1 event select MSR.\r
2073\r
2074 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
2075 @param EAX Lower 32-bits of MSR value.\r
2076 @param EDX Upper 32-bits of MSR value.\r
2077\r
2078 <b>Example usage</b>\r
2079 @code\r
2080 UINT64 Msr;\r
2081\r
2082 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);\r
2083 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);\r
2084 @endcode\r
2085 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
2086**/\r
2087#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
2088\r
2089\r
2090/**\r
2091 Package. Uncore C-Box 3, performance counter 0.\r
2092\r
2093 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)\r
2094 @param EAX Lower 32-bits of MSR value.\r
2095 @param EDX Upper 32-bits of MSR value.\r
2096\r
2097 <b>Example usage</b>\r
2098 @code\r
2099 UINT64 Msr;\r
2100\r
2101 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);\r
2102 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);\r
2103 @endcode\r
2104 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
2105**/\r
2106#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
2107\r
2108\r
2109/**\r
2110 Package. Uncore C-Box 3, performance counter 1.\r
2111\r
2112 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)\r
2113 @param EAX Lower 32-bits of MSR value.\r
2114 @param EDX Upper 32-bits of MSR value.\r
2115\r
2116 <b>Example usage</b>\r
2117 @code\r
2118 UINT64 Msr;\r
2119\r
2120 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);\r
2121 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);\r
2122 @endcode\r
2123 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
2124**/\r
2125#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
2126\r
2127\r
2128/**\r
2129 Package. Uncore PMU global control.\r
2130\r
2131 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)\r
2132 @param EAX Lower 32-bits of MSR value.\r
2133 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
2134 @param EDX Upper 32-bits of MSR value.\r
2135 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
2136\r
2137 <b>Example usage</b>\r
2138 @code\r
2139 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
2140\r
2141 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);\r
2142 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
2143 @endcode\r
2144 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
2145**/\r
2146#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
2147\r
2148/**\r
2149 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r
2150**/\r
2151typedef union {\r
2152 ///\r
2153 /// Individual bit fields\r
2154 ///\r
2155 struct {\r
2156 ///\r
2157 /// [Bit 0] Slice 0 select.\r
2158 ///\r
2159 UINT32 PMI_Sel_Slice0:1;\r
2160 ///\r
2161 /// [Bit 1] Slice 1 select.\r
2162 ///\r
2163 UINT32 PMI_Sel_Slice1:1;\r
2164 ///\r
2165 /// [Bit 2] Slice 2 select.\r
2166 ///\r
2167 UINT32 PMI_Sel_Slice2:1;\r
2168 ///\r
2169 /// [Bit 3] Slice 3 select.\r
2170 ///\r
2171 UINT32 PMI_Sel_Slice3:1;\r
2172 ///\r
2173 /// [Bit 4] Slice 4select.\r
2174 ///\r
2175 UINT32 PMI_Sel_Slice4:1;\r
2176 UINT32 Reserved1:14;\r
2177 UINT32 Reserved2:10;\r
2178 ///\r
2179 /// [Bit 29] Enable all uncore counters.\r
2180 ///\r
2181 UINT32 EN:1;\r
2182 ///\r
2183 /// [Bit 30] Enable wake on PMI.\r
2184 ///\r
2185 UINT32 WakePMI:1;\r
2186 ///\r
2187 /// [Bit 31] Enable Freezing counter when overflow.\r
2188 ///\r
2189 UINT32 FREEZE:1;\r
2190 UINT32 Reserved3:32;\r
2191 } Bits;\r
2192 ///\r
2193 /// All bit fields as a 32-bit value\r
2194 ///\r
2195 UINT32 Uint32;\r
2196 ///\r
2197 /// All bit fields as a 64-bit value\r
2198 ///\r
2199 UINT64 Uint64;\r
2200} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
2201\r
2202\r
2203/**\r
2204 Package. Uncore PMU main status.\r
2205\r
2206 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)\r
2207 @param EAX Lower 32-bits of MSR value.\r
2208 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
2209 @param EDX Upper 32-bits of MSR value.\r
2210 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
2211\r
2212 <b>Example usage</b>\r
2213 @code\r
2214 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
2215\r
2216 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);\r
2217 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
2218 @endcode\r
2219 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
2220**/\r
2221#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
2222\r
2223/**\r
2224 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r
2225**/\r
2226typedef union {\r
2227 ///\r
2228 /// Individual bit fields\r
2229 ///\r
2230 struct {\r
2231 ///\r
2232 /// [Bit 0] Fixed counter overflowed.\r
2233 ///\r
2234 UINT32 Fixed:1;\r
2235 ///\r
2236 /// [Bit 1] An ARB counter overflowed.\r
2237 ///\r
2238 UINT32 ARB:1;\r
2239 UINT32 Reserved1:1;\r
2240 ///\r
2241 /// [Bit 3] A CBox counter overflowed (on any slice).\r
2242 ///\r
2243 UINT32 CBox:1;\r
2244 UINT32 Reserved2:28;\r
2245 UINT32 Reserved3:32;\r
2246 } Bits;\r
2247 ///\r
2248 /// All bit fields as a 32-bit value\r
2249 ///\r
2250 UINT32 Uint32;\r
2251 ///\r
2252 /// All bit fields as a 64-bit value\r
2253 ///\r
2254 UINT64 Uint64;\r
2255} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
2256\r
6b55a245 2257#endif\r
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