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[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonDMsr.h
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54307cea
MK		 1/** @file\r
2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
ba1a2d11 9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
0acd8697 10 SPDX-License-Identifier: BSD-2-Clause-Patent\r
54307cea
MK		 11\r
12 @par Specification Reference:\r
ba1a2d11
ED		 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
14 May 2018, Volume 4: Model-Specific-Registers (MSR)\r
54307cea
MK		 15\r
16**/\r
17\r
18#ifndef __XEON_D_MSR_H__\r
19#define __XEON_D_MSR_H__\r
20\r
21#include <Register/ArchitecturalMsr.h>\r
22\r
f4c982bf
JF		 23/**\r
24 Is Intel(R) Xeon(R) Processor D product Family?\r
25\r
26 @param DisplayFamily Display Family ID\r
27 @param DisplayModel Display Model ID\r
28\r
29 @retval TRUE Yes, it is.\r
30 @retval FALSE No, it isn't.\r
31**/\r
32#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \\r
33 (DisplayFamily == 0x06 && \\r
34 ( \\r
35 DisplayModel == 0x4F || \\r
36 DisplayModel == 0x56 \\r
37 ) \\r
38 )\r
39\r
54307cea
MK		 40/**\r
41 Package. Protected Processor Inventory Number Enable Control (R/W).\r
42\r
43 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)\r
44 @param EAX Lower 32-bits of MSR value.\r
45 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
46 @param EDX Upper 32-bits of MSR value.\r
47 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
48\r
49 <b>Example usage</b>\r
50 @code\r
51 MSR_XEON_D_PPIN_CTL_REGISTER Msr;\r
52\r
53 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);\r
54 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);\r
55 @endcode\r
b6ae7578 56 @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
54307cea
MK		 57**/\r
58#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
59\r
60/**\r
61 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
62**/\r
63typedef union {\r
64 ///\r
65 /// Individual bit fields\r
66 ///\r
67 struct {\r
68 ///\r
ba1a2d11 69 /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
54307cea
MK		 70 ///\r
71 UINT32 LockOut:1;\r
72 ///\r
ba1a2d11 73 /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
54307cea
MK		 74 ///\r
75 UINT32 Enable_PPIN:1;\r
76 UINT32 Reserved1:30;\r
77 UINT32 Reserved2:32;\r
78 } Bits;\r
79 ///\r
80 /// All bit fields as a 32-bit value\r
81 ///\r
82 UINT32 Uint32;\r
83 ///\r
84 /// All bit fields as a 64-bit value\r
85 ///\r
86 UINT64 Uint64;\r
87} MSR_XEON_D_PPIN_CTL_REGISTER;\r
88\r
89\r
90/**\r
91 Package. Protected Processor Inventory Number (R/O). Protected Processor\r
ba1a2d11 92 Inventory Number (R/O) See Table 2-25.\r
54307cea
MK		 93\r
94 @param ECX MSR_XEON_D_PPIN (0x0000004F)\r
95 @param EAX Lower 32-bits of MSR value.\r
96 @param EDX Upper 32-bits of MSR value.\r
97\r
98 <b>Example usage</b>\r
99 @code\r
100 UINT64 Msr;\r
101\r
102 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);\r
103 @endcode\r
b6ae7578 104 @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.\r
54307cea
MK		 105**/\r
106#define MSR_XEON_D_PPIN 0x0000004F\r
107\r
108\r
109/**\r
110 Package. See http://biosbits.org.\r
111\r
112 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)\r
113 @param EAX Lower 32-bits of MSR value.\r
114 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
115 @param EDX Upper 32-bits of MSR value.\r
116 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
117\r
118 <b>Example usage</b>\r
119 @code\r
120 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;\r
121\r
122 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);\r
123 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);\r
124 @endcode\r
b6ae7578 125 @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
54307cea
MK		 126**/\r
127#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
128\r
129/**\r
130 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
131**/\r
132typedef union {\r
133 ///\r
134 /// Individual bit fields\r
135 ///\r
136 struct {\r
137 UINT32 Reserved1:8;\r
138 ///\r
ba1a2d11 139 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
54307cea
MK		 140 ///\r
141 UINT32 MaximumNonTurboRatio:8;\r
142 UINT32 Reserved2:7;\r
143 ///\r
ba1a2d11 144 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
54307cea
MK		 145 ///\r
146 UINT32 PPIN_CAP:1;\r
147 UINT32 Reserved3:4;\r
148 ///\r
149 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
ba1a2d11 150 /// Table 2-25.\r
54307cea
MK		 151 ///\r
152 UINT32 RatioLimit:1;\r
153 ///\r
154 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
ba1a2d11 155 /// Table 2-25.\r
54307cea
MK		 156 ///\r
157 UINT32 TDPLimit:1;\r
158 ///\r
ba1a2d11 159 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
54307cea
MK		 160 ///\r
161 UINT32 TJOFFSET:1;\r
162 UINT32 Reserved4:1;\r
163 UINT32 Reserved5:8;\r
164 ///\r
ba1a2d11 165 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
54307cea
MK		 166 ///\r
167 UINT32 MaximumEfficiencyRatio:8;\r
168 UINT32 Reserved6:16;\r
169 } Bits;\r
170 ///\r
171 /// All bit fields as a 64-bit value\r
172 ///\r
173 UINT64 Uint64;\r
174} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
175\r
176\r
177/**\r
178 Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
179 specific C-state code names, unrelated to MWAIT extension C-state parameters\r
180 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
181\r
182 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
183 @param EAX Lower 32-bits of MSR value.\r
184 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
185 @param EDX Upper 32-bits of MSR value.\r
186 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
187\r
188 <b>Example usage</b>\r
189 @code\r
190 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
191\r
192 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);\r
193 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
194 @endcode\r
b6ae7578 195 @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
54307cea
MK		 196**/\r
197#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
198\r
199/**\r
200 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
201**/\r
202typedef union {\r
203 ///\r
204 /// Individual bit fields\r
205 ///\r
206 struct {\r
207 ///\r
208 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
209 /// processor-specific C-state code name (consuming the least power) for\r
210 /// the package. The default is set as factory-configured package C-state\r
211 /// limit. The following C-state code name encodings are supported: 000b:\r
212 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
213 /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
214 /// supported by the processor are available.\r
215 ///\r
216 UINT32 Limit:3;\r
217 UINT32 Reserved1:7;\r
218 ///\r
219 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
220 ///\r
221 UINT32 IO_MWAIT:1;\r
222 UINT32 Reserved2:4;\r
223 ///\r
224 /// [Bit 15] CFG Lock (R/WO).\r
225 ///\r
226 UINT32 CFGLock:1;\r
227 ///\r
228 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
229 /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
230 ///\r
231 UINT32 CStateConversion:1;\r
232 UINT32 Reserved3:8;\r
233 ///\r
234 /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
235 ///\r
236 UINT32 C3AutoDemotion:1;\r
237 ///\r
238 /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
239 ///\r
240 UINT32 C1AutoDemotion:1;\r
241 ///\r
242 /// [Bit 27] Enable C3 Undemotion (R/W).\r
243 ///\r
244 UINT32 C3Undemotion:1;\r
245 ///\r
246 /// [Bit 28] Enable C1 Undemotion (R/W).\r
247 ///\r
248 UINT32 C1Undemotion:1;\r
249 ///\r
250 /// [Bit 29] Package C State Demotion Enable (R/W).\r
251 ///\r
252 UINT32 CStateDemotion:1;\r
253 ///\r
254 /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
255 ///\r
256 UINT32 CStateUndemotion:1;\r
257 UINT32 Reserved4:1;\r
258 UINT32 Reserved5:32;\r
259 } Bits;\r
260 ///\r
261 /// All bit fields as a 32-bit value\r
262 ///\r
263 UINT32 Uint32;\r
264 ///\r
265 /// All bit fields as a 64-bit value\r
266 ///\r
267 UINT64 Uint64;\r
268} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
269\r
270\r
271/**\r
272 Thread. Global Machine Check Capability (R/O).\r
273\r
274 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)\r
275 @param EAX Lower 32-bits of MSR value.\r
276 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
277 @param EDX Upper 32-bits of MSR value.\r
278 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
279\r
280 <b>Example usage</b>\r
281 @code\r
282 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;\r
283\r
284 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);\r
285 @endcode\r
b6ae7578 286 @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
54307cea
MK		 287**/\r
288#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
289\r
290/**\r
291 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
292**/\r
293typedef union {\r
294 ///\r
295 /// Individual bit fields\r
296 ///\r
297 struct {\r
298 ///\r
299 /// [Bits 7:0] Count.\r
300 ///\r
301 UINT32 Count:8;\r
302 ///\r
303 /// [Bit 8] MCG_CTL_P.\r
304 ///\r
305 UINT32 MCG_CTL_P:1;\r
306 ///\r
307 /// [Bit 9] MCG_EXT_P.\r
308 ///\r
309 UINT32 MCG_EXT_P:1;\r
310 ///\r
311 /// [Bit 10] MCP_CMCI_P.\r
312 ///\r
313 UINT32 MCP_CMCI_P:1;\r
314 ///\r
315 /// [Bit 11] MCG_TES_P.\r
316 ///\r
317 UINT32 MCG_TES_P:1;\r
318 UINT32 Reserved1:4;\r
319 ///\r
320 /// [Bits 23:16] MCG_EXT_CNT.\r
321 ///\r
322 UINT32 MCG_EXT_CNT:8;\r
323 ///\r
324 /// [Bit 24] MCG_SER_P.\r
325 ///\r
326 UINT32 MCG_SER_P:1;\r
327 ///\r
328 /// [Bit 25] MCG_EM_P.\r
329 ///\r
330 UINT32 MCG_EM_P:1;\r
331 ///\r
332 /// [Bit 26] MCG_ELOG_P.\r
333 ///\r
334 UINT32 MCG_ELOG_P:1;\r
335 UINT32 Reserved2:5;\r
336 UINT32 Reserved3:32;\r
337 } Bits;\r
338 ///\r
339 /// All bit fields as a 32-bit value\r
340 ///\r
341 UINT32 Uint32;\r
342 ///\r
343 /// All bit fields as a 64-bit value\r
344 ///\r
345 UINT64 Uint64;\r
346} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
347\r
348\r
349/**\r
350 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
351 Enhancement. Accessible only while in SMM.\r
352\r
353 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)\r
354 @param EAX Lower 32-bits of MSR value.\r
355 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
356 @param EDX Upper 32-bits of MSR value.\r
357 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
358\r
359 <b>Example usage</b>\r
360 @code\r
361 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;\r
362\r
363 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);\r
364 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);\r
365 @endcode\r
b6ae7578 366 @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
54307cea
MK		 367**/\r
368#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
369\r
370/**\r
371 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
372**/\r
373typedef union {\r
374 ///\r
375 /// Individual bit fields\r
376 ///\r
377 struct {\r
378 UINT32 Reserved1:32;\r
379 UINT32 Reserved2:26;\r
380 ///\r
381 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
382 /// SMM code access restriction is supported and a host-space interface\r
383 /// available to SMM handler.\r
384 ///\r
385 UINT32 SMM_Code_Access_Chk:1;\r
386 ///\r
387 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
388 /// SMM long flow indicator is supported and a host-space interface\r
389 /// available to SMM handler.\r
390 ///\r
391 UINT32 Long_Flow_Indication:1;\r
392 UINT32 Reserved3:4;\r
393 } Bits;\r
394 ///\r
395 /// All bit fields as a 64-bit value\r
396 ///\r
397 UINT64 Uint64;\r
398} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
399\r
400\r
401/**\r
402 Package.\r
403\r
404 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)\r
405 @param EAX Lower 32-bits of MSR value.\r
406 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
407 @param EDX Upper 32-bits of MSR value.\r
408 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
409\r
410 <b>Example usage</b>\r
411 @code\r
412 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;\r
413\r
414 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);\r
415 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);\r
416 @endcode\r
b6ae7578 417 @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
54307cea
MK		 418**/\r
419#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
420\r
421/**\r
422 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
423**/\r
424typedef union {\r
425 ///\r
426 /// Individual bit fields\r
427 ///\r
428 struct {\r
429 UINT32 Reserved1:16;\r
430 ///\r
ba1a2d11 431 /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
54307cea
MK		 432 ///\r
433 UINT32 TemperatureTarget:8;\r
434 ///\r
ba1a2d11 435 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
54307cea
MK		 436 ///\r
437 UINT32 TCCActivationOffset:4;\r
438 UINT32 Reserved2:4;\r
439 UINT32 Reserved3:32;\r
440 } Bits;\r
441 ///\r
442 /// All bit fields as a 32-bit value\r
443 ///\r
444 UINT32 Uint32;\r
445 ///\r
446 /// All bit fields as a 64-bit value\r
447 ///\r
448 UINT64 Uint64;\r
449} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
450\r
451\r
452/**\r
453 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
454 RW if MSR_PLATFORM_INFO.[28] = 1.\r
455\r
456 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)\r
457 @param EAX Lower 32-bits of MSR value.\r
458 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
459 @param EDX Upper 32-bits of MSR value.\r
460 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
461\r
462 <b>Example usage</b>\r
463 @code\r
464 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;\r
465\r
466 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);\r
467 @endcode\r
b6ae7578 468 @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
54307cea
MK		 469**/\r
470#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
471\r
472/**\r
473 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
474**/\r
475typedef union {\r
476 ///\r
477 /// Individual bit fields\r
478 ///\r
479 struct {\r
480 ///\r
481 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
482 ///\r
483 UINT32 Maximum1C:8;\r
484 ///\r
485 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
486 ///\r
487 UINT32 Maximum2C:8;\r
488 ///\r
489 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
490 ///\r
491 UINT32 Maximum3C:8;\r
492 ///\r
493 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
494 ///\r
495 UINT32 Maximum4C:8;\r
496 ///\r
497 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
498 ///\r
499 UINT32 Maximum5C:8;\r
500 ///\r
501 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
502 ///\r
503 UINT32 Maximum6C:8;\r
504 ///\r
505 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
506 ///\r
507 UINT32 Maximum7C:8;\r
508 ///\r
509 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
510 ///\r
511 UINT32 Maximum8C:8;\r
512 } Bits;\r
513 ///\r
514 /// All bit fields as a 64-bit value\r
515 ///\r
516 UINT64 Uint64;\r
517} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
518\r
519\r
520/**\r
521 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
522 RW if MSR_PLATFORM_INFO.[28] = 1.\r
523\r
524 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)\r
525 @param EAX Lower 32-bits of MSR value.\r
526 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
527 @param EDX Upper 32-bits of MSR value.\r
528 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
529\r
530 <b>Example usage</b>\r
531 @code\r
532 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
533\r
534 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);\r
535 @endcode\r
b6ae7578 536 @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
54307cea
MK		 537**/\r
538#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
539\r
540/**\r
541 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
542**/\r
543typedef union {\r
544 ///\r
545 /// Individual bit fields\r
546 ///\r
547 struct {\r
548 ///\r
549 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
550 ///\r
551 UINT32 Maximum9C:8;\r
552 ///\r
553 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
554 ///\r
555 UINT32 Maximum10C:8;\r
556 ///\r
557 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
558 ///\r
559 UINT32 Maximum11C:8;\r
560 ///\r
561 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
562 ///\r
563 UINT32 Maximum12C:8;\r
564 ///\r
565 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
566 ///\r
567 UINT32 Maximum13C:8;\r
568 ///\r
569 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
570 ///\r
571 UINT32 Maximum14C:8;\r
572 ///\r
573 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
574 ///\r
575 UINT32 Maximum15C:8;\r
576 ///\r
577 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
578 ///\r
579 UINT32 Maximum16C:8;\r
580 } Bits;\r
581 ///\r
582 /// All bit fields as a 64-bit value\r
583 ///\r
584 UINT64 Uint64;\r
585} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
586\r
587\r
588/**\r
589 Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
590\r
591 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)\r
592 @param EAX Lower 32-bits of MSR value.\r
593 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
594 @param EDX Upper 32-bits of MSR value.\r
595 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
596\r
597 <b>Example usage</b>\r
598 @code\r
599 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;\r
600\r
601 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);\r
602 @endcode\r
b6ae7578 603 @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
54307cea
MK		 604**/\r
605#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
606\r
607/**\r
608 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
609**/\r
610typedef union {\r
611 ///\r
612 /// Individual bit fields\r
613 ///\r
614 struct {\r
615 ///\r
616 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
617 ///\r
618 UINT32 PowerUnits:4;\r
619 UINT32 Reserved1:4;\r
620 ///\r
621 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
622 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
623 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
624 /// micro-joules).\r
625 ///\r
626 UINT32 EnergyStatusUnits:5;\r
627 UINT32 Reserved2:3;\r
628 ///\r
629 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
630 /// Interfaces.".\r
631 ///\r
632 UINT32 TimeUnits:4;\r
633 UINT32 Reserved3:12;\r
634 UINT32 Reserved4:32;\r
635 } Bits;\r
636 ///\r
637 /// All bit fields as a 32-bit value\r
638 ///\r
639 UINT32 Uint32;\r
640 ///\r
641 /// All bit fields as a 64-bit value\r
642 ///\r
643 UINT64 Uint64;\r
644} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
645\r
646\r
647/**\r
648 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
649 Domain.".\r
650\r
651 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)\r
652 @param EAX Lower 32-bits of MSR value.\r
653 @param EDX Upper 32-bits of MSR value.\r
654\r
655 <b>Example usage</b>\r
656 @code\r
657 UINT64 Msr;\r
658\r
659 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);\r
660 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);\r
661 @endcode\r
b6ae7578 662 @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
54307cea
MK		 663**/\r
664#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
665\r
666\r
667/**\r
0f16be6d 668 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
54307cea
MK		 669\r
670 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
671 @param EAX Lower 32-bits of MSR value.\r
0f16be6d 672 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
54307cea 673 @param EDX Upper 32-bits of MSR value.\r
0f16be6d 674 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
54307cea
MK		 675\r
676 <b>Example usage</b>\r
677 @code\r
0f16be6d 678 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;\r
54307cea 679\r
0f16be6d 680 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
54307cea 681 @endcode\r
b6ae7578 682 @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
54307cea
MK		 683**/\r
684#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
685\r
0f16be6d
HW		 686/**\r
687 MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
688**/\r
689typedef union {\r
690 ///\r
691 /// Individual bit fields\r
692 ///\r
693 struct {\r
694 ///\r
695 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
696 /// to enable DRAM RAPL mode 0 (Direct VR).\r
697 ///\r
698 UINT32 Energy:32;\r
699 UINT32 Reserved:32;\r
700 } Bits;\r
701 ///\r
702 /// All bit fields as a 32-bit value\r
703 ///\r
704 UINT32 Uint32;\r
705 ///\r
706 /// All bit fields as a 64-bit value\r
707 ///\r
708 UINT64 Uint64;\r
709} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
710\r
54307cea
MK		 711\r
712/**\r
713 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
714 RAPL Domain.".\r
715\r
716 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)\r
717 @param EAX Lower 32-bits of MSR value.\r
718 @param EDX Upper 32-bits of MSR value.\r
719\r
720 <b>Example usage</b>\r
721 @code\r
722 UINT64 Msr;\r
723\r
724 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);\r
725 @endcode\r
b6ae7578 726 @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
54307cea
MK		 727**/\r
728#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
729\r
730\r
731/**\r
732 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
733\r
734 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)\r
735 @param EAX Lower 32-bits of MSR value.\r
736 @param EDX Upper 32-bits of MSR value.\r
737\r
738 <b>Example usage</b>\r
739 @code\r
740 UINT64 Msr;\r
741\r
742 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);\r
743 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);\r
744 @endcode\r
b6ae7578 745 @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
54307cea
MK		 746**/\r
747#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
748\r
749\r
0f16be6d 750/**\r
c4b07363
ED		 751 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
752 fields represent the widest possible range of uncore frequencies. Writing to\r
753 these fields allows software to control the minimum and the maximum\r
754 frequency that hardware will select.\r
755\r
756 @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
757 @param EAX Lower 32-bits of MSR value.\r
758 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
759 @param EDX Upper 32-bits of MSR value.\r
760 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
761\r
762 <b>Example usage</b>\r
763 @code\r
764 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
765\r
766 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);\r
767 AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
768 @endcode\r
769**/\r
770#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
771\r
772/**\r
773 MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT\r
774**/\r
775typedef union {\r
776 ///\r
777 /// Individual bit fields\r
778 ///\r
779 struct {\r
780 ///\r
781 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
782 /// LLC/Ring.\r
783 ///\r
784 UINT32 MAX_RATIO:7;\r
785 UINT32 Reserved1:1;\r
786 ///\r
787 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
788 /// possible ratio of the LLC/Ring.\r
789 ///\r
790 UINT32 MIN_RATIO:7;\r
791 UINT32 Reserved2:17;\r
792 UINT32 Reserved3:32;\r
793 } Bits;\r
794 ///\r
795 /// All bit fields as a 32-bit value\r
796 ///\r
797 UINT32 Uint32;\r
798 ///\r
799 /// All bit fields as a 64-bit value\r
800 ///\r
801 UINT64 Uint64;\r
802} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
803\r
804/**\r
805 Package. Reserved (R/O) Reads return 0.\r
0f16be6d
HW		 806\r
807 @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)\r
808 @param EAX Lower 32-bits of MSR value.\r
809 @param EDX Upper 32-bits of MSR value.\r
810\r
811 <b>Example usage</b>\r
812 @code\r
813 UINT64 Msr;\r
814\r
815 Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);\r
816 @endcode\r
817 @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
818**/\r
819#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
820\r
821\r
54307cea
MK		 822/**\r
823 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
824 refers to processor core frequency).\r
825\r
826 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)\r
827 @param EAX Lower 32-bits of MSR value.\r
828 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
829 @param EDX Upper 32-bits of MSR value.\r
830 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
831\r
832 <b>Example usage</b>\r
833 @code\r
834 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
835\r
836 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);\r
837 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
838 @endcode\r
b6ae7578 839 @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
54307cea
MK		 840**/\r
841#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
842\r
843/**\r
844 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
845**/\r
846typedef union {\r
847 ///\r
848 /// Individual bit fields\r
849 ///\r
850 struct {\r
851 ///\r
852 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
853 /// reduced below the operating system request due to assertion of\r
854 /// external PROCHOT.\r
855 ///\r
856 UINT32 PROCHOT_Status:1;\r
857 ///\r
858 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
859 /// operating system request due to a thermal event.\r
860 ///\r
861 UINT32 ThermalStatus:1;\r
862 ///\r
863 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
864 /// reduced below the operating system request due to PBM limit.\r
865 ///\r
866 UINT32 PowerBudgetManagementStatus:1;\r
867 ///\r
868 /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
869 /// frequency is reduced below the operating system request due to PCS\r
870 /// limit.\r
871 ///\r
872 UINT32 PlatformConfigurationServicesStatus:1;\r
873 UINT32 Reserved1:1;\r
874 ///\r
875 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
876 /// When set, frequency is reduced below the operating system request\r
877 /// because the processor has detected that utilization is low.\r
878 ///\r
879 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
880 ///\r
881 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
882 /// below the operating system request due to a thermal alert from the\r
883 /// Voltage Regulator.\r
884 ///\r
885 UINT32 VRThermAlertStatus:1;\r
886 UINT32 Reserved2:1;\r
887 ///\r
888 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
889 /// reduced below the operating system request due to electrical design\r
890 /// point constraints (e.g. maximum electrical current consumption).\r
891 ///\r
892 UINT32 ElectricalDesignPointStatus:1;\r
893 UINT32 Reserved3:1;\r
894 ///\r
895 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
896 /// below the operating system request due to Multi-Core Turbo limits.\r
897 ///\r
898 UINT32 MultiCoreTurboStatus:1;\r
899 UINT32 Reserved4:2;\r
900 ///\r
901 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
902 /// below max non-turbo P1.\r
903 ///\r
904 UINT32 FrequencyP1Status:1;\r
905 ///\r
906 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
907 /// set, frequency is reduced below max n-core turbo frequency.\r
908 ///\r
909 UINT32 TurboFrequencyLimitingStatus:1;\r
910 ///\r
911 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
912 /// reduced below the operating system request.\r
913 ///\r
914 UINT32 FrequencyLimitingStatus:1;\r
915 ///\r
916 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
917 /// has asserted since the log bit was last cleared. This log bit will\r
918 /// remain set until cleared by software writing 0.\r
919 ///\r
920 UINT32 PROCHOT_Log:1;\r
921 ///\r
922 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
923 /// has asserted since the log bit was last cleared. This log bit will\r
924 /// remain set until cleared by software writing 0.\r
925 ///\r
926 UINT32 ThermalLog:1;\r
927 ///\r
928 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
929 /// Status bit has asserted since the log bit was last cleared. This log\r
930 /// bit will remain set until cleared by software writing 0.\r
931 ///\r
932 UINT32 PowerBudgetManagementLog:1;\r
933 ///\r
934 /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
935 /// the PCS Status bit has asserted since the log bit was last cleared.\r
936 /// This log bit will remain set until cleared by software writing 0.\r
937 ///\r
938 UINT32 PlatformConfigurationServicesLog:1;\r
939 UINT32 Reserved5:1;\r
940 ///\r
941 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
942 /// indicates that the AUBFC Status bit has asserted since the log bit was\r
943 /// last cleared. This log bit will remain set until cleared by software\r
944 /// writing 0.\r
945 ///\r
946 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
947 ///\r
948 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
949 /// Alert Status bit has asserted since the log bit was last cleared. This\r
950 /// log bit will remain set until cleared by software writing 0.\r
951 ///\r
952 UINT32 VRThermAlertLog:1;\r
953 UINT32 Reserved6:1;\r
954 ///\r
955 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
956 /// Status bit has asserted since the log bit was last cleared. This log\r
957 /// bit will remain set until cleared by software writing 0.\r
958 ///\r
959 UINT32 ElectricalDesignPointLog:1;\r
960 UINT32 Reserved7:1;\r
961 ///\r
962 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
963 /// Turbo Status bit has asserted since the log bit was last cleared. This\r
964 /// log bit will remain set until cleared by software writing 0.\r
965 ///\r
966 UINT32 MultiCoreTurboLog:1;\r
967 UINT32 Reserved8:2;\r
968 ///\r
969 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
970 /// Frequency P1 Status bit has asserted since the log bit was last\r
971 /// cleared. This log bit will remain set until cleared by software\r
972 /// writing 0.\r
973 ///\r
974 UINT32 CoreFrequencyP1Log:1;\r
975 ///\r
976 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
977 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
978 /// has asserted since the log bit was last cleared. This log bit will\r
979 /// remain set until cleared by software writing 0.\r
980 ///\r
981 UINT32 TurboFrequencyLimitingLog:1;\r
982 ///\r
983 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
984 /// Frequency Limiting Status bit has asserted since the log bit was last\r
985 /// cleared. This log bit will remain set until cleared by software\r
986 /// writing 0.\r
987 ///\r
988 UINT32 CoreFrequencyLimitingLog:1;\r
989 UINT32 Reserved9:32;\r
990 } Bits;\r
991 ///\r
992 /// All bit fields as a 32-bit value\r
993 ///\r
994 UINT32 Uint32;\r
995 ///\r
996 /// All bit fields as a 64-bit value\r
997 ///\r
998 UINT64 Uint64;\r
999} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
1000\r
1001\r
1002/**\r
1003 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
0f16be6d 1004 ECX=0):EBX.RDT-M[bit 12] = 1.\r
54307cea
MK		 1005\r
1006 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
1007 @param EAX Lower 32-bits of MSR value.\r
1008 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
1009 @param EDX Upper 32-bits of MSR value.\r
1010 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
1011\r
1012 <b>Example usage</b>\r
1013 @code\r
1014 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;\r
1015\r
1016 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);\r
1017 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);\r
1018 @endcode\r
b6ae7578 1019 @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
54307cea
MK		 1020**/\r
1021#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
1022\r
1023/**\r
1024 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
1025**/\r
1026typedef union {\r
1027 ///\r
1028 /// Individual bit fields\r
1029 ///\r
1030 struct {\r
1031 ///\r
1032 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3\r
1033 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
1034 /// Local memory bandwidth monitoring All other encoding reserved.\r
1035 ///\r
1036 UINT32 EventID:8;\r
1037 UINT32 Reserved1:24;\r
1038 ///\r
1039 /// [Bits 41:32] RMID (RW).\r
1040 ///\r
1041 UINT32 RMID:10;\r
1042 UINT32 Reserved2:22;\r
1043 } Bits;\r
1044 ///\r
1045 /// All bit fields as a 64-bit value\r
1046 ///\r
1047 UINT64 Uint64;\r
1048} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
1049\r
1050\r
1051/**\r
1052 THREAD. Resource Association Register (R/W).\r
1053\r
1054 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)\r
1055 @param EAX Lower 32-bits of MSR value.\r
1056 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
1057 @param EDX Upper 32-bits of MSR value.\r
1058 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
1059\r
1060 <b>Example usage</b>\r
1061 @code\r
1062 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;\r
1063\r
1064 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);\r
1065 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);\r
1066 @endcode\r
b6ae7578 1067 @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
54307cea
MK		 1068**/\r
1069#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
1070\r
1071/**\r
1072 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
1073**/\r
1074typedef union {\r
1075 ///\r
1076 /// Individual bit fields\r
1077 ///\r
1078 struct {\r
1079 ///\r
1080 /// [Bits 9:0] RMID.\r
1081 ///\r
1082 UINT32 RMID:10;\r
1083 UINT32 Reserved1:22;\r
1084 ///\r
1085 /// [Bits 51:32] COS (R/W).\r
1086 ///\r
1087 UINT32 COS:20;\r
1088 UINT32 Reserved2:12;\r
1089 } Bits;\r
1090 ///\r
1091 /// All bit fields as a 64-bit value\r
1092 ///\r
1093 UINT64 Uint64;\r
1094} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
1095\r
1096\r
1097/**\r
1098 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
1099 ECX=1):EDX.COS_MAX[15:0] >= n.\r
1100\r
1101 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n\r
1102 @param EAX Lower 32-bits of MSR value.\r
1103 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
1104 @param EDX Upper 32-bits of MSR value.\r
1105 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
1106\r
1107 <b>Example usage</b>\r
1108 @code\r
1109 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;\r
1110\r
1111 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);\r
1112 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);\r
1113 @endcode\r
b6ae7578
JF		 1114 @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM.\r
1115 MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM.\r
1116 MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM.\r
1117 MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM.\r
1118 MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM.\r
1119 MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM.\r
1120 MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM.\r
1121 MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM.\r
1122 MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM.\r
1123 MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM.\r
1124 MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.\r
1125 MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.\r
1126 MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.\r
1127 MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.\r
1128 MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.\r
1129 MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.\r
54307cea
MK		 1130 @{\r
1131**/\r
1132#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
1133#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
1134#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
1135#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
1136#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
1137#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
1138#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
1139#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
1140#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
1141#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
1142#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
1143#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
1144#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
1145#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
1146#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
1147#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
1148/// @}\r
1149\r
1150/**\r
1151 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0\r
1152 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.\r
1153**/\r
1154typedef union {\r
1155 ///\r
1156 /// Individual bit fields\r
1157 ///\r
1158 struct {\r
1159 ///\r
1160 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
1161 ///\r
1162 UINT32 CBM:20;\r
1163 UINT32 Reserved2:12;\r
1164 UINT32 Reserved3:32;\r
1165 } Bits;\r
1166 ///\r
1167 /// All bit fields as a 32-bit value\r
1168 ///\r
1169 UINT32 Uint32;\r
1170 ///\r
1171 /// All bit fields as a 64-bit value\r
1172 ///\r
1173 UINT64 Uint64;\r
1174} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
1175\r
1176\r
1177/**\r
1178 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
1179 RW if MSR_PLATFORM_INFO.[28] = 1.\r
1180\r
1181 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)\r
1182 @param EAX Lower 32-bits of MSR value.\r
1183 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1184 @param EDX Upper 32-bits of MSR value.\r
1185 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1186\r
1187 <b>Example usage</b>\r
1188 @code\r
1189 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;\r
1190\r
1191 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);\r
1192 @endcode\r
b6ae7578 1193 @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.\r
54307cea
MK		 1194**/\r
1195#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
1196\r
1197/**\r
1198 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
1199**/\r
1200typedef union {\r
1201 ///\r
1202 /// Individual bit fields\r
1203 ///\r
1204 struct {\r
1205 UINT32 Reserved1:32;\r
1206 UINT32 Reserved2:31;\r
1207 ///\r
1208 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
1209 /// the processor uses override configuration specified in\r
1210 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
1211 /// uses factory-set configuration (Default).\r
1212 ///\r
1213 UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
1214 } Bits;\r
1215 ///\r
1216 /// All bit fields as a 64-bit value\r
1217 ///\r
1218 UINT64 Uint64;\r
1219} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
1220\r
1221\r
54307cea
MK		 1222/**\r
1223 Package. Cache Allocation Technology Configuration (R/W).\r
1224\r
1225 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)\r
1226 @param EAX Lower 32-bits of MSR value.\r
1227 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1228 @param EDX Upper 32-bits of MSR value.\r
1229 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1230\r
1231 <b>Example usage</b>\r
1232 @code\r
1233 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;\r
1234\r
1235 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);\r
1236 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);\r
1237 @endcode\r
b6ae7578 1238 @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
54307cea
MK		 1239**/\r
1240#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
1241\r
1242/**\r
1243 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
1244**/\r
1245typedef union {\r
1246 ///\r
1247 /// Individual bit fields\r
1248 ///\r
1249 struct {\r
1250 ///\r
1251 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
1252 ///\r
1253 UINT32 CAT:1;\r
1254 UINT32 Reserved1:31;\r
1255 UINT32 Reserved2:32;\r
1256 } Bits;\r
1257 ///\r
1258 /// All bit fields as a 32-bit value\r
1259 ///\r
1260 UINT32 Uint32;\r
1261 ///\r
1262 /// All bit fields as a 64-bit value\r
1263 ///\r
1264 UINT64 Uint64;\r
1265} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
1266\r
1267#endif\r
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