[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonE7Msr.h

/** @file\r
  MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.\r
\r
**/\r
\r
#ifndef __XEON_E7_MSR_H__\r
#define __XEON_E7_MSR_H__\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel(R) Xeon(R) Processor E7 Family?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x2F    \\r
    )                       \\r
   )\r
\r
/**\r
  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
  handler to handle unsuccessful read of this MSR.\r
\r
  @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
  AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
  @endcode\r
  @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
#define MSR_XEON_E7_FEATURE_CONFIG               0x0000013C\r
\r
/**\r
  MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this\r
    /// MSR, the configuration of AES instruction set availability is as\r
    /// follows: 11b: AES instructions are not available until next RESET.\r
    /// otherwise, AES instructions are available. Note, AES instruction set\r
    /// is not available if read is unsuccessful. If the configuration is not\r
    /// 01b, AES instruction can be mis-configured if a privileged agent\r
    /// unintentionally writes 11b.\r
    ///\r
    UINT32  AESConfiguration:2;\r
    UINT32  Reserved1:30;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
\r
\r
/**\r
  Thread. Offcore Response Event Select Register (R/W).\r
\r
  @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
  AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
#define MSR_XEON_E7_OFFCORE_RSP_1                0x000001A7\r
\r
\r
/**\r
  Package. Reserved Attempt to read/write will cause #UD.\r
\r
  @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
  AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD\r
\r
\r
/**\r
  Package. Uncore C-box 8 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40\r
\r
\r
/**\r
  Package. Uncore C-box 8 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41\r
\r
\r
/**\r
  Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42\r
\r
\r
/**\r
  Package. Uncore C-box 8 perfmon event select MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL1            0x00000F52\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL2            0x00000F54\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL3            0x00000F56\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL4            0x00000F58\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL5            0x00000F5A\r
/// @}\r
\r
\r
/**\r
  Package. Uncore C-box 8 perfmon counter MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_CTRn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51\r
#define MSR_XEON_E7_C8_PMON_CTR1                 0x00000F53\r
#define MSR_XEON_E7_C8_PMON_CTR2                 0x00000F55\r
#define MSR_XEON_E7_C8_PMON_CTR3                 0x00000F57\r
#define MSR_XEON_E7_C8_PMON_CTR4                 0x00000F59\r
#define MSR_XEON_E7_C8_PMON_CTR5                 0x00000F5B\r
/// @}\r
\r
\r
/**\r
  Package. Uncore C-box 9 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0\r
\r
\r
/**\r
  Package. Uncore C-box 9 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1\r
\r
\r
/**\r
  Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2\r
\r
\r
/**\r
  Package. Uncore C-box 9 perfmon event select MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL1            0x00000FD2\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL2            0x00000FD4\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL3            0x00000FD6\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL4            0x00000FD8\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL5            0x00000FDA\r
/// @}\r
\r
\r
/**\r
  Package. Uncore C-box 9 perfmon counter MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_CTRn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1\r
#define MSR_XEON_E7_C9_PMON_CTR1                 0x00000FD3\r
#define MSR_XEON_E7_C9_PMON_CTR2                 0x00000FD5\r
#define MSR_XEON_E7_C9_PMON_CTR3                 0x00000FD7\r
#define MSR_XEON_E7_C9_PMON_CTR4                 0x00000FD9\r
#define MSR_XEON_E7_C9_PMON_CTR5                 0x00000FDB\r
/// @}\r
\r
#endif\r
Commit	Line	Data
ebb74e4a MK	1	/** @file\r
	2	MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
f4c982bf	9	Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
ebb74e4a MK	10	This program and the accompanying materials\r
	11	are licensed and made available under the terms and conditions of the BSD License\r
	12	which accompanies this distribution. The full text of the license may be found at\r
	13	http://opensource.org/licenses/bsd-license.php\r
	14	\r
	15	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	16	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	17	\r
	18	@par Specification Reference:\r
	19	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
0f16be6d	20	September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.\r
ebb74e4a MK	21	\r
	22	**/\r
	23	\r
	24	#ifndef __XEON_E7_MSR_H__\r
	25	#define __XEON_E7_MSR_H__\r
	26	\r
	27	#include <Register/ArchitecturalMsr.h>\r
	28	\r
f4c982bf JF	29	/**\r
	30	Is Intel(R) Xeon(R) Processor E7 Family?\r
	31	\r
	32	@param DisplayFamily Display Family ID\r
	33	@param DisplayModel Display Model ID\r
	34	\r
	35	@retval TRUE Yes, it is.\r
	36	@retval FALSE No, it isn't.\r
	37	**/\r
	38	#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \\r
	39	(DisplayFamily == 0x06 && \\r
	40	( \\r
	41	DisplayModel == 0x2F \\r
	42	) \\r
	43	)\r
	44	\r
0f16be6d HW	45	/**\r
	46	Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
	47	handler to handle unsuccessful read of this MSR.\r
	48	\r
	49	@param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
	50	@param EAX Lower 32-bits of MSR value.\r
	51	Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
	52	@param EDX Upper 32-bits of MSR value.\r
	53	Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
	54	\r
	55	<b>Example usage</b>\r
	56	@code\r
	57	MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;\r
	58	\r
	59	Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
	60	AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
	61	@endcode\r
	62	@note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
	63	**/\r
	64	#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r
	65	\r
	66	/**\r
	67	MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
	68	**/\r
	69	typedef union {\r
	70	///\r
	71	/// Individual bit fields\r
	72	///\r
	73	struct {\r
	74	///\r
	75	/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
	76	/// MSR, the configuration of AES instruction set availability is as\r
	77	/// follows: 11b: AES instructions are not available until next RESET.\r
	78	/// otherwise, AES instructions are available. Note, AES instruction set\r
	79	/// is not available if read is unsuccessful. If the configuration is not\r
	80	/// 01b, AES instruction can be mis-configured if a privileged agent\r
	81	/// unintentionally writes 11b.\r
	82	///\r
	83	UINT32 AESConfiguration:2;\r
	84	UINT32 Reserved1:30;\r
	85	UINT32 Reserved2:32;\r
	86	} Bits;\r
	87	///\r
	88	/// All bit fields as a 32-bit value\r
	89	///\r
	90	UINT32 Uint32;\r
	91	///\r
	92	/// All bit fields as a 64-bit value\r
	93	///\r
	94	UINT64 Uint64;\r
	95	} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
	96	\r
	97	\r
	98	/**\r
	99	Thread. Offcore Response Event Select Register (R/W).\r
	100	\r
	101	@param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
	102	@param EAX Lower 32-bits of MSR value.\r
	103	@param EDX Upper 32-bits of MSR value.\r
	104	\r
	105	<b>Example usage</b>\r
	106	@code\r
	107	UINT64 Msr;\r
	108	\r
109	Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
110	AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
111	@endcode\r
112	@note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
113	**/\r
114	#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r
115	\r
116	\r
ebb74e4a MK	117	/**\r
	118	Package. Reserved Attempt to read/write will cause #UD.\r
	119	\r
	120	@param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r
	121	@param EAX Lower 32-bits of MSR value.\r
	122	@param EDX Upper 32-bits of MSR value.\r
	123	\r
	124	<b>Example usage</b>\r
	125	@code\r
	126	UINT64 Msr;\r
	127	\r
	128	Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
	129	AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
	130	@endcode\r
97ea5b7f	131	@note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
ebb74e4a MK	132	**/\r
	133	#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r
	134	\r
	135	\r
	136	/**\r
	137	Package. Uncore C-box 8 perfmon local box control MSR.\r
	138	\r
	139	@param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r
	140	@param EAX Lower 32-bits of MSR value.\r
	141	@param EDX Upper 32-bits of MSR value.\r
	142	\r
	143	<b>Example usage</b>\r
	144	@code\r
	145	UINT64 Msr;\r
	146	\r
	147	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
	148	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
	149	@endcode\r
97ea5b7f	150	@note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
ebb74e4a MK	151	**/\r
	152	#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r
	153	\r
	154	\r
	155	/**\r
	156	Package. Uncore C-box 8 perfmon local box status MSR.\r
	157	\r
	158	@param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r
	159	@param EAX Lower 32-bits of MSR value.\r
	160	@param EDX Upper 32-bits of MSR value.\r
	161	\r
	162	<b>Example usage</b>\r
	163	@code\r
	164	UINT64 Msr;\r
	165	\r
	166	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
	167	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
	168	@endcode\r
97ea5b7f	169	@note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
ebb74e4a MK	170	**/\r
	171	#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r
	172	\r
	173	\r
	174	/**\r
	175	Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
	176	\r
	177	@param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r
	178	@param EAX Lower 32-bits of MSR value.\r
	179	@param EDX Upper 32-bits of MSR value.\r
	180	\r
	181	<b>Example usage</b>\r
	182	@code\r
	183	UINT64 Msr;\r
	184	\r
	185	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
	186	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
	187	@endcode\r
97ea5b7f	188	@note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
ebb74e4a MK	189	**/\r
	190	#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r
	191	\r
	192	\r
	193	/**\r
	194	Package. Uncore C-box 8 perfmon event select MSR.\r
	195	\r
	196	@param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn\r
	197	@param EAX Lower 32-bits of MSR value.\r
	198	@param EDX Upper 32-bits of MSR value.\r
	199	\r
	200	<b>Example usage</b>\r
	201	@code\r
	202	UINT64 Msr;\r
	203	\r
	204	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
	205	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
	206	@endcode\r
97ea5b7f JF	207	@note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
	208	MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
	209	MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
	210	MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
	211	MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
	212	MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
ebb74e4a MK	213	@{\r
	214	**/\r
	215	#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r
	216	#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r
	217	#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r
	218	#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r
	219	#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r
	220	#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r
	221	/// @}\r
	222	\r
	223	\r
	224	/**\r
	225	Package. Uncore C-box 8 perfmon counter MSR.\r
	226	\r
	227	@param ECX MSR_XEON_E7_C8_PMON_CTRn\r
	228	@param EAX Lower 32-bits of MSR value.\r
	229	@param EDX Upper 32-bits of MSR value.\r
	230	\r
	231	<b>Example usage</b>\r
	232	@code\r
	233	UINT64 Msr;\r
	234	\r
	235	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
	236	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
	237	@endcode\r
97ea5b7f JF	238	@note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
	239	MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
	240	MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
	241	MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
	242	MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
	243	MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
ebb74e4a MK	244	@{\r
	245	**/\r
	246	#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r
	247	#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r
	248	#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r
	249	#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r
	250	#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r
	251	#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r
	252	/// @}\r
	253	\r
	254	\r
	255	/**\r
	256	Package. Uncore C-box 9 perfmon local box control MSR.\r
	257	\r
	258	@param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r
	259	@param EAX Lower 32-bits of MSR value.\r
	260	@param EDX Upper 32-bits of MSR value.\r
	261	\r
	262	<b>Example usage</b>\r
	263	@code\r
	264	UINT64 Msr;\r
	265	\r
	266	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
	267	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
	268	@endcode\r
97ea5b7f	269	@note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
ebb74e4a MK	270	**/\r
	271	#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r
	272	\r
	273	\r
	274	/**\r
	275	Package. Uncore C-box 9 perfmon local box status MSR.\r
	276	\r
	277	@param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r
	278	@param EAX Lower 32-bits of MSR value.\r
	279	@param EDX Upper 32-bits of MSR value.\r
	280	\r
	281	<b>Example usage</b>\r
	282	@code\r
	283	UINT64 Msr;\r
	284	\r
	285	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
	286	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
	287	@endcode\r
97ea5b7f	288	@note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
ebb74e4a MK	289	**/\r
	290	#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r
	291	\r
	292	\r
	293	/**\r
	294	Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
	295	\r
	296	@param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r
	297	@param EAX Lower 32-bits of MSR value.\r
	298	@param EDX Upper 32-bits of MSR value.\r
	299	\r
	300	<b>Example usage</b>\r
	301	@code\r
	302	UINT64 Msr;\r
	303	\r
	304	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
	305	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
	306	@endcode\r
97ea5b7f	307	@note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
ebb74e4a MK	308	**/\r
	309	#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r
	310	\r
	311	\r
	312	/**\r
	313	Package. Uncore C-box 9 perfmon event select MSR.\r
	314	\r
	315	@param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn\r
	316	@param EAX Lower 32-bits of MSR value.\r
	317	@param EDX Upper 32-bits of MSR value.\r
	318	\r
	319	<b>Example usage</b>\r
	320	@code\r
	321	UINT64 Msr;\r
	322	\r
	323	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
	324	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
	325	@endcode\r
97ea5b7f JF	326	@note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
	327	MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
	328	MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
	329	MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
	330	MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
	331	MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
ebb74e4a MK	332	@{\r
	333	**/\r
	334	#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r
	335	#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r
	336	#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r
	337	#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r
	338	#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r
	339	#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r
	340	/// @}\r
	341	\r
	342	\r
	343	/**\r
	344	Package. Uncore C-box 9 perfmon counter MSR.\r
	345	\r
	346	@param ECX MSR_XEON_E7_C9_PMON_CTRn\r
	347	@param EAX Lower 32-bits of MSR value.\r
	348	@param EDX Upper 32-bits of MSR value.\r
	349	\r
	350	<b>Example usage</b>\r
	351	@code\r
	352	UINT64 Msr;\r
	353	\r
	354	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
	355	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
	356	@endcode\r
97ea5b7f JF	357	@note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
	358	MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
	359	MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
	360	MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
	361	MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
	362	MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
ebb74e4a MK	363	@{\r
	364	**/\r
	365	#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r
	366	#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r
	367	#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r
	368	#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r
	369	#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r
	370	#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r
	371	/// @}\r
	372	\r
	373	#endif\r