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1 | /** @file\r |
2 | MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3adf6316 MK |
11 | \r |
12 | @par Specification Reference:\r | |
ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
3adf6316 MK |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __XEON_PHI_MSR_H__\r | |
19 | #define __XEON_PHI_MSR_H__\r | |
20 | \r | |
21 | #include <Register/ArchitecturalMsr.h>\r | |
22 | \r | |
f4c982bf JF |
23 | /**\r |
24 | Is Intel(R) Xeon(R) Phi(TM) processor Family?\r | |
25 | \r | |
26 | @param DisplayFamily Display Family ID\r | |
27 | @param DisplayModel Display Model ID\r | |
28 | \r | |
29 | @retval TRUE Yes, it is.\r | |
30 | @retval FALSE No, it isn't.\r | |
31 | **/\r | |
32 | #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
33 | (DisplayFamily == 0x06 && \\r | |
34 | ( \\r | |
dfb20851 ED |
35 | DisplayModel == 0x57 || \\r |
36 | DisplayModel == 0x85 \\r | |
f4c982bf JF |
37 | ) \\r |
38 | )\r | |
39 | \r | |
3adf6316 MK |
40 | /**\r |
41 | Thread. SMI Counter (R/O).\r | |
42 | \r | |
43 | @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)\r | |
44 | @param EAX Lower 32-bits of MSR value.\r | |
45 | Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r | |
46 | @param EDX Upper 32-bits of MSR value.\r | |
47 | Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r | |
48 | \r | |
49 | <b>Example usage</b>\r | |
50 | @code\r | |
51 | MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;\r | |
52 | \r | |
53 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r | |
54 | @endcode\r | |
ad8a2f5e | 55 | @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r |
3adf6316 MK |
56 | **/\r |
57 | #define MSR_XEON_PHI_SMI_COUNT 0x00000034\r | |
58 | \r | |
59 | /**\r | |
60 | MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r | |
61 | **/\r | |
62 | typedef union {\r | |
63 | ///\r | |
64 | /// Individual bit fields\r | |
65 | ///\r | |
66 | struct {\r | |
67 | ///\r | |
68 | /// [Bits 31:0] SMI Count (R/O).\r | |
69 | ///\r | |
70 | UINT32 SMICount:32;\r | |
71 | UINT32 Reserved:32;\r | |
72 | } Bits;\r | |
73 | ///\r | |
74 | /// All bit fields as a 32-bit value\r | |
75 | ///\r | |
76 | UINT32 Uint32;\r | |
77 | ///\r | |
78 | /// All bit fields as a 64-bit value\r | |
79 | ///\r | |
80 | UINT64 Uint64;\r | |
81 | } MSR_XEON_PHI_SMI_COUNT_REGISTER;\r | |
82 | \r | |
dfb20851 ED |
83 | /**\r |
84 | Package. Protected Processor Inventory Number Enable Control (R/W).\r | |
85 | \r | |
86 | @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)\r | |
87 | @param EAX Lower 32-bits of MSR value.\r | |
88 | Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r | |
89 | @param EDX Upper 32-bits of MSR value.\r | |
90 | Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r | |
91 | \r | |
92 | <b>Example usage</b>\r | |
93 | @code\r | |
94 | MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;\r | |
95 | \r | |
96 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);\r | |
97 | AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r | |
98 | @endcode\r | |
99 | **/\r | |
100 | #define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r | |
3adf6316 MK |
101 | \r |
102 | /**\r | |
dfb20851 ED |
103 | MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r |
104 | **/\r | |
105 | typedef union {\r | |
106 | ///\r | |
107 | /// Individual bit fields\r | |
108 | ///\r | |
109 | struct {\r | |
110 | ///\r | |
111 | /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to\r | |
112 | /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if\r | |
113 | /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an\r | |
114 | /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a\r | |
115 | /// privileged inventory initialization agent to access MSR_PPIN. After\r | |
116 | /// reading MSR_PPIN, the privileged inventory initialization agent should\r | |
117 | /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r | |
118 | /// prevent unauthorized modification to MSR_PPIN_CTL.\r | |
119 | ///\r | |
120 | UINT32 LockOut:1;\r | |
121 | ///\r | |
122 | /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r | |
123 | /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r | |
124 | /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r | |
125 | /// Default is 0.\r | |
126 | ///\r | |
127 | UINT32 Enable_PPIN:1;\r | |
128 | UINT32 Reserved1:30;\r | |
129 | UINT32 Reserved2:32;\r | |
130 | } Bits;\r | |
131 | ///\r | |
132 | /// All bit fields as a 32-bit value\r | |
133 | ///\r | |
134 | UINT32 Uint32;\r | |
135 | ///\r | |
136 | /// All bit fields as a 64-bit value\r | |
137 | ///\r | |
138 | UINT64 Uint64;\r | |
139 | } MSR_XEON_PHI_PPIN_CTL_REGISTER;\r | |
140 | \r | |
141 | \r | |
142 | /**\r | |
143 | Package. Protected Processor Inventory Number (R/O). Protected Processor\r | |
144 | Inventory Number (R/O) A unique value within a given CPUID\r | |
145 | family/model/stepping signature that a privileged inventory initialization\r | |
146 | agent can access to identify each physical processor, when access to\r | |
147 | MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r | |
148 | MSR_PPIN_CTL[bits 1:0] = '10b'.\r | |
149 | \r | |
150 | @param ECX MSR_XEON_PHI_PPIN (0x0000004F)\r | |
151 | @param EAX Lower 32-bits of MSR value.\r | |
152 | @param EDX Upper 32-bits of MSR value.\r | |
153 | \r | |
154 | <b>Example usage</b>\r | |
155 | @code\r | |
156 | UINT64 Msr;\r | |
157 | \r | |
158 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r | |
159 | @endcode\r | |
160 | **/\r | |
161 | #define MSR_XEON_PHI_PPIN 0x0000004F\r | |
162 | \r | |
163 | /**\r | |
164 | Package. Platform Information Contains power management and other model\r | |
165 | specific features enumeration. See http://biosbits.org.\r | |
3adf6316 MK |
166 | \r |
167 | @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r | |
168 | @param EAX Lower 32-bits of MSR value.\r | |
169 | Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r | |
170 | @param EDX Upper 32-bits of MSR value.\r | |
171 | Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r | |
172 | \r | |
173 | <b>Example usage</b>\r | |
174 | @code\r | |
175 | MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;\r | |
176 | \r | |
177 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r | |
178 | AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r | |
179 | @endcode\r | |
ad8a2f5e | 180 | @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
3adf6316 MK |
181 | **/\r |
182 | #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r | |
183 | \r | |
184 | /**\r | |
185 | MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r | |
186 | **/\r | |
187 | typedef union {\r | |
188 | ///\r | |
189 | /// Individual bit fields\r | |
190 | ///\r | |
191 | struct {\r | |
192 | UINT32 Reserved1:8;\r | |
193 | ///\r | |
194 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
195 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
196 | /// MHz.\r | |
197 | ///\r | |
198 | UINT32 MaximumNonTurboRatio:8;\r | |
199 | UINT32 Reserved2:12;\r | |
200 | ///\r | |
201 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
202 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
203 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
204 | /// Turbo mode is disabled.\r | |
205 | ///\r | |
206 | UINT32 RatioLimit:1;\r | |
207 | ///\r | |
208 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
209 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
210 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
211 | /// programmable.\r | |
212 | ///\r | |
213 | UINT32 TDPLimit:1;\r | |
214 | UINT32 Reserved3:2;\r | |
215 | UINT32 Reserved4:8;\r | |
216 | ///\r | |
217 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
218 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
219 | /// units of 100MHz.\r | |
220 | ///\r | |
221 | UINT32 MaximumEfficiencyRatio:8;\r | |
222 | UINT32 Reserved5:16;\r | |
223 | } Bits;\r | |
224 | ///\r | |
225 | /// All bit fields as a 64-bit value\r | |
226 | ///\r | |
227 | UINT64 Uint64;\r | |
228 | } MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r | |
229 | \r | |
230 | \r | |
231 | /**\r | |
232 | Module. C-State Configuration Control (R/W).\r | |
233 | \r | |
234 | @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
235 | @param EAX Lower 32-bits of MSR value.\r | |
236 | Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
237 | @param EDX Upper 32-bits of MSR value.\r | |
238 | Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
239 | \r | |
240 | <b>Example usage</b>\r | |
241 | @code\r | |
242 | MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
243 | \r | |
244 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r | |
245 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
246 | @endcode\r | |
ad8a2f5e | 247 | @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
3adf6316 MK |
248 | **/\r |
249 | #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
250 | \r | |
251 | /**\r | |
252 | MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r | |
253 | **/\r | |
254 | typedef union {\r | |
255 | ///\r | |
256 | /// Individual bit fields\r | |
257 | ///\r | |
258 | struct {\r | |
259 | ///\r | |
260 | /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code\r | |
261 | /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r | |
262 | /// Retention 011b: C6 Retention 111b: No limit.\r | |
263 | ///\r | |
264 | UINT32 Limit:3;\r | |
265 | UINT32 Reserved1:7;\r | |
266 | ///\r | |
267 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
268 | ///\r | |
269 | UINT32 IO_MWAIT:1;\r | |
270 | UINT32 Reserved2:4;\r | |
271 | ///\r | |
272 | /// [Bit 15] CFG Lock (R/WO).\r | |
273 | ///\r | |
274 | UINT32 CFGLock:1;\r | |
53002b7e ED |
275 | UINT32 Reserved5:10;\r |
276 | ///\r | |
277 | /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor\r | |
278 | /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r | |
279 | /// auto-demote information.\r | |
280 | ///\r | |
281 | UINT32 C1StateAutoDemotionEnable:1;\r | |
282 | UINT32 Reserved6:1;\r | |
283 | ///\r | |
284 | /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables\r | |
285 | /// Undemotion from Demoted C1.\r | |
286 | ///\r | |
287 | UINT32 C1StateAutoUndemotionEnable:1;\r | |
288 | ///\r | |
289 | /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables\r | |
290 | /// Package C state demotion.\r | |
291 | ///\r | |
292 | UINT32 PKGC_StateAutoDemotionEnable:1;\r | |
293 | UINT32 Reserved7:2;\r | |
3adf6316 MK |
294 | UINT32 Reserved4:32;\r |
295 | } Bits;\r | |
296 | ///\r | |
297 | /// All bit fields as a 32-bit value\r | |
298 | ///\r | |
299 | UINT32 Uint32;\r | |
300 | ///\r | |
301 | /// All bit fields as a 64-bit value\r | |
302 | ///\r | |
303 | UINT64 Uint64;\r | |
304 | } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
305 | \r | |
306 | \r | |
307 | /**\r | |
308 | Module. Power Management IO Redirection in C-state (R/W).\r | |
309 | \r | |
310 | @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)\r | |
311 | @param EAX Lower 32-bits of MSR value.\r | |
312 | Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
313 | @param EDX Upper 32-bits of MSR value.\r | |
314 | Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
315 | \r | |
316 | <b>Example usage</b>\r | |
317 | @code\r | |
318 | MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r | |
319 | \r | |
320 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r | |
321 | AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r | |
322 | @endcode\r | |
ad8a2f5e | 323 | @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r |
3adf6316 MK |
324 | **/\r |
325 | #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r | |
326 | \r | |
327 | /**\r | |
328 | MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r | |
329 | **/\r | |
330 | typedef union {\r | |
331 | ///\r | |
332 | /// Individual bit fields\r | |
333 | ///\r | |
334 | struct {\r | |
335 | ///\r | |
336 | /// [Bits 15:0] LVL_2 Base Address (R/W).\r | |
337 | ///\r | |
338 | UINT32 Lvl2Base:16;\r | |
339 | ///\r | |
53002b7e ED |
340 | /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which\r |
341 | /// IO-redirection will be executed (0-127). Should be programmed based on\r | |
342 | /// the number of LVLx registers existing in the chipset.\r | |
3adf6316 | 343 | ///\r |
53002b7e ED |
344 | UINT32 CStateRange:7;\r |
345 | UINT32 Reserved3:9;\r | |
3adf6316 MK |
346 | UINT32 Reserved2:32;\r |
347 | } Bits;\r | |
348 | ///\r | |
349 | /// All bit fields as a 32-bit value\r | |
350 | ///\r | |
351 | UINT32 Uint32;\r | |
352 | ///\r | |
353 | /// All bit fields as a 64-bit value\r | |
354 | ///\r | |
355 | UINT64 Uint64;\r | |
356 | } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r | |
357 | \r | |
358 | \r | |
359 | /**\r | |
360 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
361 | handler to handle unsuccessful read of this MSR.\r | |
362 | \r | |
363 | @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)\r | |
364 | @param EAX Lower 32-bits of MSR value.\r | |
365 | Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r | |
366 | @param EDX Upper 32-bits of MSR value.\r | |
367 | Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r | |
368 | \r | |
369 | <b>Example usage</b>\r | |
370 | @code\r | |
371 | MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;\r | |
372 | \r | |
373 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r | |
374 | AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r | |
375 | @endcode\r | |
ad8a2f5e | 376 | @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r |
3adf6316 MK |
377 | **/\r |
378 | #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r | |
379 | \r | |
380 | /**\r | |
381 | MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r | |
382 | **/\r | |
383 | typedef union {\r | |
384 | ///\r | |
385 | /// Individual bit fields\r | |
386 | ///\r | |
387 | struct {\r | |
388 | ///\r | |
389 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
390 | /// MSR, the configuration of AES instruction set availability is as\r | |
391 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
392 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
393 | /// is not available if read is unsuccessful. If the configuration is not\r | |
394 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
395 | /// unintentionally writes 11b.\r | |
396 | ///\r | |
397 | UINT32 AESConfiguration:2;\r | |
398 | UINT32 Reserved1:30;\r | |
399 | UINT32 Reserved2:32;\r | |
400 | } Bits;\r | |
401 | ///\r | |
402 | /// All bit fields as a 32-bit value\r | |
403 | ///\r | |
404 | UINT32 Uint32;\r | |
405 | ///\r | |
406 | /// All bit fields as a 64-bit value\r | |
407 | ///\r | |
408 | UINT64 Uint64;\r | |
409 | } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r | |
410 | \r | |
411 | \r | |
dfb20851 ED |
412 | /**\r |
413 | Thread. MISC_FEATURE_ENABLES.\r | |
414 | \r | |
415 | @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)\r | |
416 | @param EAX Lower 32-bits of MSR value.\r | |
417 | Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r | |
418 | @param EDX Upper 32-bits of MSR value.\r | |
419 | Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r | |
420 | \r | |
421 | <b>Example usage</b>\r | |
422 | @code\r | |
423 | MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;\r | |
424 | \r | |
425 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);\r | |
426 | AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r | |
427 | @endcode\r | |
428 | **/\r | |
429 | #define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r | |
430 | \r | |
431 | /**\r | |
432 | MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r | |
433 | **/\r | |
434 | typedef union {\r | |
435 | ///\r | |
436 | /// Individual bit fields\r | |
437 | ///\r | |
438 | struct {\r | |
439 | UINT32 Reserved1:1;\r | |
440 | ///\r | |
441 | /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r | |
442 | /// MWAIT instructions do not cause invalid-opcode exceptions when\r | |
443 | /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed\r | |
444 | /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state\r | |
445 | /// other than C0 or C1, the instruction operates as if EAX indicated the\r | |
446 | /// C-state C1.\r | |
447 | ///\r | |
448 | UINT32 UserModeMonitorAndMwait:1;\r | |
449 | UINT32 Reserved2:30;\r | |
450 | UINT32 Reserved3:32;\r | |
451 | } Bits;\r | |
452 | ///\r | |
453 | /// All bit fields as a 32-bit value\r | |
454 | ///\r | |
455 | UINT32 Uint32;\r | |
456 | ///\r | |
457 | /// All bit fields as a 64-bit value\r | |
458 | ///\r | |
459 | UINT64 Uint64;\r | |
460 | } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r | |
461 | \r | |
0f16be6d HW |
462 | /**\r |
463 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
464 | Enhancement. Accessible only while in SMM.\r | |
465 | \r | |
466 | @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r | |
467 | @param EAX Lower 32-bits of MSR value.\r | |
468 | Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r | |
469 | @param EDX Upper 32-bits of MSR value.\r | |
470 | Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r | |
471 | \r | |
472 | <b>Example usage</b>\r | |
473 | @code\r | |
474 | MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r | |
475 | \r | |
476 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r | |
477 | AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r | |
478 | @endcode\r | |
479 | @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r | |
480 | **/\r | |
481 | #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r | |
482 | \r | |
483 | /**\r | |
484 | MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r | |
485 | **/\r | |
486 | typedef union {\r | |
487 | ///\r | |
488 | /// Individual bit fields\r | |
489 | ///\r | |
490 | struct {\r | |
53002b7e ED |
491 | ///\r |
492 | /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is\r | |
493 | /// set, that bank supports Enhanced MCA (Default all 0; does not support\r | |
494 | /// EMCA).\r | |
495 | ///\r | |
496 | UINT32 BankSupport:32;\r | |
497 | UINT32 Reserved4:24;\r | |
498 | ///\r | |
499 | /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.\r | |
500 | ///\r | |
501 | UINT32 TargetedSMI:1;\r | |
502 | ///\r | |
503 | /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature\r | |
504 | /// is supported.\r | |
505 | ///\r | |
506 | UINT32 SMM_CPU_SVRSTR:1;\r | |
0f16be6d HW |
507 | ///\r |
508 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
509 | /// SMM code access restriction is supported and a host-space interface\r | |
510 | /// available to SMM handler.\r | |
511 | ///\r | |
512 | UINT32 SMM_Code_Access_Chk:1;\r | |
513 | ///\r | |
514 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
515 | /// SMM long flow indicator is supported and a host-space interface\r | |
516 | /// available to SMM handler.\r | |
517 | ///\r | |
518 | UINT32 Long_Flow_Indication:1;\r | |
519 | UINT32 Reserved3:4;\r | |
520 | } Bits;\r | |
521 | ///\r | |
522 | /// All bit fields as a 64-bit value\r | |
523 | ///\r | |
524 | UINT64 Uint64;\r | |
525 | } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r | |
526 | \r | |
527 | \r | |
3adf6316 MK |
528 | /**\r |
529 | Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
530 | functions to be enabled and disabled.\r | |
531 | \r | |
532 | @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)\r | |
533 | @param EAX Lower 32-bits of MSR value.\r | |
534 | Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r | |
535 | @param EDX Upper 32-bits of MSR value.\r | |
536 | Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r | |
537 | \r | |
538 | <b>Example usage</b>\r | |
539 | @code\r | |
540 | MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;\r | |
541 | \r | |
542 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r | |
543 | AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r | |
544 | @endcode\r | |
ad8a2f5e | 545 | @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
3adf6316 MK |
546 | **/\r |
547 | #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r | |
548 | \r | |
549 | /**\r | |
550 | MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r | |
551 | **/\r | |
552 | typedef union {\r | |
553 | ///\r | |
554 | /// Individual bit fields\r | |
555 | ///\r | |
556 | struct {\r | |
557 | ///\r | |
558 | /// [Bit 0] Fast-Strings Enable.\r | |
559 | ///\r | |
560 | UINT32 FastStrings:1;\r | |
561 | UINT32 Reserved1:2;\r | |
562 | ///\r | |
0f16be6d HW |
563 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r |
564 | /// is 1.\r | |
3adf6316 MK |
565 | ///\r |
566 | UINT32 AutomaticThermalControlCircuit:1;\r | |
567 | UINT32 Reserved2:3;\r | |
568 | ///\r | |
569 | /// [Bit 7] Performance Monitoring Available (R).\r | |
570 | ///\r | |
571 | UINT32 PerformanceMonitoring:1;\r | |
572 | UINT32 Reserved3:3;\r | |
573 | ///\r | |
574 | /// [Bit 11] Branch Trace Storage Unavailable (RO).\r | |
575 | ///\r | |
576 | UINT32 BTS:1;\r | |
577 | ///\r | |
0f16be6d | 578 | /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r |
3adf6316 MK |
579 | ///\r |
580 | UINT32 PEBS:1;\r | |
581 | UINT32 Reserved4:3;\r | |
582 | ///\r | |
583 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r | |
584 | ///\r | |
585 | UINT32 EIST:1;\r | |
586 | UINT32 Reserved5:1;\r | |
587 | ///\r | |
588 | /// [Bit 18] ENABLE MONITOR FSM (R/W).\r | |
589 | ///\r | |
590 | UINT32 MONITOR:1;\r | |
591 | UINT32 Reserved6:3;\r | |
592 | ///\r | |
593 | /// [Bit 22] Limit CPUID Maxval (R/W).\r | |
594 | ///\r | |
595 | UINT32 LimitCpuidMaxval:1;\r | |
596 | ///\r | |
597 | /// [Bit 23] xTPR Message Disable (R/W).\r | |
598 | ///\r | |
599 | UINT32 xTPR_Message_Disable:1;\r | |
600 | UINT32 Reserved7:8;\r | |
601 | UINT32 Reserved8:2;\r | |
602 | ///\r | |
603 | /// [Bit 34] XD Bit Disable (R/W).\r | |
604 | ///\r | |
605 | UINT32 XD:1;\r | |
606 | UINT32 Reserved9:3;\r | |
607 | ///\r | |
608 | /// [Bit 38] Turbo Mode Disable (R/W).\r | |
609 | ///\r | |
610 | UINT32 TurboModeDisable:1;\r | |
611 | UINT32 Reserved10:25;\r | |
612 | } Bits;\r | |
613 | ///\r | |
614 | /// All bit fields as a 64-bit value\r | |
615 | ///\r | |
616 | UINT64 Uint64;\r | |
617 | } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r | |
618 | \r | |
619 | \r | |
620 | /**\r | |
621 | Package.\r | |
622 | \r | |
623 | @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)\r | |
624 | @param EAX Lower 32-bits of MSR value.\r | |
625 | Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r | |
626 | @param EDX Upper 32-bits of MSR value.\r | |
627 | Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r | |
628 | \r | |
629 | <b>Example usage</b>\r | |
630 | @code\r | |
631 | MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;\r | |
632 | \r | |
633 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r | |
634 | AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r | |
635 | @endcode\r | |
ad8a2f5e | 636 | @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
3adf6316 MK |
637 | **/\r |
638 | #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r | |
639 | \r | |
640 | /**\r | |
641 | MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r | |
642 | **/\r | |
643 | typedef union {\r | |
644 | ///\r | |
645 | /// Individual bit fields\r | |
646 | ///\r | |
647 | struct {\r | |
648 | UINT32 Reserved1:16;\r | |
649 | ///\r | |
650 | /// [Bits 23:16] Temperature Target (R).\r | |
651 | ///\r | |
652 | UINT32 TemperatureTarget:8;\r | |
653 | ///\r | |
654 | /// [Bits 29:24] Target Offset (R/W).\r | |
655 | ///\r | |
656 | UINT32 TargetOffset:6;\r | |
657 | UINT32 Reserved2:2;\r | |
658 | UINT32 Reserved3:32;\r | |
659 | } Bits;\r | |
660 | ///\r | |
661 | /// All bit fields as a 32-bit value\r | |
662 | ///\r | |
663 | UINT32 Uint32;\r | |
664 | ///\r | |
665 | /// All bit fields as a 64-bit value\r | |
666 | ///\r | |
667 | UINT64 Uint64;\r | |
668 | } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r | |
669 | \r | |
670 | \r | |
0f16be6d HW |
671 | /**\r |
672 | Miscellaneous Feature Control (R/W).\r | |
673 | \r | |
674 | @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r | |
675 | @param EAX Lower 32-bits of MSR value.\r | |
676 | Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r | |
677 | @param EDX Upper 32-bits of MSR value.\r | |
678 | Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r | |
679 | \r | |
680 | <b>Example usage</b>\r | |
681 | @code\r | |
682 | MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
683 | \r | |
684 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r | |
685 | AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
686 | @endcode\r | |
687 | @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r | |
688 | **/\r | |
689 | #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r | |
690 | \r | |
691 | /**\r | |
692 | MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r | |
693 | **/\r | |
694 | typedef union {\r | |
695 | ///\r | |
696 | /// Individual bit fields\r | |
697 | ///\r | |
698 | struct {\r | |
699 | ///\r | |
700 | /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
701 | /// L1 data cache prefetcher.\r | |
702 | ///\r | |
703 | UINT32 DCUHardwarePrefetcherDisable:1;\r | |
704 | ///\r | |
705 | /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
706 | /// L2 hardware prefetcher.\r | |
707 | ///\r | |
708 | UINT32 L2HardwarePrefetcherDisable:1;\r | |
709 | UINT32 Reserved1:30;\r | |
710 | UINT32 Reserved2:32;\r | |
711 | } Bits;\r | |
712 | ///\r | |
713 | /// All bit fields as a 32-bit value\r | |
714 | ///\r | |
715 | UINT32 Uint32;\r | |
716 | ///\r | |
717 | /// All bit fields as a 64-bit value\r | |
718 | ///\r | |
719 | UINT64 Uint64;\r | |
720 | } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r | |
721 | \r | |
722 | \r | |
3adf6316 MK |
723 | /**\r |
724 | Shared. Offcore Response Event Select Register (R/W).\r | |
725 | \r | |
726 | @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)\r | |
727 | @param EAX Lower 32-bits of MSR value.\r | |
728 | @param EDX Upper 32-bits of MSR value.\r | |
729 | \r | |
730 | <b>Example usage</b>\r | |
731 | @code\r | |
732 | UINT64 Msr;\r | |
733 | \r | |
734 | Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r | |
735 | AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r | |
736 | @endcode\r | |
ad8a2f5e | 737 | @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r |
3adf6316 MK |
738 | **/\r |
739 | #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r | |
740 | \r | |
741 | \r | |
742 | /**\r | |
743 | Shared. Offcore Response Event Select Register (R/W).\r | |
744 | \r | |
745 | @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)\r | |
746 | @param EAX Lower 32-bits of MSR value.\r | |
747 | @param EDX Upper 32-bits of MSR value.\r | |
748 | \r | |
749 | <b>Example usage</b>\r | |
750 | @code\r | |
751 | UINT64 Msr;\r | |
752 | \r | |
753 | Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r | |
754 | AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r | |
755 | @endcode\r | |
ad8a2f5e | 756 | @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r |
3adf6316 MK |
757 | **/\r |
758 | #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r | |
759 | \r | |
760 | \r | |
761 | /**\r | |
762 | Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r | |
763 | \r | |
764 | @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)\r | |
765 | @param EAX Lower 32-bits of MSR value.\r | |
766 | Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r | |
767 | @param EDX Upper 32-bits of MSR value.\r | |
768 | Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r | |
769 | \r | |
770 | <b>Example usage</b>\r | |
771 | @code\r | |
772 | MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
773 | \r | |
774 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r | |
775 | AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r | |
776 | @endcode\r | |
ad8a2f5e | 777 | @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
3adf6316 MK |
778 | **/\r |
779 | #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r | |
780 | \r | |
781 | /**\r | |
782 | MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r | |
783 | **/\r | |
784 | typedef union {\r | |
785 | ///\r | |
786 | /// Individual bit fields\r | |
787 | ///\r | |
788 | struct {\r | |
789 | UINT32 Reserved:1;\r | |
790 | ///\r | |
791 | /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r | |
792 | /// processor cores which operates under the maximum ratio limit for group\r | |
793 | /// 0.\r | |
794 | ///\r | |
795 | UINT32 MaxCoresGroup0:7;\r | |
796 | ///\r | |
797 | /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r | |
798 | /// ratio limit when the number of active cores are not more than the\r | |
799 | /// group 0 maximum core count.\r | |
800 | ///\r | |
801 | UINT32 MaxRatioLimitGroup0:8;\r | |
802 | ///\r | |
803 | /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r | |
804 | /// Group 1, which includes the specified number of additional cores plus\r | |
805 | /// the cores in group 0, operates under the group 1 turbo max ratio limit\r | |
806 | /// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r | |
807 | ///\r | |
808 | UINT32 MaxIncrementalCoresGroup1:5;\r | |
809 | ///\r | |
810 | /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r | |
811 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
812 | /// to Group 0.\r | |
813 | ///\r | |
814 | UINT32 DeltaRatioGroup1:3;\r | |
815 | ///\r | |
816 | /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r | |
817 | /// Group 2, which includes the specified number of additional cores plus\r | |
818 | /// all the cores in group 1, operates under the group 2 turbo max ratio\r | |
819 | /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r | |
820 | ///\r | |
821 | UINT32 MaxIncrementalCoresGroup2:5;\r | |
822 | ///\r | |
823 | /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r | |
824 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
825 | /// for Group 1.\r | |
826 | ///\r | |
827 | UINT32 DeltaRatioGroup2:3;\r | |
828 | ///\r | |
829 | /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r | |
830 | /// Group 3, which includes the specified number of additional cores plus\r | |
831 | /// all the cores in group 2, operates under the group 3 turbo max ratio\r | |
832 | /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r | |
833 | ///\r | |
834 | UINT32 MaxIncrementalCoresGroup3:5;\r | |
835 | ///\r | |
836 | /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r | |
837 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
838 | /// for Group 2.\r | |
839 | ///\r | |
840 | UINT32 DeltaRatioGroup3:3;\r | |
841 | ///\r | |
842 | /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r | |
843 | /// Group 4, which includes the specified number of additional cores plus\r | |
844 | /// all the cores in group 3, operates under the group 4 turbo max ratio\r | |
845 | /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r | |
846 | ///\r | |
847 | UINT32 MaxIncrementalCoresGroup4:5;\r | |
848 | ///\r | |
849 | /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r | |
850 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
851 | /// for Group 3.\r | |
852 | ///\r | |
853 | UINT32 DeltaRatioGroup4:3;\r | |
854 | ///\r | |
855 | /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r | |
856 | /// Group 5, which includes the specified number of additional cores plus\r | |
857 | /// all the cores in group 4, operates under the group 5 turbo max ratio\r | |
858 | /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r | |
859 | ///\r | |
860 | UINT32 MaxIncrementalCoresGroup5:5;\r | |
861 | ///\r | |
862 | /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r | |
863 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
864 | /// for Group 4.\r | |
865 | ///\r | |
866 | UINT32 DeltaRatioGroup5:3;\r | |
867 | ///\r | |
868 | /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r | |
869 | /// Group 6, which includes the specified number of additional cores plus\r | |
870 | /// all the cores in group 5, operates under the group 6 turbo max ratio\r | |
871 | /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r | |
872 | ///\r | |
873 | UINT32 MaxIncrementalCoresGroup6:5;\r | |
874 | ///\r | |
875 | /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r | |
876 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
877 | /// for Group 5.\r | |
878 | ///\r | |
879 | UINT32 DeltaRatioGroup6:3;\r | |
880 | } Bits;\r | |
881 | ///\r | |
882 | /// All bit fields as a 64-bit value\r | |
883 | ///\r | |
884 | UINT64 Uint64;\r | |
885 | } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r | |
886 | \r | |
887 | \r | |
888 | /**\r | |
889 | Thread. Last Branch Record Filtering Select Register (R/W).\r | |
890 | \r | |
891 | @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)\r | |
892 | @param EAX Lower 32-bits of MSR value.\r | |
893 | @param EDX Upper 32-bits of MSR value.\r | |
894 | \r | |
895 | <b>Example usage</b>\r | |
896 | @code\r | |
897 | UINT64 Msr;\r | |
898 | \r | |
899 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r | |
900 | AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r | |
901 | @endcode\r | |
ad8a2f5e | 902 | @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r |
3adf6316 MK |
903 | **/\r |
904 | #define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r | |
905 | \r | |
906 | \r | |
dfb20851 ED |
907 | /**\r |
908 | MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r | |
909 | **/\r | |
910 | typedef union {\r | |
911 | ///\r | |
912 | /// Individual bit fields\r | |
913 | ///\r | |
914 | struct {\r | |
915 | ///\r | |
916 | /// [Bit 0] CPL_EQ_0.\r | |
917 | ///\r | |
918 | UINT32 CPL_EQ_0:1;\r | |
919 | ///\r | |
920 | /// [Bit 1] CPL_NEQ_0.\r | |
921 | ///\r | |
922 | UINT32 CPL_NEQ_0:1;\r | |
923 | ///\r | |
924 | /// [Bit 2] JCC.\r | |
925 | ///\r | |
926 | UINT32 JCC:1;\r | |
927 | ///\r | |
928 | /// [Bit 3] NEAR_REL_CALL.\r | |
929 | ///\r | |
930 | UINT32 NEAR_REL_CALL:1;\r | |
931 | ///\r | |
932 | /// [Bit 4] NEAR_IND_CALL.\r | |
933 | ///\r | |
934 | UINT32 NEAR_IND_CALL:1;\r | |
935 | ///\r | |
936 | /// [Bit 5] NEAR_RET.\r | |
937 | ///\r | |
938 | UINT32 NEAR_RET:1;\r | |
939 | ///\r | |
940 | /// [Bit 6] NEAR_IND_JMP.\r | |
941 | ///\r | |
942 | UINT32 NEAR_IND_JMP:1;\r | |
943 | ///\r | |
944 | /// [Bit 7] NEAR_REL_JMP.\r | |
945 | ///\r | |
946 | UINT32 NEAR_REL_JMP:1;\r | |
947 | ///\r | |
948 | /// [Bit 8] FAR_BRANCH.\r | |
949 | ///\r | |
950 | UINT32 FAR_BRANCH:1;\r | |
951 | UINT32 Reserved1:23;\r | |
952 | UINT32 Reserved2:32;\r | |
953 | } Bits;\r | |
954 | ///\r | |
955 | /// All bit fields as a 32-bit value\r | |
956 | ///\r | |
957 | UINT32 Uint32;\r | |
958 | ///\r | |
959 | /// All bit fields as a 64-bit value\r | |
960 | ///\r | |
961 | UINT64 Uint64;\r | |
962 | } MSR_XEON_PHI_LBR_SELECT_REGISTER;\r | |
963 | \r | |
3adf6316 MK |
964 | /**\r |
965 | Thread. Last Branch Record Stack TOS (R/W).\r | |
966 | \r | |
967 | @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)\r | |
968 | @param EAX Lower 32-bits of MSR value.\r | |
969 | @param EDX Upper 32-bits of MSR value.\r | |
970 | \r | |
971 | <b>Example usage</b>\r | |
972 | @code\r | |
973 | UINT64 Msr;\r | |
974 | \r | |
975 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r | |
976 | AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r | |
977 | @endcode\r | |
ad8a2f5e | 978 | @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
3adf6316 MK |
979 | **/\r |
980 | #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r | |
981 | \r | |
982 | \r | |
983 | /**\r | |
984 | Thread. Last Exception Record From Linear IP (R).\r | |
985 | \r | |
986 | @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)\r | |
987 | @param EAX Lower 32-bits of MSR value.\r | |
988 | @param EDX Upper 32-bits of MSR value.\r | |
989 | \r | |
990 | <b>Example usage</b>\r | |
991 | @code\r | |
992 | UINT64 Msr;\r | |
993 | \r | |
994 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r | |
995 | @endcode\r | |
ad8a2f5e | 996 | @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
3adf6316 MK |
997 | **/\r |
998 | #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r | |
999 | \r | |
1000 | \r | |
1001 | /**\r | |
1002 | Thread. Last Exception Record To Linear IP (R).\r | |
1003 | \r | |
1004 | @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)\r | |
1005 | @param EAX Lower 32-bits of MSR value.\r | |
1006 | @param EDX Upper 32-bits of MSR value.\r | |
1007 | \r | |
1008 | <b>Example usage</b>\r | |
1009 | @code\r | |
1010 | UINT64 Msr;\r | |
1011 | \r | |
1012 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r | |
1013 | @endcode\r | |
ad8a2f5e | 1014 | @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
3adf6316 MK |
1015 | **/\r |
1016 | #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r | |
1017 | \r | |
1018 | \r | |
3adf6316 | 1019 | /**\r |
ba1a2d11 | 1020 | Thread. See Table 2-2.\r |
3adf6316 MK |
1021 | \r |
1022 | @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)\r | |
1023 | @param EAX Lower 32-bits of MSR value.\r | |
1024 | @param EDX Upper 32-bits of MSR value.\r | |
1025 | \r | |
1026 | <b>Example usage</b>\r | |
1027 | @code\r | |
1028 | UINT64 Msr;\r | |
1029 | \r | |
1030 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r | |
1031 | AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r | |
1032 | @endcode\r | |
ad8a2f5e | 1033 | @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
3adf6316 MK |
1034 | **/\r |
1035 | #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r | |
1036 | \r | |
1037 | \r | |
1038 | /**\r | |
1039 | Package. Note: C-state values are processor specific C-state code names,\r | |
1040 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3\r | |
1041 | Residency Counter. (R/O).\r | |
1042 | \r | |
1043 | @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)\r | |
1044 | @param EAX Lower 32-bits of MSR value.\r | |
1045 | @param EDX Upper 32-bits of MSR value.\r | |
1046 | \r | |
1047 | <b>Example usage</b>\r | |
1048 | @code\r | |
1049 | UINT64 Msr;\r | |
1050 | \r | |
1051 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r | |
1052 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r | |
1053 | @endcode\r | |
ad8a2f5e | 1054 | @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r |
3adf6316 MK |
1055 | **/\r |
1056 | #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r | |
1057 | \r | |
1058 | \r | |
1059 | /**\r | |
1060 | Package. Package C6 Residency Counter. (R/O).\r | |
1061 | \r | |
1062 | @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)\r | |
1063 | @param EAX Lower 32-bits of MSR value.\r | |
1064 | @param EDX Upper 32-bits of MSR value.\r | |
1065 | \r | |
1066 | <b>Example usage</b>\r | |
1067 | @code\r | |
1068 | UINT64 Msr;\r | |
1069 | \r | |
1070 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r | |
1071 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r | |
1072 | @endcode\r | |
ad8a2f5e | 1073 | @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
3adf6316 MK |
1074 | **/\r |
1075 | #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r | |
1076 | \r | |
1077 | \r | |
1078 | /**\r | |
1079 | Package. Package C7 Residency Counter. (R/O).\r | |
1080 | \r | |
1081 | @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)\r | |
1082 | @param EAX Lower 32-bits of MSR value.\r | |
1083 | @param EDX Upper 32-bits of MSR value.\r | |
1084 | \r | |
1085 | <b>Example usage</b>\r | |
1086 | @code\r | |
1087 | UINT64 Msr;\r | |
1088 | \r | |
1089 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r | |
1090 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r | |
1091 | @endcode\r | |
ad8a2f5e | 1092 | @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r |
3adf6316 MK |
1093 | **/\r |
1094 | #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r | |
1095 | \r | |
1096 | \r | |
1097 | /**\r | |
1098 | Module. Note: C-state values are processor specific C-state code names,\r | |
1099 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0\r | |
1100 | Residency Counter. (R/O).\r | |
1101 | \r | |
1102 | @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)\r | |
1103 | @param EAX Lower 32-bits of MSR value.\r | |
1104 | @param EDX Upper 32-bits of MSR value.\r | |
1105 | \r | |
1106 | <b>Example usage</b>\r | |
1107 | @code\r | |
1108 | UINT64 Msr;\r | |
1109 | \r | |
1110 | Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r | |
1111 | AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r | |
1112 | @endcode\r | |
ad8a2f5e | 1113 | @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r |
3adf6316 MK |
1114 | **/\r |
1115 | #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r | |
1116 | \r | |
1117 | \r | |
1118 | /**\r | |
1119 | Module. Module C6 Residency Counter. (R/O).\r | |
1120 | \r | |
1121 | @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)\r | |
1122 | @param EAX Lower 32-bits of MSR value.\r | |
1123 | @param EDX Upper 32-bits of MSR value.\r | |
1124 | \r | |
1125 | <b>Example usage</b>\r | |
1126 | @code\r | |
1127 | UINT64 Msr;\r | |
1128 | \r | |
1129 | Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r | |
1130 | AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r | |
1131 | @endcode\r | |
ad8a2f5e | 1132 | @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r |
3adf6316 MK |
1133 | **/\r |
1134 | #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r | |
1135 | \r | |
1136 | \r | |
1137 | /**\r | |
1138 | Core. Note: C-state values are processor specific C-state code names,\r | |
1139 | unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6\r | |
1140 | Residency Counter. (R/O).\r | |
1141 | \r | |
1142 | @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)\r | |
1143 | @param EAX Lower 32-bits of MSR value.\r | |
1144 | @param EDX Upper 32-bits of MSR value.\r | |
1145 | \r | |
1146 | <b>Example usage</b>\r | |
1147 | @code\r | |
1148 | UINT64 Msr;\r | |
1149 | \r | |
1150 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r | |
1151 | AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r | |
1152 | @endcode\r | |
ad8a2f5e | 1153 | @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r |
3adf6316 MK |
1154 | **/\r |
1155 | #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r | |
1156 | \r | |
1157 | \r | |
3adf6316 | 1158 | /**\r |
ba1a2d11 | 1159 | Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r |
3adf6316 MK |
1160 | \r |
1161 | @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r | |
1162 | @param EAX Lower 32-bits of MSR value.\r | |
1163 | @param EDX Upper 32-bits of MSR value.\r | |
1164 | \r | |
1165 | <b>Example usage</b>\r | |
1166 | @code\r | |
1167 | UINT64 Msr;\r | |
1168 | \r | |
1169 | Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r | |
1170 | @endcode\r | |
ad8a2f5e | 1171 | @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r |
3adf6316 MK |
1172 | **/\r |
1173 | #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r | |
1174 | \r | |
1175 | \r | |
1176 | /**\r | |
ba1a2d11 ED |
1177 | Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r |
1178 | 2-2.\r | |
3adf6316 MK |
1179 | \r |
1180 | @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)\r | |
1181 | @param EAX Lower 32-bits of MSR value.\r | |
1182 | @param EDX Upper 32-bits of MSR value.\r | |
1183 | \r | |
1184 | <b>Example usage</b>\r | |
1185 | @code\r | |
1186 | UINT64 Msr;\r | |
1187 | \r | |
1188 | Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r | |
1189 | @endcode\r | |
ad8a2f5e | 1190 | @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r |
3adf6316 MK |
1191 | **/\r |
1192 | #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r | |
1193 | \r | |
1194 | \r | |
1195 | /**\r | |
1196 | Package. Unit Multipliers used in RAPL Interfaces (R/O).\r | |
1197 | \r | |
1198 | @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)\r | |
1199 | @param EAX Lower 32-bits of MSR value.\r | |
1200 | Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r | |
1201 | @param EDX Upper 32-bits of MSR value.\r | |
1202 | Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r | |
1203 | \r | |
1204 | <b>Example usage</b>\r | |
1205 | @code\r | |
1206 | MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;\r | |
1207 | \r | |
1208 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r | |
1209 | @endcode\r | |
ad8a2f5e | 1210 | @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
3adf6316 MK |
1211 | **/\r |
1212 | #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r | |
1213 | \r | |
1214 | /**\r | |
1215 | MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r | |
1216 | **/\r | |
1217 | typedef union {\r | |
1218 | ///\r | |
1219 | /// Individual bit fields\r | |
1220 | ///\r | |
1221 | struct {\r | |
1222 | ///\r | |
1223 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
1224 | ///\r | |
1225 | UINT32 PowerUnits:4;\r | |
1226 | UINT32 Reserved1:4;\r | |
1227 | ///\r | |
1228 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
1229 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
1230 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
1231 | /// micro-joules).\r | |
1232 | ///\r | |
1233 | UINT32 EnergyStatusUnits:5;\r | |
1234 | UINT32 Reserved2:3;\r | |
1235 | ///\r | |
1236 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
1237 | /// Interfaces.".\r | |
1238 | ///\r | |
1239 | UINT32 TimeUnits:4;\r | |
1240 | UINT32 Reserved3:12;\r | |
1241 | UINT32 Reserved4:32;\r | |
1242 | } Bits;\r | |
1243 | ///\r | |
1244 | /// All bit fields as a 32-bit value\r | |
1245 | ///\r | |
1246 | UINT32 Uint32;\r | |
1247 | ///\r | |
1248 | /// All bit fields as a 64-bit value\r | |
1249 | ///\r | |
1250 | UINT64 Uint64;\r | |
1251 | } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r | |
1252 | \r | |
1253 | \r | |
1254 | /**\r | |
1255 | Package. Note: C-state values are processor specific C-state code names,\r | |
1256 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r | |
1257 | Residency Counter. (R/O).\r | |
1258 | \r | |
1259 | @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)\r | |
1260 | @param EAX Lower 32-bits of MSR value.\r | |
1261 | @param EDX Upper 32-bits of MSR value.\r | |
1262 | \r | |
1263 | <b>Example usage</b>\r | |
1264 | @code\r | |
1265 | UINT64 Msr;\r | |
1266 | \r | |
1267 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r | |
1268 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r | |
1269 | @endcode\r | |
ad8a2f5e | 1270 | @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r |
3adf6316 MK |
1271 | **/\r |
1272 | #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r | |
1273 | \r | |
1274 | \r | |
1275 | /**\r | |
1276 | Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r | |
1277 | RAPL Domain.".\r | |
1278 | \r | |
1279 | @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)\r | |
1280 | @param EAX Lower 32-bits of MSR value.\r | |
1281 | @param EDX Upper 32-bits of MSR value.\r | |
1282 | \r | |
1283 | <b>Example usage</b>\r | |
1284 | @code\r | |
1285 | UINT64 Msr;\r | |
1286 | \r | |
1287 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r | |
1288 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r | |
1289 | @endcode\r | |
ad8a2f5e | 1290 | @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r |
3adf6316 MK |
1291 | **/\r |
1292 | #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r | |
1293 | \r | |
1294 | \r | |
1295 | /**\r | |
1296 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
1297 | \r | |
1298 | @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)\r | |
1299 | @param EAX Lower 32-bits of MSR value.\r | |
1300 | @param EDX Upper 32-bits of MSR value.\r | |
1301 | \r | |
1302 | <b>Example usage</b>\r | |
1303 | @code\r | |
1304 | UINT64 Msr;\r | |
1305 | \r | |
1306 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r | |
1307 | @endcode\r | |
ad8a2f5e | 1308 | @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r |
3adf6316 MK |
1309 | **/\r |
1310 | #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r | |
1311 | \r | |
1312 | \r | |
1313 | /**\r | |
1314 | Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
1315 | \r | |
1316 | @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)\r | |
1317 | @param EAX Lower 32-bits of MSR value.\r | |
1318 | @param EDX Upper 32-bits of MSR value.\r | |
1319 | \r | |
1320 | <b>Example usage</b>\r | |
1321 | @code\r | |
1322 | UINT64 Msr;\r | |
1323 | \r | |
1324 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r | |
1325 | @endcode\r | |
ad8a2f5e | 1326 | @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
3adf6316 MK |
1327 | **/\r |
1328 | #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r | |
1329 | \r | |
1330 | \r | |
1331 | /**\r | |
1332 | Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r | |
1333 | Domain.".\r | |
1334 | \r | |
1335 | @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)\r | |
1336 | @param EAX Lower 32-bits of MSR value.\r | |
1337 | @param EDX Upper 32-bits of MSR value.\r | |
1338 | \r | |
1339 | <b>Example usage</b>\r | |
1340 | @code\r | |
1341 | UINT64 Msr;\r | |
1342 | \r | |
1343 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r | |
1344 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r | |
1345 | @endcode\r | |
ad8a2f5e | 1346 | @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r |
3adf6316 MK |
1347 | **/\r |
1348 | #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r | |
1349 | \r | |
1350 | \r | |
1351 | /**\r | |
1352 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
1353 | Domain.".\r | |
1354 | \r | |
1355 | @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)\r | |
1356 | @param EAX Lower 32-bits of MSR value.\r | |
1357 | @param EDX Upper 32-bits of MSR value.\r | |
1358 | \r | |
1359 | <b>Example usage</b>\r | |
1360 | @code\r | |
1361 | UINT64 Msr;\r | |
1362 | \r | |
1363 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r | |
1364 | AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r | |
1365 | @endcode\r | |
ad8a2f5e | 1366 | @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
3adf6316 MK |
1367 | **/\r |
1368 | #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r | |
1369 | \r | |
1370 | \r | |
1371 | /**\r | |
1372 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
1373 | \r | |
1374 | @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)\r | |
1375 | @param EAX Lower 32-bits of MSR value.\r | |
1376 | @param EDX Upper 32-bits of MSR value.\r | |
1377 | \r | |
1378 | <b>Example usage</b>\r | |
1379 | @code\r | |
1380 | UINT64 Msr;\r | |
1381 | \r | |
1382 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r | |
1383 | @endcode\r | |
ad8a2f5e | 1384 | @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
3adf6316 MK |
1385 | **/\r |
1386 | #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r | |
1387 | \r | |
1388 | \r | |
1389 | /**\r | |
1390 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
1391 | RAPL Domain.".\r | |
1392 | \r | |
1393 | @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)\r | |
1394 | @param EAX Lower 32-bits of MSR value.\r | |
1395 | @param EDX Upper 32-bits of MSR value.\r | |
1396 | \r | |
1397 | <b>Example usage</b>\r | |
1398 | @code\r | |
1399 | UINT64 Msr;\r | |
1400 | \r | |
1401 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r | |
1402 | @endcode\r | |
ad8a2f5e | 1403 | @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
3adf6316 MK |
1404 | **/\r |
1405 | #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r | |
1406 | \r | |
1407 | \r | |
1408 | /**\r | |
1409 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
1410 | \r | |
1411 | @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)\r | |
1412 | @param EAX Lower 32-bits of MSR value.\r | |
1413 | @param EDX Upper 32-bits of MSR value.\r | |
1414 | \r | |
1415 | <b>Example usage</b>\r | |
1416 | @code\r | |
1417 | UINT64 Msr;\r | |
1418 | \r | |
1419 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r | |
1420 | AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r | |
1421 | @endcode\r | |
ad8a2f5e | 1422 | @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
3adf6316 MK |
1423 | **/\r |
1424 | #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r | |
1425 | \r | |
1426 | \r | |
1427 | /**\r | |
dfb20851 ED |
1428 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r |
1429 | fields represent the widest possible range of uncore frequencies. Writing to\r | |
1430 | these fields allows software to control the minimum and the maximum\r | |
1431 | frequency that hardware will select.\r | |
1432 | \r | |
1433 | @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)\r | |
1434 | @param EAX Lower 32-bits of MSR value.\r | |
1435 | Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
1436 | @param EDX Upper 32-bits of MSR value.\r | |
1437 | Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
1438 | \r | |
1439 | <b>Example usage</b>\r | |
1440 | @code\r | |
1441 | MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r | |
1442 | \r | |
1443 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);\r | |
1444 | AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r | |
1445 | @endcode\r | |
1446 | **/\r | |
1447 | #define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r | |
1448 | \r | |
1449 | /**\r | |
1450 | MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r | |
1451 | **/\r | |
1452 | typedef union {\r | |
1453 | ///\r | |
1454 | /// Individual bit fields\r | |
1455 | ///\r | |
1456 | struct {\r | |
1457 | ///\r | |
1458 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r | |
1459 | /// LLC/Ring.\r | |
1460 | ///\r | |
1461 | UINT32 MAX_RATIO:7;\r | |
1462 | UINT32 Reserved1:1;\r | |
1463 | ///\r | |
1464 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r | |
1465 | /// possible ratio of the LLC/Ring.\r | |
1466 | ///\r | |
1467 | UINT32 MIN_RATIO:7;\r | |
1468 | UINT32 Reserved2:17;\r | |
1469 | UINT32 Reserved3:32;\r | |
1470 | } Bits;\r | |
1471 | ///\r | |
1472 | /// All bit fields as a 32-bit value\r | |
1473 | ///\r | |
1474 | UINT32 Uint32;\r | |
1475 | ///\r | |
1476 | /// All bit fields as a 64-bit value\r | |
1477 | ///\r | |
1478 | UINT64 Uint64;\r | |
1479 | } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r | |
1480 | \r | |
1481 | \r | |
1482 | /**\r | |
1483 | Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r | |
3adf6316 MK |
1484 | RAPL Domains.".\r |
1485 | \r | |
1486 | @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r | |
1487 | @param EAX Lower 32-bits of MSR value.\r | |
1488 | @param EDX Upper 32-bits of MSR value.\r | |
1489 | \r | |
1490 | <b>Example usage</b>\r | |
1491 | @code\r | |
1492 | UINT64 Msr;\r | |
1493 | \r | |
1494 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r | |
1495 | AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r | |
1496 | @endcode\r | |
ad8a2f5e | 1497 | @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r |
3adf6316 MK |
1498 | **/\r |
1499 | #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r | |
1500 | \r | |
1501 | \r | |
1502 | /**\r | |
1503 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
1504 | Domains.".\r | |
1505 | \r | |
1506 | @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)\r | |
1507 | @param EAX Lower 32-bits of MSR value.\r | |
1508 | @param EDX Upper 32-bits of MSR value.\r | |
1509 | \r | |
1510 | <b>Example usage</b>\r | |
1511 | @code\r | |
1512 | UINT64 Msr;\r | |
1513 | \r | |
1514 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r | |
1515 | @endcode\r | |
ad8a2f5e | 1516 | @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r |
3adf6316 MK |
1517 | **/\r |
1518 | #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r | |
1519 | \r | |
1520 | \r | |
1521 | /**\r | |
ba1a2d11 | 1522 | Package. Base TDP Ratio (R/O) See Table 2-24.\r |
3adf6316 MK |
1523 | \r |
1524 | @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r | |
1525 | @param EAX Lower 32-bits of MSR value.\r | |
1526 | @param EDX Upper 32-bits of MSR value.\r | |
1527 | \r | |
1528 | <b>Example usage</b>\r | |
1529 | @code\r | |
1530 | UINT64 Msr;\r | |
1531 | \r | |
1532 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r | |
1533 | @endcode\r | |
ad8a2f5e | 1534 | @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r |
3adf6316 MK |
1535 | **/\r |
1536 | #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r | |
1537 | \r | |
1538 | \r | |
1539 | /**\r | |
ba1a2d11 | 1540 | Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.\r |
3adf6316 MK |
1541 | \r |
1542 | @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r | |
1543 | @param EAX Lower 32-bits of MSR value.\r | |
1544 | @param EDX Upper 32-bits of MSR value.\r | |
1545 | \r | |
1546 | <b>Example usage</b>\r | |
1547 | @code\r | |
1548 | UINT64 Msr;\r | |
1549 | \r | |
1550 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r | |
1551 | @endcode\r | |
ad8a2f5e | 1552 | @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r |
3adf6316 MK |
1553 | **/\r |
1554 | #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r | |
1555 | \r | |
1556 | \r | |
1557 | /**\r | |
ba1a2d11 | 1558 | Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.\r |
3adf6316 MK |
1559 | \r |
1560 | @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r | |
1561 | @param EAX Lower 32-bits of MSR value.\r | |
1562 | @param EDX Upper 32-bits of MSR value.\r | |
1563 | \r | |
1564 | <b>Example usage</b>\r | |
1565 | @code\r | |
1566 | UINT64 Msr;\r | |
1567 | \r | |
1568 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r | |
1569 | @endcode\r | |
ad8a2f5e | 1570 | @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r |
3adf6316 MK |
1571 | **/\r |
1572 | #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r | |
1573 | \r | |
1574 | \r | |
1575 | /**\r | |
ba1a2d11 | 1576 | Package. ConfigTDP Control (R/W) See Table 2-24.\r |
3adf6316 MK |
1577 | \r |
1578 | @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r | |
1579 | @param EAX Lower 32-bits of MSR value.\r | |
1580 | @param EDX Upper 32-bits of MSR value.\r | |
1581 | \r | |
1582 | <b>Example usage</b>\r | |
1583 | @code\r | |
1584 | UINT64 Msr;\r | |
1585 | \r | |
1586 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r | |
1587 | AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r | |
1588 | @endcode\r | |
ad8a2f5e | 1589 | @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r |
3adf6316 MK |
1590 | **/\r |
1591 | #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r | |
1592 | \r | |
1593 | \r | |
1594 | /**\r | |
ba1a2d11 | 1595 | Package. ConfigTDP Control (R/W) See Table 2-24.\r |
3adf6316 MK |
1596 | \r |
1597 | @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
1598 | @param EAX Lower 32-bits of MSR value.\r | |
1599 | @param EDX Upper 32-bits of MSR value.\r | |
1600 | \r | |
1601 | <b>Example usage</b>\r | |
1602 | @code\r | |
1603 | UINT64 Msr;\r | |
1604 | \r | |
1605 | Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r | |
1606 | AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r | |
1607 | @endcode\r | |
ad8a2f5e | 1608 | @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r |
3adf6316 MK |
1609 | **/\r |
1610 | #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
1611 | \r | |
1612 | \r | |
1613 | /**\r | |
1614 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
1615 | refers to processor core frequency).\r | |
1616 | \r | |
1617 | @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)\r | |
1618 | @param EAX Lower 32-bits of MSR value.\r | |
1619 | Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
1620 | @param EDX Upper 32-bits of MSR value.\r | |
1621 | Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
1622 | \r | |
1623 | <b>Example usage</b>\r | |
1624 | @code\r | |
1625 | MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
1626 | \r | |
1627 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r | |
1628 | AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
1629 | @endcode\r | |
ad8a2f5e | 1630 | @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r |
3adf6316 MK |
1631 | **/\r |
1632 | #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r | |
1633 | \r | |
1634 | /**\r | |
1635 | MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r | |
1636 | **/\r | |
1637 | typedef union {\r | |
1638 | ///\r | |
1639 | /// Individual bit fields\r | |
1640 | ///\r | |
1641 | struct {\r | |
1642 | ///\r | |
1643 | /// [Bit 0] PROCHOT Status (R0).\r | |
1644 | ///\r | |
1645 | UINT32 PROCHOT_Status:1;\r | |
1646 | ///\r | |
1647 | /// [Bit 1] Thermal Status (R0).\r | |
1648 | ///\r | |
1649 | UINT32 ThermalStatus:1;\r | |
1650 | UINT32 Reserved1:4;\r | |
1651 | ///\r | |
1652 | /// [Bit 6] VR Therm Alert Status (R0).\r | |
1653 | ///\r | |
1654 | UINT32 VRThermAlertStatus:1;\r | |
1655 | UINT32 Reserved2:1;\r | |
1656 | ///\r | |
1657 | /// [Bit 8] Electrical Design Point Status (R0).\r | |
1658 | ///\r | |
1659 | UINT32 ElectricalDesignPointStatus:1;\r | |
1660 | UINT32 Reserved3:23;\r | |
1661 | UINT32 Reserved4:32;\r | |
1662 | } Bits;\r | |
1663 | ///\r | |
1664 | /// All bit fields as a 32-bit value\r | |
1665 | ///\r | |
1666 | UINT32 Uint32;\r | |
1667 | ///\r | |
1668 | /// All bit fields as a 64-bit value\r | |
1669 | ///\r | |
1670 | UINT64 Uint64;\r | |
1671 | } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r | |
1672 | \r | |
1673 | #endif\r |