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1/** @file\r
2 STM Resource Descriptor\r
3\r
4 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
0acd8697 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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6\r
7 @par Specification Reference:\r
8 SMI Transfer Monitor (STM) User Guide Revision 1.00\r
9\r
10**/\r
11\r
12#ifndef _STM_RESOURCE_DESCRIPTOR_H_\r
13#define _STM_RESOURCE_DESCRIPTOR_H_\r
14\r
15#pragma pack (1)\r
16\r
17/**\r
18 STM Resource Descriptor Header\r
19**/\r
20typedef struct {\r
21 UINT32 RscType;\r
22 UINT16 Length;\r
23 UINT16 ReturnStatus:1;\r
24 UINT16 Reserved:14;\r
25 UINT16 IgnoreResource:1;\r
26} STM_RSC_DESC_HEADER;\r
27\r
28/**\r
29 Define values for the RscType field of #STM_RSC_DESC_HEADER\r
30 @{\r
31**/\r
32#define END_OF_RESOURCES 0\r
33#define MEM_RANGE 1\r
34#define IO_RANGE 2\r
35#define MMIO_RANGE 3\r
36#define MACHINE_SPECIFIC_REG 4\r
37#define PCI_CFG_RANGE 5\r
38#define TRAPPED_IO_RANGE 6\r
39#define ALL_RESOURCES 7\r
40#define REGISTER_VIOLATION 8\r
41#define MAX_DESC_TYPE 8\r
42/// @}\r
43\r
44/**\r
45 STM Resource End Descriptor\r
46**/\r
47typedef struct {\r
48 STM_RSC_DESC_HEADER Hdr;\r
49 UINT64 ResourceListContinuation;\r
50} STM_RSC_END;\r
51\r
52/**\r
53 STM Resource Memory Descriptor\r
54**/\r
55typedef struct {\r
56 STM_RSC_DESC_HEADER Hdr;\r
57 UINT64 Base;\r
58 UINT64 Length;\r
59 UINT32 RWXAttributes:3;\r
60 UINT32 Reserved:29;\r
61 UINT32 Reserved_2;\r
62} STM_RSC_MEM_DESC;\r
63\r
64/**\r
65 Define values for the RWXAttributes field of #STM_RSC_MEM_DESC\r
66 @{\r
67**/\r
68#define STM_RSC_MEM_R 0x1\r
69#define STM_RSC_MEM_W 0x2\r
70#define STM_RSC_MEM_X 0x4\r
71/// @}\r
72\r
73/**\r
74 STM Resource I/O Descriptor\r
75**/\r
76typedef struct {\r
77 STM_RSC_DESC_HEADER Hdr;\r
78 UINT16 Base;\r
79 UINT16 Length;\r
80 UINT32 Reserved;\r
81} STM_RSC_IO_DESC;\r
82\r
83/**\r
84 STM Resource MMIO Descriptor\r
85**/\r
86typedef struct {\r
87 STM_RSC_DESC_HEADER Hdr;\r
88 UINT64 Base;\r
89 UINT64 Length;\r
90 UINT32 RWXAttributes:3;\r
91 UINT32 Reserved:29;\r
92 UINT32 Reserved_2;\r
93} STM_RSC_MMIO_DESC;\r
94\r
95/**\r
96 Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC\r
97 @{\r
98**/\r
99#define STM_RSC_MMIO_R 0x1\r
100#define STM_RSC_MMIO_W 0x2\r
101#define STM_RSC_MMIO_X 0x4\r
102/// @}\r
103\r
104/**\r
105 STM Resource MSR Descriptor\r
106**/\r
107typedef struct {\r
108 STM_RSC_DESC_HEADER Hdr;\r
109 UINT32 MsrIndex;\r
110 UINT32 KernelModeProcessing:1;\r
111 UINT32 Reserved:31;\r
112 UINT64 ReadMask;\r
113 UINT64 WriteMask;\r
114} STM_RSC_MSR_DESC;\r
115\r
116/**\r
117 STM PCI Device Path node used for the PciDevicePath field of\r
118 #STM_RSC_PCI_CFG_DESC\r
119**/\r
120typedef struct {\r
121 ///\r
122 /// Must be 1, indicating Hardware Device Path\r
123 ///\r
124 UINT8 Type;\r
125 ///\r
126 /// Must be 1, indicating PCI\r
127 ///\r
128 UINT8 Subtype;\r
129 ///\r
130 /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6\r
131 ///\r
132 UINT16 Length;\r
133 UINT8 PciFunction;\r
134 UINT8 PciDevice;\r
135} STM_PCI_DEVICE_PATH_NODE;\r
136\r
137/**\r
138 STM Resource PCI Configuration Descriptor\r
139**/\r
140typedef struct {\r
141 STM_RSC_DESC_HEADER Hdr;\r
142 UINT16 RWAttributes:2;\r
143 UINT16 Reserved:14;\r
144 UINT16 Base;\r
145 UINT16 Length;\r
146 UINT8 OriginatingBusNumber;\r
147 UINT8 LastNodeIndex;\r
148 STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];\r
149//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];\r
150} STM_RSC_PCI_CFG_DESC;\r
151\r
152/**\r
153 Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC\r
154 @{\r
155**/\r
156#define STM_RSC_PCI_CFG_R 0x1\r
157#define STM_RSC_PCI_CFG_W 0x2\r
158/// @}\r
159\r
160/**\r
161 STM Resource Trapped I/O Descriptor\r
162**/\r
163typedef struct {\r
164 STM_RSC_DESC_HEADER Hdr;\r
165 UINT16 Base;\r
166 UINT16 Length;\r
167 UINT16 In:1;\r
168 UINT16 Out:1;\r
169 UINT16 Api:1;\r
170 UINT16 Reserved1:13;\r
171 UINT16 Reserved2;\r
172} STM_RSC_TRAPPED_IO_DESC;\r
173\r
174/**\r
175 STM Resource All Descriptor\r
176**/\r
177typedef struct {\r
178 STM_RSC_DESC_HEADER Hdr;\r
179} STM_RSC_ALL_RESOURCES_DESC;\r
180\r
181/**\r
182 STM Register Volation Descriptor\r
183**/\r
184typedef struct {\r
185 STM_RSC_DESC_HEADER Hdr;\r
186 UINT32 RegisterType;\r
187 UINT32 Reserved;\r
188 UINT64 ReadMask;\r
189 UINT64 WriteMask;\r
190} STM_REGISTER_VIOLATION_DESC;\r
191\r
192/**\r
193 Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC\r
194**/\r
195typedef enum {\r
196 StmRegisterCr0,\r
197 StmRegisterCr2,\r
198 StmRegisterCr3,\r
199 StmRegisterCr4,\r
200 StmRegisterCr8,\r
201 StmRegisterMax,\r
202} STM_REGISTER_VIOLATION_TYPE;\r
203\r
204/**\r
205 Union of all STM resource types\r
206**/\r
207typedef union {\r
208 STM_RSC_DESC_HEADER Header;\r
209 STM_RSC_END End;\r
210 STM_RSC_MEM_DESC Mem;\r
211 STM_RSC_IO_DESC Io;\r
212 STM_RSC_MMIO_DESC Mmio;\r
213 STM_RSC_MSR_DESC Msr;\r
214 STM_RSC_PCI_CFG_DESC PciCfg;\r
215 STM_RSC_TRAPPED_IO_DESC TrappedIo;\r
216 STM_RSC_ALL_RESOURCES_DESC All;\r
217 STM_REGISTER_VIOLATION_DESC RegisterViolation;\r
218} STM_RSC;\r
219\r
220#pragma pack ()\r
221\r
222#endif\r