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d6d8e892 | 1 | #------------------------------------------------------------------------------\r |
2 | #*\r | |
3 | #* Copyright 2009, Intel Corporation\r | |
4 | #* All rights reserved. This program and the accompanying materials\r | |
5 | #* are licensed and made available under the terms and conditions of the BSD License\r | |
6 | #* which accompanies this distribution. The full text of the license may be found at\r | |
7 | #* http://opensource.org/licenses/bsd-license.php\r | |
8 | #*\r | |
9 | #* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | #* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | #*\r | |
12 | #*\r | |
13 | #------------------------------------------------------------------------------\r | |
14 | \r | |
15 | \r | |
16 | \r | |
989322c3 | 17 | #\r |
18 | # Float control word initial value: \r | |
19 | # all exceptions masked, double-precision, round-to-nearest\r | |
20 | #\r | |
21 | ASM_PFX(mFpuControlWord): .word 0x027F\r | |
22 | #\r | |
23 | # Multimedia-extensions control word:\r | |
24 | # all exceptions masked, round-to-nearest, flush to zero for masked underflow\r | |
25 | #\r | |
d6d8e892 | 26 | ASM_PFX(mMmxControlWord): .long 0x01F80\r |
27 | \r | |
28 | #\r | |
989322c3 | 29 | # Initializes floating point units for requirement of UEFI specification.\r |
30 | #\r | |
31 | # This function initializes floating-point control word to 0x027F (all exceptions\r | |
32 | # masked,double-precision, round-to-nearest) and multimedia-extensions control word\r | |
33 | # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r | |
d6d8e892 | 34 | # for masked underflow).\r |
35 | #\r | |
36 | ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)\r | |
37 | ASM_PFX(InitializeFloatingPointUnits):\r | |
38 | \r | |
39 | pushl %ebx\r | |
40 | \r | |
989322c3 | 41 | #\r |
42 | # Initialize floating point units\r | |
43 | #\r | |
44 | finit\r | |
45 | fldcw ASM_PFX(mFpuControlWord)\r | |
46 | \r | |
47 | #\r | |
48 | # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r | |
49 | # whether the processor supports SSE instruction.\r | |
50 | #\r | |
51 | movl $1, %eax\r | |
52 | cpuid\r | |
53 | btl $25, %edx\r | |
54 | jnc Done\r | |
d6d8e892 | 55 | \r |
56 | #\r | |
57 | # Set OSFXSR bit 9 in CR4\r | |
58 | #\r | |
59 | movl %cr4, %eax \r | |
60 | or $200, %eax\r | |
61 | movl %eax, %cr4\r | |
62 | \r | |
989322c3 | 63 | #\r |
64 | # The processor should support SSE instruction and we can use\r | |
65 | # ldmxcsr instruction\r | |
66 | #\r | |
d6d8e892 | 67 | ldmxcsr ASM_PFX(mMmxControlWord)\r |
68 | \r | |
69 | Done:\r | |
70 | popl %ebx\r | |
71 | \r | |
72 | ret\r | |
73 | \r | |
74 | #END\r | |
75 | \r |