UefiCpuPkg/CpuDxe: Enable protection for newly added page table
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c
CommitLineData
bf73cc4b 1/** @file\r
2 Local APIC Library.\r
3\r
4 This local APIC library instance supports xAPIC mode only.\r
5\r
a742e186 6 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
061ead7a
LD
7 Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
8\r
bf73cc4b 9 This program and the accompanying materials\r
10 are licensed and made available under the terms and conditions of the BSD License\r
11 which accompanies this distribution. The full text of the license may be found at\r
12 http://opensource.org/licenses/bsd-license.php\r
13\r
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
16\r
17**/\r
18\r
28a7ddf0 19#include <Register/Cpuid.h>\r
061ead7a 20#include <Register/Amd/Cpuid.h>\r
a742e186 21#include <Register/Msr.h>\r
bf73cc4b 22#include <Register/LocalApic.h>\r
23\r
24#include <Library/BaseLib.h>\r
25#include <Library/DebugLib.h>\r
26#include <Library/LocalApicLib.h>\r
27#include <Library/IoLib.h>\r
28#include <Library/TimerLib.h>\r
59d67246 29#include <Library/PcdLib.h>\r
bf73cc4b 30\r
31//\r
32// Library internal functions\r
33//\r
34\r
061ead7a
LD
35/**\r
36 Determine if the standard CPU signature is "AuthenticAMD".\r
37\r
38 @retval TRUE The CPU signature matches.\r
39 @retval FALSE The CPU signature does not match.\r
40\r
41**/\r
42BOOLEAN\r
43StandardSignatureIsAuthenticAMD (\r
44 VOID\r
45 )\r
46{\r
47 UINT32 RegEbx;\r
48 UINT32 RegEcx;\r
49 UINT32 RegEdx;\r
50\r
ae66c6f1 51 AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
061ead7a
LD
52 return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&\r
53 RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&\r
54 RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);\r
55}\r
56\r
59d67246
MK
57/**\r
58 Determine if the CPU supports the Local APIC Base Address MSR.\r
59\r
60 @retval TRUE The CPU supports the Local APIC Base Address MSR.\r
61 @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r
62\r
63**/\r
64BOOLEAN\r
65LocalApicBaseAddressMsrSupported (\r
66 VOID\r
67 )\r
68{\r
69 UINT32 RegEax;\r
70 UINTN FamilyId;\r
71 \r
72 AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
73 FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
74 if (FamilyId == 0x04 || FamilyId == 0x05) {\r
75 //\r
76 // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r
77 // Local APIC Base Address MSR\r
78 //\r
79 return FALSE;\r
80 }\r
81 return TRUE;\r
82}\r
83\r
a66e0c7d 84/**\r
85 Retrieve the base address of local APIC.\r
86\r
87 @return The base address of local APIC.\r
88\r
89**/\r
90UINTN\r
91EFIAPI\r
92GetLocalApicBaseAddress (\r
93 VOID\r
94 )\r
95{\r
a742e186 96 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
59d67246
MK
97\r
98 if (!LocalApicBaseAddressMsrSupported ()) {\r
99 //\r
100 // If CPU does not support Local APIC Base Address MSR, then retrieve\r
101 // Local APIC Base Address from PCD\r
102 //\r
103 return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
104 }\r
105\r
a742e186 106 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
a66e0c7d 107 \r
a742e186
JF
108 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
109 (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
a66e0c7d 110}\r
111\r
112/**\r
113 Set the base address of local APIC.\r
114\r
115 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
116\r
117 @param[in] BaseAddress Local APIC base address to be set.\r
118\r
119**/\r
120VOID\r
121EFIAPI\r
122SetLocalApicBaseAddress (\r
123 IN UINTN BaseAddress\r
124 )\r
125{\r
a742e186 126 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
a66e0c7d 127\r
128 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
129\r
59d67246
MK
130 if (!LocalApicBaseAddressMsrSupported ()) {\r
131 //\r
132 // Ignore set request if the CPU does not support APIC Base Address MSR\r
133 //\r
134 return;\r
135 }\r
136\r
a742e186 137 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
a66e0c7d 138\r
a742e186
JF
139 ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);\r
140 ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
a66e0c7d 141\r
a742e186 142 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
a66e0c7d 143}\r
144\r
bf73cc4b 145/**\r
146 Read from a local APIC register.\r
147\r
148 This function reads from a local APIC register either in xAPIC or x2APIC mode.\r
149 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
150 accessed using multiple 32-bit loads or stores, so this function only performs\r
151 32-bit read.\r
152\r
153 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
154 It must be 16-byte aligned.\r
155\r
156 @return 32-bit Value read from the register.\r
157**/\r
158UINT32\r
159EFIAPI\r
160ReadLocalApicReg (\r
161 IN UINTN MmioOffset\r
162 )\r
163{\r
164 ASSERT ((MmioOffset & 0xf) == 0);\r
165 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
166\r
a66e0c7d 167 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
bf73cc4b 168}\r
169\r
170/**\r
171 Write to a local APIC register.\r
172\r
173 This function writes to a local APIC register either in xAPIC or x2APIC mode.\r
174 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
175 accessed using multiple 32-bit loads or stores, so this function only performs\r
176 32-bit write.\r
177\r
178 if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r
179\r
180 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
181 It must be 16-byte aligned.\r
182 @param Value Value to be written to the register.\r
183**/\r
184VOID\r
185EFIAPI\r
186WriteLocalApicReg (\r
187 IN UINTN MmioOffset,\r
188 IN UINT32 Value\r
189 )\r
190{\r
191 ASSERT ((MmioOffset & 0xf) == 0);\r
192 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
193\r
a66e0c7d 194 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
bf73cc4b 195}\r
196\r
197/**\r
198 Send an IPI by writing to ICR.\r
199\r
200 This function returns after the IPI has been accepted by the target processor. \r
201\r
202 @param IcrLow 32-bit value to be written to the low half of ICR.\r
203 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
204**/\r
205VOID\r
206SendIpi (\r
207 IN UINT32 IcrLow,\r
208 IN UINT32 ApicId\r
209 )\r
210{\r
211 LOCAL_APIC_ICR_LOW IcrLowReg;\r
9c71e1e0
JF
212 UINT32 IcrHigh;\r
213 BOOLEAN InterruptState;\r
bf73cc4b 214\r
215 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
216 ASSERT (ApicId <= 0xff);\r
217\r
9c71e1e0
JF
218 InterruptState = SaveAndDisableInterrupts ();\r
219\r
220 //\r
221 // Save existing contents of ICR high 32 bits\r
222 //\r
223 IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);\r
224\r
225 //\r
226 // Wait for DeliveryStatus clear in case a previous IPI\r
227 // is still being sent\r
228 //\r
229 do {\r
230 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r
231 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
232\r
bf73cc4b 233 //\r
234 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
235 //\r
236 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
237 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r
9c71e1e0
JF
238\r
239 //\r
240 // Wait for DeliveryStatus clear again\r
241 //\r
bf73cc4b 242 do {\r
243 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r
244 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
9c71e1e0
JF
245\r
246 //\r
247 // And restore old contents of ICR high\r
248 //\r
249 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
250\r
251 SetInterruptState (InterruptState);\r
252\r
bf73cc4b 253}\r
254\r
255//\r
256// Library API implementation functions\r
257//\r
258\r
259/**\r
260 Get the current local APIC mode.\r
261\r
262 If local APIC is disabled, then ASSERT.\r
263\r
264 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
265 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
266**/\r
267UINTN\r
268EFIAPI\r
269GetApicMode (\r
270 VOID\r
271 )\r
272{\r
273 DEBUG_CODE (\r
274 {\r
a742e186 275 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
bf73cc4b 276\r
bf73cc4b 277 //\r
59d67246 278 // Check to see if the CPU supports the APIC Base Address MSR \r
bf73cc4b 279 //\r
59d67246 280 if (LocalApicBaseAddressMsrSupported ()) {\r
a742e186 281 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
59d67246
MK
282 //\r
283 // Local APIC should have been enabled\r
284 //\r
a742e186
JF
285 ASSERT (ApicBaseMsr.Bits.EN != 0);\r
286 ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r
59d67246 287 }\r
bf73cc4b 288 }\r
289 );\r
290 return LOCAL_APIC_MODE_XAPIC;\r
291}\r
292\r
293/**\r
294 Set the current local APIC mode.\r
295\r
296 If the specified local APIC mode is not valid, then ASSERT.\r
297 If the specified local APIC mode can't be set as current, then ASSERT.\r
298\r
299 @param ApicMode APIC mode to be set.\r
9c71e1e0
JF
300\r
301 @note This API must not be called from an interrupt handler or SMI handler.\r
302 It may result in unpredictable behavior.\r
bf73cc4b 303**/\r
304VOID\r
305EFIAPI\r
306SetApicMode (\r
307 IN UINTN ApicMode\r
308 )\r
309{\r
310 ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r
311 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
312}\r
313\r
314/**\r
315 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
316\r
6e3e4d70 317 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
bf73cc4b 318 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
319 the 32-bit local APIC ID is returned as initial APIC ID.\r
320\r
321 @return 32-bit initial local APIC ID of the executing processor.\r
322**/\r
323UINT32\r
324EFIAPI\r
325GetInitialApicId (\r
326 VOID\r
327 )\r
328{\r
6e3e4d70
JF
329 UINT32 ApicId;\r
330 UINT32 MaxCpuIdIndex;\r
bf73cc4b 331 UINT32 RegEbx;\r
332\r
333 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
334\r
6e3e4d70
JF
335 //\r
336 // Get the max index of basic CPUID\r
337 //\r
338 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
339\r
340 //\r
341 // If CPUID Leaf B is supported, \r
4af3ae14 342 // And CPUID.0BH:EBX[15:0] reports a non-zero value,\r
6e3e4d70
JF
343 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
344 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
345 //\r
346 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
4af3ae14
LE
347 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);\r
348 if ((RegEbx & (BIT16 - 1)) != 0) {\r
349 return ApicId;\r
350 }\r
6e3e4d70
JF
351 }\r
352\r
bf73cc4b 353 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
354 return RegEbx >> 24;\r
355}\r
356\r
357/**\r
358 Get the local APIC ID of the executing processor.\r
359\r
360 @return 32-bit local APIC ID of the executing processor.\r
361**/\r
362UINT32\r
363EFIAPI\r
364GetApicId (\r
365 VOID\r
366 )\r
367{\r
368 UINT32 ApicId;\r
369\r
370 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
6e3e4d70
JF
371 \r
372 if ((ApicId = GetInitialApicId ()) < 0x100) {\r
373 //\r
374 // If the initial local APIC ID is less 0x100, read APIC ID from\r
375 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.\r
376 //\r
377 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
378 ApicId >>= 24;\r
379 }\r
bf73cc4b 380 return ApicId;\r
381}\r
382\r
ae40aef1 383/**\r
384 Get the value of the local APIC version register.\r
385\r
386 @return the value of the local APIC version register.\r
387**/\r
388UINT32\r
389EFIAPI\r
390GetApicVersion (\r
391 VOID\r
392 )\r
393{\r
394 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r
395}\r
396\r
397/**\r
398 Send a Fixed IPI to a specified target processor.\r
399\r
400 This function returns after the IPI has been accepted by the target processor. \r
401\r
402 @param ApicId The local APIC ID of the target processor.\r
403 @param Vector The vector number of the interrupt being sent.\r
404**/\r
405VOID\r
406EFIAPI\r
407SendFixedIpi (\r
408 IN UINT32 ApicId,\r
409 IN UINT8 Vector\r
410 )\r
411{\r
412 LOCAL_APIC_ICR_LOW IcrLow;\r
413\r
414 IcrLow.Uint32 = 0;\r
415 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
416 IcrLow.Bits.Level = 1;\r
417 IcrLow.Bits.Vector = Vector;\r
418 SendIpi (IcrLow.Uint32, ApicId);\r
419}\r
420\r
421/**\r
422 Send a Fixed IPI to all processors excluding self.\r
423\r
424 This function returns after the IPI has been accepted by the target processors. \r
425\r
426 @param Vector The vector number of the interrupt being sent.\r
427**/\r
428VOID\r
429EFIAPI\r
430SendFixedIpiAllExcludingSelf (\r
431 IN UINT8 Vector\r
432 )\r
433{\r
434 LOCAL_APIC_ICR_LOW IcrLow;\r
435\r
436 IcrLow.Uint32 = 0;\r
437 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
438 IcrLow.Bits.Level = 1;\r
439 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
440 IcrLow.Bits.Vector = Vector;\r
441 SendIpi (IcrLow.Uint32, 0);\r
442}\r
443\r
bf73cc4b 444/**\r
445 Send a SMI IPI to a specified target processor.\r
446\r
447 This function returns after the IPI has been accepted by the target processor. \r
448\r
449 @param ApicId Specify the local APIC ID of the target processor.\r
450**/\r
451VOID\r
452EFIAPI\r
453SendSmiIpi (\r
454 IN UINT32 ApicId\r
455 )\r
456{\r
457 LOCAL_APIC_ICR_LOW IcrLow;\r
458\r
459 IcrLow.Uint32 = 0;\r
460 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
461 IcrLow.Bits.Level = 1;\r
462 SendIpi (IcrLow.Uint32, ApicId);\r
463}\r
464\r
465/**\r
466 Send a SMI IPI to all processors excluding self.\r
467\r
468 This function returns after the IPI has been accepted by the target processors. \r
469**/\r
470VOID\r
471EFIAPI\r
472SendSmiIpiAllExcludingSelf (\r
473 VOID\r
474 )\r
475{\r
476 LOCAL_APIC_ICR_LOW IcrLow;\r
477\r
478 IcrLow.Uint32 = 0;\r
479 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
480 IcrLow.Bits.Level = 1;\r
481 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
482 SendIpi (IcrLow.Uint32, 0);\r
483}\r
484\r
485/**\r
486 Send an INIT IPI to a specified target processor.\r
487\r
488 This function returns after the IPI has been accepted by the target processor. \r
489\r
490 @param ApicId Specify the local APIC ID of the target processor.\r
491**/\r
492VOID\r
493EFIAPI\r
494SendInitIpi (\r
495 IN UINT32 ApicId\r
496 )\r
497{\r
498 LOCAL_APIC_ICR_LOW IcrLow;\r
499\r
500 IcrLow.Uint32 = 0;\r
501 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
502 IcrLow.Bits.Level = 1;\r
503 SendIpi (IcrLow.Uint32, ApicId);\r
504}\r
505\r
506/**\r
507 Send an INIT IPI to all processors excluding self.\r
508\r
509 This function returns after the IPI has been accepted by the target processors. \r
510**/\r
511VOID\r
512EFIAPI\r
513SendInitIpiAllExcludingSelf (\r
514 VOID\r
515 )\r
516{\r
517 LOCAL_APIC_ICR_LOW IcrLow;\r
518\r
519 IcrLow.Uint32 = 0;\r
520 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
521 IcrLow.Bits.Level = 1;\r
522 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
523 SendIpi (IcrLow.Uint32, 0);\r
524}\r
525\r
526/**\r
527 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
528\r
529 This function returns after the IPI has been accepted by the target processor. \r
530\r
531 if StartupRoutine >= 1M, then ASSERT.\r
532 if StartupRoutine is not multiple of 4K, then ASSERT.\r
533\r
534 @param ApicId Specify the local APIC ID of the target processor.\r
535 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
536 address and 4K aligned.\r
537**/\r
538VOID\r
539EFIAPI\r
540SendInitSipiSipi (\r
541 IN UINT32 ApicId,\r
542 IN UINT32 StartupRoutine\r
543 )\r
544{\r
545 LOCAL_APIC_ICR_LOW IcrLow;\r
546\r
547 ASSERT (StartupRoutine < 0x100000);\r
548 ASSERT ((StartupRoutine & 0xfff) == 0);\r
549\r
550 SendInitIpi (ApicId);\r
cf1eb6e6 551 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
bf73cc4b 552 IcrLow.Uint32 = 0;\r
553 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
554 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
555 IcrLow.Bits.Level = 1;\r
556 SendIpi (IcrLow.Uint32, ApicId);\r
557 MicroSecondDelay (200);\r
558 SendIpi (IcrLow.Uint32, ApicId);\r
559}\r
560\r
561/**\r
562 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
563\r
564 This function returns after the IPI has been accepted by the target processors. \r
565\r
566 if StartupRoutine >= 1M, then ASSERT.\r
567 if StartupRoutine is not multiple of 4K, then ASSERT.\r
568\r
569 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
570 address and 4K aligned.\r
571**/\r
572VOID\r
573EFIAPI\r
574SendInitSipiSipiAllExcludingSelf (\r
575 IN UINT32 StartupRoutine\r
576 )\r
577{\r
578 LOCAL_APIC_ICR_LOW IcrLow;\r
579\r
580 ASSERT (StartupRoutine < 0x100000);\r
581 ASSERT ((StartupRoutine & 0xfff) == 0);\r
582\r
583 SendInitIpiAllExcludingSelf ();\r
cf1eb6e6 584 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
bf73cc4b 585 IcrLow.Uint32 = 0;\r
586 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
587 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
588 IcrLow.Bits.Level = 1;\r
589 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
590 SendIpi (IcrLow.Uint32, 0);\r
591 MicroSecondDelay (200);\r
592 SendIpi (IcrLow.Uint32, 0);\r
593}\r
594\r
14e4ca25
MK
595/**\r
596 Initialize the state of the SoftwareEnable bit in the Local APIC\r
597 Spurious Interrupt Vector register.\r
598\r
599 @param Enable If TRUE, then set SoftwareEnable to 1\r
600 If FALSE, then set SoftwareEnable to 0.\r
601\r
602**/\r
603VOID\r
604EFIAPI\r
605InitializeLocalApicSoftwareEnable (\r
606 IN BOOLEAN Enable\r
607 )\r
608{\r
609 LOCAL_APIC_SVR Svr;\r
610\r
611 //\r
612 // Set local APIC software-enabled bit.\r
613 //\r
614 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
615 if (Enable) {\r
616 if (Svr.Bits.SoftwareEnable == 0) {\r
617 Svr.Bits.SoftwareEnable = 1;\r
618 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
619 }\r
620 } else {\r
621 if (Svr.Bits.SoftwareEnable == 1) {\r
622 Svr.Bits.SoftwareEnable = 0;\r
623 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
624 }\r
625 }\r
626}\r
627\r
bf73cc4b 628/**\r
629 Programming Virtual Wire Mode.\r
630\r
631 This function programs the local APIC for virtual wire mode following\r
632 the example described in chapter A.3 of the MP 1.4 spec.\r
633\r
634 IOxAPIC is not involved in this type of virtual wire mode.\r
635**/\r
636VOID\r
637EFIAPI\r
638ProgramVirtualWireMode (\r
639 VOID\r
640 )\r
641{\r
642 LOCAL_APIC_SVR Svr;\r
643 LOCAL_APIC_LVT_LINT Lint;\r
644\r
645 //\r
646 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
647 //\r
648 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
649 Svr.Bits.SpuriousVector = 0xf;\r
650 Svr.Bits.SoftwareEnable = 1;\r
651 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
652\r
653 //\r
654 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
655 //\r
ae40aef1 656 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
bf73cc4b 657 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
658 Lint.Bits.InputPinPolarity = 0;\r
659 Lint.Bits.TriggerMode = 0;\r
660 Lint.Bits.Mask = 0;\r
ae40aef1 661 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r
bf73cc4b 662\r
663 //\r
664 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
665 //\r
ae40aef1 666 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
bf73cc4b 667 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
668 Lint.Bits.InputPinPolarity = 0;\r
669 Lint.Bits.TriggerMode = 0;\r
670 Lint.Bits.Mask = 0;\r
ae40aef1 671 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
bf73cc4b 672}\r
673\r
b1b8c631 674/**\r
675 Disable LINT0 & LINT1 interrupts.\r
676\r
677 This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
678**/\r
679VOID\r
680EFIAPI\r
681DisableLvtInterrupts (\r
682 VOID\r
683 )\r
684{\r
685 LOCAL_APIC_LVT_LINT LvtLint;\r
686\r
687 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
688 LvtLint.Bits.Mask = 1;\r
689 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r
690\r
691 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
692 LvtLint.Bits.Mask = 1;\r
693 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r
694}\r
695\r
bf73cc4b 696/**\r
697 Read the initial count value from the init-count register.\r
698\r
699 @return The initial count value read from the init-count register.\r
700**/\r
701UINT32\r
702EFIAPI\r
703GetApicTimerInitCount (\r
704 VOID\r
705 )\r
706{\r
707 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r
708}\r
709\r
710/**\r
711 Read the current count value from the current-count register.\r
712\r
713 @return The current count value read from the current-count register.\r
714**/\r
715UINT32\r
716EFIAPI\r
717GetApicTimerCurrentCount (\r
718 VOID\r
719 )\r
720{\r
721 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r
722}\r
723\r
724/**\r
725 Initialize the local APIC timer.\r
726\r
727 The local APIC timer is initialized and enabled.\r
728\r
729 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
730 If it is 0, then use the current divide value in the DCR.\r
731 @param InitCount The initial count value.\r
732 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
733 @param Vector The timer interrupt vector number.\r
734**/\r
735VOID\r
736EFIAPI\r
737InitializeApicTimer (\r
738 IN UINTN DivideValue,\r
739 IN UINT32 InitCount,\r
740 IN BOOLEAN PeriodicMode,\r
741 IN UINT8 Vector\r
742 )\r
743{\r
bf73cc4b 744 LOCAL_APIC_DCR Dcr;\r
745 LOCAL_APIC_LVT_TIMER LvtTimer;\r
746 UINT32 Divisor;\r
747\r
748 //\r
749 // Ensure local APIC is in software-enabled state.\r
750 //\r
14e4ca25 751 InitializeLocalApicSoftwareEnable (TRUE);\r
bf73cc4b 752\r
753 //\r
754 // Program init-count register.\r
755 //\r
756 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r
757\r
758 if (DivideValue != 0) {\r
759 ASSERT (DivideValue <= 128);\r
760 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
761 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
762\r
763 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
764 Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
765 Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
766 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r
767 }\r
768\r
769 //\r
770 // Enable APIC timer interrupt with specified timer mode.\r
771 //\r
772 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
773 if (PeriodicMode) {\r
774 LvtTimer.Bits.TimerMode = 1;\r
775 } else {\r
776 LvtTimer.Bits.TimerMode = 0;\r
777 }\r
778 LvtTimer.Bits.Mask = 0;\r
779 LvtTimer.Bits.Vector = Vector;\r
780 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
781}\r
782\r
ae40aef1 783/**\r
784 Get the state of the local APIC timer.\r
785\r
6d72ff7d
HW
786 This function will ASSERT if the local APIC is not software enabled.\r
787\r
ae40aef1 788 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
789 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
790 @param Vector Return the timer interrupt vector number.\r
791**/\r
792VOID\r
793EFIAPI\r
794GetApicTimerState (\r
795 OUT UINTN *DivideValue OPTIONAL,\r
796 OUT BOOLEAN *PeriodicMode OPTIONAL,\r
797 OUT UINT8 *Vector OPTIONAL\r
798 )\r
799{\r
800 UINT32 Divisor;\r
801 LOCAL_APIC_DCR Dcr;\r
802 LOCAL_APIC_LVT_TIMER LvtTimer;\r
803\r
6d72ff7d
HW
804 //\r
805 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
806 // Vector Register.\r
807 // This bit will be 1, if local APIC is software enabled.\r
808 //\r
809 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
810\r
ae40aef1 811 if (DivideValue != NULL) {\r
812 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
813 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
814 Divisor = (Divisor + 1) & 0x7;\r
815 *DivideValue = ((UINTN)1) << Divisor;\r
816 }\r
817\r
818 if (PeriodicMode != NULL || Vector != NULL) {\r
819 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
820 if (PeriodicMode != NULL) {\r
821 if (LvtTimer.Bits.TimerMode == 1) {\r
822 *PeriodicMode = TRUE;\r
823 } else {\r
824 *PeriodicMode = FALSE;\r
825 }\r
826 }\r
827 if (Vector != NULL) {\r
828 *Vector = (UINT8) LvtTimer.Bits.Vector;\r
829 }\r
830 }\r
831}\r
832\r
bf73cc4b 833/**\r
834 Enable the local APIC timer interrupt.\r
835**/\r
836VOID\r
837EFIAPI\r
838EnableApicTimerInterrupt (\r
839 VOID\r
840 )\r
841{\r
842 LOCAL_APIC_LVT_TIMER LvtTimer;\r
843\r
844 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
845 LvtTimer.Bits.Mask = 0;\r
846 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
847}\r
848\r
849/**\r
850 Disable the local APIC timer interrupt.\r
851**/\r
852VOID\r
853EFIAPI\r
854DisableApicTimerInterrupt (\r
855 VOID\r
856 )\r
857{\r
858 LOCAL_APIC_LVT_TIMER LvtTimer;\r
859\r
860 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
861 LvtTimer.Bits.Mask = 1;\r
862 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
863}\r
864\r
865/**\r
866 Get the local APIC timer interrupt state.\r
867\r
868 @retval TRUE The local APIC timer interrupt is enabled.\r
869 @retval FALSE The local APIC timer interrupt is disabled.\r
870**/\r
871BOOLEAN\r
872EFIAPI\r
873GetApicTimerInterruptState (\r
874 VOID\r
875 )\r
876{\r
877 LOCAL_APIC_LVT_TIMER LvtTimer;\r
878\r
879 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
880 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
881}\r
882\r
883/**\r
884 Send EOI to the local APIC.\r
885**/\r
886VOID\r
887EFIAPI\r
888SendApicEoi (\r
889 VOID\r
890 )\r
891{\r
892 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
893}\r
894\r
5f867ad0 895/**\r
896 Get the 32-bit address that a device should use to send a Message Signaled \r
897 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
898\r
899 @return 32-bit address used to send an MSI to the Local APIC.\r
900**/\r
901UINT32\r
902EFIAPI \r
903GetApicMsiAddress (\r
904 VOID\r
905 )\r
906{\r
907 LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
908\r
909 //\r
910 // Return address for an MSI interrupt to be delivered only to the APIC ID \r
911 // of the currently executing processor.\r
912 //\r
913 MsiAddress.Uint32 = 0;\r
914 MsiAddress.Bits.BaseAddress = 0xFEE;\r
915 MsiAddress.Bits.DestinationId = GetApicId ();\r
916 return MsiAddress.Uint32;\r
917}\r
918 \r
919/**\r
920 Get the 64-bit data value that a device should use to send a Message Signaled \r
921 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
922\r
923 If Vector is not in range 0x10..0xFE, then ASSERT().\r
924 If DeliveryMode is not supported, then ASSERT().\r
925 \r
926 @param Vector The 8-bit interrupt vector associated with the MSI. \r
927 Must be in the range 0x10..0xFE\r
928 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
929 is handled. The only supported values are:\r
930 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
931 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
932 2: LOCAL_APIC_DELIVERY_MODE_SMI\r
933 4: LOCAL_APIC_DELIVERY_MODE_NMI\r
934 5: LOCAL_APIC_DELIVERY_MODE_INIT\r
935 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
936 \r
937 @param LevelTriggered TRUE specifies a level triggered interrupt. \r
938 FALSE specifies an edge triggered interrupt.\r
939 @param AssertionLevel Ignored if LevelTriggered is FALSE.\r
940 TRUE specifies a level triggered interrupt that active \r
941 when the interrupt line is asserted.\r
942 FALSE specifies a level triggered interrupt that active \r
943 when the interrupt line is deasserted.\r
944\r
945 @return 64-bit data value used to send an MSI to the Local APIC.\r
946**/\r
947UINT64\r
948EFIAPI \r
949GetApicMsiValue (\r
950 IN UINT8 Vector,\r
951 IN UINTN DeliveryMode,\r
952 IN BOOLEAN LevelTriggered,\r
953 IN BOOLEAN AssertionLevel\r
954 )\r
955{\r
956 LOCAL_APIC_MSI_DATA MsiData;\r
957\r
958 ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
959 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
960 \r
961 MsiData.Uint64 = 0;\r
962 MsiData.Bits.Vector = Vector;\r
963 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
964 if (LevelTriggered) {\r
965 MsiData.Bits.TriggerMode = 1;\r
966 if (AssertionLevel) {\r
967 MsiData.Bits.Level = 1;\r
968 }\r
969 }\r
970 return MsiData.Uint64;\r
971}\r
73152f19
LD
972\r
973/**\r
974 Get Package ID/Core ID/Thread ID of a processor.\r
975\r
976 The algorithm assumes the target system has symmetry across physical\r
977 package boundaries with respect to the number of logical processors\r
978 per package, number of cores per package.\r
979\r
980 @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
981 @param[out] Package Returns the processor package ID.\r
982 @param[out] Core Returns the processor core ID.\r
983 @param[out] Thread Returns the processor thread ID.\r
984**/\r
985VOID\r
1c8ca9a0 986EFIAPI\r
262128e5 987GetProcessorLocationByApicId (\r
73152f19
LD
988 IN UINT32 InitialApicId,\r
989 OUT UINT32 *Package OPTIONAL,\r
990 OUT UINT32 *Core OPTIONAL,\r
991 OUT UINT32 *Thread OPTIONAL\r
992 )\r
993{\r
061ead7a
LD
994 BOOLEAN TopologyLeafSupported;\r
995 CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
996 CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
997 CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
998 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
999 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
1000 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
1001 CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r
1002 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r
061ead7a
LD
1003 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r
1004 UINT32 MaxStandardCpuIdIndex;\r
1005 UINT32 MaxExtendedCpuIdIndex;\r
1006 UINT32 SubIndex;\r
1007 UINTN LevelType;\r
1008 UINT32 MaxLogicProcessorsPerPackage;\r
1009 UINT32 MaxCoresPerPackage;\r
061ead7a
LD
1010 UINTN ThreadBits;\r
1011 UINTN CoreBits;\r
73152f19
LD
1012\r
1013 //\r
1014 // Check if the processor is capable of supporting more than one logical processor.\r
1015 //\r
ae66c6f1 1016 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
73152f19
LD
1017 if (VersionInfoEdx.Bits.HTT == 0) {\r
1018 if (Thread != NULL) {\r
061ead7a 1019 *Thread = 0;\r
73152f19
LD
1020 }\r
1021 if (Core != NULL) {\r
061ead7a 1022 *Core = 0;\r
73152f19
LD
1023 }\r
1024 if (Package != NULL) {\r
1025 *Package = 0;\r
1026 }\r
1027 return;\r
1028 }\r
1029\r
061ead7a
LD
1030 //\r
1031 // Assume three-level mapping of APIC ID: Package|Core|Thread.\r
1032 //\r
73152f19
LD
1033 ThreadBits = 0;\r
1034 CoreBits = 0;\r
1035\r
1036 //\r
061ead7a 1037 // Get max index of CPUID\r
73152f19 1038 //\r
ae66c6f1
LD
1039 AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
1040 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
73152f19
LD
1041\r
1042 //\r
1043 // If the extended topology enumeration leaf is available, it\r
1044 // is the preferred mechanism for enumerating topology.\r
1045 //\r
061ead7a
LD
1046 TopologyLeafSupported = FALSE;\r
1047 if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
73152f19
LD
1048 AsmCpuidEx(\r
1049 CPUID_EXTENDED_TOPOLOGY,\r
1050 0,\r
1051 &ExtendedTopologyEax.Uint32,\r
1052 &ExtendedTopologyEbx.Uint32,\r
1053 &ExtendedTopologyEcx.Uint32,\r
1054 NULL\r
1055 );\r
1056 //\r
1057 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
1058 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
1059 // supported on that processor.\r
1060 //\r
1061 if (ExtendedTopologyEbx.Uint32 != 0) {\r
1062 TopologyLeafSupported = TRUE;\r
1063\r
1064 //\r
1065 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
1066 // the SMT sub-field of x2APIC ID.\r
1067 //\r
1068 LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
ae66c6f1 1069 ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
73152f19
LD
1070 ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
1071\r
1072 //\r
1073 // Software must not assume any "level type" encoding\r
1074 // value to be related to any sub-leaf index, except sub-leaf 0.\r
1075 //\r
1076 SubIndex = 1;\r
1077 do {\r
ae66c6f1 1078 AsmCpuidEx (\r
73152f19
LD
1079 CPUID_EXTENDED_TOPOLOGY,\r
1080 SubIndex,\r
1081 &ExtendedTopologyEax.Uint32,\r
1082 NULL,\r
1083 &ExtendedTopologyEcx.Uint32,\r
1084 NULL\r
1085 );\r
1086 LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
1087 if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
1088 CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
1089 break;\r
1090 }\r
1091 SubIndex++;\r
1092 } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
1093 }\r
1094 }\r
1095\r
1096 if (!TopologyLeafSupported) {\r
061ead7a
LD
1097 //\r
1098 // Get logical processor count\r
1099 //\r
ae66c6f1 1100 AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
73152f19 1101 MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
061ead7a
LD
1102\r
1103 //\r
1104 // Assume single-core processor\r
1105 //\r
1106 MaxCoresPerPackage = 1;\r
1107\r
1108 //\r
1109 // Check for topology extensions on AMD processor\r
1110 //\r
1111 if (StandardSignatureIsAuthenticAMD()) {\r
1112 if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
ae66c6f1 1113 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
061ead7a 1114 if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
061ead7a 1115 //\r
ae66c6f1 1116 // Account for max possible thread count to decode ApicId\r
061ead7a 1117 //\r
ae66c6f1
LD
1118 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
1119 MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
061ead7a
LD
1120\r
1121 //\r
ae66c6f1 1122 // Get cores per processor package\r
061ead7a 1123 //\r
ae66c6f1
LD
1124 AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r
1125 MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
061ead7a
LD
1126 }\r
1127 }\r
73152f19
LD
1128 }\r
1129 else {\r
1130 //\r
061ead7a 1131 // Extract core count based on CACHE information\r
73152f19 1132 //\r
061ead7a 1133 if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
ae66c6f1 1134 AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
061ead7a
LD
1135 if (CacheParamsEax.Uint32 != 0) {\r
1136 MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
1137 }\r
1138 }\r
73152f19
LD
1139 }\r
1140\r
1141 ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
061ead7a
LD
1142 CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r
1143 }\r
73152f19
LD
1144\r
1145 if (Thread != NULL) {\r
061ead7a 1146 *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
73152f19
LD
1147 }\r
1148 if (Core != NULL) {\r
061ead7a 1149 *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
73152f19
LD
1150 }\r
1151 if (Package != NULL) {\r
1152 *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
1153 }\r
1154}\r