UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c
CommitLineData
bf73cc4b 1/** @file\r
2 Local APIC Library.\r
3\r
4 This local APIC library instance supports xAPIC mode only.\r
5\r
a742e186 6 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
bf73cc4b 7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
28a7ddf0 17#include <Register/Cpuid.h>\r
a742e186 18#include <Register/Msr.h>\r
bf73cc4b 19#include <Register/LocalApic.h>\r
20\r
21#include <Library/BaseLib.h>\r
22#include <Library/DebugLib.h>\r
23#include <Library/LocalApicLib.h>\r
24#include <Library/IoLib.h>\r
25#include <Library/TimerLib.h>\r
59d67246 26#include <Library/PcdLib.h>\r
bf73cc4b 27\r
28//\r
29// Library internal functions\r
30//\r
31\r
59d67246
MK
32/**\r
33 Determine if the CPU supports the Local APIC Base Address MSR.\r
34\r
35 @retval TRUE The CPU supports the Local APIC Base Address MSR.\r
36 @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r
37\r
38**/\r
39BOOLEAN\r
40LocalApicBaseAddressMsrSupported (\r
41 VOID\r
42 )\r
43{\r
44 UINT32 RegEax;\r
45 UINTN FamilyId;\r
46 \r
47 AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
48 FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
49 if (FamilyId == 0x04 || FamilyId == 0x05) {\r
50 //\r
51 // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r
52 // Local APIC Base Address MSR\r
53 //\r
54 return FALSE;\r
55 }\r
56 return TRUE;\r
57}\r
58\r
a66e0c7d 59/**\r
60 Retrieve the base address of local APIC.\r
61\r
62 @return The base address of local APIC.\r
63\r
64**/\r
65UINTN\r
66EFIAPI\r
67GetLocalApicBaseAddress (\r
68 VOID\r
69 )\r
70{\r
a742e186 71 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
59d67246
MK
72\r
73 if (!LocalApicBaseAddressMsrSupported ()) {\r
74 //\r
75 // If CPU does not support Local APIC Base Address MSR, then retrieve\r
76 // Local APIC Base Address from PCD\r
77 //\r
78 return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
79 }\r
80\r
a742e186 81 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
a66e0c7d 82 \r
a742e186
JF
83 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
84 (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
a66e0c7d 85}\r
86\r
87/**\r
88 Set the base address of local APIC.\r
89\r
90 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
91\r
92 @param[in] BaseAddress Local APIC base address to be set.\r
93\r
94**/\r
95VOID\r
96EFIAPI\r
97SetLocalApicBaseAddress (\r
98 IN UINTN BaseAddress\r
99 )\r
100{\r
a742e186 101 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
a66e0c7d 102\r
103 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
104\r
59d67246
MK
105 if (!LocalApicBaseAddressMsrSupported ()) {\r
106 //\r
107 // Ignore set request if the CPU does not support APIC Base Address MSR\r
108 //\r
109 return;\r
110 }\r
111\r
a742e186 112 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
a66e0c7d 113\r
a742e186
JF
114 ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);\r
115 ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
a66e0c7d 116\r
a742e186 117 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
a66e0c7d 118}\r
119\r
bf73cc4b 120/**\r
121 Read from a local APIC register.\r
122\r
123 This function reads from a local APIC register either in xAPIC or x2APIC mode.\r
124 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
125 accessed using multiple 32-bit loads or stores, so this function only performs\r
126 32-bit read.\r
127\r
128 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
129 It must be 16-byte aligned.\r
130\r
131 @return 32-bit Value read from the register.\r
132**/\r
133UINT32\r
134EFIAPI\r
135ReadLocalApicReg (\r
136 IN UINTN MmioOffset\r
137 )\r
138{\r
139 ASSERT ((MmioOffset & 0xf) == 0);\r
140 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
141\r
a66e0c7d 142 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
bf73cc4b 143}\r
144\r
145/**\r
146 Write to a local APIC register.\r
147\r
148 This function writes to a local APIC register either in xAPIC or x2APIC mode.\r
149 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
150 accessed using multiple 32-bit loads or stores, so this function only performs\r
151 32-bit write.\r
152\r
153 if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r
154\r
155 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
156 It must be 16-byte aligned.\r
157 @param Value Value to be written to the register.\r
158**/\r
159VOID\r
160EFIAPI\r
161WriteLocalApicReg (\r
162 IN UINTN MmioOffset,\r
163 IN UINT32 Value\r
164 )\r
165{\r
166 ASSERT ((MmioOffset & 0xf) == 0);\r
167 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
168\r
a66e0c7d 169 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
bf73cc4b 170}\r
171\r
172/**\r
173 Send an IPI by writing to ICR.\r
174\r
175 This function returns after the IPI has been accepted by the target processor. \r
176\r
177 @param IcrLow 32-bit value to be written to the low half of ICR.\r
178 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
179**/\r
180VOID\r
181SendIpi (\r
182 IN UINT32 IcrLow,\r
183 IN UINT32 ApicId\r
184 )\r
185{\r
186 LOCAL_APIC_ICR_LOW IcrLowReg;\r
9c71e1e0
JF
187 UINT32 IcrHigh;\r
188 BOOLEAN InterruptState;\r
bf73cc4b 189\r
190 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
191 ASSERT (ApicId <= 0xff);\r
192\r
9c71e1e0
JF
193 InterruptState = SaveAndDisableInterrupts ();\r
194\r
195 //\r
196 // Save existing contents of ICR high 32 bits\r
197 //\r
198 IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);\r
199\r
200 //\r
201 // Wait for DeliveryStatus clear in case a previous IPI\r
202 // is still being sent\r
203 //\r
204 do {\r
205 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r
206 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
207\r
bf73cc4b 208 //\r
209 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
210 //\r
211 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
212 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r
9c71e1e0
JF
213\r
214 //\r
215 // Wait for DeliveryStatus clear again\r
216 //\r
bf73cc4b 217 do {\r
218 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r
219 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
9c71e1e0
JF
220\r
221 //\r
222 // And restore old contents of ICR high\r
223 //\r
224 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
225\r
226 SetInterruptState (InterruptState);\r
227\r
bf73cc4b 228}\r
229\r
230//\r
231// Library API implementation functions\r
232//\r
233\r
234/**\r
235 Get the current local APIC mode.\r
236\r
237 If local APIC is disabled, then ASSERT.\r
238\r
239 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
240 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
241**/\r
242UINTN\r
243EFIAPI\r
244GetApicMode (\r
245 VOID\r
246 )\r
247{\r
248 DEBUG_CODE (\r
249 {\r
a742e186 250 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
bf73cc4b 251\r
bf73cc4b 252 //\r
59d67246 253 // Check to see if the CPU supports the APIC Base Address MSR \r
bf73cc4b 254 //\r
59d67246 255 if (LocalApicBaseAddressMsrSupported ()) {\r
a742e186 256 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
59d67246
MK
257 //\r
258 // Local APIC should have been enabled\r
259 //\r
a742e186
JF
260 ASSERT (ApicBaseMsr.Bits.EN != 0);\r
261 ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r
59d67246 262 }\r
bf73cc4b 263 }\r
264 );\r
265 return LOCAL_APIC_MODE_XAPIC;\r
266}\r
267\r
268/**\r
269 Set the current local APIC mode.\r
270\r
271 If the specified local APIC mode is not valid, then ASSERT.\r
272 If the specified local APIC mode can't be set as current, then ASSERT.\r
273\r
274 @param ApicMode APIC mode to be set.\r
9c71e1e0
JF
275\r
276 @note This API must not be called from an interrupt handler or SMI handler.\r
277 It may result in unpredictable behavior.\r
bf73cc4b 278**/\r
279VOID\r
280EFIAPI\r
281SetApicMode (\r
282 IN UINTN ApicMode\r
283 )\r
284{\r
285 ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r
286 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
287}\r
288\r
289/**\r
290 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
291\r
6e3e4d70 292 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
bf73cc4b 293 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
294 the 32-bit local APIC ID is returned as initial APIC ID.\r
295\r
296 @return 32-bit initial local APIC ID of the executing processor.\r
297**/\r
298UINT32\r
299EFIAPI\r
300GetInitialApicId (\r
301 VOID\r
302 )\r
303{\r
6e3e4d70
JF
304 UINT32 ApicId;\r
305 UINT32 MaxCpuIdIndex;\r
bf73cc4b 306 UINT32 RegEbx;\r
307\r
308 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
309\r
6e3e4d70
JF
310 //\r
311 // Get the max index of basic CPUID\r
312 //\r
313 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
314\r
315 //\r
316 // If CPUID Leaf B is supported, \r
317 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
318 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
319 //\r
320 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
321 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);\r
322 return ApicId;\r
323 }\r
324\r
bf73cc4b 325 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
326 return RegEbx >> 24;\r
327}\r
328\r
329/**\r
330 Get the local APIC ID of the executing processor.\r
331\r
332 @return 32-bit local APIC ID of the executing processor.\r
333**/\r
334UINT32\r
335EFIAPI\r
336GetApicId (\r
337 VOID\r
338 )\r
339{\r
340 UINT32 ApicId;\r
341\r
342 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
6e3e4d70
JF
343 \r
344 if ((ApicId = GetInitialApicId ()) < 0x100) {\r
345 //\r
346 // If the initial local APIC ID is less 0x100, read APIC ID from\r
347 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.\r
348 //\r
349 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
350 ApicId >>= 24;\r
351 }\r
bf73cc4b 352 return ApicId;\r
353}\r
354\r
ae40aef1 355/**\r
356 Get the value of the local APIC version register.\r
357\r
358 @return the value of the local APIC version register.\r
359**/\r
360UINT32\r
361EFIAPI\r
362GetApicVersion (\r
363 VOID\r
364 )\r
365{\r
366 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r
367}\r
368\r
369/**\r
370 Send a Fixed IPI to a specified target processor.\r
371\r
372 This function returns after the IPI has been accepted by the target processor. \r
373\r
374 @param ApicId The local APIC ID of the target processor.\r
375 @param Vector The vector number of the interrupt being sent.\r
376**/\r
377VOID\r
378EFIAPI\r
379SendFixedIpi (\r
380 IN UINT32 ApicId,\r
381 IN UINT8 Vector\r
382 )\r
383{\r
384 LOCAL_APIC_ICR_LOW IcrLow;\r
385\r
386 IcrLow.Uint32 = 0;\r
387 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
388 IcrLow.Bits.Level = 1;\r
389 IcrLow.Bits.Vector = Vector;\r
390 SendIpi (IcrLow.Uint32, ApicId);\r
391}\r
392\r
393/**\r
394 Send a Fixed IPI to all processors excluding self.\r
395\r
396 This function returns after the IPI has been accepted by the target processors. \r
397\r
398 @param Vector The vector number of the interrupt being sent.\r
399**/\r
400VOID\r
401EFIAPI\r
402SendFixedIpiAllExcludingSelf (\r
403 IN UINT8 Vector\r
404 )\r
405{\r
406 LOCAL_APIC_ICR_LOW IcrLow;\r
407\r
408 IcrLow.Uint32 = 0;\r
409 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
410 IcrLow.Bits.Level = 1;\r
411 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
412 IcrLow.Bits.Vector = Vector;\r
413 SendIpi (IcrLow.Uint32, 0);\r
414}\r
415\r
bf73cc4b 416/**\r
417 Send a SMI IPI to a specified target processor.\r
418\r
419 This function returns after the IPI has been accepted by the target processor. \r
420\r
421 @param ApicId Specify the local APIC ID of the target processor.\r
422**/\r
423VOID\r
424EFIAPI\r
425SendSmiIpi (\r
426 IN UINT32 ApicId\r
427 )\r
428{\r
429 LOCAL_APIC_ICR_LOW IcrLow;\r
430\r
431 IcrLow.Uint32 = 0;\r
432 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
433 IcrLow.Bits.Level = 1;\r
434 SendIpi (IcrLow.Uint32, ApicId);\r
435}\r
436\r
437/**\r
438 Send a SMI IPI to all processors excluding self.\r
439\r
440 This function returns after the IPI has been accepted by the target processors. \r
441**/\r
442VOID\r
443EFIAPI\r
444SendSmiIpiAllExcludingSelf (\r
445 VOID\r
446 )\r
447{\r
448 LOCAL_APIC_ICR_LOW IcrLow;\r
449\r
450 IcrLow.Uint32 = 0;\r
451 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
452 IcrLow.Bits.Level = 1;\r
453 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
454 SendIpi (IcrLow.Uint32, 0);\r
455}\r
456\r
457/**\r
458 Send an INIT IPI to a specified target processor.\r
459\r
460 This function returns after the IPI has been accepted by the target processor. \r
461\r
462 @param ApicId Specify the local APIC ID of the target processor.\r
463**/\r
464VOID\r
465EFIAPI\r
466SendInitIpi (\r
467 IN UINT32 ApicId\r
468 )\r
469{\r
470 LOCAL_APIC_ICR_LOW IcrLow;\r
471\r
472 IcrLow.Uint32 = 0;\r
473 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
474 IcrLow.Bits.Level = 1;\r
475 SendIpi (IcrLow.Uint32, ApicId);\r
476}\r
477\r
478/**\r
479 Send an INIT IPI to all processors excluding self.\r
480\r
481 This function returns after the IPI has been accepted by the target processors. \r
482**/\r
483VOID\r
484EFIAPI\r
485SendInitIpiAllExcludingSelf (\r
486 VOID\r
487 )\r
488{\r
489 LOCAL_APIC_ICR_LOW IcrLow;\r
490\r
491 IcrLow.Uint32 = 0;\r
492 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
493 IcrLow.Bits.Level = 1;\r
494 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
495 SendIpi (IcrLow.Uint32, 0);\r
496}\r
497\r
498/**\r
499 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
500\r
501 This function returns after the IPI has been accepted by the target processor. \r
502\r
503 if StartupRoutine >= 1M, then ASSERT.\r
504 if StartupRoutine is not multiple of 4K, then ASSERT.\r
505\r
506 @param ApicId Specify the local APIC ID of the target processor.\r
507 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
508 address and 4K aligned.\r
509**/\r
510VOID\r
511EFIAPI\r
512SendInitSipiSipi (\r
513 IN UINT32 ApicId,\r
514 IN UINT32 StartupRoutine\r
515 )\r
516{\r
517 LOCAL_APIC_ICR_LOW IcrLow;\r
518\r
519 ASSERT (StartupRoutine < 0x100000);\r
520 ASSERT ((StartupRoutine & 0xfff) == 0);\r
521\r
522 SendInitIpi (ApicId);\r
cf1eb6e6 523 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
bf73cc4b 524 IcrLow.Uint32 = 0;\r
525 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
526 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
527 IcrLow.Bits.Level = 1;\r
528 SendIpi (IcrLow.Uint32, ApicId);\r
529 MicroSecondDelay (200);\r
530 SendIpi (IcrLow.Uint32, ApicId);\r
531}\r
532\r
533/**\r
534 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
535\r
536 This function returns after the IPI has been accepted by the target processors. \r
537\r
538 if StartupRoutine >= 1M, then ASSERT.\r
539 if StartupRoutine is not multiple of 4K, then ASSERT.\r
540\r
541 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
542 address and 4K aligned.\r
543**/\r
544VOID\r
545EFIAPI\r
546SendInitSipiSipiAllExcludingSelf (\r
547 IN UINT32 StartupRoutine\r
548 )\r
549{\r
550 LOCAL_APIC_ICR_LOW IcrLow;\r
551\r
552 ASSERT (StartupRoutine < 0x100000);\r
553 ASSERT ((StartupRoutine & 0xfff) == 0);\r
554\r
555 SendInitIpiAllExcludingSelf ();\r
cf1eb6e6 556 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
bf73cc4b 557 IcrLow.Uint32 = 0;\r
558 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
559 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
560 IcrLow.Bits.Level = 1;\r
561 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
562 SendIpi (IcrLow.Uint32, 0);\r
563 MicroSecondDelay (200);\r
564 SendIpi (IcrLow.Uint32, 0);\r
565}\r
566\r
14e4ca25
MK
567/**\r
568 Initialize the state of the SoftwareEnable bit in the Local APIC\r
569 Spurious Interrupt Vector register.\r
570\r
571 @param Enable If TRUE, then set SoftwareEnable to 1\r
572 If FALSE, then set SoftwareEnable to 0.\r
573\r
574**/\r
575VOID\r
576EFIAPI\r
577InitializeLocalApicSoftwareEnable (\r
578 IN BOOLEAN Enable\r
579 )\r
580{\r
581 LOCAL_APIC_SVR Svr;\r
582\r
583 //\r
584 // Set local APIC software-enabled bit.\r
585 //\r
586 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
587 if (Enable) {\r
588 if (Svr.Bits.SoftwareEnable == 0) {\r
589 Svr.Bits.SoftwareEnable = 1;\r
590 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
591 }\r
592 } else {\r
593 if (Svr.Bits.SoftwareEnable == 1) {\r
594 Svr.Bits.SoftwareEnable = 0;\r
595 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
596 }\r
597 }\r
598}\r
599\r
bf73cc4b 600/**\r
601 Programming Virtual Wire Mode.\r
602\r
603 This function programs the local APIC for virtual wire mode following\r
604 the example described in chapter A.3 of the MP 1.4 spec.\r
605\r
606 IOxAPIC is not involved in this type of virtual wire mode.\r
607**/\r
608VOID\r
609EFIAPI\r
610ProgramVirtualWireMode (\r
611 VOID\r
612 )\r
613{\r
614 LOCAL_APIC_SVR Svr;\r
615 LOCAL_APIC_LVT_LINT Lint;\r
616\r
617 //\r
618 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
619 //\r
620 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
621 Svr.Bits.SpuriousVector = 0xf;\r
622 Svr.Bits.SoftwareEnable = 1;\r
623 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
624\r
625 //\r
626 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
627 //\r
ae40aef1 628 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
bf73cc4b 629 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
630 Lint.Bits.InputPinPolarity = 0;\r
631 Lint.Bits.TriggerMode = 0;\r
632 Lint.Bits.Mask = 0;\r
ae40aef1 633 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r
bf73cc4b 634\r
635 //\r
636 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
637 //\r
ae40aef1 638 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
bf73cc4b 639 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
640 Lint.Bits.InputPinPolarity = 0;\r
641 Lint.Bits.TriggerMode = 0;\r
642 Lint.Bits.Mask = 0;\r
ae40aef1 643 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
bf73cc4b 644}\r
645\r
b1b8c631 646/**\r
647 Disable LINT0 & LINT1 interrupts.\r
648\r
649 This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
650**/\r
651VOID\r
652EFIAPI\r
653DisableLvtInterrupts (\r
654 VOID\r
655 )\r
656{\r
657 LOCAL_APIC_LVT_LINT LvtLint;\r
658\r
659 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
660 LvtLint.Bits.Mask = 1;\r
661 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r
662\r
663 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
664 LvtLint.Bits.Mask = 1;\r
665 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r
666}\r
667\r
bf73cc4b 668/**\r
669 Read the initial count value from the init-count register.\r
670\r
671 @return The initial count value read from the init-count register.\r
672**/\r
673UINT32\r
674EFIAPI\r
675GetApicTimerInitCount (\r
676 VOID\r
677 )\r
678{\r
679 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r
680}\r
681\r
682/**\r
683 Read the current count value from the current-count register.\r
684\r
685 @return The current count value read from the current-count register.\r
686**/\r
687UINT32\r
688EFIAPI\r
689GetApicTimerCurrentCount (\r
690 VOID\r
691 )\r
692{\r
693 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r
694}\r
695\r
696/**\r
697 Initialize the local APIC timer.\r
698\r
699 The local APIC timer is initialized and enabled.\r
700\r
701 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
702 If it is 0, then use the current divide value in the DCR.\r
703 @param InitCount The initial count value.\r
704 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
705 @param Vector The timer interrupt vector number.\r
706**/\r
707VOID\r
708EFIAPI\r
709InitializeApicTimer (\r
710 IN UINTN DivideValue,\r
711 IN UINT32 InitCount,\r
712 IN BOOLEAN PeriodicMode,\r
713 IN UINT8 Vector\r
714 )\r
715{\r
bf73cc4b 716 LOCAL_APIC_DCR Dcr;\r
717 LOCAL_APIC_LVT_TIMER LvtTimer;\r
718 UINT32 Divisor;\r
719\r
720 //\r
721 // Ensure local APIC is in software-enabled state.\r
722 //\r
14e4ca25 723 InitializeLocalApicSoftwareEnable (TRUE);\r
bf73cc4b 724\r
725 //\r
726 // Program init-count register.\r
727 //\r
728 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r
729\r
730 if (DivideValue != 0) {\r
731 ASSERT (DivideValue <= 128);\r
732 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
733 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
734\r
735 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
736 Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
737 Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
738 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r
739 }\r
740\r
741 //\r
742 // Enable APIC timer interrupt with specified timer mode.\r
743 //\r
744 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
745 if (PeriodicMode) {\r
746 LvtTimer.Bits.TimerMode = 1;\r
747 } else {\r
748 LvtTimer.Bits.TimerMode = 0;\r
749 }\r
750 LvtTimer.Bits.Mask = 0;\r
751 LvtTimer.Bits.Vector = Vector;\r
752 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
753}\r
754\r
ae40aef1 755/**\r
756 Get the state of the local APIC timer.\r
757\r
6d72ff7d
HW
758 This function will ASSERT if the local APIC is not software enabled.\r
759\r
ae40aef1 760 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
761 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
762 @param Vector Return the timer interrupt vector number.\r
763**/\r
764VOID\r
765EFIAPI\r
766GetApicTimerState (\r
767 OUT UINTN *DivideValue OPTIONAL,\r
768 OUT BOOLEAN *PeriodicMode OPTIONAL,\r
769 OUT UINT8 *Vector OPTIONAL\r
770 )\r
771{\r
772 UINT32 Divisor;\r
773 LOCAL_APIC_DCR Dcr;\r
774 LOCAL_APIC_LVT_TIMER LvtTimer;\r
775\r
6d72ff7d
HW
776 //\r
777 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
778 // Vector Register.\r
779 // This bit will be 1, if local APIC is software enabled.\r
780 //\r
781 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
782\r
ae40aef1 783 if (DivideValue != NULL) {\r
784 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
785 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
786 Divisor = (Divisor + 1) & 0x7;\r
787 *DivideValue = ((UINTN)1) << Divisor;\r
788 }\r
789\r
790 if (PeriodicMode != NULL || Vector != NULL) {\r
791 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
792 if (PeriodicMode != NULL) {\r
793 if (LvtTimer.Bits.TimerMode == 1) {\r
794 *PeriodicMode = TRUE;\r
795 } else {\r
796 *PeriodicMode = FALSE;\r
797 }\r
798 }\r
799 if (Vector != NULL) {\r
800 *Vector = (UINT8) LvtTimer.Bits.Vector;\r
801 }\r
802 }\r
803}\r
804\r
bf73cc4b 805/**\r
806 Enable the local APIC timer interrupt.\r
807**/\r
808VOID\r
809EFIAPI\r
810EnableApicTimerInterrupt (\r
811 VOID\r
812 )\r
813{\r
814 LOCAL_APIC_LVT_TIMER LvtTimer;\r
815\r
816 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
817 LvtTimer.Bits.Mask = 0;\r
818 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
819}\r
820\r
821/**\r
822 Disable the local APIC timer interrupt.\r
823**/\r
824VOID\r
825EFIAPI\r
826DisableApicTimerInterrupt (\r
827 VOID\r
828 )\r
829{\r
830 LOCAL_APIC_LVT_TIMER LvtTimer;\r
831\r
832 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
833 LvtTimer.Bits.Mask = 1;\r
834 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
835}\r
836\r
837/**\r
838 Get the local APIC timer interrupt state.\r
839\r
840 @retval TRUE The local APIC timer interrupt is enabled.\r
841 @retval FALSE The local APIC timer interrupt is disabled.\r
842**/\r
843BOOLEAN\r
844EFIAPI\r
845GetApicTimerInterruptState (\r
846 VOID\r
847 )\r
848{\r
849 LOCAL_APIC_LVT_TIMER LvtTimer;\r
850\r
851 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
852 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
853}\r
854\r
855/**\r
856 Send EOI to the local APIC.\r
857**/\r
858VOID\r
859EFIAPI\r
860SendApicEoi (\r
861 VOID\r
862 )\r
863{\r
864 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
865}\r
866\r
5f867ad0 867/**\r
868 Get the 32-bit address that a device should use to send a Message Signaled \r
869 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
870\r
871 @return 32-bit address used to send an MSI to the Local APIC.\r
872**/\r
873UINT32\r
874EFIAPI \r
875GetApicMsiAddress (\r
876 VOID\r
877 )\r
878{\r
879 LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
880\r
881 //\r
882 // Return address for an MSI interrupt to be delivered only to the APIC ID \r
883 // of the currently executing processor.\r
884 //\r
885 MsiAddress.Uint32 = 0;\r
886 MsiAddress.Bits.BaseAddress = 0xFEE;\r
887 MsiAddress.Bits.DestinationId = GetApicId ();\r
888 return MsiAddress.Uint32;\r
889}\r
890 \r
891/**\r
892 Get the 64-bit data value that a device should use to send a Message Signaled \r
893 Interrupt (MSI) to the Local APIC of the currently executing processor.\r
894\r
895 If Vector is not in range 0x10..0xFE, then ASSERT().\r
896 If DeliveryMode is not supported, then ASSERT().\r
897 \r
898 @param Vector The 8-bit interrupt vector associated with the MSI. \r
899 Must be in the range 0x10..0xFE\r
900 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
901 is handled. The only supported values are:\r
902 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
903 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
904 2: LOCAL_APIC_DELIVERY_MODE_SMI\r
905 4: LOCAL_APIC_DELIVERY_MODE_NMI\r
906 5: LOCAL_APIC_DELIVERY_MODE_INIT\r
907 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
908 \r
909 @param LevelTriggered TRUE specifies a level triggered interrupt. \r
910 FALSE specifies an edge triggered interrupt.\r
911 @param AssertionLevel Ignored if LevelTriggered is FALSE.\r
912 TRUE specifies a level triggered interrupt that active \r
913 when the interrupt line is asserted.\r
914 FALSE specifies a level triggered interrupt that active \r
915 when the interrupt line is deasserted.\r
916\r
917 @return 64-bit data value used to send an MSI to the Local APIC.\r
918**/\r
919UINT64\r
920EFIAPI \r
921GetApicMsiValue (\r
922 IN UINT8 Vector,\r
923 IN UINTN DeliveryMode,\r
924 IN BOOLEAN LevelTriggered,\r
925 IN BOOLEAN AssertionLevel\r
926 )\r
927{\r
928 LOCAL_APIC_MSI_DATA MsiData;\r
929\r
930 ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
931 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
932 \r
933 MsiData.Uint64 = 0;\r
934 MsiData.Bits.Vector = Vector;\r
935 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
936 if (LevelTriggered) {\r
937 MsiData.Bits.TriggerMode = 1;\r
938 if (AssertionLevel) {\r
939 MsiData.Bits.Level = 1;\r
940 }\r
941 }\r
942 return MsiData.Uint64;\r
943}\r
73152f19
LD
944\r
945/**\r
946 Get Package ID/Core ID/Thread ID of a processor.\r
947\r
948 The algorithm assumes the target system has symmetry across physical\r
949 package boundaries with respect to the number of logical processors\r
950 per package, number of cores per package.\r
951\r
952 @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
953 @param[out] Package Returns the processor package ID.\r
954 @param[out] Core Returns the processor core ID.\r
955 @param[out] Thread Returns the processor thread ID.\r
956**/\r
957VOID\r
958GetProcessorLocation(\r
959 IN UINT32 InitialApicId,\r
960 OUT UINT32 *Package OPTIONAL,\r
961 OUT UINT32 *Core OPTIONAL,\r
962 OUT UINT32 *Thread OPTIONAL\r
963 )\r
964{\r
965 BOOLEAN TopologyLeafSupported;\r
966 UINTN ThreadBits;\r
967 UINTN CoreBits;\r
968 CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
969 CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
970 CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
971 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
972 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
973 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
974 UINT32 MaxCpuIdIndex;\r
975 UINT32 SubIndex;\r
976 UINTN LevelType;\r
977 UINT32 MaxLogicProcessorsPerPackage;\r
978 UINT32 MaxCoresPerPackage;\r
979\r
980 //\r
981 // Check if the processor is capable of supporting more than one logical processor.\r
982 //\r
983 AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
984 if (VersionInfoEdx.Bits.HTT == 0) {\r
985 if (Thread != NULL) {\r
986 *Thread = 0;\r
987 }\r
988 if (Core != NULL) {\r
989 *Core = 0;\r
990 }\r
991 if (Package != NULL) {\r
992 *Package = 0;\r
993 }\r
994 return;\r
995 }\r
996\r
997 ThreadBits = 0;\r
998 CoreBits = 0;\r
999\r
1000 //\r
1001 // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
1002 //\r
1003 TopologyLeafSupported = FALSE;\r
1004\r
1005 //\r
1006 // Get the max index of basic CPUID\r
1007 //\r
1008 AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
1009\r
1010 //\r
1011 // If the extended topology enumeration leaf is available, it\r
1012 // is the preferred mechanism for enumerating topology.\r
1013 //\r
1014 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
1015 AsmCpuidEx(\r
1016 CPUID_EXTENDED_TOPOLOGY,\r
1017 0,\r
1018 &ExtendedTopologyEax.Uint32,\r
1019 &ExtendedTopologyEbx.Uint32,\r
1020 &ExtendedTopologyEcx.Uint32,\r
1021 NULL\r
1022 );\r
1023 //\r
1024 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
1025 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
1026 // supported on that processor.\r
1027 //\r
1028 if (ExtendedTopologyEbx.Uint32 != 0) {\r
1029 TopologyLeafSupported = TRUE;\r
1030\r
1031 //\r
1032 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
1033 // the SMT sub-field of x2APIC ID.\r
1034 //\r
1035 LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
1036 ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
1037 ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
1038\r
1039 //\r
1040 // Software must not assume any "level type" encoding\r
1041 // value to be related to any sub-leaf index, except sub-leaf 0.\r
1042 //\r
1043 SubIndex = 1;\r
1044 do {\r
1045 AsmCpuidEx(\r
1046 CPUID_EXTENDED_TOPOLOGY,\r
1047 SubIndex,\r
1048 &ExtendedTopologyEax.Uint32,\r
1049 NULL,\r
1050 &ExtendedTopologyEcx.Uint32,\r
1051 NULL\r
1052 );\r
1053 LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
1054 if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
1055 CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
1056 break;\r
1057 }\r
1058 SubIndex++;\r
1059 } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
1060 }\r
1061 }\r
1062\r
1063 if (!TopologyLeafSupported) {\r
1064 AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
1065 MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
1066 if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
1067 AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
1068 MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
1069 }\r
1070 else {\r
1071 //\r
1072 // Must be a single-core processor.\r
1073 //\r
1074 MaxCoresPerPackage = 1;\r
1075 }\r
1076\r
1077 ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
1078 CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }\r
1079\r
1080 if (Thread != NULL) {\r
1081 *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
1082 }\r
1083 if (Core != NULL) {\r
1084 *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
1085 }\r
1086 if (Package != NULL) {\r
1087 *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
1088 }\r
1089}\r