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bf73cc4b | 1 | /** @file\r |
2 | Local APIC Library.\r | |
3 | \r | |
4 | This local APIC library instance supports xAPIC mode only.\r | |
5 | \r | |
7367cc6c | 6 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
061ead7a LD |
7 | Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r |
8 | \r | |
bf73cc4b | 9 | This program and the accompanying materials\r |
10 | are licensed and made available under the terms and conditions of the BSD License\r | |
11 | which accompanies this distribution. The full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
28a7ddf0 | 19 | #include <Register/Cpuid.h>\r |
061ead7a | 20 | #include <Register/Amd/Cpuid.h>\r |
a742e186 | 21 | #include <Register/Msr.h>\r |
bf73cc4b | 22 | #include <Register/LocalApic.h>\r |
23 | \r | |
24 | #include <Library/BaseLib.h>\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/LocalApicLib.h>\r | |
27 | #include <Library/IoLib.h>\r | |
28 | #include <Library/TimerLib.h>\r | |
59d67246 | 29 | #include <Library/PcdLib.h>\r |
bf73cc4b | 30 | \r |
31 | //\r | |
32 | // Library internal functions\r | |
33 | //\r | |
34 | \r | |
061ead7a LD |
35 | /**\r |
36 | Determine if the standard CPU signature is "AuthenticAMD".\r | |
37 | \r | |
38 | @retval TRUE The CPU signature matches.\r | |
39 | @retval FALSE The CPU signature does not match.\r | |
40 | \r | |
41 | **/\r | |
42 | BOOLEAN\r | |
43 | StandardSignatureIsAuthenticAMD (\r | |
44 | VOID\r | |
45 | )\r | |
46 | {\r | |
47 | UINT32 RegEbx;\r | |
48 | UINT32 RegEcx;\r | |
49 | UINT32 RegEdx;\r | |
50 | \r | |
ae66c6f1 | 51 | AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r |
061ead7a LD |
52 | return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&\r |
53 | RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&\r | |
54 | RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);\r | |
55 | }\r | |
56 | \r | |
59d67246 MK |
57 | /**\r |
58 | Determine if the CPU supports the Local APIC Base Address MSR.\r | |
59 | \r | |
60 | @retval TRUE The CPU supports the Local APIC Base Address MSR.\r | |
61 | @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r | |
62 | \r | |
63 | **/\r | |
64 | BOOLEAN\r | |
65 | LocalApicBaseAddressMsrSupported (\r | |
66 | VOID\r | |
67 | )\r | |
68 | {\r | |
69 | UINT32 RegEax;\r | |
70 | UINTN FamilyId;\r | |
7367cc6c | 71 | \r |
59d67246 MK |
72 | AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r |
73 | FamilyId = BitFieldRead32 (RegEax, 8, 11);\r | |
74 | if (FamilyId == 0x04 || FamilyId == 0x05) {\r | |
75 | //\r | |
7367cc6c | 76 | // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r |
59d67246 MK |
77 | // Local APIC Base Address MSR\r |
78 | //\r | |
79 | return FALSE;\r | |
80 | }\r | |
81 | return TRUE;\r | |
82 | }\r | |
83 | \r | |
a66e0c7d | 84 | /**\r |
85 | Retrieve the base address of local APIC.\r | |
86 | \r | |
87 | @return The base address of local APIC.\r | |
88 | \r | |
89 | **/\r | |
90 | UINTN\r | |
91 | EFIAPI\r | |
92 | GetLocalApicBaseAddress (\r | |
93 | VOID\r | |
94 | )\r | |
95 | {\r | |
a742e186 | 96 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
59d67246 MK |
97 | \r |
98 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
99 | //\r | |
100 | // If CPU does not support Local APIC Base Address MSR, then retrieve\r | |
101 | // Local APIC Base Address from PCD\r | |
102 | //\r | |
103 | return PcdGet32 (PcdCpuLocalApicBaseAddress);\r | |
104 | }\r | |
105 | \r | |
a742e186 | 106 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
7367cc6c | 107 | \r |
a742e186 JF |
108 | return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r |
109 | (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r | |
a66e0c7d | 110 | }\r |
111 | \r | |
112 | /**\r | |
113 | Set the base address of local APIC.\r | |
114 | \r | |
115 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
116 | \r | |
117 | @param[in] BaseAddress Local APIC base address to be set.\r | |
118 | \r | |
119 | **/\r | |
120 | VOID\r | |
121 | EFIAPI\r | |
122 | SetLocalApicBaseAddress (\r | |
123 | IN UINTN BaseAddress\r | |
124 | )\r | |
125 | {\r | |
a742e186 | 126 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
a66e0c7d | 127 | \r |
128 | ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r | |
129 | \r | |
59d67246 MK |
130 | if (!LocalApicBaseAddressMsrSupported ()) {\r |
131 | //\r | |
132 | // Ignore set request if the CPU does not support APIC Base Address MSR\r | |
133 | //\r | |
134 | return;\r | |
135 | }\r | |
136 | \r | |
a742e186 | 137 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
a66e0c7d | 138 | \r |
a742e186 JF |
139 | ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);\r |
140 | ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r | |
a66e0c7d | 141 | \r |
a742e186 | 142 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r |
a66e0c7d | 143 | }\r |
144 | \r | |
bf73cc4b | 145 | /**\r |
146 | Read from a local APIC register.\r | |
147 | \r | |
148 | This function reads from a local APIC register either in xAPIC or x2APIC mode.\r | |
149 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
150 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
151 | 32-bit read.\r | |
152 | \r | |
153 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
154 | It must be 16-byte aligned.\r | |
155 | \r | |
156 | @return 32-bit Value read from the register.\r | |
157 | **/\r | |
158 | UINT32\r | |
159 | EFIAPI\r | |
160 | ReadLocalApicReg (\r | |
161 | IN UINTN MmioOffset\r | |
162 | )\r | |
163 | {\r | |
164 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
165 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
166 | \r | |
a66e0c7d | 167 | return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r |
bf73cc4b | 168 | }\r |
169 | \r | |
170 | /**\r | |
171 | Write to a local APIC register.\r | |
172 | \r | |
173 | This function writes to a local APIC register either in xAPIC or x2APIC mode.\r | |
174 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
175 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
176 | 32-bit write.\r | |
177 | \r | |
178 | if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r | |
179 | \r | |
180 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
181 | It must be 16-byte aligned.\r | |
182 | @param Value Value to be written to the register.\r | |
183 | **/\r | |
184 | VOID\r | |
185 | EFIAPI\r | |
186 | WriteLocalApicReg (\r | |
187 | IN UINTN MmioOffset,\r | |
188 | IN UINT32 Value\r | |
189 | )\r | |
190 | {\r | |
191 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
192 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
193 | \r | |
a66e0c7d | 194 | MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r |
bf73cc4b | 195 | }\r |
196 | \r | |
197 | /**\r | |
198 | Send an IPI by writing to ICR.\r | |
199 | \r | |
7367cc6c | 200 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 201 | \r |
202 | @param IcrLow 32-bit value to be written to the low half of ICR.\r | |
203 | @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r | |
204 | **/\r | |
205 | VOID\r | |
206 | SendIpi (\r | |
207 | IN UINT32 IcrLow,\r | |
208 | IN UINT32 ApicId\r | |
209 | )\r | |
210 | {\r | |
211 | LOCAL_APIC_ICR_LOW IcrLowReg;\r | |
9c71e1e0 JF |
212 | UINT32 IcrHigh;\r |
213 | BOOLEAN InterruptState;\r | |
bf73cc4b | 214 | \r |
215 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
216 | ASSERT (ApicId <= 0xff);\r | |
217 | \r | |
9c71e1e0 JF |
218 | InterruptState = SaveAndDisableInterrupts ();\r |
219 | \r | |
220 | //\r | |
221 | // Save existing contents of ICR high 32 bits\r | |
222 | //\r | |
223 | IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);\r | |
224 | \r | |
225 | //\r | |
226 | // Wait for DeliveryStatus clear in case a previous IPI\r | |
227 | // is still being sent\r | |
228 | //\r | |
229 | do {\r | |
230 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
231 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
232 | \r | |
bf73cc4b | 233 | //\r |
234 | // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r | |
235 | //\r | |
236 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r | |
237 | WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r | |
9c71e1e0 JF |
238 | \r |
239 | //\r | |
240 | // Wait for DeliveryStatus clear again\r | |
241 | //\r | |
bf73cc4b | 242 | do {\r |
243 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
244 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
9c71e1e0 JF |
245 | \r |
246 | //\r | |
247 | // And restore old contents of ICR high\r | |
248 | //\r | |
249 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r | |
250 | \r | |
251 | SetInterruptState (InterruptState);\r | |
252 | \r | |
bf73cc4b | 253 | }\r |
254 | \r | |
255 | //\r | |
256 | // Library API implementation functions\r | |
257 | //\r | |
258 | \r | |
259 | /**\r | |
260 | Get the current local APIC mode.\r | |
261 | \r | |
262 | If local APIC is disabled, then ASSERT.\r | |
263 | \r | |
264 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
265 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
266 | **/\r | |
267 | UINTN\r | |
268 | EFIAPI\r | |
269 | GetApicMode (\r | |
270 | VOID\r | |
271 | )\r | |
272 | {\r | |
273 | DEBUG_CODE (\r | |
274 | {\r | |
a742e186 | 275 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
bf73cc4b | 276 | \r |
bf73cc4b | 277 | //\r |
7367cc6c | 278 | // Check to see if the CPU supports the APIC Base Address MSR\r |
bf73cc4b | 279 | //\r |
59d67246 | 280 | if (LocalApicBaseAddressMsrSupported ()) {\r |
a742e186 | 281 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
59d67246 MK |
282 | //\r |
283 | // Local APIC should have been enabled\r | |
284 | //\r | |
a742e186 JF |
285 | ASSERT (ApicBaseMsr.Bits.EN != 0);\r |
286 | ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r | |
59d67246 | 287 | }\r |
bf73cc4b | 288 | }\r |
289 | );\r | |
290 | return LOCAL_APIC_MODE_XAPIC;\r | |
291 | }\r | |
292 | \r | |
293 | /**\r | |
294 | Set the current local APIC mode.\r | |
295 | \r | |
296 | If the specified local APIC mode is not valid, then ASSERT.\r | |
297 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
298 | \r | |
299 | @param ApicMode APIC mode to be set.\r | |
9c71e1e0 JF |
300 | \r |
301 | @note This API must not be called from an interrupt handler or SMI handler.\r | |
302 | It may result in unpredictable behavior.\r | |
bf73cc4b | 303 | **/\r |
304 | VOID\r | |
305 | EFIAPI\r | |
306 | SetApicMode (\r | |
307 | IN UINTN ApicMode\r | |
308 | )\r | |
309 | {\r | |
310 | ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r | |
311 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
312 | }\r | |
313 | \r | |
314 | /**\r | |
315 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
316 | \r | |
6e3e4d70 | 317 | In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r |
7367cc6c | 318 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r |
bf73cc4b | 319 | the 32-bit local APIC ID is returned as initial APIC ID.\r |
320 | \r | |
321 | @return 32-bit initial local APIC ID of the executing processor.\r | |
322 | **/\r | |
323 | UINT32\r | |
324 | EFIAPI\r | |
325 | GetInitialApicId (\r | |
326 | VOID\r | |
327 | )\r | |
328 | {\r | |
6e3e4d70 JF |
329 | UINT32 ApicId;\r |
330 | UINT32 MaxCpuIdIndex;\r | |
bf73cc4b | 331 | UINT32 RegEbx;\r |
332 | \r | |
333 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
334 | \r | |
6e3e4d70 JF |
335 | //\r |
336 | // Get the max index of basic CPUID\r | |
337 | //\r | |
338 | AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r | |
339 | \r | |
340 | //\r | |
7367cc6c | 341 | // If CPUID Leaf B is supported,\r |
4af3ae14 | 342 | // And CPUID.0BH:EBX[15:0] reports a non-zero value,\r |
6e3e4d70 JF |
343 | // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r |
344 | // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r | |
345 | //\r | |
346 | if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
4af3ae14 LE |
347 | AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);\r |
348 | if ((RegEbx & (BIT16 - 1)) != 0) {\r | |
349 | return ApicId;\r | |
350 | }\r | |
6e3e4d70 JF |
351 | }\r |
352 | \r | |
bf73cc4b | 353 | AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r |
354 | return RegEbx >> 24;\r | |
355 | }\r | |
356 | \r | |
357 | /**\r | |
358 | Get the local APIC ID of the executing processor.\r | |
359 | \r | |
360 | @return 32-bit local APIC ID of the executing processor.\r | |
361 | **/\r | |
362 | UINT32\r | |
363 | EFIAPI\r | |
364 | GetApicId (\r | |
365 | VOID\r | |
366 | )\r | |
367 | {\r | |
368 | UINT32 ApicId;\r | |
369 | \r | |
370 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
7367cc6c | 371 | \r |
6e3e4d70 JF |
372 | if ((ApicId = GetInitialApicId ()) < 0x100) {\r |
373 | //\r | |
374 | // If the initial local APIC ID is less 0x100, read APIC ID from\r | |
375 | // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.\r | |
376 | //\r | |
377 | ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r | |
378 | ApicId >>= 24;\r | |
379 | }\r | |
bf73cc4b | 380 | return ApicId;\r |
381 | }\r | |
382 | \r | |
ae40aef1 | 383 | /**\r |
384 | Get the value of the local APIC version register.\r | |
385 | \r | |
386 | @return the value of the local APIC version register.\r | |
387 | **/\r | |
388 | UINT32\r | |
389 | EFIAPI\r | |
390 | GetApicVersion (\r | |
391 | VOID\r | |
392 | )\r | |
393 | {\r | |
394 | return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r | |
395 | }\r | |
396 | \r | |
397 | /**\r | |
398 | Send a Fixed IPI to a specified target processor.\r | |
399 | \r | |
7367cc6c | 400 | This function returns after the IPI has been accepted by the target processor.\r |
ae40aef1 | 401 | \r |
402 | @param ApicId The local APIC ID of the target processor.\r | |
403 | @param Vector The vector number of the interrupt being sent.\r | |
404 | **/\r | |
405 | VOID\r | |
406 | EFIAPI\r | |
407 | SendFixedIpi (\r | |
408 | IN UINT32 ApicId,\r | |
409 | IN UINT8 Vector\r | |
410 | )\r | |
411 | {\r | |
412 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
413 | \r | |
414 | IcrLow.Uint32 = 0;\r | |
415 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
416 | IcrLow.Bits.Level = 1;\r | |
417 | IcrLow.Bits.Vector = Vector;\r | |
418 | SendIpi (IcrLow.Uint32, ApicId);\r | |
419 | }\r | |
420 | \r | |
421 | /**\r | |
422 | Send a Fixed IPI to all processors excluding self.\r | |
423 | \r | |
7367cc6c | 424 | This function returns after the IPI has been accepted by the target processors.\r |
ae40aef1 | 425 | \r |
426 | @param Vector The vector number of the interrupt being sent.\r | |
427 | **/\r | |
428 | VOID\r | |
429 | EFIAPI\r | |
430 | SendFixedIpiAllExcludingSelf (\r | |
431 | IN UINT8 Vector\r | |
432 | )\r | |
433 | {\r | |
434 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
435 | \r | |
436 | IcrLow.Uint32 = 0;\r | |
437 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
438 | IcrLow.Bits.Level = 1;\r | |
439 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
440 | IcrLow.Bits.Vector = Vector;\r | |
441 | SendIpi (IcrLow.Uint32, 0);\r | |
442 | }\r | |
443 | \r | |
bf73cc4b | 444 | /**\r |
445 | Send a SMI IPI to a specified target processor.\r | |
446 | \r | |
7367cc6c | 447 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 448 | \r |
449 | @param ApicId Specify the local APIC ID of the target processor.\r | |
450 | **/\r | |
451 | VOID\r | |
452 | EFIAPI\r | |
453 | SendSmiIpi (\r | |
454 | IN UINT32 ApicId\r | |
455 | )\r | |
456 | {\r | |
457 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
458 | \r | |
459 | IcrLow.Uint32 = 0;\r | |
460 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
461 | IcrLow.Bits.Level = 1;\r | |
462 | SendIpi (IcrLow.Uint32, ApicId);\r | |
463 | }\r | |
464 | \r | |
465 | /**\r | |
466 | Send a SMI IPI to all processors excluding self.\r | |
467 | \r | |
7367cc6c | 468 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 469 | **/\r |
470 | VOID\r | |
471 | EFIAPI\r | |
472 | SendSmiIpiAllExcludingSelf (\r | |
473 | VOID\r | |
474 | )\r | |
475 | {\r | |
476 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
477 | \r | |
478 | IcrLow.Uint32 = 0;\r | |
479 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
480 | IcrLow.Bits.Level = 1;\r | |
481 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
482 | SendIpi (IcrLow.Uint32, 0);\r | |
483 | }\r | |
484 | \r | |
485 | /**\r | |
486 | Send an INIT IPI to a specified target processor.\r | |
487 | \r | |
7367cc6c | 488 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 489 | \r |
490 | @param ApicId Specify the local APIC ID of the target processor.\r | |
491 | **/\r | |
492 | VOID\r | |
493 | EFIAPI\r | |
494 | SendInitIpi (\r | |
495 | IN UINT32 ApicId\r | |
496 | )\r | |
497 | {\r | |
498 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
499 | \r | |
500 | IcrLow.Uint32 = 0;\r | |
501 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
502 | IcrLow.Bits.Level = 1;\r | |
503 | SendIpi (IcrLow.Uint32, ApicId);\r | |
504 | }\r | |
505 | \r | |
506 | /**\r | |
507 | Send an INIT IPI to all processors excluding self.\r | |
508 | \r | |
7367cc6c | 509 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 510 | **/\r |
511 | VOID\r | |
512 | EFIAPI\r | |
513 | SendInitIpiAllExcludingSelf (\r | |
514 | VOID\r | |
515 | )\r | |
516 | {\r | |
517 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
518 | \r | |
519 | IcrLow.Uint32 = 0;\r | |
520 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
521 | IcrLow.Bits.Level = 1;\r | |
522 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
523 | SendIpi (IcrLow.Uint32, 0);\r | |
524 | }\r | |
525 | \r | |
526 | /**\r | |
527 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
528 | \r | |
7367cc6c | 529 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 530 | \r |
531 | if StartupRoutine >= 1M, then ASSERT.\r | |
532 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
533 | \r | |
534 | @param ApicId Specify the local APIC ID of the target processor.\r | |
535 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
536 | address and 4K aligned.\r | |
537 | **/\r | |
538 | VOID\r | |
539 | EFIAPI\r | |
540 | SendInitSipiSipi (\r | |
541 | IN UINT32 ApicId,\r | |
542 | IN UINT32 StartupRoutine\r | |
543 | )\r | |
544 | {\r | |
545 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
546 | \r | |
547 | ASSERT (StartupRoutine < 0x100000);\r | |
548 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
549 | \r | |
550 | SendInitIpi (ApicId);\r | |
cf1eb6e6 | 551 | MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r |
bf73cc4b | 552 | IcrLow.Uint32 = 0;\r |
553 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
554 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
555 | IcrLow.Bits.Level = 1;\r | |
556 | SendIpi (IcrLow.Uint32, ApicId);\r | |
bf252e29 ED |
557 | if (!StandardSignatureIsAuthenticAMD ()) {\r |
558 | MicroSecondDelay (200);\r | |
559 | SendIpi (IcrLow.Uint32, ApicId);\r | |
560 | }\r | |
bf73cc4b | 561 | }\r |
562 | \r | |
563 | /**\r | |
564 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
565 | \r | |
7367cc6c | 566 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 567 | \r |
568 | if StartupRoutine >= 1M, then ASSERT.\r | |
569 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
570 | \r | |
571 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
572 | address and 4K aligned.\r | |
573 | **/\r | |
574 | VOID\r | |
575 | EFIAPI\r | |
576 | SendInitSipiSipiAllExcludingSelf (\r | |
577 | IN UINT32 StartupRoutine\r | |
578 | )\r | |
579 | {\r | |
580 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
581 | \r | |
582 | ASSERT (StartupRoutine < 0x100000);\r | |
583 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
584 | \r | |
585 | SendInitIpiAllExcludingSelf ();\r | |
cf1eb6e6 | 586 | MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r |
bf73cc4b | 587 | IcrLow.Uint32 = 0;\r |
588 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
589 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
590 | IcrLow.Bits.Level = 1;\r | |
591 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
592 | SendIpi (IcrLow.Uint32, 0);\r | |
bf252e29 ED |
593 | if (!StandardSignatureIsAuthenticAMD ()) {\r |
594 | MicroSecondDelay (200);\r | |
595 | SendIpi (IcrLow.Uint32, 0);\r | |
596 | }\r | |
bf73cc4b | 597 | }\r |
598 | \r | |
14e4ca25 MK |
599 | /**\r |
600 | Initialize the state of the SoftwareEnable bit in the Local APIC\r | |
601 | Spurious Interrupt Vector register.\r | |
602 | \r | |
603 | @param Enable If TRUE, then set SoftwareEnable to 1\r | |
604 | If FALSE, then set SoftwareEnable to 0.\r | |
605 | \r | |
606 | **/\r | |
607 | VOID\r | |
608 | EFIAPI\r | |
609 | InitializeLocalApicSoftwareEnable (\r | |
610 | IN BOOLEAN Enable\r | |
611 | )\r | |
612 | {\r | |
613 | LOCAL_APIC_SVR Svr;\r | |
614 | \r | |
615 | //\r | |
616 | // Set local APIC software-enabled bit.\r | |
617 | //\r | |
618 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
619 | if (Enable) {\r | |
620 | if (Svr.Bits.SoftwareEnable == 0) {\r | |
621 | Svr.Bits.SoftwareEnable = 1;\r | |
622 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
623 | }\r | |
624 | } else {\r | |
625 | if (Svr.Bits.SoftwareEnable == 1) {\r | |
626 | Svr.Bits.SoftwareEnable = 0;\r | |
627 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
628 | }\r | |
629 | }\r | |
630 | }\r | |
631 | \r | |
bf73cc4b | 632 | /**\r |
633 | Programming Virtual Wire Mode.\r | |
634 | \r | |
635 | This function programs the local APIC for virtual wire mode following\r | |
636 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
637 | \r | |
638 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
639 | **/\r | |
640 | VOID\r | |
641 | EFIAPI\r | |
642 | ProgramVirtualWireMode (\r | |
643 | VOID\r | |
644 | )\r | |
645 | {\r | |
646 | LOCAL_APIC_SVR Svr;\r | |
647 | LOCAL_APIC_LVT_LINT Lint;\r | |
648 | \r | |
649 | //\r | |
650 | // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r | |
651 | //\r | |
652 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
653 | Svr.Bits.SpuriousVector = 0xf;\r | |
654 | Svr.Bits.SoftwareEnable = 1;\r | |
655 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
656 | \r | |
657 | //\r | |
658 | // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r | |
659 | //\r | |
ae40aef1 | 660 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r |
bf73cc4b | 661 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r |
662 | Lint.Bits.InputPinPolarity = 0;\r | |
663 | Lint.Bits.TriggerMode = 0;\r | |
664 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 665 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r |
bf73cc4b | 666 | \r |
667 | //\r | |
668 | // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r | |
669 | //\r | |
ae40aef1 | 670 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r |
bf73cc4b | 671 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r |
672 | Lint.Bits.InputPinPolarity = 0;\r | |
673 | Lint.Bits.TriggerMode = 0;\r | |
674 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 675 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r |
bf73cc4b | 676 | }\r |
677 | \r | |
b1b8c631 | 678 | /**\r |
679 | Disable LINT0 & LINT1 interrupts.\r | |
680 | \r | |
681 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
682 | **/\r | |
683 | VOID\r | |
684 | EFIAPI\r | |
685 | DisableLvtInterrupts (\r | |
686 | VOID\r | |
687 | )\r | |
688 | {\r | |
689 | LOCAL_APIC_LVT_LINT LvtLint;\r | |
690 | \r | |
691 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r | |
692 | LvtLint.Bits.Mask = 1;\r | |
693 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r | |
694 | \r | |
695 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r | |
696 | LvtLint.Bits.Mask = 1;\r | |
697 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r | |
698 | }\r | |
699 | \r | |
bf73cc4b | 700 | /**\r |
701 | Read the initial count value from the init-count register.\r | |
702 | \r | |
703 | @return The initial count value read from the init-count register.\r | |
704 | **/\r | |
705 | UINT32\r | |
706 | EFIAPI\r | |
707 | GetApicTimerInitCount (\r | |
708 | VOID\r | |
709 | )\r | |
710 | {\r | |
711 | return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r | |
712 | }\r | |
713 | \r | |
714 | /**\r | |
715 | Read the current count value from the current-count register.\r | |
716 | \r | |
717 | @return The current count value read from the current-count register.\r | |
718 | **/\r | |
719 | UINT32\r | |
720 | EFIAPI\r | |
721 | GetApicTimerCurrentCount (\r | |
722 | VOID\r | |
723 | )\r | |
724 | {\r | |
725 | return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r | |
726 | }\r | |
727 | \r | |
728 | /**\r | |
729 | Initialize the local APIC timer.\r | |
730 | \r | |
731 | The local APIC timer is initialized and enabled.\r | |
732 | \r | |
733 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
734 | If it is 0, then use the current divide value in the DCR.\r | |
735 | @param InitCount The initial count value.\r | |
736 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
737 | @param Vector The timer interrupt vector number.\r | |
738 | **/\r | |
739 | VOID\r | |
740 | EFIAPI\r | |
741 | InitializeApicTimer (\r | |
742 | IN UINTN DivideValue,\r | |
743 | IN UINT32 InitCount,\r | |
744 | IN BOOLEAN PeriodicMode,\r | |
745 | IN UINT8 Vector\r | |
746 | )\r | |
747 | {\r | |
bf73cc4b | 748 | LOCAL_APIC_DCR Dcr;\r |
749 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
750 | UINT32 Divisor;\r | |
751 | \r | |
752 | //\r | |
753 | // Ensure local APIC is in software-enabled state.\r | |
754 | //\r | |
14e4ca25 | 755 | InitializeLocalApicSoftwareEnable (TRUE);\r |
bf73cc4b | 756 | \r |
757 | //\r | |
758 | // Program init-count register.\r | |
759 | //\r | |
760 | WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r | |
761 | \r | |
762 | if (DivideValue != 0) {\r | |
763 | ASSERT (DivideValue <= 128);\r | |
764 | ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r | |
765 | Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r | |
766 | \r | |
767 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
768 | Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r | |
769 | Dcr.Bits.DivideValue2 = (Divisor >> 2);\r | |
7367cc6c | 770 | WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r |
bf73cc4b | 771 | }\r |
772 | \r | |
773 | //\r | |
774 | // Enable APIC timer interrupt with specified timer mode.\r | |
775 | //\r | |
776 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
777 | if (PeriodicMode) {\r | |
778 | LvtTimer.Bits.TimerMode = 1;\r | |
779 | } else {\r | |
780 | LvtTimer.Bits.TimerMode = 0;\r | |
781 | }\r | |
782 | LvtTimer.Bits.Mask = 0;\r | |
783 | LvtTimer.Bits.Vector = Vector;\r | |
784 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
785 | }\r | |
786 | \r | |
ae40aef1 | 787 | /**\r |
788 | Get the state of the local APIC timer.\r | |
789 | \r | |
6d72ff7d HW |
790 | This function will ASSERT if the local APIC is not software enabled.\r |
791 | \r | |
ae40aef1 | 792 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r |
793 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
794 | @param Vector Return the timer interrupt vector number.\r | |
795 | **/\r | |
796 | VOID\r | |
797 | EFIAPI\r | |
798 | GetApicTimerState (\r | |
799 | OUT UINTN *DivideValue OPTIONAL,\r | |
800 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
801 | OUT UINT8 *Vector OPTIONAL\r | |
802 | )\r | |
803 | {\r | |
804 | UINT32 Divisor;\r | |
805 | LOCAL_APIC_DCR Dcr;\r | |
806 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
807 | \r | |
6d72ff7d HW |
808 | //\r |
809 | // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r | |
810 | // Vector Register.\r | |
811 | // This bit will be 1, if local APIC is software enabled.\r | |
812 | //\r | |
813 | ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r | |
814 | \r | |
ae40aef1 | 815 | if (DivideValue != NULL) {\r |
816 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
817 | Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r | |
818 | Divisor = (Divisor + 1) & 0x7;\r | |
819 | *DivideValue = ((UINTN)1) << Divisor;\r | |
820 | }\r | |
821 | \r | |
822 | if (PeriodicMode != NULL || Vector != NULL) {\r | |
823 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
824 | if (PeriodicMode != NULL) {\r | |
825 | if (LvtTimer.Bits.TimerMode == 1) {\r | |
826 | *PeriodicMode = TRUE;\r | |
827 | } else {\r | |
828 | *PeriodicMode = FALSE;\r | |
829 | }\r | |
830 | }\r | |
831 | if (Vector != NULL) {\r | |
832 | *Vector = (UINT8) LvtTimer.Bits.Vector;\r | |
833 | }\r | |
834 | }\r | |
835 | }\r | |
836 | \r | |
bf73cc4b | 837 | /**\r |
838 | Enable the local APIC timer interrupt.\r | |
839 | **/\r | |
840 | VOID\r | |
841 | EFIAPI\r | |
842 | EnableApicTimerInterrupt (\r | |
843 | VOID\r | |
844 | )\r | |
845 | {\r | |
846 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
847 | \r | |
848 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
849 | LvtTimer.Bits.Mask = 0;\r | |
850 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
851 | }\r | |
852 | \r | |
853 | /**\r | |
854 | Disable the local APIC timer interrupt.\r | |
855 | **/\r | |
856 | VOID\r | |
857 | EFIAPI\r | |
858 | DisableApicTimerInterrupt (\r | |
859 | VOID\r | |
860 | )\r | |
861 | {\r | |
862 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
863 | \r | |
864 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
865 | LvtTimer.Bits.Mask = 1;\r | |
866 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
867 | }\r | |
868 | \r | |
869 | /**\r | |
870 | Get the local APIC timer interrupt state.\r | |
871 | \r | |
872 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
873 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
874 | **/\r | |
875 | BOOLEAN\r | |
876 | EFIAPI\r | |
877 | GetApicTimerInterruptState (\r | |
878 | VOID\r | |
879 | )\r | |
880 | {\r | |
881 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
882 | \r | |
883 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
884 | return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r | |
885 | }\r | |
886 | \r | |
887 | /**\r | |
888 | Send EOI to the local APIC.\r | |
889 | **/\r | |
890 | VOID\r | |
891 | EFIAPI\r | |
892 | SendApicEoi (\r | |
893 | VOID\r | |
894 | )\r | |
895 | {\r | |
896 | WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r | |
897 | }\r | |
898 | \r | |
5f867ad0 | 899 | /**\r |
7367cc6c | 900 | Get the 32-bit address that a device should use to send a Message Signaled\r |
5f867ad0 | 901 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r |
902 | \r | |
903 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
904 | **/\r | |
905 | UINT32\r | |
7367cc6c | 906 | EFIAPI\r |
5f867ad0 | 907 | GetApicMsiAddress (\r |
908 | VOID\r | |
909 | )\r | |
910 | {\r | |
911 | LOCAL_APIC_MSI_ADDRESS MsiAddress;\r | |
912 | \r | |
913 | //\r | |
7367cc6c | 914 | // Return address for an MSI interrupt to be delivered only to the APIC ID\r |
5f867ad0 | 915 | // of the currently executing processor.\r |
916 | //\r | |
917 | MsiAddress.Uint32 = 0;\r | |
918 | MsiAddress.Bits.BaseAddress = 0xFEE;\r | |
919 | MsiAddress.Bits.DestinationId = GetApicId ();\r | |
920 | return MsiAddress.Uint32;\r | |
921 | }\r | |
7367cc6c | 922 | \r |
5f867ad0 | 923 | /**\r |
7367cc6c | 924 | Get the 64-bit data value that a device should use to send a Message Signaled\r |
5f867ad0 | 925 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r |
926 | \r | |
927 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
928 | If DeliveryMode is not supported, then ASSERT().\r | |
7367cc6c LG |
929 | \r |
930 | @param Vector The 8-bit interrupt vector associated with the MSI.\r | |
5f867ad0 | 931 | Must be in the range 0x10..0xFE\r |
7367cc6c | 932 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r |
5f867ad0 | 933 | is handled. The only supported values are:\r |
934 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
935 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
936 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
937 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
938 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
939 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
7367cc6c LG |
940 | \r |
941 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
5f867ad0 | 942 | FALSE specifies an edge triggered interrupt.\r |
943 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
7367cc6c | 944 | TRUE specifies a level triggered interrupt that active\r |
5f867ad0 | 945 | when the interrupt line is asserted.\r |
7367cc6c | 946 | FALSE specifies a level triggered interrupt that active\r |
5f867ad0 | 947 | when the interrupt line is deasserted.\r |
948 | \r | |
949 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
950 | **/\r | |
951 | UINT64\r | |
7367cc6c | 952 | EFIAPI\r |
5f867ad0 | 953 | GetApicMsiValue (\r |
954 | IN UINT8 Vector,\r | |
955 | IN UINTN DeliveryMode,\r | |
956 | IN BOOLEAN LevelTriggered,\r | |
957 | IN BOOLEAN AssertionLevel\r | |
958 | )\r | |
959 | {\r | |
960 | LOCAL_APIC_MSI_DATA MsiData;\r | |
961 | \r | |
962 | ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r | |
963 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
7367cc6c | 964 | \r |
5f867ad0 | 965 | MsiData.Uint64 = 0;\r |
966 | MsiData.Bits.Vector = Vector;\r | |
967 | MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
968 | if (LevelTriggered) {\r | |
969 | MsiData.Bits.TriggerMode = 1;\r | |
970 | if (AssertionLevel) {\r | |
971 | MsiData.Bits.Level = 1;\r | |
972 | }\r | |
973 | }\r | |
974 | return MsiData.Uint64;\r | |
975 | }\r | |
73152f19 LD |
976 | \r |
977 | /**\r | |
978 | Get Package ID/Core ID/Thread ID of a processor.\r | |
979 | \r | |
980 | The algorithm assumes the target system has symmetry across physical\r | |
981 | package boundaries with respect to the number of logical processors\r | |
982 | per package, number of cores per package.\r | |
983 | \r | |
984 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
985 | @param[out] Package Returns the processor package ID.\r | |
986 | @param[out] Core Returns the processor core ID.\r | |
987 | @param[out] Thread Returns the processor thread ID.\r | |
988 | **/\r | |
989 | VOID\r | |
1c8ca9a0 | 990 | EFIAPI\r |
262128e5 | 991 | GetProcessorLocationByApicId (\r |
73152f19 LD |
992 | IN UINT32 InitialApicId,\r |
993 | OUT UINT32 *Package OPTIONAL,\r | |
994 | OUT UINT32 *Core OPTIONAL,\r | |
995 | OUT UINT32 *Thread OPTIONAL\r | |
996 | )\r | |
997 | {\r | |
061ead7a LD |
998 | BOOLEAN TopologyLeafSupported;\r |
999 | CPUID_VERSION_INFO_EBX VersionInfoEbx;\r | |
1000 | CPUID_VERSION_INFO_EDX VersionInfoEdx;\r | |
1001 | CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r | |
1002 | CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r | |
1003 | CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r | |
1004 | CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r | |
1005 | CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r | |
1006 | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r | |
061ead7a LD |
1007 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r |
1008 | UINT32 MaxStandardCpuIdIndex;\r | |
1009 | UINT32 MaxExtendedCpuIdIndex;\r | |
1010 | UINT32 SubIndex;\r | |
1011 | UINTN LevelType;\r | |
1012 | UINT32 MaxLogicProcessorsPerPackage;\r | |
1013 | UINT32 MaxCoresPerPackage;\r | |
061ead7a LD |
1014 | UINTN ThreadBits;\r |
1015 | UINTN CoreBits;\r | |
73152f19 LD |
1016 | \r |
1017 | //\r | |
1018 | // Check if the processor is capable of supporting more than one logical processor.\r | |
1019 | //\r | |
ae66c6f1 | 1020 | AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r |
73152f19 LD |
1021 | if (VersionInfoEdx.Bits.HTT == 0) {\r |
1022 | if (Thread != NULL) {\r | |
061ead7a | 1023 | *Thread = 0;\r |
73152f19 LD |
1024 | }\r |
1025 | if (Core != NULL) {\r | |
061ead7a | 1026 | *Core = 0;\r |
73152f19 LD |
1027 | }\r |
1028 | if (Package != NULL) {\r | |
1029 | *Package = 0;\r | |
1030 | }\r | |
1031 | return;\r | |
1032 | }\r | |
1033 | \r | |
061ead7a LD |
1034 | //\r |
1035 | // Assume three-level mapping of APIC ID: Package|Core|Thread.\r | |
1036 | //\r | |
73152f19 LD |
1037 | ThreadBits = 0;\r |
1038 | CoreBits = 0;\r | |
1039 | \r | |
1040 | //\r | |
061ead7a | 1041 | // Get max index of CPUID\r |
73152f19 | 1042 | //\r |
ae66c6f1 LD |
1043 | AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r |
1044 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r | |
73152f19 LD |
1045 | \r |
1046 | //\r | |
1047 | // If the extended topology enumeration leaf is available, it\r | |
1048 | // is the preferred mechanism for enumerating topology.\r | |
1049 | //\r | |
061ead7a LD |
1050 | TopologyLeafSupported = FALSE;\r |
1051 | if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
73152f19 LD |
1052 | AsmCpuidEx(\r |
1053 | CPUID_EXTENDED_TOPOLOGY,\r | |
1054 | 0,\r | |
1055 | &ExtendedTopologyEax.Uint32,\r | |
1056 | &ExtendedTopologyEbx.Uint32,\r | |
1057 | &ExtendedTopologyEcx.Uint32,\r | |
1058 | NULL\r | |
1059 | );\r | |
1060 | //\r | |
1061 | // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r | |
1062 | // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r | |
1063 | // supported on that processor.\r | |
1064 | //\r | |
1065 | if (ExtendedTopologyEbx.Uint32 != 0) {\r | |
1066 | TopologyLeafSupported = TRUE;\r | |
1067 | \r | |
1068 | //\r | |
1069 | // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r | |
1070 | // the SMT sub-field of x2APIC ID.\r | |
1071 | //\r | |
1072 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
ae66c6f1 | 1073 | ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r |
73152f19 LD |
1074 | ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r |
1075 | \r | |
1076 | //\r | |
1077 | // Software must not assume any "level type" encoding\r | |
1078 | // value to be related to any sub-leaf index, except sub-leaf 0.\r | |
1079 | //\r | |
1080 | SubIndex = 1;\r | |
1081 | do {\r | |
ae66c6f1 | 1082 | AsmCpuidEx (\r |
73152f19 LD |
1083 | CPUID_EXTENDED_TOPOLOGY,\r |
1084 | SubIndex,\r | |
1085 | &ExtendedTopologyEax.Uint32,\r | |
1086 | NULL,\r | |
1087 | &ExtendedTopologyEcx.Uint32,\r | |
1088 | NULL\r | |
1089 | );\r | |
1090 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1091 | if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r | |
1092 | CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r | |
1093 | break;\r | |
1094 | }\r | |
1095 | SubIndex++;\r | |
1096 | } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r | |
1097 | }\r | |
1098 | }\r | |
1099 | \r | |
1100 | if (!TopologyLeafSupported) {\r | |
061ead7a LD |
1101 | //\r |
1102 | // Get logical processor count\r | |
1103 | //\r | |
ae66c6f1 | 1104 | AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r |
73152f19 | 1105 | MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r |
061ead7a LD |
1106 | \r |
1107 | //\r | |
1108 | // Assume single-core processor\r | |
1109 | //\r | |
1110 | MaxCoresPerPackage = 1;\r | |
1111 | \r | |
1112 | //\r | |
1113 | // Check for topology extensions on AMD processor\r | |
1114 | //\r | |
1115 | if (StandardSignatureIsAuthenticAMD()) {\r | |
1116 | if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r | |
ae66c6f1 | 1117 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r |
061ead7a | 1118 | if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r |
061ead7a | 1119 | //\r |
ae66c6f1 | 1120 | // Account for max possible thread count to decode ApicId\r |
061ead7a | 1121 | //\r |
ae66c6f1 LD |
1122 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r |
1123 | MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r | |
061ead7a LD |
1124 | \r |
1125 | //\r | |
ae66c6f1 | 1126 | // Get cores per processor package\r |
061ead7a | 1127 | //\r |
ae66c6f1 LD |
1128 | AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r |
1129 | MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r | |
061ead7a LD |
1130 | }\r |
1131 | }\r | |
73152f19 LD |
1132 | }\r |
1133 | else {\r | |
1134 | //\r | |
061ead7a | 1135 | // Extract core count based on CACHE information\r |
73152f19 | 1136 | //\r |
061ead7a | 1137 | if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r |
ae66c6f1 | 1138 | AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r |
061ead7a LD |
1139 | if (CacheParamsEax.Uint32 != 0) {\r |
1140 | MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r | |
1141 | }\r | |
1142 | }\r | |
73152f19 LD |
1143 | }\r |
1144 | \r | |
1145 | ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r | |
061ead7a LD |
1146 | CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r |
1147 | }\r | |
73152f19 LD |
1148 | \r |
1149 | if (Thread != NULL) {\r | |
061ead7a | 1150 | *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r |
73152f19 LD |
1151 | }\r |
1152 | if (Core != NULL) {\r | |
061ead7a | 1153 | *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r |
73152f19 LD |
1154 | }\r |
1155 | if (Package != NULL) {\r | |
1156 | *Package = (InitialApicId >> (ThreadBits + CoreBits));\r | |
1157 | }\r | |
1158 | }\r |