Avoid DxeCore to reclaim PEI stack as IDT may be on it (like 32-bit OVMF).
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c
CommitLineData
bf73cc4b 1/** @file\r
2 Local APIC Library.\r
3\r
4 This local APIC library instance supports xAPIC mode only.\r
5\r
6 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include <Register/LocalApic.h>\r
18\r
19#include <Library/BaseLib.h>\r
20#include <Library/DebugLib.h>\r
21#include <Library/LocalApicLib.h>\r
22#include <Library/IoLib.h>\r
23#include <Library/TimerLib.h>\r
24#include <Library/PcdLib.h>\r
25\r
26//\r
27// Library internal functions\r
28//\r
29\r
30/**\r
31 Read from a local APIC register.\r
32\r
33 This function reads from a local APIC register either in xAPIC or x2APIC mode.\r
34 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
35 accessed using multiple 32-bit loads or stores, so this function only performs\r
36 32-bit read.\r
37\r
38 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
39 It must be 16-byte aligned.\r
40\r
41 @return 32-bit Value read from the register.\r
42**/\r
43UINT32\r
44EFIAPI\r
45ReadLocalApicReg (\r
46 IN UINTN MmioOffset\r
47 )\r
48{\r
49 ASSERT ((MmioOffset & 0xf) == 0);\r
50 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
51\r
52 return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);\r
53}\r
54\r
55/**\r
56 Write to a local APIC register.\r
57\r
58 This function writes to a local APIC register either in xAPIC or x2APIC mode.\r
59 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r
60 accessed using multiple 32-bit loads or stores, so this function only performs\r
61 32-bit write.\r
62\r
63 if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r
64\r
65 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r
66 It must be 16-byte aligned.\r
67 @param Value Value to be written to the register.\r
68**/\r
69VOID\r
70EFIAPI\r
71WriteLocalApicReg (\r
72 IN UINTN MmioOffset,\r
73 IN UINT32 Value\r
74 )\r
75{\r
76 ASSERT ((MmioOffset & 0xf) == 0);\r
77 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
78\r
79 MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);\r
80}\r
81\r
82/**\r
83 Send an IPI by writing to ICR.\r
84\r
85 This function returns after the IPI has been accepted by the target processor. \r
86\r
87 @param IcrLow 32-bit value to be written to the low half of ICR.\r
88 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
89**/\r
90VOID\r
91SendIpi (\r
92 IN UINT32 IcrLow,\r
93 IN UINT32 ApicId\r
94 )\r
95{\r
96 LOCAL_APIC_ICR_LOW IcrLowReg;\r
97\r
98 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
99 ASSERT (ApicId <= 0xff);\r
100\r
101 //\r
102 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
103 //\r
104 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
105 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r
106 do {\r
107 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r
108 } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
109}\r
110\r
111//\r
112// Library API implementation functions\r
113//\r
114\r
115/**\r
116 Get the current local APIC mode.\r
117\r
118 If local APIC is disabled, then ASSERT.\r
119\r
120 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
121 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
122**/\r
123UINTN\r
124EFIAPI\r
125GetApicMode (\r
126 VOID\r
127 )\r
128{\r
129 DEBUG_CODE (\r
130 {\r
131 MSR_IA32_APIC_BASE ApicBaseMsr;\r
132\r
133 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
134 //\r
135 // Local APIC should have been enabled\r
136 //\r
137 ASSERT (ApicBaseMsr.Bits.En != 0);\r
138 ASSERT (ApicBaseMsr.Bits.Extd == 0);\r
139 }\r
140 );\r
141 return LOCAL_APIC_MODE_XAPIC;\r
142}\r
143\r
144/**\r
145 Set the current local APIC mode.\r
146\r
147 If the specified local APIC mode is not valid, then ASSERT.\r
148 If the specified local APIC mode can't be set as current, then ASSERT.\r
149\r
150 @param ApicMode APIC mode to be set.\r
151**/\r
152VOID\r
153EFIAPI\r
154SetApicMode (\r
155 IN UINTN ApicMode\r
156 )\r
157{\r
158 ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r
159 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
160}\r
161\r
162/**\r
163 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
164\r
165 In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.\r
166 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
167 the 32-bit local APIC ID is returned as initial APIC ID.\r
168\r
169 @return 32-bit initial local APIC ID of the executing processor.\r
170**/\r
171UINT32\r
172EFIAPI\r
173GetInitialApicId (\r
174 VOID\r
175 )\r
176{\r
177 UINT32 RegEbx;\r
178\r
179 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
180\r
181 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
182 return RegEbx >> 24;\r
183}\r
184\r
185/**\r
186 Get the local APIC ID of the executing processor.\r
187\r
188 @return 32-bit local APIC ID of the executing processor.\r
189**/\r
190UINT32\r
191EFIAPI\r
192GetApicId (\r
193 VOID\r
194 )\r
195{\r
196 UINT32 ApicId;\r
197\r
198 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
199\r
200 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
201 ApicId >>= 24;\r
202 return ApicId;\r
203}\r
204\r
ae40aef1 205/**\r
206 Get the value of the local APIC version register.\r
207\r
208 @return the value of the local APIC version register.\r
209**/\r
210UINT32\r
211EFIAPI\r
212GetApicVersion (\r
213 VOID\r
214 )\r
215{\r
216 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r
217}\r
218\r
219/**\r
220 Send a Fixed IPI to a specified target processor.\r
221\r
222 This function returns after the IPI has been accepted by the target processor. \r
223\r
224 @param ApicId The local APIC ID of the target processor.\r
225 @param Vector The vector number of the interrupt being sent.\r
226**/\r
227VOID\r
228EFIAPI\r
229SendFixedIpi (\r
230 IN UINT32 ApicId,\r
231 IN UINT8 Vector\r
232 )\r
233{\r
234 LOCAL_APIC_ICR_LOW IcrLow;\r
235\r
236 IcrLow.Uint32 = 0;\r
237 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
238 IcrLow.Bits.Level = 1;\r
239 IcrLow.Bits.Vector = Vector;\r
240 SendIpi (IcrLow.Uint32, ApicId);\r
241}\r
242\r
243/**\r
244 Send a Fixed IPI to all processors excluding self.\r
245\r
246 This function returns after the IPI has been accepted by the target processors. \r
247\r
248 @param Vector The vector number of the interrupt being sent.\r
249**/\r
250VOID\r
251EFIAPI\r
252SendFixedIpiAllExcludingSelf (\r
253 IN UINT8 Vector\r
254 )\r
255{\r
256 LOCAL_APIC_ICR_LOW IcrLow;\r
257\r
258 IcrLow.Uint32 = 0;\r
259 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
260 IcrLow.Bits.Level = 1;\r
261 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
262 IcrLow.Bits.Vector = Vector;\r
263 SendIpi (IcrLow.Uint32, 0);\r
264}\r
265\r
bf73cc4b 266/**\r
267 Send a SMI IPI to a specified target processor.\r
268\r
269 This function returns after the IPI has been accepted by the target processor. \r
270\r
271 @param ApicId Specify the local APIC ID of the target processor.\r
272**/\r
273VOID\r
274EFIAPI\r
275SendSmiIpi (\r
276 IN UINT32 ApicId\r
277 )\r
278{\r
279 LOCAL_APIC_ICR_LOW IcrLow;\r
280\r
281 IcrLow.Uint32 = 0;\r
282 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
283 IcrLow.Bits.Level = 1;\r
284 SendIpi (IcrLow.Uint32, ApicId);\r
285}\r
286\r
287/**\r
288 Send a SMI IPI to all processors excluding self.\r
289\r
290 This function returns after the IPI has been accepted by the target processors. \r
291**/\r
292VOID\r
293EFIAPI\r
294SendSmiIpiAllExcludingSelf (\r
295 VOID\r
296 )\r
297{\r
298 LOCAL_APIC_ICR_LOW IcrLow;\r
299\r
300 IcrLow.Uint32 = 0;\r
301 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
302 IcrLow.Bits.Level = 1;\r
303 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
304 SendIpi (IcrLow.Uint32, 0);\r
305}\r
306\r
307/**\r
308 Send an INIT IPI to a specified target processor.\r
309\r
310 This function returns after the IPI has been accepted by the target processor. \r
311\r
312 @param ApicId Specify the local APIC ID of the target processor.\r
313**/\r
314VOID\r
315EFIAPI\r
316SendInitIpi (\r
317 IN UINT32 ApicId\r
318 )\r
319{\r
320 LOCAL_APIC_ICR_LOW IcrLow;\r
321\r
322 IcrLow.Uint32 = 0;\r
323 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
324 IcrLow.Bits.Level = 1;\r
325 SendIpi (IcrLow.Uint32, ApicId);\r
326}\r
327\r
328/**\r
329 Send an INIT IPI to all processors excluding self.\r
330\r
331 This function returns after the IPI has been accepted by the target processors. \r
332**/\r
333VOID\r
334EFIAPI\r
335SendInitIpiAllExcludingSelf (\r
336 VOID\r
337 )\r
338{\r
339 LOCAL_APIC_ICR_LOW IcrLow;\r
340\r
341 IcrLow.Uint32 = 0;\r
342 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
343 IcrLow.Bits.Level = 1;\r
344 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
345 SendIpi (IcrLow.Uint32, 0);\r
346}\r
347\r
348/**\r
349 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
350\r
351 This function returns after the IPI has been accepted by the target processor. \r
352\r
353 if StartupRoutine >= 1M, then ASSERT.\r
354 if StartupRoutine is not multiple of 4K, then ASSERT.\r
355\r
356 @param ApicId Specify the local APIC ID of the target processor.\r
357 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
358 address and 4K aligned.\r
359**/\r
360VOID\r
361EFIAPI\r
362SendInitSipiSipi (\r
363 IN UINT32 ApicId,\r
364 IN UINT32 StartupRoutine\r
365 )\r
366{\r
367 LOCAL_APIC_ICR_LOW IcrLow;\r
368\r
369 ASSERT (StartupRoutine < 0x100000);\r
370 ASSERT ((StartupRoutine & 0xfff) == 0);\r
371\r
372 SendInitIpi (ApicId);\r
373 MicroSecondDelay (10);\r
374 IcrLow.Uint32 = 0;\r
375 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
376 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
377 IcrLow.Bits.Level = 1;\r
378 SendIpi (IcrLow.Uint32, ApicId);\r
379 MicroSecondDelay (200);\r
380 SendIpi (IcrLow.Uint32, ApicId);\r
381}\r
382\r
383/**\r
384 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
385\r
386 This function returns after the IPI has been accepted by the target processors. \r
387\r
388 if StartupRoutine >= 1M, then ASSERT.\r
389 if StartupRoutine is not multiple of 4K, then ASSERT.\r
390\r
391 @param StartupRoutine Points to a start-up routine which is below 1M physical\r
392 address and 4K aligned.\r
393**/\r
394VOID\r
395EFIAPI\r
396SendInitSipiSipiAllExcludingSelf (\r
397 IN UINT32 StartupRoutine\r
398 )\r
399{\r
400 LOCAL_APIC_ICR_LOW IcrLow;\r
401\r
402 ASSERT (StartupRoutine < 0x100000);\r
403 ASSERT ((StartupRoutine & 0xfff) == 0);\r
404\r
405 SendInitIpiAllExcludingSelf ();\r
406 MicroSecondDelay (10);\r
407 IcrLow.Uint32 = 0;\r
408 IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
409 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
410 IcrLow.Bits.Level = 1;\r
411 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
412 SendIpi (IcrLow.Uint32, 0);\r
413 MicroSecondDelay (200);\r
414 SendIpi (IcrLow.Uint32, 0);\r
415}\r
416\r
417/**\r
418 Programming Virtual Wire Mode.\r
419\r
420 This function programs the local APIC for virtual wire mode following\r
421 the example described in chapter A.3 of the MP 1.4 spec.\r
422\r
423 IOxAPIC is not involved in this type of virtual wire mode.\r
424**/\r
425VOID\r
426EFIAPI\r
427ProgramVirtualWireMode (\r
428 VOID\r
429 )\r
430{\r
431 LOCAL_APIC_SVR Svr;\r
432 LOCAL_APIC_LVT_LINT Lint;\r
433\r
434 //\r
435 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
436 //\r
437 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
438 Svr.Bits.SpuriousVector = 0xf;\r
439 Svr.Bits.SoftwareEnable = 1;\r
440 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
441\r
442 //\r
443 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
444 //\r
ae40aef1 445 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
bf73cc4b 446 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
447 Lint.Bits.InputPinPolarity = 0;\r
448 Lint.Bits.TriggerMode = 0;\r
449 Lint.Bits.Mask = 0;\r
ae40aef1 450 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r
bf73cc4b 451\r
452 //\r
453 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
454 //\r
ae40aef1 455 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
bf73cc4b 456 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
457 Lint.Bits.InputPinPolarity = 0;\r
458 Lint.Bits.TriggerMode = 0;\r
459 Lint.Bits.Mask = 0;\r
ae40aef1 460 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
bf73cc4b 461}\r
462\r
463/**\r
464 Read the initial count value from the init-count register.\r
465\r
466 @return The initial count value read from the init-count register.\r
467**/\r
468UINT32\r
469EFIAPI\r
470GetApicTimerInitCount (\r
471 VOID\r
472 )\r
473{\r
474 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r
475}\r
476\r
477/**\r
478 Read the current count value from the current-count register.\r
479\r
480 @return The current count value read from the current-count register.\r
481**/\r
482UINT32\r
483EFIAPI\r
484GetApicTimerCurrentCount (\r
485 VOID\r
486 )\r
487{\r
488 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r
489}\r
490\r
491/**\r
492 Initialize the local APIC timer.\r
493\r
494 The local APIC timer is initialized and enabled.\r
495\r
496 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
497 If it is 0, then use the current divide value in the DCR.\r
498 @param InitCount The initial count value.\r
499 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
500 @param Vector The timer interrupt vector number.\r
501**/\r
502VOID\r
503EFIAPI\r
504InitializeApicTimer (\r
505 IN UINTN DivideValue,\r
506 IN UINT32 InitCount,\r
507 IN BOOLEAN PeriodicMode,\r
508 IN UINT8 Vector\r
509 )\r
510{\r
511 LOCAL_APIC_SVR Svr;\r
512 LOCAL_APIC_DCR Dcr;\r
513 LOCAL_APIC_LVT_TIMER LvtTimer;\r
514 UINT32 Divisor;\r
515\r
516 //\r
517 // Ensure local APIC is in software-enabled state.\r
518 //\r
519 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
520 Svr.Bits.SoftwareEnable = 1;\r
521 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
522\r
523 //\r
524 // Program init-count register.\r
525 //\r
526 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r
527\r
528 if (DivideValue != 0) {\r
529 ASSERT (DivideValue <= 128);\r
530 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
531 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
532\r
533 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
534 Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
535 Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
536 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r
537 }\r
538\r
539 //\r
540 // Enable APIC timer interrupt with specified timer mode.\r
541 //\r
542 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
543 if (PeriodicMode) {\r
544 LvtTimer.Bits.TimerMode = 1;\r
545 } else {\r
546 LvtTimer.Bits.TimerMode = 0;\r
547 }\r
548 LvtTimer.Bits.Mask = 0;\r
549 LvtTimer.Bits.Vector = Vector;\r
550 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
551}\r
552\r
ae40aef1 553/**\r
554 Get the state of the local APIC timer.\r
555\r
556 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
557 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
558 @param Vector Return the timer interrupt vector number.\r
559**/\r
560VOID\r
561EFIAPI\r
562GetApicTimerState (\r
563 OUT UINTN *DivideValue OPTIONAL,\r
564 OUT BOOLEAN *PeriodicMode OPTIONAL,\r
565 OUT UINT8 *Vector OPTIONAL\r
566 )\r
567{\r
568 UINT32 Divisor;\r
569 LOCAL_APIC_DCR Dcr;\r
570 LOCAL_APIC_LVT_TIMER LvtTimer;\r
571\r
572 if (DivideValue != NULL) {\r
573 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
574 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
575 Divisor = (Divisor + 1) & 0x7;\r
576 *DivideValue = ((UINTN)1) << Divisor;\r
577 }\r
578\r
579 if (PeriodicMode != NULL || Vector != NULL) {\r
580 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
581 if (PeriodicMode != NULL) {\r
582 if (LvtTimer.Bits.TimerMode == 1) {\r
583 *PeriodicMode = TRUE;\r
584 } else {\r
585 *PeriodicMode = FALSE;\r
586 }\r
587 }\r
588 if (Vector != NULL) {\r
589 *Vector = (UINT8) LvtTimer.Bits.Vector;\r
590 }\r
591 }\r
592}\r
593\r
bf73cc4b 594/**\r
595 Enable the local APIC timer interrupt.\r
596**/\r
597VOID\r
598EFIAPI\r
599EnableApicTimerInterrupt (\r
600 VOID\r
601 )\r
602{\r
603 LOCAL_APIC_LVT_TIMER LvtTimer;\r
604\r
605 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
606 LvtTimer.Bits.Mask = 0;\r
607 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
608}\r
609\r
610/**\r
611 Disable the local APIC timer interrupt.\r
612**/\r
613VOID\r
614EFIAPI\r
615DisableApicTimerInterrupt (\r
616 VOID\r
617 )\r
618{\r
619 LOCAL_APIC_LVT_TIMER LvtTimer;\r
620\r
621 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
622 LvtTimer.Bits.Mask = 1;\r
623 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
624}\r
625\r
626/**\r
627 Get the local APIC timer interrupt state.\r
628\r
629 @retval TRUE The local APIC timer interrupt is enabled.\r
630 @retval FALSE The local APIC timer interrupt is disabled.\r
631**/\r
632BOOLEAN\r
633EFIAPI\r
634GetApicTimerInterruptState (\r
635 VOID\r
636 )\r
637{\r
638 LOCAL_APIC_LVT_TIMER LvtTimer;\r
639\r
640 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
641 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
642}\r
643\r
644/**\r
645 Send EOI to the local APIC.\r
646**/\r
647VOID\r
648EFIAPI\r
649SendApicEoi (\r
650 VOID\r
651 )\r
652{\r
653 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
654}\r
655\r