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1 | /** @file |
2 | AESNI feature. | |
3 | ||
4 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> | |
5 | This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #include "CpuCommonFeatures.h" | |
16 | ||
17 | /** | |
18 | Prepares for the data used by CPU feature detection and initialization. | |
19 | ||
20 | @param[in] NumberOfProcessors The number of CPUs in the platform. | |
21 | ||
22 | @return Pointer to a buffer of CPU related configuration data. | |
23 | ||
24 | @note This service could be called by BSP only. | |
25 | **/ | |
26 | VOID * | |
27 | EFIAPI | |
28 | AesniGetConfigData ( | |
29 | IN UINTN NumberOfProcessors | |
30 | ) | |
31 | { | |
32 | UINT64 *ConfigData; | |
33 | ||
34 | ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors); | |
35 | ASSERT (ConfigData != NULL); | |
36 | return ConfigData; | |
37 | } | |
38 | ||
39 | /** | |
40 | Detects if AESNI feature supported on current processor. | |
41 | ||
42 | @param[in] ProcessorNumber The index of the CPU executing this function. | |
43 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION | |
44 | structure for the CPU executing this function. | |
45 | @param[in] ConfigData A pointer to the configuration buffer returned | |
46 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if | |
47 | CPU_FEATURE_GET_CONFIG_DATA was not provided in | |
48 | RegisterCpuFeature(). | |
49 | ||
50 | @retval TRUE AESNI feature is supported. | |
51 | @retval FALSE AESNI feature is not supported. | |
52 | ||
53 | @note This service could be called by BSP/APs. | |
54 | **/ | |
55 | BOOLEAN | |
56 | EFIAPI | |
57 | AesniSupport ( | |
58 | IN UINTN ProcessorNumber, | |
59 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, | |
60 | IN VOID *ConfigData OPTIONAL | |
61 | ) | |
62 | { | |
63 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; | |
64 | ||
65 | if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || | |
66 | IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || | |
67 | IS_XEON_5600_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || | |
68 | IS_XEON_E7_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || | |
69 | IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { | |
70 | MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; | |
71 | MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG); | |
72 | return (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1); | |
73 | } | |
74 | return FALSE; | |
75 | } | |
76 | ||
77 | /** | |
78 | Initializes AESNI feature to specific state. | |
79 | ||
80 | @param[in] ProcessorNumber The index of the CPU executing this function. | |
81 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION | |
82 | structure for the CPU executing this function. | |
83 | @param[in] ConfigData A pointer to the configuration buffer returned | |
84 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if | |
85 | CPU_FEATURE_GET_CONFIG_DATA was not provided in | |
86 | RegisterCpuFeature(). | |
87 | @param[in] State If TRUE, then the AESNI feature must be enabled. | |
88 | If FALSE, then the AESNI feature must be disabled. | |
89 | ||
90 | @retval RETURN_SUCCESS AESNI feature is initialized. | |
91 | ||
92 | @note This service could be called by BSP only. | |
93 | **/ | |
94 | RETURN_STATUS | |
95 | EFIAPI | |
96 | AesniInitialize ( | |
97 | IN UINTN ProcessorNumber, | |
98 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, | |
99 | IN VOID *ConfigData, OPTIONAL | |
100 | IN BOOLEAN State | |
101 | ) | |
102 | { | |
103 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; | |
104 | ||
105 | // | |
106 | // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index, | |
107 | // Simply use MSR_SANDY_BRIDGE_FEATURE_CONFIG here | |
108 | // | |
109 | // The scope of the MSR_SANDY_BRIDGE_FEATURE_CONFIG is Core, only program MSR_FEATURE_CONFIG for thread 0 | |
110 | // of each core. Otherwise, once a thread in the core disabled AES, the other thread will cause GP when | |
111 | // programming it. | |
112 | // | |
113 | if (CpuInfo->ProcessorInfo.Location.Thread == 0) { | |
114 | MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; | |
115 | if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) { | |
116 | CPU_REGISTER_TABLE_WRITE_FIELD ( | |
117 | ProcessorNumber, | |
118 | Msr, | |
119 | MSR_SANDY_BRIDGE_FEATURE_CONFIG, | |
120 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER, | |
121 | Bits.AESConfiguration, | |
122 | BIT1 | ((State) ? 0 : BIT0) | |
123 | ); | |
124 | } | |
125 | } | |
126 | return RETURN_SUCCESS; | |
127 | } |