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80c4b236 JF |
1 | /** @file\r |
2 | AESNI feature.\r | |
3 | \r | |
4 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "CpuCommonFeatures.h"\r | |
16 | \r | |
17 | /**\r | |
18 | Prepares for the data used by CPU feature detection and initialization.\r | |
19 | \r | |
20 | @param[in] NumberOfProcessors The number of CPUs in the platform.\r | |
21 | \r | |
22 | @return Pointer to a buffer of CPU related configuration data.\r | |
23 | \r | |
24 | @note This service could be called by BSP only.\r | |
25 | **/\r | |
26 | VOID *\r | |
27 | EFIAPI\r | |
28 | AesniGetConfigData (\r | |
29 | IN UINTN NumberOfProcessors\r | |
30 | )\r | |
31 | {\r | |
32 | UINT64 *ConfigData;\r | |
33 | \r | |
34 | ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);\r | |
35 | ASSERT (ConfigData != NULL);\r | |
36 | return ConfigData;\r | |
37 | }\r | |
38 | \r | |
39 | /**\r | |
40 | Detects if AESNI feature supported on current processor.\r | |
41 | \r | |
42 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
43 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
44 | structure for the CPU executing this function.\r | |
45 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
46 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
47 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
48 | RegisterCpuFeature().\r | |
49 | \r | |
50 | @retval TRUE AESNI feature is supported.\r | |
51 | @retval FALSE AESNI feature is not supported.\r | |
52 | \r | |
53 | @note This service could be called by BSP/APs.\r | |
54 | **/\r | |
55 | BOOLEAN\r | |
56 | EFIAPI\r | |
57 | AesniSupport (\r | |
58 | IN UINTN ProcessorNumber,\r | |
59 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
60 | IN VOID *ConfigData OPTIONAL\r | |
61 | )\r | |
62 | {\r | |
63 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;\r | |
64 | \r | |
9d02c34f SB |
65 | if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {\r |
66 | if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
67 | IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
68 | IS_XEON_5600_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
69 | IS_XEON_E7_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
70 | IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
71 | MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;\r | |
72 | ASSERT (MsrFeatureConfig != NULL);\r | |
73 | MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r | |
74 | }\r | |
75 | return TRUE;\r | |
80c4b236 JF |
76 | }\r |
77 | return FALSE;\r | |
78 | }\r | |
79 | \r | |
80 | /**\r | |
81 | Initializes AESNI feature to specific state.\r | |
82 | \r | |
83 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
84 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
85 | structure for the CPU executing this function.\r | |
86 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
87 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
88 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
89 | RegisterCpuFeature().\r | |
90 | @param[in] State If TRUE, then the AESNI feature must be enabled.\r | |
91 | If FALSE, then the AESNI feature must be disabled.\r | |
92 | \r | |
93 | @retval RETURN_SUCCESS AESNI feature is initialized.\r | |
94 | \r | |
95 | @note This service could be called by BSP only.\r | |
96 | **/\r | |
97 | RETURN_STATUS\r | |
98 | EFIAPI\r | |
99 | AesniInitialize (\r | |
100 | IN UINTN ProcessorNumber,\r | |
101 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
102 | IN VOID *ConfigData, OPTIONAL\r | |
103 | IN BOOLEAN State\r | |
104 | )\r | |
105 | {\r | |
106 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;\r | |
107 | \r | |
108 | //\r | |
109 | // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,\r | |
110 | // Simply use MSR_SANDY_BRIDGE_FEATURE_CONFIG here\r | |
111 | //\r | |
112 | // The scope of the MSR_SANDY_BRIDGE_FEATURE_CONFIG is Core, only program MSR_FEATURE_CONFIG for thread 0\r | |
113 | // of each core. Otherwise, once a thread in the core disabled AES, the other thread will cause GP when\r | |
114 | // programming it.\r | |
115 | //\r | |
116 | if (CpuInfo->ProcessorInfo.Location.Thread == 0) {\r | |
117 | MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;\r | |
3dcb5325 | 118 | ASSERT (MsrFeatureConfig != NULL);\r |
80c4b236 JF |
119 | if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {\r |
120 | CPU_REGISTER_TABLE_WRITE_FIELD (\r | |
121 | ProcessorNumber,\r | |
122 | Msr,\r | |
123 | MSR_SANDY_BRIDGE_FEATURE_CONFIG,\r | |
124 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,\r | |
125 | Bits.AESConfiguration,\r | |
126 | BIT1 | ((State) ? 0 : BIT0)\r | |
127 | );\r | |
128 | }\r | |
129 | }\r | |
130 | return RETURN_SUCCESS;\r | |
131 | }\r |