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80c4b236 JF |
1 | /** @file\r |
2 | Machine Check features.\r | |
3 | \r | |
dc7363f8 | 4 | Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
80c4b236 JF |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include "CpuCommonFeatures.h"\r | |
10 | \r | |
11 | /**\r | |
12 | Detects if Machine Check Exception feature supported on current processor.\r | |
13 | \r | |
14 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
15 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
16 | structure for the CPU executing this function.\r | |
17 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
18 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
19 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
20 | RegisterCpuFeature().\r | |
21 | \r | |
22 | @retval TRUE Machine Check Exception feature is supported.\r | |
23 | @retval FALSE Machine Check Exception feature is not supported.\r | |
24 | \r | |
25 | @note This service could be called by BSP/APs.\r | |
26 | **/\r | |
27 | BOOLEAN\r | |
28 | EFIAPI\r | |
29 | MceSupport (\r | |
30 | IN UINTN ProcessorNumber,\r | |
31 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
32 | IN VOID *ConfigData OPTIONAL\r | |
33 | )\r | |
34 | {\r | |
35 | return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCE == 1);\r | |
36 | }\r | |
37 | \r | |
38 | /**\r | |
39 | Initializes Machine Check Exception feature to specific state.\r | |
40 | \r | |
41 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
42 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
43 | structure for the CPU executing this function.\r | |
44 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
45 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
46 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
47 | RegisterCpuFeature().\r | |
48 | @param[in] State If TRUE, then the Machine Check Exception feature must be enabled.\r | |
49 | If FALSE, then the Machine Check Exception feature must be disabled.\r | |
50 | \r | |
51 | @retval RETURN_SUCCESS Machine Check Exception feature is initialized.\r | |
52 | \r | |
53 | @note This service could be called by BSP only.\r | |
54 | **/\r | |
55 | RETURN_STATUS\r | |
56 | EFIAPI\r | |
57 | MceInitialize (\r | |
58 | IN UINTN ProcessorNumber,\r | |
59 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
60 | IN VOID *ConfigData, OPTIONAL\r | |
61 | IN BOOLEAN State\r | |
62 | )\r | |
63 | {\r | |
64 | //\r | |
65 | // Set MCE bit in CR4\r | |
66 | //\r | |
67 | CPU_REGISTER_TABLE_WRITE_FIELD (\r | |
68 | ProcessorNumber,\r | |
69 | ControlRegister,\r | |
70 | 4,\r | |
71 | IA32_CR4,\r | |
72 | Bits.MCE,\r | |
73 | (State) ? 1 : 0\r | |
74 | );\r | |
75 | return RETURN_SUCCESS;\r | |
76 | }\r | |
77 | \r | |
78 | /**\r | |
79 | Detects if Machine Check Architecture feature supported on current processor.\r | |
80 | \r | |
81 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
82 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
83 | structure for the CPU executing this function.\r | |
84 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
85 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
86 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
87 | RegisterCpuFeature().\r | |
88 | \r | |
89 | @retval TRUE Machine Check Architecture feature is supported.\r | |
90 | @retval FALSE Machine Check Architecture feature is not supported.\r | |
91 | \r | |
92 | @note This service could be called by BSP/APs.\r | |
93 | **/\r | |
94 | BOOLEAN\r | |
95 | EFIAPI\r | |
96 | McaSupport (\r | |
97 | IN UINTN ProcessorNumber,\r | |
98 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
99 | IN VOID *ConfigData OPTIONAL\r | |
100 | )\r | |
101 | {\r | |
57d1afc8 SB |
102 | if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r |
103 | return FALSE;\r | |
104 | }\r | |
80c4b236 JF |
105 | return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);\r |
106 | }\r | |
107 | \r | |
108 | /**\r | |
109 | Initializes Machine Check Architecture feature to specific state.\r | |
110 | \r | |
111 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
112 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
113 | structure for the CPU executing this function.\r | |
114 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
115 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
116 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
117 | RegisterCpuFeature().\r | |
118 | @param[in] State If TRUE, then the Machine Check Architecture feature must be enabled.\r | |
119 | If FALSE, then the Machine Check Architecture feature must be disabled.\r | |
120 | \r | |
121 | @retval RETURN_SUCCESS Machine Check Architecture feature is initialized.\r | |
122 | \r | |
123 | @note This service could be called by BSP only.\r | |
124 | **/\r | |
125 | RETURN_STATUS\r | |
126 | EFIAPI\r | |
127 | McaInitialize (\r | |
128 | IN UINTN ProcessorNumber,\r | |
129 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
130 | IN VOID *ConfigData, OPTIONAL\r | |
131 | IN BOOLEAN State\r | |
132 | )\r | |
133 | {\r | |
134 | MSR_IA32_MCG_CAP_REGISTER McgCap;\r | |
135 | UINT32 BankIndex;\r | |
136 | \r | |
d28daadd ED |
137 | //\r |
138 | // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is core for below processor type, only program\r | |
139 | // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 in each core.\r | |
140 | //\r | |
141 | if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
142 | IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
143 | IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
144 | IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
145 | IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
146 | IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
147 | IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
148 | if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r | |
149 | return RETURN_SUCCESS;\r | |
150 | }\r | |
151 | }\r | |
152 | \r | |
153 | //\r | |
154 | // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program\r | |
155 | // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.\r | |
156 | //\r | |
157 | if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
158 | if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r | |
159 | return RETURN_SUCCESS;\r | |
160 | }\r | |
161 | }\r | |
162 | \r | |
e01d92d4 | 163 | if (State) {\r |
dc7363f8 RN |
164 | McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r |
165 | for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {\r | |
80c4b236 JF |
166 | CPU_REGISTER_TABLE_WRITE64 (\r |
167 | ProcessorNumber,\r | |
168 | Msr,\r | |
dc7363f8 RN |
169 | MSR_IA32_MC0_CTL + BankIndex * 4,\r |
170 | MAX_UINT64\r | |
80c4b236 JF |
171 | );\r |
172 | }\r | |
dc7363f8 RN |
173 | \r |
174 | if (PcdGetBool (PcdIsPowerOnReset)) {\r | |
175 | for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {\r | |
176 | CPU_REGISTER_TABLE_WRITE64 (\r | |
177 | ProcessorNumber,\r | |
178 | Msr,\r | |
179 | MSR_IA32_MC0_STATUS + BankIndex * 4,\r | |
180 | 0\r | |
181 | );\r | |
182 | }\r | |
183 | }\r | |
80c4b236 JF |
184 | }\r |
185 | \r | |
186 | return RETURN_SUCCESS;\r | |
187 | }\r | |
188 | \r | |
189 | /**\r | |
190 | Detects if IA32_MCG_CTL feature supported on current processor.\r | |
191 | \r | |
192 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
193 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
194 | structure for the CPU executing this function.\r | |
195 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
196 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
197 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
198 | RegisterCpuFeature().\r | |
199 | \r | |
200 | @retval TRUE IA32_MCG_CTL feature is supported.\r | |
201 | @retval FALSE IA32_MCG_CTL feature is not supported.\r | |
202 | \r | |
203 | @note This service could be called by BSP/APs.\r | |
204 | **/\r | |
205 | BOOLEAN\r | |
206 | EFIAPI\r | |
207 | McgCtlSupport (\r | |
208 | IN UINTN ProcessorNumber,\r | |
209 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
210 | IN VOID *ConfigData OPTIONAL\r | |
211 | )\r | |
212 | {\r | |
213 | MSR_IA32_MCG_CAP_REGISTER McgCap;\r | |
214 | \r | |
215 | if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r | |
216 | return FALSE;\r | |
217 | }\r | |
218 | McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
219 | return (McgCap.Bits.MCG_CTL_P == 1);\r | |
220 | }\r | |
221 | \r | |
222 | /**\r | |
223 | Initializes IA32_MCG_CTL feature to specific state.\r | |
224 | \r | |
225 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
226 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
227 | structure for the CPU executing this function.\r | |
228 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
229 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
230 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
231 | RegisterCpuFeature().\r | |
232 | @param[in] State If TRUE, then the IA32_MCG_CTL feature must be enabled.\r | |
233 | If FALSE, then the IA32_MCG_CTL feature must be disabled.\r | |
234 | \r | |
235 | @retval RETURN_SUCCESS IA32_MCG_CTL feature is initialized.\r | |
236 | \r | |
237 | @note This service could be called by BSP only.\r | |
238 | **/\r | |
239 | RETURN_STATUS\r | |
240 | EFIAPI\r | |
241 | McgCtlInitialize (\r | |
242 | IN UINTN ProcessorNumber,\r | |
243 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
244 | IN VOID *ConfigData, OPTIONAL\r | |
245 | IN BOOLEAN State\r | |
246 | )\r | |
247 | {\r | |
248 | CPU_REGISTER_TABLE_WRITE64 (\r | |
249 | ProcessorNumber,\r | |
250 | Msr,\r | |
251 | MSR_IA32_MCG_CTL,\r | |
252 | (State)? MAX_UINT64 : 0\r | |
253 | );\r | |
254 | return RETURN_SUCCESS;\r | |
255 | }\r | |
256 | \r | |
306a5bcc | 257 | /**\r |
7367cc6c | 258 | Detects if Local machine check exception feature supported on current\r |
306a5bcc ED |
259 | processor.\r |
260 | \r | |
261 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
262 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
263 | structure for the CPU executing this function.\r | |
264 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
265 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
266 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
267 | RegisterCpuFeature().\r | |
268 | \r | |
269 | @retval TRUE Local machine check exception feature is supported.\r | |
270 | @retval FALSE Local machine check exception feature is not supported.\r | |
271 | \r | |
272 | @note This service could be called by BSP/APs.\r | |
273 | **/\r | |
274 | BOOLEAN\r | |
275 | EFIAPI\r | |
276 | LmceSupport (\r | |
277 | IN UINTN ProcessorNumber,\r | |
278 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
279 | IN VOID *ConfigData OPTIONAL\r | |
280 | )\r | |
281 | {\r | |
282 | MSR_IA32_MCG_CAP_REGISTER McgCap;\r | |
283 | \r | |
284 | if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r | |
285 | return FALSE;\r | |
286 | }\r | |
287 | \r | |
288 | McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
289 | if (ProcessorNumber == 0) {\r | |
290 | DEBUG ((EFI_D_INFO, "LMCE eanble = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0)));\r | |
291 | }\r | |
292 | return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);\r | |
293 | }\r | |
294 | \r | |
295 | /**\r | |
296 | Initializes Local machine check exception feature to specific state.\r | |
297 | \r | |
298 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
299 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
300 | structure for the CPU executing this function.\r | |
301 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
302 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
303 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
304 | RegisterCpuFeature().\r | |
305 | @param[in] State If TRUE, then the Local machine check exception\r | |
306 | feature must be enabled.\r | |
307 | If FALSE, then the Local machine check exception\r | |
308 | feature must be disabled.\r | |
309 | \r | |
310 | @retval RETURN_SUCCESS Local machine check exception feature is initialized.\r | |
311 | \r | |
312 | **/\r | |
313 | RETURN_STATUS\r | |
314 | EFIAPI\r | |
315 | LmceInitialize (\r | |
316 | IN UINTN ProcessorNumber,\r | |
317 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
318 | IN VOID *ConfigData, OPTIONAL\r | |
319 | IN BOOLEAN State\r | |
320 | )\r | |
321 | {\r | |
322 | MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;\r | |
323 | \r | |
d28daadd | 324 | //\r |
2b0c1994 | 325 | // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program\r |
d28daadd ED |
326 | // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r |
327 | //\r | |
328 | if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
329 | IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
330 | IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
331 | if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r | |
332 | return RETURN_SUCCESS;\r | |
333 | }\r | |
334 | }\r | |
335 | \r | |
306a5bcc ED |
336 | ASSERT (ConfigData != NULL);\r |
337 | MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;\r | |
338 | if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {\r | |
339 | CPU_REGISTER_TABLE_WRITE_FIELD (\r | |
340 | ProcessorNumber,\r | |
341 | Msr,\r | |
342 | MSR_IA32_FEATURE_CONTROL,\r | |
343 | MSR_IA32_FEATURE_CONTROL_REGISTER,\r | |
344 | Bits.LmceOn,\r | |
345 | (State) ? 1 : 0\r | |
346 | );\r | |
347 | }\r | |
348 | return RETURN_SUCCESS;\r | |
349 | }\r |