[mirror_edk2.git] / UefiCpuPkg / Library / MpInitLib / Ia32 / MpFuncs.nasm

;------------------------------------------------------------------------------ ;\r
; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;\r
;   MpFuncs.nasm\r
;\r
; Abstract:\r
;\r
;   This is the assembly code for MP support\r
;\r
;-------------------------------------------------------------------------------\r
\r
%include "MpEqu.inc"\r
extern ASM_PFX(InitializeFloatingPointUnits)\r
\r
SECTION .text\r
\r
;-------------------------------------------------------------------------------------\r
;RendezvousFunnelProc  procedure follows. All APs execute their procedure. This\r
;procedure serializes all the AP processors through an Init sequence. It must be\r
;noted that APs arrive here very raw...ie: real mode, no stack.\r
;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
;IS IN MACHINE CODE.\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(RendezvousFunnelProc)\r
ASM_PFX(RendezvousFunnelProc):\r
RendezvousFunnelProcStart:\r
; At this point CS = 0x(vv00) and ip= 0x0.\r
BITS 16\r
    mov        ebp, eax                        ; save BIST information\r
\r
    mov        ax, cs\r
    mov        ds, ax\r
    mov        es, ax\r
    mov        ss, ax\r
    xor        ax, ax\r
    mov        fs, ax\r
    mov        gs, ax\r
\r
    mov        si,  BufferStartLocation\r
    mov        ebx, [si]\r
\r
    mov        si,  DataSegmentLocation\r
    mov        edx, [si]\r
\r
    ;\r
    ; Get start address of 32-bit code in low memory (<1MB)\r
    ;\r
    mov        edi, ModeTransitionMemoryLocation\r
\r
    mov        si, GdtrLocation\r
o32 lgdt       [cs:si]\r
\r
    mov        si, IdtrLocation\r
o32 lidt       [cs:si]\r
\r
    ;\r
    ; Switch to protected mode\r
    ;\r
    mov        eax, cr0                        ; Get control register 0\r
    or         eax, 000000003h                 ; Set PE bit (bit #0) & MP\r
    mov        cr0, eax\r
\r
    ; Switch to 32-bit code in executable memory (>1MB)\r
o32 jmp far    [cs:di]\r
\r
;\r
; Following code may be copied to memory with type of EfiBootServicesCode.\r
; This is required at DXE phase if NX is enabled for EfiBootServicesCode of\r
; memory.\r
;\r
BITS 32\r
Flat32Start:                                   ; protected mode entry point\r
    mov        ds, dx\r
    mov        es, dx\r
    mov        fs, dx\r
    mov        gs, dx\r
    mov        ss, dx\r
\r
    mov        esi, ebx\r
\r
    ; Increment the number of APs executing here as early as possible\r
    ; This is decremented in C code when AP is finished executing\r
    mov        edi, esi\r
    add        edi, NumApsExecutingLocation\r
    lock inc   dword [edi]\r
\r
    mov         edi, esi\r
    add         edi, EnableExecuteDisableLocation\r
    cmp         byte [edi], 0\r
    jz          SkipEnableExecuteDisable\r
\r
    ;\r
    ; Enable IA32 PAE execute disable\r
    ;\r
\r
    mov         ecx, 0xc0000080\r
    rdmsr\r
    bts         eax, 11\r
    wrmsr\r
\r
    mov         edi, esi\r
    add         edi, Cr3Location\r
    mov         eax, dword [edi]\r
    mov         cr3, eax\r
\r
    mov         eax, cr4\r
    bts         eax, 5\r
    mov         cr4, eax\r
\r
    mov         eax, cr0\r
    bts         eax, 31\r
    mov         cr0, eax\r
\r
SkipEnableExecuteDisable:\r
    mov        edi, esi\r
    add        edi, InitFlagLocation\r
    cmp        dword [edi], 1       ; 1 == ApInitConfig\r
    jnz        GetApicId\r
\r
    ; AP init\r
    mov        edi, esi\r
    add        edi, LockLocation\r
    mov        eax, NotVacantFlag\r
\r
TestLock:\r
    xchg       [edi], eax\r
    cmp        eax, NotVacantFlag\r
    jz         TestLock\r
\r
    mov        ecx, esi\r
    add        ecx, ApIndexLocation\r
    inc        dword [ecx]\r
    mov        ebx, [ecx]\r
\r
Releaselock:\r
    mov        eax, VacantFlag\r
    xchg       [edi], eax\r
\r
    mov        edi, esi\r
    add        edi, StackSizeLocation\r
    mov        eax, [edi]\r
    mov        ecx, ebx\r
    inc        ecx\r
    mul        ecx                               ; EAX = StackSize * (CpuNumber + 1)\r
    mov        edi, esi\r
    add        edi, StackStartAddressLocation\r
    add        eax, [edi]\r
    mov        esp, eax\r
    jmp        CProcedureInvoke\r
\r
GetApicId:\r
    mov        eax, 0\r
    cpuid\r
    cmp        eax, 0bh\r
    jb         NoX2Apic             ; CPUID level below CPUID_EXTENDED_TOPOLOGY\r
\r
    mov        eax, 0bh\r
    xor        ecx, ecx\r
    cpuid\r
    test       ebx, 0ffffh\r
    jz         NoX2Apic             ; CPUID.0BH:EBX[15:0] is zero\r
\r
    ; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX\r
    jmp        GetProcessorNumber\r
\r
NoX2Apic:\r
    ; Processor is not x2APIC capable, so get 8-bit APIC ID\r
    mov        eax, 1\r
    cpuid\r
    shr        ebx, 24\r
    mov        edx, ebx\r
\r
GetProcessorNumber:\r
    ;\r
    ; Get processor number for this AP\r
    ; Note that BSP may become an AP due to SwitchBsp()\r
    ;\r
    xor         ebx, ebx\r
    lea         eax, [esi + CpuInfoLocation]\r
    mov         edi, [eax]\r
\r
GetNextProcNumber:\r
    cmp         [edi], edx                       ; APIC ID match?\r
    jz          ProgramStack\r
    add         edi, 20\r
    inc         ebx\r
    jmp         GetNextProcNumber\r
\r
ProgramStack:\r
    mov         esp, [edi + 12]\r
\r
CProcedureInvoke:\r
    push       ebp               ; push BIST data at top of AP stack\r
    xor        ebp, ebp          ; clear ebp for call stack trace\r
    push       ebp\r
    mov        ebp, esp\r
\r
    mov        eax, ASM_PFX(InitializeFloatingPointUnits)\r
    call       eax               ; Call assembly function to initialize FPU per UEFI spec\r
\r
    push       ebx               ; Push ApIndex\r
    mov        eax, esi\r
    add        eax, LockLocation\r
    push       eax               ; push address of exchange info data buffer\r
\r
    mov        edi, esi\r
    add        edi, ApProcedureLocation\r
    mov        eax, [edi]\r
\r
    call       eax               ; Invoke C function\r
\r
    jmp        $                 ; Never reach here\r
RendezvousFunnelProcEnd:\r
\r
;-------------------------------------------------------------------------------------\r
;  AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmRelocateApLoop)\r
ASM_PFX(AsmRelocateApLoop):\r
AsmRelocateApLoopStart:\r
    mov        eax, esp\r
    mov        esp, [eax + 16]     ; TopOfApStack\r
    push       dword [eax]         ; push return address for stack trace\r
    push       ebp\r
    mov        ebp, esp\r
    mov        ebx, [eax + 8]      ; ApTargetCState\r
    mov        ecx, [eax + 4]      ; MwaitSupport\r
    mov        eax, [eax + 20]     ; CountTofinish\r
    lock dec   dword [eax]         ; (*CountTofinish)--\r
    cmp        cl,  1              ; Check mwait-monitor support\r
    jnz        HltLoop\r
MwaitLoop:\r
    cli\r
    mov        eax, esp\r
    xor        ecx, ecx\r
    xor        edx, edx\r
    monitor\r
    mov        eax, ebx            ; Mwait Cx, Target C-State per eax[7:4]\r
    shl        eax, 4\r
    mwait\r
    jmp        MwaitLoop\r
HltLoop:\r
    cli\r
    hlt\r
    jmp        HltLoop\r
AsmRelocateApLoopEnd:\r
\r
;-------------------------------------------------------------------------------------\r
;  AsmGetAddressMap (&AddressMap);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmGetAddressMap)\r
ASM_PFX(AsmGetAddressMap):\r
    pushad\r
    mov        ebp,esp\r
\r
    mov        ebx,  [ebp + 24h]\r
    mov        dword [ebx], RendezvousFunnelProcStart\r
    mov        dword [ebx +  4h], Flat32Start - RendezvousFunnelProcStart\r
    mov        dword [ebx +  8h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
    mov        dword [ebx + 0Ch], AsmRelocateApLoopStart\r
    mov        dword [ebx + 10h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
    mov        dword [ebx + 14h], Flat32Start - RendezvousFunnelProcStart\r
\r
    popad\r
    ret\r
\r
;-------------------------------------------------------------------------------------\r
;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
;about to become an AP. It switches it'stack with the current AP.\r
;AsmExchangeRole (IN   CPU_EXCHANGE_INFO    *MyInfo, IN   CPU_EXCHANGE_INFO    *OthersInfo);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmExchangeRole)\r
ASM_PFX(AsmExchangeRole):\r
    ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
    ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
    pushad\r
    mov        ebp,esp\r
\r
    ; esi contains MyInfo pointer\r
    mov        esi, [ebp + 24h]\r
\r
    ; edi contains OthersInfo pointer\r
    mov        edi, [ebp + 28h]\r
\r
    ;Store EFLAGS, GDTR and IDTR register to stack\r
    pushfd\r
    mov        eax, cr4\r
    push       eax       ; push cr4 firstly\r
    mov        eax, cr0\r
    push       eax\r
\r
    sgdt       [esi + 8]\r
    sidt       [esi + 14]\r
\r
    ; Store the its StackPointer\r
    mov        [esi + 4],esp\r
\r
    ; update its switch state to STORED\r
    mov        byte [esi], CPU_SWITCH_STATE_STORED\r
\r
WaitForOtherStored:\r
    ; wait until the other CPU finish storing its state\r
    cmp        byte [edi], CPU_SWITCH_STATE_STORED\r
    jz         OtherStored\r
    pause\r
    jmp        WaitForOtherStored\r
\r
OtherStored:\r
    ; Since another CPU already stored its state, load them\r
    ; load GDTR value\r
    lgdt       [edi + 8]\r
\r
    ; load IDTR value\r
    lidt       [edi + 14]\r
\r
    ; load its future StackPointer\r
    mov        esp, [edi + 4]\r
\r
    ; update the other CPU's switch state to LOADED\r
    mov        byte [edi], CPU_SWITCH_STATE_LOADED\r
\r
WaitForOtherLoaded:\r
    ; wait until the other CPU finish loading new state,\r
    ; otherwise the data in stack may corrupt\r
    cmp        byte [esi], CPU_SWITCH_STATE_LOADED\r
    jz         OtherLoaded\r
    pause\r
    jmp        WaitForOtherLoaded\r
\r
OtherLoaded:\r
    ; since the other CPU already get the data it want, leave this procedure\r
    pop        eax\r
    mov        cr0, eax\r
    pop        eax\r
    mov        cr4, eax\r
    popfd\r
\r
    popad\r
    ret\r
Commit	Line	Data
d94e5f67	1	;------------------------------------------------------------------------------ ;\r
a7bbe9d2	2	; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
0acd8697	3	; SPDX-License-Identifier: BSD-2-Clause-Patent\r
d94e5f67 JF	4	;\r
	5	; Module Name:\r
	6	;\r
	7	; MpFuncs.nasm\r
	8	;\r
	9	; Abstract:\r
	10	;\r
	11	; This is the assembly code for MP support\r
	12	;\r
	13	;-------------------------------------------------------------------------------\r
	14	\r
	15	%include "MpEqu.inc"\r
	16	extern ASM_PFX(InitializeFloatingPointUnits)\r
	17	\r
	18	SECTION .text\r
	19	\r
	20	;-------------------------------------------------------------------------------------\r
	21	;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
	22	;procedure serializes all the AP processors through an Init sequence. It must be\r
	23	;noted that APs arrive here very raw...ie: real mode, no stack.\r
	24	;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
	25	;IS IN MACHINE CODE.\r
	26	;-------------------------------------------------------------------------------------\r
	27	global ASM_PFX(RendezvousFunnelProc)\r
	28	ASM_PFX(RendezvousFunnelProc):\r
	29	RendezvousFunnelProcStart:\r
	30	; At this point CS = 0x(vv00) and ip= 0x0.\r
	31	BITS 16\r
	32	mov ebp, eax ; save BIST information\r
	33	\r
	34	mov ax, cs\r
	35	mov ds, ax\r
	36	mov es, ax\r
	37	mov ss, ax\r
	38	xor ax, ax\r
	39	mov fs, ax\r
	40	mov gs, ax\r
	41	\r
	42	mov si, BufferStartLocation\r
	43	mov ebx, [si]\r
	44	\r
d94e5f67 JF	45	mov si, DataSegmentLocation\r
	46	mov edx, [si]\r
	47	\r
f32bfe6d JW	48	;\r
	49	; Get start address of 32-bit code in low memory (<1MB)\r
	50	;\r
	51	mov edi, ModeTransitionMemoryLocation\r
	52	\r
d94e5f67 JF	53	mov si, GdtrLocation\r
	54	o32 lgdt [cs:si]\r
	55	\r
	56	mov si, IdtrLocation\r
	57	o32 lidt [cs:si]\r
	58	\r
f32bfe6d JW	59	;\r
	60	; Switch to protected mode\r
	61	;\r
8396e2dd JF	62	mov eax, cr0 ; Get control register 0\r
8396e2dd JF	63	or eax, 000000003h ; Set PE bit (bit #0) & MP\r
d94e5f67 JF	64	mov cr0, eax\r
d94e5f67 JF	65	\r
f32bfe6d JW	66	; Switch to 32-bit code in executable memory (>1MB)\r
	67	o32 jmp far [cs:di]\r
	68	\r
	69	;\r
	70	; Following code may be copied to memory with type of EfiBootServicesCode.\r
	71	; This is required at DXE phase if NX is enabled for EfiBootServicesCode of\r
	72	; memory.\r
	73	;\r
d94e5f67 JF	74	BITS 32\r
	75	Flat32Start: ; protected mode entry point\r
	76	mov ds, dx\r
	77	mov es, dx\r
	78	mov fs, dx\r
	79	mov gs, dx\r
	80	mov ss, dx\r
	81	\r
	82	mov esi, ebx\r
5c66d125	83	\r
0594ec41 ED	84	; Increment the number of APs executing here as early as possible\r
	85	; This is decremented in C code when AP is finished executing\r
	86	mov edi, esi\r
	87	add edi, NumApsExecutingLocation\r
	88	lock inc dword [edi]\r
	89	\r
5c66d125 JF	90	mov edi, esi\r
	91	add edi, EnableExecuteDisableLocation\r
	92	cmp byte [edi], 0\r
	93	jz SkipEnableExecuteDisable\r
	94	\r
	95	;\r
	96	; Enable IA32 PAE execute disable\r
	97	;\r
	98	\r
	99	mov ecx, 0xc0000080\r
	100	rdmsr\r
	101	bts eax, 11\r
	102	wrmsr\r
	103	\r
	104	mov edi, esi\r
	105	add edi, Cr3Location\r
	106	mov eax, dword [edi]\r
	107	mov cr3, eax\r
	108	\r
	109	mov eax, cr4\r
	110	bts eax, 5\r
	111	mov cr4, eax\r
	112	\r
	113	mov eax, cr0\r
	114	bts eax, 31\r
	115	mov cr0, eax\r
	116	\r
	117	SkipEnableExecuteDisable:\r
845c5be1 JF	118	mov edi, esi\r
	119	add edi, InitFlagLocation\r
	120	cmp dword [edi], 1 ; 1 == ApInitConfig\r
	121	jnz GetApicId\r
5c66d125	122	\r
845c5be1	123	; AP init\r
d94e5f67 JF	124	mov edi, esi\r
	125	add edi, LockLocation\r
	126	mov eax, NotVacantFlag\r
	127	\r
	128	TestLock:\r
	129	xchg [edi], eax\r
	130	cmp eax, NotVacantFlag\r
	131	jz TestLock\r
	132	\r
845c5be1	133	mov ecx, esi\r
37676b9f	134	add ecx, ApIndexLocation\r
845c5be1 JF	135	inc dword [ecx]\r
	136	mov ebx, [ecx]\r
	137	\r
	138	Releaselock:\r
	139	mov eax, VacantFlag\r
	140	xchg [edi], eax\r
d94e5f67	141	\r
d94e5f67 JF	142	mov edi, esi\r
	143	add edi, StackSizeLocation\r
	144	mov eax, [edi]\r
845c5be1 JF	145	mov ecx, ebx\r
	146	inc ecx\r
	147	mul ecx ; EAX = StackSize * (CpuNumber + 1)\r
d94e5f67 JF	148	mov edi, esi\r
	149	add edi, StackStartAddressLocation\r
	150	add eax, [edi]\r
	151	mov esp, eax\r
845c5be1 JF	152	jmp CProcedureInvoke\r
	153	\r
	154	GetApicId:\r
	155	mov eax, 0\r
	156	cpuid\r
	157	cmp eax, 0bh\r
1cbd8330 LE	158	jb NoX2Apic ; CPUID level below CPUID_EXTENDED_TOPOLOGY\r
	159	\r
	160	mov eax, 0bh\r
	161	xor ecx, ecx\r
	162	cpuid\r
	163	test ebx, 0ffffh\r
	164	jz NoX2Apic ; CPUID.0BH:EBX[15:0] is zero\r
	165	\r
	166	; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX\r
	167	jmp GetProcessorNumber\r
	168	\r
	169	NoX2Apic:\r
845c5be1 JF	170	; Processor is not x2APIC capable, so get 8-bit APIC ID\r
	171	mov eax, 1\r
	172	cpuid\r
	173	shr ebx, 24\r
	174	mov edx, ebx\r
845c5be1	175	\r
845c5be1 JF	176	GetProcessorNumber:\r
	177	;\r
	178	; Get processor number for this AP\r
	179	; Note that BSP may become an AP due to SwitchBsp()\r
	180	;\r
	181	xor ebx, ebx\r
	182	lea eax, [esi + CpuInfoLocation]\r
	183	mov edi, [eax]\r
d94e5f67	184	\r
845c5be1 JF	185	GetNextProcNumber:\r
	186	cmp [edi], edx ; APIC ID match?\r
	187	jz ProgramStack\r
dd3fa0cd	188	add edi, 20\r
845c5be1	189	inc ebx\r
7367cc6c	190	jmp GetNextProcNumber\r
d94e5f67	191	\r
845c5be1 JF	192	ProgramStack:\r
845c5be1 JF	193	mov esp, [edi + 12]\r
7367cc6c	194	\r
d94e5f67 JF	195	CProcedureInvoke:\r
	196	push ebp ; push BIST data at top of AP stack\r
	197	xor ebp, ebp ; clear ebp for call stack trace\r
	198	push ebp\r
	199	mov ebp, esp\r
	200	\r
	201	mov eax, ASM_PFX(InitializeFloatingPointUnits)\r
	202	call eax ; Call assembly function to initialize FPU per UEFI spec\r
	203	\r
37676b9f	204	push ebx ; Push ApIndex\r
d94e5f67 JF	205	mov eax, esi\r
	206	add eax, LockLocation\r
	207	push eax ; push address of exchange info data buffer\r
	208	\r
	209	mov edi, esi\r
	210	add edi, ApProcedureLocation\r
	211	mov eax, [edi]\r
	212	\r
8396e2dd	213	call eax ; Invoke C function\r
d94e5f67	214	\r
8396e2dd	215	jmp $ ; Never reach here\r
d94e5f67 JF	216	RendezvousFunnelProcEnd:\r
d94e5f67 JF	217	\r
76157021	218	;-------------------------------------------------------------------------------------\r
9f91cb01	219	; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);\r
76157021 JF	220	;-------------------------------------------------------------------------------------\r
	221	global ASM_PFX(AsmRelocateApLoop)\r
	222	ASM_PFX(AsmRelocateApLoop):\r
	223	AsmRelocateApLoopStart:\r
bf2786dc JF	224	mov eax, esp\r
	225	mov esp, [eax + 16] ; TopOfApStack\r
	226	push dword [eax] ; push return address for stack trace\r
	227	push ebp\r
	228	mov ebp, esp\r
	229	mov ebx, [eax + 8] ; ApTargetCState\r
	230	mov ecx, [eax + 4] ; MwaitSupport\r
9f91cb01 JF	231	mov eax, [eax + 20] ; CountTofinish\r
9f91cb01 JF	232	lock dec dword [eax] ; (*CountTofinish)--\r
bf2786dc	233	cmp cl, 1 ; Check mwait-monitor support\r
76157021 JF	234	jnz HltLoop\r
76157021 JF	235	MwaitLoop:\r
a7bbe9d2	236	cli\r
76157021 JF	237	mov eax, esp\r
	238	xor ecx, ecx\r
	239	xor edx, edx\r
	240	monitor\r
bf2786dc	241	mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]\r
76157021 JF	242	shl eax, 4\r
	243	mwait\r
	244	jmp MwaitLoop\r
	245	HltLoop:\r
	246	cli\r
	247	hlt\r
	248	jmp HltLoop\r
76157021 JF	249	AsmRelocateApLoopEnd:\r
76157021 JF	250	\r
d94e5f67 JF	251	;-------------------------------------------------------------------------------------\r
	252	; AsmGetAddressMap (&AddressMap);\r
	253	;-------------------------------------------------------------------------------------\r
	254	global ASM_PFX(AsmGetAddressMap)\r
	255	ASM_PFX(AsmGetAddressMap):\r
	256	pushad\r
	257	mov ebp,esp\r
	258	\r
	259	mov ebx, [ebp + 24h]\r
	260	mov dword [ebx], RendezvousFunnelProcStart\r
	261	mov dword [ebx + 4h], Flat32Start - RendezvousFunnelProcStart\r
	262	mov dword [ebx + 8h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
f7f85d83 JF	263	mov dword [ebx + 0Ch], AsmRelocateApLoopStart\r
f7f85d83 JF	264	mov dword [ebx + 10h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
f32bfe6d	265	mov dword [ebx + 14h], Flat32Start - RendezvousFunnelProcStart\r
d94e5f67 JF	266	\r
	267	popad\r
	268	ret\r
	269	\r
	270	;-------------------------------------------------------------------------------------\r
	271	;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
	272	;about to become an AP. It switches it'stack with the current AP.\r
	273	;AsmExchangeRole (IN CPU_EXCHANGE_INFO MyInfo, IN CPU_EXCHANGE_INFO OthersInfo);\r
	274	;-------------------------------------------------------------------------------------\r
	275	global ASM_PFX(AsmExchangeRole)\r
	276	ASM_PFX(AsmExchangeRole):\r
	277	; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
	278	; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
	279	pushad\r
	280	mov ebp,esp\r
	281	\r
	282	; esi contains MyInfo pointer\r
	283	mov esi, [ebp + 24h]\r
	284	\r
	285	; edi contains OthersInfo pointer\r
	286	mov edi, [ebp + 28h]\r
	287	\r
	288	;Store EFLAGS, GDTR and IDTR register to stack\r
	289	pushfd\r
	290	mov eax, cr4\r
	291	push eax ; push cr4 firstly\r
	292	mov eax, cr0\r
	293	push eax\r
	294	\r
	295	sgdt [esi + 8]\r
	296	sidt [esi + 14]\r
	297	\r
	298	; Store the its StackPointer\r
	299	mov [esi + 4],esp\r
	300	\r
	301	; update its switch state to STORED\r
	302	mov byte [esi], CPU_SWITCH_STATE_STORED\r
	303	\r
	304	WaitForOtherStored:\r
	305	; wait until the other CPU finish storing its state\r
	306	cmp byte [edi], CPU_SWITCH_STATE_STORED\r
	307	jz OtherStored\r
	308	pause\r
	309	jmp WaitForOtherStored\r
	310	\r
	311	OtherStored:\r
	312	; Since another CPU already stored its state, load them\r
	313	; load GDTR value\r
	314	lgdt [edi + 8]\r
	315	\r
	316	; load IDTR value\r
	317	lidt [edi + 14]\r
	318	\r
	319	; load its future StackPointer\r
	320	mov esp, [edi + 4]\r
	321	\r
	322	; update the other CPU's switch state to LOADED\r
	323	mov byte [edi], CPU_SWITCH_STATE_LOADED\r
	324	\r
	325	WaitForOtherLoaded:\r
	326	; wait until the other CPU finish loading new state,\r
	327	; otherwise the data in stack may corrupt\r
	328	cmp byte [esi], CPU_SWITCH_STATE_LOADED\r
	329	jz OtherLoaded\r
330	pause\r
331	jmp WaitForOtherLoaded\r
332	\r
333	OtherLoaded:\r
334	; since the other CPU already get the data it want, leave this procedure\r
335	pop eax\r
336	mov cr0, eax\r
337	pop eax\r
338	mov cr4, eax\r
339	popfd\r
340	\r
341	popad\r
342	ret\r