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UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settings
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e50466da 1/** @file\r
2 MTRR setting library\r
3\r
81f56049
JF
4 @par Note: \r
5 Most of services in this library instance are suggested to be invoked by BSP only,\r
6 except for MtrrSetAllMtrrs() which is used to sync BSP's MTRR setting to APs.\r
7\r
341fea64 8 Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc 9 This program and the accompanying materials\r
e50466da 10 are licensed and made available under the terms and conditions of the BSD License\r
11 which accompanies this distribution. The full text of the license may be found at\r
12 http://opensource.org/licenses/bsd-license.php\r
13\r
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
16\r
17**/\r
18\r
2bbd7e2f 19#include <Uefi.h>\r
3bb13d35
RN
20#include <Register/Cpuid.h>\r
21#include <Register/Msr.h>\r
22\r
e50466da 23#include <Library/MtrrLib.h>\r
24#include <Library/BaseLib.h>\r
25#include <Library/CpuLib.h>\r
26#include <Library/BaseMemoryLib.h>\r
27#include <Library/DebugLib.h>\r
28\r
eecad349
JF
29#define OR_SEED 0x0101010101010101ull\r
30#define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull\r
2bbd7e2f
RN
31#define MAX_WEIGHT MAX_UINT8\r
32#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB)\r
8051302a 33#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B);\r
2bbd7e2f
RN
34\r
35#define M(x,y) ((x) * VectorCount + (y))\r
36#define O(x,y) ((y) * VectorCount + (x))\r
37\r
c878cee4 38//\r
39// Context to save and restore when MTRRs are programmed\r
40//\r
41typedef struct {\r
42 UINTN Cr4;\r
43 BOOLEAN InterruptState;\r
44} MTRR_CONTEXT;\r
45\r
8051302a 46typedef struct {\r
2bbd7e2f
RN
47 UINT64 Address;\r
48 UINT64 Alignment;\r
8051302a 49 UINT64 Length;\r
2bbd7e2f
RN
50 UINT8 Type : 7;\r
51\r
52 //\r
53 // Temprary use for calculating the best MTRR settings.\r
54 //\r
55 BOOLEAN Visited : 1;\r
56 UINT8 Weight;\r
57 UINT16 Previous;\r
58} MTRR_LIB_ADDRESS;\r
8051302a 59\r
e50466da 60//\r
61// This table defines the offset, base and length of the fixed MTRRs\r
62//\r
f877f300 63CONST FIXED_MTRR mMtrrLibFixedMtrrTable[] = {\r
e50466da 64 {\r
af838805 65 MSR_IA32_MTRR_FIX64K_00000,\r
e50466da 66 0,\r
67 SIZE_64KB\r
68 },\r
69 {\r
af838805 70 MSR_IA32_MTRR_FIX16K_80000,\r
e50466da 71 0x80000,\r
72 SIZE_16KB\r
73 },\r
74 {\r
af838805 75 MSR_IA32_MTRR_FIX16K_A0000,\r
e50466da 76 0xA0000,\r
77 SIZE_16KB\r
78 },\r
79 {\r
af838805 80 MSR_IA32_MTRR_FIX4K_C0000,\r
e50466da 81 0xC0000,\r
82 SIZE_4KB\r
83 },\r
84 {\r
af838805 85 MSR_IA32_MTRR_FIX4K_C8000,\r
e50466da 86 0xC8000,\r
87 SIZE_4KB\r
88 },\r
89 {\r
af838805 90 MSR_IA32_MTRR_FIX4K_D0000,\r
e50466da 91 0xD0000,\r
92 SIZE_4KB\r
93 },\r
94 {\r
af838805 95 MSR_IA32_MTRR_FIX4K_D8000,\r
e50466da 96 0xD8000,\r
97 SIZE_4KB\r
98 },\r
99 {\r
af838805 100 MSR_IA32_MTRR_FIX4K_E0000,\r
e50466da 101 0xE0000,\r
102 SIZE_4KB\r
103 },\r
104 {\r
af838805 105 MSR_IA32_MTRR_FIX4K_E8000,\r
e50466da 106 0xE8000,\r
107 SIZE_4KB\r
108 },\r
109 {\r
af838805 110 MSR_IA32_MTRR_FIX4K_F0000,\r
e50466da 111 0xF0000,\r
112 SIZE_4KB\r
113 },\r
114 {\r
af838805 115 MSR_IA32_MTRR_FIX4K_F8000,\r
e50466da 116 0xF8000,\r
117 SIZE_4KB\r
76b4cae3 118 }\r
e50466da 119};\r
120\r
f877f300 121//\r
122// Lookup table used to print MTRRs\r
123//\r
124GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {\r
125 "UC", // CacheUncacheable\r
126 "WC", // CacheWriteCombining\r
127 "R*", // Invalid\r
128 "R*", // Invalid\r
129 "WT", // CacheWriteThrough\r
130 "WP", // CacheWriteProtected\r
131 "WB", // CacheWriteBack\r
132 "R*" // Invalid\r
133};\r
134\r
2bbd7e2f
RN
135\r
136/**\r
137 Worker function prints all MTRRs for debugging.\r
138\r
139 If MtrrSetting is not NULL, print MTRR settings from input MTRR\r
140 settings buffer.\r
141 If MtrrSetting is NULL, print MTRR settings from MTRRs.\r
142\r
143 @param MtrrSetting A buffer holding all MTRRs content.\r
144**/\r
145VOID\r
146MtrrDebugPrintAllMtrrsWorker (\r
147 IN MTRR_SETTINGS *MtrrSetting\r
148 );\r
149\r
31b3597e
MK
150/**\r
151 Worker function returns the variable MTRR count for the CPU.\r
152\r
153 @return Variable MTRR count\r
154\r
155**/\r
156UINT32\r
157GetVariableMtrrCountWorker (\r
158 VOID\r
159 )\r
160{\r
386f5785 161 MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
31b3597e 162\r
386f5785 163 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
2bbd7e2f 164 ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *) 0)->Mtrr));\r
386f5785 165 return MtrrCap.Bits.VCNT;\r
31b3597e
MK
166}\r
167\r
3b9be416
JY
168/**\r
169 Returns the variable MTRR count for the CPU.\r
170\r
171 @return Variable MTRR count\r
172\r
173**/\r
174UINT32\r
ed8dfd7b 175EFIAPI\r
3b9be416
JY
176GetVariableMtrrCount (\r
177 VOID\r
178 )\r
179{\r
947a573a 180 if (!IsMtrrSupported ()) {\r
181 return 0;\r
182 }\r
31b3597e 183 return GetVariableMtrrCountWorker ();\r
3b9be416
JY
184}\r
185\r
186/**\r
31b3597e 187 Worker function returns the firmware usable variable MTRR count for the CPU.\r
3b9be416
JY
188\r
189 @return Firmware usable variable MTRR count\r
190\r
191**/\r
192UINT32\r
31b3597e 193GetFirmwareVariableMtrrCountWorker (\r
3b9be416
JY
194 VOID\r
195 )\r
196{\r
947a573a 197 UINT32 VariableMtrrCount;\r
46309b11 198 UINT32 ReservedMtrrNumber;\r
947a573a 199\r
31b3597e 200 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
46309b11
JF
201 ReservedMtrrNumber = PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);\r
202 if (VariableMtrrCount < ReservedMtrrNumber) {\r
947a573a 203 return 0;\r
204 }\r
205\r
46309b11 206 return VariableMtrrCount - ReservedMtrrNumber;\r
3b9be416 207}\r
e50466da 208\r
31b3597e
MK
209/**\r
210 Returns the firmware usable variable MTRR count for the CPU.\r
211\r
212 @return Firmware usable variable MTRR count\r
213\r
214**/\r
215UINT32\r
216EFIAPI\r
217GetFirmwareVariableMtrrCount (\r
218 VOID\r
219 )\r
220{\r
221 if (!IsMtrrSupported ()) {\r
222 return 0;\r
223 }\r
224 return GetFirmwareVariableMtrrCountWorker ();\r
225}\r
226\r
227/**\r
228 Worker function returns the default MTRR cache type for the system.\r
229\r
5abd5ed4
MK
230 If MtrrSetting is not NULL, returns the default MTRR cache type from input\r
231 MTRR settings buffer.\r
232 If MtrrSetting is NULL, returns the default MTRR cache type from MSR.\r
233\r
234 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
235\r
31b3597e
MK
236 @return The default MTRR cache type.\r
237\r
238**/\r
239MTRR_MEMORY_CACHE_TYPE\r
240MtrrGetDefaultMemoryTypeWorker (\r
5abd5ed4 241 IN MTRR_SETTINGS *MtrrSetting\r
31b3597e
MK
242 )\r
243{\r
af838805
RN
244 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
245\r
5abd5ed4 246 if (MtrrSetting == NULL) {\r
af838805 247 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
5abd5ed4 248 } else {\r
af838805 249 DefType.Uint64 = MtrrSetting->MtrrDefType;\r
5abd5ed4 250 }\r
af838805
RN
251\r
252 return (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
31b3597e
MK
253}\r
254\r
255\r
e50466da 256/**\r
257 Returns the default MTRR cache type for the system.\r
258\r
91ec7824 259 @return The default MTRR cache type.\r
e50466da 260\r
261**/\r
91ec7824 262MTRR_MEMORY_CACHE_TYPE\r
263EFIAPI\r
264MtrrGetDefaultMemoryType (\r
e50466da 265 VOID\r
91ec7824 266 )\r
e50466da 267{\r
91ec7824 268 if (!IsMtrrSupported ()) {\r
269 return CacheUncacheable;\r
270 }\r
5abd5ed4 271 return MtrrGetDefaultMemoryTypeWorker (NULL);\r
91ec7824 272}\r
e50466da 273\r
274/**\r
275 Preparation before programming MTRR.\r
276\r
277 This function will do some preparation for programming MTRRs:\r
278 disable cache, invalid cache and disable MTRR caching functionality\r
279\r
a5953380 280 @param[out] MtrrContext Pointer to context to save\r
e50466da 281\r
282**/\r
c878cee4 283VOID\r
b8f01599 284MtrrLibPreMtrrChange (\r
c878cee4 285 OUT MTRR_CONTEXT *MtrrContext\r
e50466da 286 )\r
287{\r
af838805 288 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
c878cee4 289 //\r
290 // Disable interrupts and save current interrupt state\r
291 //\r
292 MtrrContext->InterruptState = SaveAndDisableInterrupts();\r
76b4cae3 293\r
e50466da 294 //\r
295 // Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)\r
296 //\r
58b23d90 297 AsmDisableCache ();\r
298\r
e50466da 299 //\r
58b23d90 300 // Save original CR4 value and clear PGE flag (Bit 7)\r
e50466da 301 //\r
c878cee4 302 MtrrContext->Cr4 = AsmReadCr4 ();\r
303 AsmWriteCr4 (MtrrContext->Cr4 & (~BIT7));\r
58b23d90 304\r
e50466da 305 //\r
306 // Flush all TLBs\r
307 //\r
308 CpuFlushTlb ();\r
58b23d90 309\r
e50466da 310 //\r
76b4cae3 311 // Disable MTRRs\r
e50466da 312 //\r
af838805
RN
313 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
314 DefType.Bits.E = 0;\r
315 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);\r
e50466da 316}\r
317\r
e50466da 318/**\r
319 Cleaning up after programming MTRRs.\r
320\r
321 This function will do some clean up after programming MTRRs:\r
0779e5bf 322 Flush all TLBs, re-enable caching, restore CR4.\r
e50466da 323\r
a5953380 324 @param[in] MtrrContext Pointer to context to restore\r
e50466da 325\r
326**/\r
327VOID\r
b8f01599 328MtrrLibPostMtrrChangeEnableCache (\r
c878cee4 329 IN MTRR_CONTEXT *MtrrContext\r
e50466da 330 )\r
331{\r
e50466da 332 //\r
76b4cae3 333 // Flush all TLBs\r
e50466da 334 //\r
e50466da 335 CpuFlushTlb ();\r
336\r
337 //\r
338 // Enable Normal Mode caching CD=NW=0, CD(Bit30), NW(Bit29)\r
339 //\r
58b23d90 340 AsmEnableCache ();\r
e50466da 341\r
58b23d90 342 //\r
343 // Restore original CR4 value\r
344 //\r
c878cee4 345 AsmWriteCr4 (MtrrContext->Cr4);\r
76b4cae3 346\r
c878cee4 347 //\r
348 // Restore original interrupt state\r
349 //\r
350 SetInterruptState (MtrrContext->InterruptState);\r
e50466da 351}\r
352\r
0779e5bf 353/**\r
354 Cleaning up after programming MTRRs.\r
355\r
356 This function will do some clean up after programming MTRRs:\r
357 enable MTRR caching functionality, and enable cache\r
358\r
a5953380 359 @param[in] MtrrContext Pointer to context to restore\r
0779e5bf 360\r
361**/\r
362VOID\r
b8f01599 363MtrrLibPostMtrrChange (\r
c878cee4 364 IN MTRR_CONTEXT *MtrrContext\r
0779e5bf 365 )\r
366{\r
af838805 367 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
0779e5bf 368 //\r
369 // Enable Cache MTRR\r
370 //\r
af838805
RN
371 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
372 DefType.Bits.E = 1;\r
373 DefType.Bits.FE = 1;\r
374 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);\r
0779e5bf 375\r
b8f01599 376 MtrrLibPostMtrrChangeEnableCache (MtrrContext);\r
0779e5bf 377}\r
378\r
85b7f65b
MK
379/**\r
380 Worker function gets the content in fixed MTRRs\r
381\r
382 @param[out] FixedSettings A buffer to hold fixed MTRRs content.\r
383\r
384 @retval The pointer of FixedSettings\r
385\r
386**/\r
387MTRR_FIXED_SETTINGS*\r
388MtrrGetFixedMtrrWorker (\r
389 OUT MTRR_FIXED_SETTINGS *FixedSettings\r
390 )\r
391{\r
392 UINT32 Index;\r
393\r
394 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
395 FixedSettings->Mtrr[Index] =\r
396 AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
397 }\r
398\r
399 return FixedSettings;\r
400}\r
401\r
402\r
403/**\r
404 This function gets the content in fixed MTRRs\r
405\r
406 @param[out] FixedSettings A buffer to hold fixed MTRRs content.\r
407\r
408 @retval The pointer of FixedSettings\r
409\r
410**/\r
411MTRR_FIXED_SETTINGS*\r
412EFIAPI\r
413MtrrGetFixedMtrr (\r
414 OUT MTRR_FIXED_SETTINGS *FixedSettings\r
415 )\r
416{\r
417 if (!IsMtrrSupported ()) {\r
418 return FixedSettings;\r
419 }\r
420\r
421 return MtrrGetFixedMtrrWorker (FixedSettings);\r
422}\r
423\r
424\r
425/**\r
426 Worker function will get the raw value in variable MTRRs\r
427\r
5abd5ed4
MK
428 If MtrrSetting is not NULL, gets the variable MTRRs raw value from input\r
429 MTRR settings buffer.\r
430 If MtrrSetting is NULL, gets the variable MTRRs raw value from MTRRs.\r
431\r
432 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
433 @param[in] VariableMtrrCount Number of variable MTRRs.\r
85b7f65b
MK
434 @param[out] VariableSettings A buffer to hold variable MTRRs content.\r
435\r
436 @return The VariableSettings input pointer\r
437\r
438**/\r
439MTRR_VARIABLE_SETTINGS*\r
440MtrrGetVariableMtrrWorker (\r
5abd5ed4 441 IN MTRR_SETTINGS *MtrrSetting,\r
acf431e6 442 IN UINT32 VariableMtrrCount,\r
85b7f65b
MK
443 OUT MTRR_VARIABLE_SETTINGS *VariableSettings\r
444 )\r
445{\r
446 UINT32 Index;\r
85b7f65b 447\r
2bbd7e2f 448 ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));\r
85b7f65b
MK
449\r
450 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
5abd5ed4
MK
451 if (MtrrSetting == NULL) {\r
452 VariableSettings->Mtrr[Index].Base =\r
af838805 453 AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));\r
5abd5ed4 454 VariableSettings->Mtrr[Index].Mask =\r
af838805 455 AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));\r
5abd5ed4
MK
456 } else {\r
457 VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base;\r
458 VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask;\r
459 }\r
85b7f65b
MK
460 }\r
461\r
462 return VariableSettings;\r
463}\r
464\r
465/**\r
466 This function will get the raw value in variable MTRRs\r
467\r
468 @param[out] VariableSettings A buffer to hold variable MTRRs content.\r
469\r
470 @return The VariableSettings input pointer\r
471\r
472**/\r
473MTRR_VARIABLE_SETTINGS*\r
474EFIAPI\r
475MtrrGetVariableMtrr (\r
476 OUT MTRR_VARIABLE_SETTINGS *VariableSettings\r
477 )\r
478{\r
479 if (!IsMtrrSupported ()) {\r
480 return VariableSettings;\r
481 }\r
482\r
483 return MtrrGetVariableMtrrWorker (\r
5abd5ed4 484 NULL,\r
acf431e6 485 GetVariableMtrrCountWorker (),\r
85b7f65b
MK
486 VariableSettings\r
487 );\r
488}\r
e50466da 489\r
490/**\r
491 Programs fixed MTRRs registers.\r
492\r
94240f1b 493 @param[in] Type The memory type to set.\r
76b4cae3
MK
494 @param[in, out] Base The base address of memory range.\r
495 @param[in, out] Length The length of memory range.\r
5fbb5ade 496 @param[in, out] LastMsrIndex On input, the last index of the fixed MTRR MSR to program.\r
0f354122 497 On return, the current index of the fixed MTRR MSR to program.\r
5fbb5ade
RN
498 @param[out] ClearMask The bits to clear in the fixed MTRR MSR.\r
499 @param[out] OrMask The bits to set in the fixed MTRR MSR.\r
e50466da 500\r
501 @retval RETURN_SUCCESS The cache type was updated successfully\r
502 @retval RETURN_UNSUPPORTED The requested range or cache type was invalid\r
503 for the fixed MTRRs.\r
504\r
505**/\r
506RETURN_STATUS\r
94240f1b
RN
507MtrrLibProgramFixedMtrr (\r
508 IN MTRR_MEMORY_CACHE_TYPE Type,\r
509 IN OUT UINT64 *Base,\r
510 IN OUT UINT64 *Length,\r
5fbb5ade
RN
511 IN OUT UINT32 *LastMsrIndex,\r
512 OUT UINT64 *ClearMask,\r
513 OUT UINT64 *OrMask\r
e50466da 514 )\r
515{\r
5fbb5ade 516 UINT32 MsrIndex;\r
eecad349
JF
517 UINT32 LeftByteShift;\r
518 UINT32 RightByteShift;\r
07e88920 519 UINT64 SubLength;\r
e50466da 520\r
eecad349
JF
521 //\r
522 // Find the fixed MTRR index to be programmed\r
523 //\r
5fbb5ade
RN
524 for (MsrIndex = *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
525 if ((*Base >= mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) &&\r
e50466da 526 (*Base <\r
527 (\r
5fbb5ade
RN
528 mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +\r
529 (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)\r
e50466da 530 )\r
531 )\r
532 ) {\r
533 break;\r
534 }\r
535 }\r
536\r
5fbb5ade 537 ASSERT (MsrIndex != ARRAY_SIZE (mMtrrLibFixedMtrrTable));\r
e50466da 538\r
539 //\r
eecad349 540 // Find the begin offset in fixed MTRR and calculate byte offset of left shift\r
e50466da 541 //\r
5fbb5ade
RN
542 if ((((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {\r
543 //\r
544 // Base address should be aligned to the begin of a certain Fixed MTRR range.\r
545 //\r
e50466da 546 return RETURN_UNSUPPORTED;\r
547 }\r
5fbb5ade
RN
548 LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) / mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
549 ASSERT (LeftByteShift < 8);\r
e50466da 550\r
eecad349
JF
551 //\r
552 // Find the end offset in fixed MTRR and calculate byte offset of right shift\r
553 //\r
5fbb5ade 554 SubLength = mMtrrLibFixedMtrrTable[MsrIndex].Length * (8 - LeftByteShift);\r
eecad349
JF
555 if (*Length >= SubLength) {\r
556 RightByteShift = 0;\r
07e88920 557 } else {\r
5fbb5ade
RN
558 if (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {\r
559 //\r
560 // Length should be aligned to the end of a certain Fixed MTRR range.\r
561 //\r
eecad349
JF
562 return RETURN_UNSUPPORTED;\r
563 }\r
5fbb5ade 564 RightByteShift = 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
eecad349
JF
565 //\r
566 // Update SubLength by actual length\r
567 //\r
568 SubLength = *Length;\r
e50466da 569 }\r
570\r
5fbb5ade
RN
571 *ClearMask = CLEAR_SEED;\r
572 *OrMask = MultU64x32 (OR_SEED, (UINT32) Type);\r
eecad349
JF
573\r
574 if (LeftByteShift != 0) {\r
575 //\r
576 // Clear the low bits by LeftByteShift\r
577 //\r
5fbb5ade
RN
578 *ClearMask &= LShiftU64 (*ClearMask, LeftByteShift * 8);\r
579 *OrMask &= LShiftU64 (*OrMask, LeftByteShift * 8);\r
eecad349
JF
580 }\r
581\r
582 if (RightByteShift != 0) {\r
583 //\r
584 // Clear the high bits by RightByteShift\r
585 //\r
5fbb5ade
RN
586 *ClearMask &= RShiftU64 (*ClearMask, RightByteShift * 8);\r
587 *OrMask &= RShiftU64 (*OrMask, RightByteShift * 8);\r
e50466da 588 }\r
589\r
07e88920
JF
590 *Length -= SubLength;\r
591 *Base += SubLength;\r
592\r
5fbb5ade 593 *LastMsrIndex = MsrIndex;\r
fa25cf38 594\r
e50466da 595 return RETURN_SUCCESS;\r
596}\r
597\r
598\r
d0baed7d
MK
599/**\r
600 Worker function gets the attribute of variable MTRRs.\r
601\r
602 This function shadows the content of variable MTRRs into an\r
603 internal array: VariableMtrr.\r
604\r
10c361ad
RN
605 @param[in] VariableSettings The variable MTRR values to shadow\r
606 @param[in] VariableMtrrCount The number of variable MTRRs\r
607 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
608 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
609 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
d0baed7d 610\r
10c361ad 611 @return Number of MTRRs which has been used.\r
d0baed7d
MK
612\r
613**/\r
614UINT32\r
615MtrrGetMemoryAttributeInVariableMtrrWorker (\r
616 IN MTRR_VARIABLE_SETTINGS *VariableSettings,\r
10c361ad 617 IN UINTN VariableMtrrCount,\r
d0baed7d
MK
618 IN UINT64 MtrrValidBitsMask,\r
619 IN UINT64 MtrrValidAddressMask,\r
620 OUT VARIABLE_MTRR *VariableMtrr\r
621 )\r
622{\r
623 UINTN Index;\r
624 UINT32 UsedMtrr;\r
625\r
2bbd7e2f 626 ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * ARRAY_SIZE (VariableSettings->Mtrr));\r
10c361ad 627 for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {\r
af838805 628 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
d0baed7d
MK
629 VariableMtrr[Index].Msr = (UINT32)Index;\r
630 VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);\r
2bbd7e2f
RN
631 VariableMtrr[Index].Length =\r
632 ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
d0baed7d
MK
633 VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff);\r
634 VariableMtrr[Index].Valid = TRUE;\r
635 VariableMtrr[Index].Used = TRUE;\r
636 UsedMtrr++;\r
637 }\r
638 }\r
639 return UsedMtrr;\r
640}\r
641\r
2bbd7e2f
RN
642/**\r
643 Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.\r
644 One MTRR_MEMORY_RANGE element is created for each MTRR setting.\r
645 The routine doesn't remove the overlap or combine the near-by region.\r
646\r
647 @param[in] VariableSettings The variable MTRR values to shadow\r
648 @param[in] VariableMtrrCount The number of variable MTRRs\r
649 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
650 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
651 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
652\r
653 @return Number of MTRRs which has been used.\r
654\r
655**/\r
656UINT32\r
657MtrrLibGetRawVariableRanges (\r
658 IN MTRR_VARIABLE_SETTINGS *VariableSettings,\r
659 IN UINTN VariableMtrrCount,\r
660 IN UINT64 MtrrValidBitsMask,\r
661 IN UINT64 MtrrValidAddressMask,\r
662 OUT MTRR_MEMORY_RANGE *VariableMtrr\r
663 )\r
664{\r
665 UINTN Index;\r
666 UINT32 UsedMtrr;\r
667\r
668 ZeroMem (VariableMtrr, sizeof (MTRR_MEMORY_RANGE) * ARRAY_SIZE (VariableSettings->Mtrr));\r
669 for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {\r
670 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
671 VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);\r
672 VariableMtrr[Index].Length =\r
673 ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
674 VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff);\r
675 UsedMtrr++;\r
676 }\r
677 }\r
678 return UsedMtrr;\r
679}\r
d0baed7d 680\r
e50466da 681/**\r
76b4cae3 682 Gets the attribute of variable MTRRs.\r
e50466da 683\r
3ba736f3
JY
684 This function shadows the content of variable MTRRs into an\r
685 internal array: VariableMtrr.\r
e50466da 686\r
76b4cae3
MK
687 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
688 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
689 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
e50466da 690\r
438f1766 691 @return The return value of this parameter indicates the\r
3ba736f3 692 number of MTRRs which has been used.\r
e50466da 693\r
694**/\r
3ba736f3 695UINT32\r
e50466da 696EFIAPI\r
697MtrrGetMemoryAttributeInVariableMtrr (\r
698 IN UINT64 MtrrValidBitsMask,\r
699 IN UINT64 MtrrValidAddressMask,\r
700 OUT VARIABLE_MTRR *VariableMtrr\r
701 )\r
702{\r
d0baed7d 703 MTRR_VARIABLE_SETTINGS VariableSettings;\r
3b9be416 704\r
947a573a 705 if (!IsMtrrSupported ()) {\r
706 return 0;\r
707 }\r
708\r
d0baed7d 709 MtrrGetVariableMtrrWorker (\r
5abd5ed4 710 NULL,\r
d0baed7d
MK
711 GetVariableMtrrCountWorker (),\r
712 &VariableSettings\r
713 );\r
e50466da 714\r
d0baed7d
MK
715 return MtrrGetMemoryAttributeInVariableMtrrWorker (\r
716 &VariableSettings,\r
717 GetFirmwareVariableMtrrCountWorker (),\r
718 MtrrValidBitsMask,\r
719 MtrrValidAddressMask,\r
720 VariableMtrr\r
721 );\r
e50466da 722}\r
723\r
e50466da 724/**\r
1416ecb4
RN
725 Return the biggest alignment (lowest set bit) of address.\r
726 The function is equivalent to: 1 << LowBitSet64 (Address).\r
e50466da 727\r
8051302a
RN
728 @param Address The address to return the alignment.\r
729 @param Alignment0 The alignment to return when Address is 0.\r
e50466da 730\r
8051302a 731 @return The least alignment of the Address.\r
e50466da 732**/\r
8051302a 733UINT64\r
1416ecb4 734MtrrLibBiggestAlignment (\r
8051302a
RN
735 UINT64 Address,\r
736 UINT64 Alignment0\r
737)\r
e50466da 738{\r
8051302a
RN
739 if (Address == 0) {\r
740 return Alignment0;\r
e50466da 741 }\r
742\r
1416ecb4 743 return Address & ((~Address) + 1);\r
e50466da 744}\r
745\r
e50466da 746/**\r
8051302a 747 Return whether the left MTRR type precedes the right MTRR type.\r
76b4cae3 748\r
8051302a 749 The MTRR type precedence rules are:\r
10c361ad
RN
750 1. UC precedes any other type\r
751 2. WT precedes WB\r
752 For further details, please refer the IA32 Software Developer's Manual,\r
753 Volume 3, Section "MTRR Precedences".\r
e50466da 754\r
8051302a
RN
755 @param Left The left MTRR type.\r
756 @param Right The right MTRR type.\r
e50466da 757\r
8051302a
RN
758 @retval TRUE Left precedes Right.\r
759 @retval FALSE Left doesn't precede Right.\r
e50466da 760**/\r
8051302a
RN
761BOOLEAN\r
762MtrrLibTypeLeftPrecedeRight (\r
763 IN MTRR_MEMORY_CACHE_TYPE Left,\r
764 IN MTRR_MEMORY_CACHE_TYPE Right\r
765)\r
e50466da 766{\r
8051302a 767 return (BOOLEAN) (Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));\r
e50466da 768}\r
769\r
e50466da 770/**\r
771 Initializes the valid bits mask and valid address mask for MTRRs.\r
772\r
773 This function initializes the valid bits mask and valid address mask for MTRRs.\r
774\r
76b4cae3
MK
775 @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
776 @param[out] MtrrValidAddressMask The valid address mask for the MTRR\r
e50466da 777\r
778**/\r
e50466da 779VOID\r
780MtrrLibInitializeMtrrMask (\r
781 OUT UINT64 *MtrrValidBitsMask,\r
782 OUT UINT64 *MtrrValidAddressMask\r
783 )\r
784{\r
012f4054
RN
785 UINT32 MaxExtendedFunction;\r
786 CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;\r
e50466da 787\r
e50466da 788\r
012f4054 789 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);\r
e50466da 790\r
012f4054
RN
791 if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
792 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);\r
e50466da 793 } else {\r
012f4054 794 VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
e50466da 795 }\r
012f4054
RN
796\r
797 *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
798 *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;\r
e50466da 799}\r
800\r
801\r
802/**\r
76b4cae3 803 Determines the real attribute of a memory range.\r
e50466da 804\r
805 This function is to arbitrate the real attribute of the memory when\r
10c361ad 806 there are 2 MTRRs covers the same memory range. For further details,\r
e50466da 807 please refer the IA32 Software Developer's Manual, Volume 3,\r
10c361ad 808 Section "MTRR Precedences".\r
e50466da 809\r
76b4cae3
MK
810 @param[in] MtrrType1 The first kind of Memory type\r
811 @param[in] MtrrType2 The second kind of memory type\r
e50466da 812\r
813**/\r
10c361ad 814MTRR_MEMORY_CACHE_TYPE\r
b8f01599 815MtrrLibPrecedence (\r
10c361ad
RN
816 IN MTRR_MEMORY_CACHE_TYPE MtrrType1,\r
817 IN MTRR_MEMORY_CACHE_TYPE MtrrType2\r
e50466da 818 )\r
819{\r
10c361ad
RN
820 if (MtrrType1 == MtrrType2) {\r
821 return MtrrType1;\r
e50466da 822 }\r
823\r
10c361ad
RN
824 ASSERT (\r
825 MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) ||\r
826 MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1)\r
827 );\r
828\r
829 if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) {\r
830 return MtrrType1;\r
831 } else {\r
832 return MtrrType2;\r
e50466da 833 }\r
e50466da 834}\r
835\r
e50466da 836/**\r
5abd5ed4 837 Worker function will get the memory cache type of the specific address.\r
e50466da 838\r
5abd5ed4
MK
839 If MtrrSetting is not NULL, gets the memory cache type from input\r
840 MTRR settings buffer.\r
841 If MtrrSetting is NULL, gets the memory cache type from MTRRs.\r
e50466da 842\r
5abd5ed4 843 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
85b7f65b
MK
844 @param[in] Address The specific address\r
845\r
846 @return Memory cache type of the specific address\r
e50466da 847\r
848**/\r
85b7f65b 849MTRR_MEMORY_CACHE_TYPE\r
5abd5ed4
MK
850MtrrGetMemoryAttributeByAddressWorker (\r
851 IN MTRR_SETTINGS *MtrrSetting,\r
85b7f65b 852 IN PHYSICAL_ADDRESS Address\r
e50466da 853 )\r
854{\r
10c361ad
RN
855 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
856 UINT64 FixedMtrr;\r
857 UINTN Index;\r
858 UINTN SubIndex;\r
859 MTRR_MEMORY_CACHE_TYPE MtrrType;\r
2bbd7e2f 860 MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
10c361ad
RN
861 UINT64 MtrrValidBitsMask;\r
862 UINT64 MtrrValidAddressMask;\r
863 UINT32 VariableMtrrCount;\r
864 MTRR_VARIABLE_SETTINGS VariableSettings;\r
f877f300 865\r
e50466da 866 //\r
85b7f65b 867 // Check if MTRR is enabled, if not, return UC as attribute\r
e50466da 868 //\r
5abd5ed4 869 if (MtrrSetting == NULL) {\r
10c361ad 870 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
5abd5ed4 871 } else {\r
10c361ad 872 DefType.Uint64 = MtrrSetting->MtrrDefType;\r
5abd5ed4 873 }\r
e50466da 874\r
10c361ad 875 if (DefType.Bits.E == 0) {\r
85b7f65b 876 return CacheUncacheable;\r
e50466da 877 }\r
878\r
879 //\r
85b7f65b 880 // If address is less than 1M, then try to go through the fixed MTRR\r
e50466da 881 //\r
85b7f65b 882 if (Address < BASE_1MB) {\r
10c361ad 883 if (DefType.Bits.FE != 0) {\r
85b7f65b
MK
884 //\r
885 // Go through the fixed MTRR\r
886 //\r
887 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
10c361ad
RN
888 if (Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress &&\r
889 Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +\r
890 (mMtrrLibFixedMtrrTable[Index].Length * 8)) {\r
891 SubIndex =\r
892 ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /\r
893 mMtrrLibFixedMtrrTable[Index].Length;\r
894 if (MtrrSetting == NULL) {\r
895 FixedMtrr = AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
896 } else {\r
897 FixedMtrr = MtrrSetting->Fixed.Mtrr[Index];\r
898 }\r
899 return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);\r
900 }\r
85b7f65b 901 }\r
e50466da 902 }\r
903 }\r
d0baed7d 904\r
10c361ad 905 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
2bbd7e2f 906 ASSERT (VariableMtrrCount <= ARRAY_SIZE (MtrrSetting->Variables.Mtrr));\r
10c361ad 907 MtrrGetVariableMtrrWorker (MtrrSetting, VariableMtrrCount, &VariableSettings);\r
e50466da 908\r
10c361ad 909 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
2bbd7e2f 910 MtrrLibGetRawVariableRanges (\r
10c361ad
RN
911 &VariableSettings,\r
912 VariableMtrrCount,\r
913 MtrrValidBitsMask,\r
914 MtrrValidAddressMask,\r
915 VariableMtrr\r
916 );\r
d0baed7d 917\r
e50466da 918 //\r
85b7f65b 919 // Go through the variable MTRR\r
e50466da 920 //\r
10c361ad 921 MtrrType = CacheInvalid;\r
85b7f65b 922 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
2bbd7e2f 923 if (VariableMtrr[Index].Length != 0) {\r
85b7f65b 924 if (Address >= VariableMtrr[Index].BaseAddress &&\r
10c361ad
RN
925 Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length) {\r
926 if (MtrrType == CacheInvalid) {\r
927 MtrrType = (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type;\r
928 } else {\r
929 MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type);\r
930 }\r
85b7f65b
MK
931 }\r
932 }\r
e50466da 933 }\r
934\r
10c361ad
RN
935 //\r
936 // If there is no MTRR which covers the Address, use the default MTRR type.\r
937 //\r
938 if (MtrrType == CacheInvalid) {\r
939 MtrrType = (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
940 }\r
941\r
942 return MtrrType;\r
85b7f65b
MK
943}\r
944\r
945\r
5abd5ed4
MK
946/**\r
947 This function will get the memory cache type of the specific address.\r
948\r
949 This function is mainly for debug purpose.\r
950\r
951 @param[in] Address The specific address\r
952\r
953 @return Memory cache type of the specific address\r
954\r
955**/\r
956MTRR_MEMORY_CACHE_TYPE\r
957EFIAPI\r
958MtrrGetMemoryAttribute (\r
959 IN PHYSICAL_ADDRESS Address\r
960 )\r
961{\r
962 if (!IsMtrrSupported ()) {\r
963 return CacheUncacheable;\r
964 }\r
965\r
966 return MtrrGetMemoryAttributeByAddressWorker (NULL, Address);\r
967}\r
968\r
8051302a
RN
969/**\r
970 Update the Ranges array to change the specified range identified by\r
971 BaseAddress and Length to Type.\r
972\r
973 @param Ranges Array holding memory type settings for all memory regions.\r
974 @param Capacity The maximum count of memory ranges the array can hold.\r
975 @param Count Return the new memory range count in the array.\r
976 @param BaseAddress The base address of the memory range to change type.\r
977 @param Length The length of the memory range to change type.\r
978 @param Type The new type of the specified memory range.\r
979\r
980 @retval RETURN_SUCCESS The type of the specified memory range is\r
981 changed successfully.\r
2bbd7e2f
RN
982 @retval RETURN_ALREADY_STARTED The type of the specified memory range equals\r
983 to the desired type.\r
8051302a
RN
984 @retval RETURN_OUT_OF_RESOURCES The new type set causes the count of memory\r
985 range exceeds capacity.\r
986**/\r
987RETURN_STATUS\r
988MtrrLibSetMemoryType (\r
2bbd7e2f
RN
989 IN MTRR_MEMORY_RANGE *Ranges,\r
990 IN UINTN Capacity,\r
991 IN OUT UINTN *Count,\r
8051302a
RN
992 IN UINT64 BaseAddress,\r
993 IN UINT64 Length,\r
994 IN MTRR_MEMORY_CACHE_TYPE Type\r
995 )\r
996{\r
2bbd7e2f 997 UINTN Index;\r
8051302a
RN
998 UINT64 Limit;\r
999 UINT64 LengthLeft;\r
1000 UINT64 LengthRight;\r
2bbd7e2f
RN
1001 UINTN StartIndex;\r
1002 UINTN EndIndex;\r
1003 UINTN DeltaCount;\r
8051302a 1004\r
4ef6c385
RN
1005 LengthRight = 0;\r
1006 LengthLeft = 0;\r
8051302a
RN
1007 Limit = BaseAddress + Length;\r
1008 StartIndex = *Count;\r
1009 EndIndex = *Count;\r
1010 for (Index = 0; Index < *Count; Index++) {\r
1011 if ((StartIndex == *Count) &&\r
1012 (Ranges[Index].BaseAddress <= BaseAddress) &&\r
1013 (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
1014 StartIndex = Index;\r
1015 LengthLeft = BaseAddress - Ranges[Index].BaseAddress;\r
1016 }\r
1017\r
1018 if ((EndIndex == *Count) &&\r
1019 (Ranges[Index].BaseAddress < Limit) &&\r
1020 (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
1021 EndIndex = Index;\r
1022 LengthRight = Ranges[Index].BaseAddress + Ranges[Index].Length - Limit;\r
1023 break;\r
1024 }\r
1025 }\r
1026\r
1027 ASSERT (StartIndex != *Count && EndIndex != *Count);\r
1028 if (StartIndex == EndIndex && Ranges[StartIndex].Type == Type) {\r
2bbd7e2f 1029 return RETURN_ALREADY_STARTED;\r
8051302a
RN
1030 }\r
1031\r
1032 //\r
1033 // The type change may cause merging with previous range or next range.\r
1034 // Update the StartIndex, EndIndex, BaseAddress, Length so that following\r
1035 // logic doesn't need to consider merging.\r
1036 //\r
1037 if (StartIndex != 0) {\r
1038 if (LengthLeft == 0 && Ranges[StartIndex - 1].Type == Type) {\r
1039 StartIndex--;\r
1040 Length += Ranges[StartIndex].Length;\r
1041 BaseAddress -= Ranges[StartIndex].Length;\r
1042 }\r
1043 }\r
1044 if (EndIndex != (*Count) - 1) {\r
1045 if (LengthRight == 0 && Ranges[EndIndex + 1].Type == Type) {\r
1046 EndIndex++;\r
1047 Length += Ranges[EndIndex].Length;\r
1048 }\r
1049 }\r
1050\r
1051 //\r
1052 // |- 0 -|- 1 -|- 2 -|- 3 -| StartIndex EndIndex DeltaCount Count (Count = 4)\r
1053 // |++++++++++++++++++| 0 3 1=3-0-2 3\r
1054 // |+++++++| 0 1 -1=1-0-2 5\r
1055 // |+| 0 0 -2=0-0-2 6\r
1056 // |+++| 0 0 -1=0-0-2+1 5\r
1057 //\r
1058 //\r
1059 DeltaCount = EndIndex - StartIndex - 2;\r
1060 if (LengthLeft == 0) {\r
1061 DeltaCount++;\r
1062 }\r
1063 if (LengthRight == 0) {\r
1064 DeltaCount++;\r
1065 }\r
1066 if (*Count - DeltaCount > Capacity) {\r
1067 return RETURN_OUT_OF_RESOURCES;\r
1068 }\r
1069\r
1070 //\r
1071 // Reserve (-DeltaCount) space\r
1072 //\r
1073 CopyMem (&Ranges[EndIndex + 1 - DeltaCount], &Ranges[EndIndex + 1], (*Count - EndIndex - 1) * sizeof (Ranges[0]));\r
1074 *Count -= DeltaCount;\r
1075\r
1076 if (LengthLeft != 0) {\r
1077 Ranges[StartIndex].Length = LengthLeft;\r
1078 StartIndex++;\r
1079 }\r
1080 if (LengthRight != 0) {\r
1081 Ranges[EndIndex - DeltaCount].BaseAddress = BaseAddress + Length;\r
1082 Ranges[EndIndex - DeltaCount].Length = LengthRight;\r
1083 Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type;\r
1084 }\r
1085 Ranges[StartIndex].BaseAddress = BaseAddress;\r
1086 Ranges[StartIndex].Length = Length;\r
1087 Ranges[StartIndex].Type = Type;\r
1088 return RETURN_SUCCESS;\r
1089}\r
1090\r
1091/**\r
2bbd7e2f 1092 Return the number of memory types in range [BaseAddress, BaseAddress + Length).\r
8051302a 1093\r
2bbd7e2f
RN
1094 @param Ranges Array holding memory type settings for all memory regions.\r
1095 @param RangeCount The count of memory ranges the array holds.\r
1096 @param BaseAddress Base address.\r
1097 @param Length Length.\r
1098 @param Types Return bit mask to indicate all memory types in the specified range.\r
8051302a 1099\r
2bbd7e2f 1100 @retval Number of memory types.\r
8051302a 1101**/\r
2bbd7e2f
RN
1102UINT8\r
1103MtrrLibGetNumberOfTypes (\r
1104 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1105 IN UINTN RangeCount,\r
1106 IN UINT64 BaseAddress,\r
1107 IN UINT64 Length,\r
1108 IN OUT UINT8 *Types OPTIONAL\r
1109 )\r
1110{\r
1111 UINTN Index;\r
1112 UINT8 TypeCount;\r
1113 UINT8 LocalTypes;\r
1114\r
1115 TypeCount = 0;\r
1116 LocalTypes = 0;\r
1117 for (Index = 0; Index < RangeCount; Index++) {\r
1118 if ((Ranges[Index].BaseAddress <= BaseAddress) &&\r
1119 (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)\r
1120 ) {\r
1121 if ((LocalTypes & (1 << Ranges[Index].Type)) == 0) {\r
1122 LocalTypes |= (UINT8)(1 << Ranges[Index].Type);\r
1123 TypeCount++;\r
1124 }\r
1125\r
1126 if (BaseAddress + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
1127 Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;\r
1128 BaseAddress = Ranges[Index].BaseAddress + Ranges[Index].Length;\r
1129 } else {\r
1130 break;\r
1131 }\r
1132 }\r
1133 }\r
1134\r
1135 if (Types != NULL) {\r
1136 *Types = LocalTypes;\r
1137 }\r
1138 return TypeCount;\r
1139}\r
8051302a
RN
1140\r
1141/**\r
2bbd7e2f
RN
1142 Calculate the least MTRR number from vector Start to Stop and update\r
1143 the Previous of all vectors from Start to Stop is updated to reflect\r
1144 how the memory range is covered by MTRR.\r
1145\r
1146 @param VectorCount The count of vectors in the graph.\r
1147 @param Vector Array holding all vectors.\r
1148 @param Weight 2-dimention array holding weights between vectors.\r
1149 @param Start Start vector.\r
1150 @param Stop Stop vector.\r
1151 @param IncludeOptional TRUE to count the optional weight.\r
1152**/\r
1153VOID\r
1154MtrrLibCalculateLeastMtrrs (\r
1155 IN UINT16 VectorCount,\r
1156 IN MTRR_LIB_ADDRESS *Vector,\r
1157 IN OUT CONST UINT8 *Weight,\r
1158 IN UINT16 Start,\r
1159 IN UINT16 Stop,\r
1160 IN BOOLEAN IncludeOptional\r
1161 )\r
1162{\r
1163 UINT16 Index;\r
1164 UINT8 MinWeight;\r
1165 UINT16 MinI;\r
1166 UINT8 Mandatory;\r
1167 UINT8 Optional;\r
1168\r
1169 for (Index = Start; Index <= Stop; Index++) {\r
1170 Vector[Index].Visited = FALSE;\r
1171 Vector[Index].Previous = VectorCount;\r
1172 Mandatory = Weight[M(Start,Index)];\r
1173 Vector[Index].Weight = Mandatory;\r
1174 if (Mandatory != MAX_WEIGHT) {\r
1175 Optional = IncludeOptional ? Weight[O(Start, Index)] : 0;\r
1176 Vector[Index].Weight += Optional;\r
1177 ASSERT (Vector[Index].Weight >= Optional);\r
1178 }\r
1179 }\r
8051302a 1180\r
2bbd7e2f
RN
1181 MinI = Start;\r
1182 MinWeight = 0;\r
1183 while (!Vector[Stop].Visited) {\r
1184 //\r
1185 // Update the weight from the shortest vector to other unvisited vectors\r
1186 //\r
1187 for (Index = Start + 1; Index <= Stop; Index++) {\r
1188 if (!Vector[Index].Visited) {\r
1189 Mandatory = Weight[M(MinI, Index)];\r
1190 if (Mandatory != MAX_WEIGHT) {\r
1191 Optional = IncludeOptional ? Weight[O(MinI, Index)] : 0;\r
1192 if (MinWeight + Mandatory + Optional <= Vector[Index].Weight) {\r
1193 Vector[Index].Weight = MinWeight + Mandatory + Optional;\r
1194 Vector[Index].Previous = MinI; // Previous is Start based.\r
1195 }\r
1196 }\r
1197 }\r
1198 }\r
8051302a 1199\r
2bbd7e2f
RN
1200 //\r
1201 // Find the shortest vector from Start\r
1202 //\r
1203 MinI = VectorCount;\r
1204 MinWeight = MAX_WEIGHT;\r
1205 for (Index = Start + 1; Index <= Stop; Index++) {\r
1206 if (!Vector[Index].Visited && MinWeight > Vector[Index].Weight) {\r
1207 MinI = Index;\r
1208 MinWeight = Vector[Index].Weight;\r
1209 }\r
1210 }\r
8051302a 1211\r
2bbd7e2f
RN
1212 //\r
1213 // Mark the shortest vector from Start as visited\r
1214 //\r
1215 Vector[MinI].Visited = TRUE;\r
1216 }\r
1217}\r
1218\r
1219/**\r
1220 Append the MTRR setting to MTRR setting array.\r
1221\r
1222 @param Mtrrs Array holding all MTRR settings.\r
1223 @param MtrrCapacity Capacity of the MTRR array.\r
1224 @param MtrrCount The count of MTRR settings in array.\r
1225 @param BaseAddress Base address.\r
1226 @param Length Length.\r
1227 @param Type Memory type.\r
1228\r
1229 @retval RETURN_SUCCESS MTRR setting is appended to array.\r
1230 @retval RETURN_OUT_OF_RESOURCES Array is full.\r
8051302a
RN
1231**/\r
1232RETURN_STATUS\r
2bbd7e2f
RN
1233MtrrLibAppendVariableMtrr (\r
1234 IN OUT MTRR_MEMORY_RANGE *Mtrrs,\r
1235 IN UINT32 MtrrCapacity,\r
1236 IN OUT UINT32 *MtrrCount,\r
1237 IN UINT64 BaseAddress,\r
1238 IN UINT64 Length,\r
1239 IN MTRR_MEMORY_CACHE_TYPE Type\r
1240 )\r
1241{\r
1242 if (*MtrrCount == MtrrCapacity) {\r
1243 return RETURN_OUT_OF_RESOURCES;\r
1244 }\r
1245\r
1246 Mtrrs[*MtrrCount].BaseAddress = BaseAddress;\r
1247 Mtrrs[*MtrrCount].Length = Length;\r
1248 Mtrrs[*MtrrCount].Type = Type;\r
1249 (*MtrrCount)++;\r
1250 return RETURN_SUCCESS;\r
1251}\r
1252\r
1253/**\r
1254 Return the memory type that has the least precedence.\r
1255\r
1256 @param TypeBits Bit mask of memory type.\r
1257\r
1258 @retval Memory type that has the least precedence.\r
1259**/\r
1260MTRR_MEMORY_CACHE_TYPE\r
1261MtrrLibLowestType (\r
1262 IN UINT8 TypeBits\r
8051302a
RN
1263)\r
1264{\r
2bbd7e2f 1265 INT8 Type;\r
8051302a 1266\r
2bbd7e2f
RN
1267 ASSERT (TypeBits != 0);\r
1268 for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1);\r
1269 return (MTRR_MEMORY_CACHE_TYPE)Type;\r
1270}\r
8051302a 1271\r
2bbd7e2f
RN
1272/**\r
1273 Return TRUE when the Operand is exactly power of 2.\r
1274\r
1275 @retval TRUE Operand is exactly power of 2.\r
1276 @retval FALSE Operand is not power of 2.\r
1277**/\r
1278BOOLEAN\r
1279MtrrLibIsPowerOfTwo (\r
1280 IN UINT64 Operand\r
1281)\r
1282{\r
1283 ASSERT (Operand != 0);\r
1284 return (BOOLEAN) ((Operand & (Operand - 1)) == 0);\r
1285}\r
1286\r
1287/**\r
1288 Calculate the subtractive path from vector Start to Stop.\r
1289\r
1290 @param DefaultType Default memory type.\r
1291 @param A0 Alignment to use when base address is 0.\r
1292 @param Ranges Array holding memory type settings for all memory regions.\r
1293 @param RangeCount The count of memory ranges the array holds.\r
1294 @param VectorCount The count of vectors in the graph.\r
1295 @param Vector Array holding all vectors.\r
1296 @param Weight 2-dimention array holding weights between vectors.\r
1297 @param Start Start vector.\r
1298 @param Stop Stop vector.\r
1299 @param Types Type bit mask of memory range from Start to Stop.\r
1300 @param TypeCount Number of different memory types from Start to Stop.\r
1301 @param Mtrrs Array holding all MTRR settings.\r
1302 @param MtrrCapacity Capacity of the MTRR array.\r
1303 @param MtrrCount The count of MTRR settings in array.\r
1304\r
1305 @retval RETURN_SUCCESS The subtractive path is calculated successfully.\r
1306 @retval RETURN_OUT_OF_RESOURCES The MTRR setting array is full.\r
1307\r
1308**/\r
1309RETURN_STATUS\r
1310MtrrLibCalculateSubtractivePath (\r
1311 IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
1312 IN UINT64 A0,\r
1313 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1314 IN UINTN RangeCount,\r
1315 IN UINT16 VectorCount,\r
1316 IN MTRR_LIB_ADDRESS *Vector,\r
1317 IN OUT UINT8 *Weight,\r
1318 IN UINT16 Start,\r
1319 IN UINT16 Stop,\r
1320 IN UINT8 Types,\r
1321 IN UINT8 TypeCount,\r
1322 IN OUT MTRR_MEMORY_RANGE *Mtrrs, OPTIONAL\r
1323 IN UINT32 MtrrCapacity, OPTIONAL\r
1324 IN OUT UINT32 *MtrrCount OPTIONAL\r
1325 )\r
1326{\r
1327 RETURN_STATUS Status;\r
1328 UINT64 Base;\r
1329 UINT64 Length;\r
1330 UINT8 PrecedentTypes;\r
1331 UINTN Index;\r
1332 UINT64 HBase;\r
1333 UINT64 HLength;\r
1334 UINT64 SubLength;\r
1335 UINT16 SubStart;\r
1336 UINT16 SubStop;\r
1337 UINT16 Cur;\r
1338 UINT16 Pre;\r
1339 MTRR_MEMORY_CACHE_TYPE LowestType;\r
1340 MTRR_MEMORY_CACHE_TYPE LowestPrecedentType;\r
1341\r
1342 Base = Vector[Start].Address;\r
1343 Length = Vector[Stop].Address - Base;\r
1344\r
1345 LowestType = MtrrLibLowestType (Types);\r
1346\r
1347 //\r
1348 // Clear the lowest type (highest bit) to get the precedent types\r
1349 //\r
1350 PrecedentTypes = ~(1 << LowestType) & Types;\r
1351 LowestPrecedentType = MtrrLibLowestType (PrecedentTypes);\r
1352\r
1353 if (Mtrrs == NULL) {\r
1354 Weight[M(Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1);\r
1355 Weight[O(Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0);\r
1356 }\r
1357\r
1358 // Add all high level ranges\r
1359 HBase = MAX_UINT64;\r
1360 HLength = 0;\r
1361 for (Index = 0; Index < RangeCount; Index++) {\r
1362 if (Length == 0) {\r
1363 break;\r
1364 }\r
1365 if ((Base < Ranges[Index].BaseAddress) || (Ranges[Index].BaseAddress + Ranges[Index].Length <= Base)) {\r
1366 continue;\r
8051302a
RN
1367 }\r
1368\r
1369 //\r
2bbd7e2f 1370 // Base is in the Range[Index]\r
8051302a 1371 //\r
2bbd7e2f
RN
1372 if (Base + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
1373 SubLength = Ranges[Index].BaseAddress + Ranges[Index].Length - Base;\r
1374 } else {\r
1375 SubLength = Length;\r
1376 }\r
1377 if (((1 << Ranges[Index].Type) & PrecedentTypes) != 0) {\r
1378 //\r
1379 // Meet a range whose types take precedence.\r
1380 // Update the [HBase, HBase + HLength) to include the range,\r
1381 // [HBase, HBase + HLength) may contain sub ranges with 2 different types, and both take precedence.\r
1382 //\r
1383 if (HBase == MAX_UINT64) {\r
1384 HBase = Base;\r
8051302a 1385 }\r
2bbd7e2f 1386 HLength += SubLength;\r
8051302a 1387 }\r
2bbd7e2f
RN
1388\r
1389 Base += SubLength;\r
1390 Length -= SubLength;\r
1391\r
1392 if (HLength == 0) {\r
1393 continue;\r
1394 }\r
1395\r
1396 if ((Ranges[Index].Type == LowestType) || (Length == 0)) { // meet low type or end\r
1397\r
1398 //\r
1399 // Add the MTRRs for each high priority type range\r
1400 // the range[HBase, HBase + HLength) contains only two types.\r
1401 // We might use positive or subtractive, depending on which way uses less MTRR\r
1402 //\r
1403 for (SubStart = Start; SubStart <= Stop; SubStart++) {\r
1404 if (Vector[SubStart].Address == HBase) {\r
1405 break;\r
1406 }\r
8051302a 1407 }\r
2bbd7e2f
RN
1408\r
1409 for (SubStop = SubStart; SubStop <= Stop; SubStop++) {\r
1410 if (Vector[SubStop].Address == HBase + HLength) {\r
1411 break;\r
1412 }\r
1413 }\r
1414 ASSERT (Vector[SubStart].Address == HBase);\r
1415 ASSERT (Vector[SubStop].Address == HBase + HLength);\r
1416\r
1417 if ((TypeCount == 2) || (SubStart == SubStop - 1)) {\r
1418 //\r
1419 // add subtractive MTRRs for [HBase, HBase + HLength)\r
1420 // [HBase, HBase + HLength) contains only one type.\r
1421 // while - loop is to split the range to MTRR - compliant aligned range.\r
1422 //\r
1423 if (Mtrrs == NULL) {\r
1424 Weight[M (Start, Stop)] += (UINT8)(SubStop - SubStart);\r
1425 } else {\r
1426 while (SubStart != SubStop) {\r
1427 Status = MtrrLibAppendVariableMtrr (\r
1428 Mtrrs, MtrrCapacity, MtrrCount,\r
1429 Vector[SubStart].Address, Vector[SubStart].Length, (MTRR_MEMORY_CACHE_TYPE) Vector[SubStart].Type\r
1430 );\r
1431 if (RETURN_ERROR (Status)) {\r
1432 return Status;\r
1433 }\r
1434 SubStart++;\r
1435 }\r
1436 }\r
1437 } else {\r
1438 ASSERT (TypeCount == 3);\r
1439 MtrrLibCalculateLeastMtrrs (VectorCount, Vector, Weight, SubStart, SubStop, TRUE);\r
1440\r
1441 if (Mtrrs == NULL) {\r
1442 Weight[M (Start, Stop)] += Vector[SubStop].Weight;\r
1443 } else {\r
1444 // When we need to collect the optimal path from SubStart to SubStop\r
1445 while (SubStop != SubStart) {\r
1446 Cur = SubStop;\r
1447 Pre = Vector[Cur].Previous;\r
1448 SubStop = Pre;\r
1449\r
1450 if (Weight[M (Pre, Cur)] != 0) {\r
1451 Status = MtrrLibAppendVariableMtrr (\r
1452 Mtrrs, MtrrCapacity, MtrrCount,\r
1453 Vector[Pre].Address, Vector[Cur].Address - Vector[Pre].Address, LowestPrecedentType\r
1454 );\r
1455 if (RETURN_ERROR (Status)) {\r
1456 return Status;\r
1457 }\r
1458 }\r
1459 if (Pre != Cur - 1) {\r
1460 Status = MtrrLibCalculateSubtractivePath (\r
1461 DefaultType, A0,\r
1462 Ranges, RangeCount,\r
1463 VectorCount, Vector, Weight,\r
1464 Pre, Cur, PrecedentTypes, 2,\r
1465 Mtrrs, MtrrCapacity, MtrrCount\r
1466 );\r
1467 if (RETURN_ERROR (Status)) {\r
1468 return Status;\r
1469 }\r
1470 }\r
1471 }\r
1472 }\r
1473\r
1474 }\r
1475 //\r
1476 // Reset HBase, HLength\r
1477 //\r
1478 HBase = MAX_UINT64;\r
1479 HLength = 0;\r
8051302a 1480 }\r
8051302a 1481 }\r
2bbd7e2f 1482 return RETURN_SUCCESS;\r
8051302a
RN
1483}\r
1484\r
1485/**\r
2bbd7e2f
RN
1486 Calculate MTRR settings to cover the specified memory ranges.\r
1487\r
1488 @param DefaultType Default memory type.\r
1489 @param A0 Alignment to use when base address is 0.\r
1490 @param Ranges Memory range array holding the memory type\r
1491 settings for all memory address.\r
1492 @param RangeCount Count of memory ranges.\r
1493 @param Scratch A temporary scratch buffer that is used to perform the calculation.\r
1494 This is an optional parameter that may be NULL.\r
1495 @param ScratchSize Pointer to the size in bytes of the scratch buffer.\r
1496 It may be updated to the actual required size when the calculation\r
1497 needs more scratch buffer.\r
1498 @param Mtrrs Array holding all MTRR settings.\r
1499 @param MtrrCapacity Capacity of the MTRR array.\r
1500 @param MtrrCount The count of MTRR settings in array.\r
8051302a
RN
1501\r
1502 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.\r
1503 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.\r
2bbd7e2f 1504 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
8051302a
RN
1505**/\r
1506RETURN_STATUS\r
2bbd7e2f
RN
1507MtrrLibCalculateMtrrs (\r
1508 IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
1509 IN UINT64 A0,\r
1510 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1511 IN UINTN RangeCount,\r
1512 IN VOID *Scratch,\r
1513 IN OUT UINTN *ScratchSize,\r
1514 IN OUT MTRR_MEMORY_RANGE *Mtrrs,\r
1515 IN UINT32 MtrrCapacity,\r
1516 IN OUT UINT32 *MtrrCount\r
1517 )\r
8051302a 1518{\r
2bbd7e2f
RN
1519 UINT64 Base0;\r
1520 UINT64 Base1;\r
1521 UINTN Index;\r
1522 UINT64 Base;\r
1523 UINT64 Length;\r
8051302a 1524 UINT64 Alignment;\r
2bbd7e2f
RN
1525 UINT64 SubLength;\r
1526 MTRR_LIB_ADDRESS *Vector;\r
1527 UINT8 *Weight;\r
1528 UINT32 VectorIndex;\r
1529 UINT32 VectorCount;\r
1530 UINTN RequiredScratchSize;\r
1531 UINT8 TypeCount;\r
1532 UINT16 Start;\r
1533 UINT16 Stop;\r
1534 UINT8 Type;\r
1535 RETURN_STATUS Status;\r
3ff1e898 1536\r
2bbd7e2f
RN
1537 Base0 = Ranges[0].BaseAddress;\r
1538 Base1 = Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length;\r
1539 MTRR_LIB_ASSERT_ALIGNED (Base0, Base1 - Base0);\r
8051302a 1540\r
2bbd7e2f
RN
1541 //\r
1542 // Count the number of vectors.\r
1543 //\r
1544 Vector = (MTRR_LIB_ADDRESS*)Scratch;\r
1545 for (VectorIndex = 0, Index = 0; Index < RangeCount; Index++) {\r
1546 Base = Ranges[Index].BaseAddress;\r
1547 Length = Ranges[Index].Length;\r
1548 while (Length != 0) {\r
1549 Alignment = MtrrLibBiggestAlignment (Base, A0);\r
1550 SubLength = Alignment;\r
1551 if (SubLength > Length) {\r
1552 SubLength = GetPowerOfTwo64 (Length);\r
1553 }\r
1554 if (VectorIndex < *ScratchSize / sizeof (*Vector)) {\r
1555 Vector[VectorIndex].Address = Base;\r
1556 Vector[VectorIndex].Alignment = Alignment;\r
1557 Vector[VectorIndex].Type = Ranges[Index].Type;\r
1558 Vector[VectorIndex].Length = SubLength;\r
1559 }\r
1560 Base += SubLength;\r
1561 Length -= SubLength;\r
1562 VectorIndex++;\r
1563 }\r
8051302a 1564 }\r
2bbd7e2f
RN
1565 //\r
1566 // Vector[VectorIndex] = Base1, so whole vector count is (VectorIndex + 1).\r
1567 //\r
1568 VectorCount = VectorIndex + 1;\r
1569 DEBUG ((\r
1570 DEBUG_CACHE, "VectorCount (%016lx - %016lx) = %d\n", \r
1571 Ranges[0].BaseAddress, Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length, VectorCount\r
1572 ));\r
1573 ASSERT (VectorCount < MAX_UINT16);\r
8051302a 1574\r
2bbd7e2f
RN
1575 RequiredScratchSize = VectorCount * sizeof (*Vector) + VectorCount * VectorCount * sizeof (*Weight);\r
1576 if (*ScratchSize < RequiredScratchSize) {\r
1577 *ScratchSize = RequiredScratchSize;\r
1578 return RETURN_BUFFER_TOO_SMALL;\r
8051302a 1579 }\r
2bbd7e2f 1580 Vector[VectorCount - 1].Address = Base1;\r
8051302a 1581\r
2bbd7e2f
RN
1582 Weight = (UINT8 *) &Vector[VectorCount];\r
1583 //\r
1584 // Set mandatory weight between any vector to max\r
1585 // Set optional weight and between any vector and self->self to 0\r
1586 // E.g.:\r
1587 // 00 FF FF FF\r
1588 // 00 00 FF FF\r
1589 // 00 00 00 FF\r
1590 // 00 00 00 00\r
1591 //\r
1592 for (VectorIndex = 0; VectorIndex < VectorCount; VectorIndex++) {\r
1593 SetMem (&Weight[M(VectorIndex, 0)], VectorIndex + 1, 0);\r
1594 if (VectorIndex != VectorCount - 1) {\r
1595 Weight[M (VectorIndex, VectorIndex + 1)] = (DefaultType == Vector[VectorIndex].Type) ? 0 : 1;\r
1596 SetMem (&Weight[M (VectorIndex, VectorIndex + 2)], VectorCount - VectorIndex - 2, MAX_WEIGHT);\r
8051302a 1597 }\r
8051302a
RN
1598 }\r
1599\r
2bbd7e2f
RN
1600 for (TypeCount = 2; TypeCount <= 3; TypeCount++) {\r
1601 for (Start = 0; Start < VectorCount; Start++) {\r
1602 for (Stop = Start + 2; Stop < VectorCount; Stop++) {\r
1603 ASSERT (Vector[Stop].Address > Vector[Start].Address);\r
1604 Length = Vector[Stop].Address - Vector[Start].Address;\r
1605 if (Length > Vector[Start].Alignment) {\r
1606 //\r
1607 // Pickup a new Start when [Start, Stop) cannot be described by one MTRR.\r
1608 //\r
1609 break;\r
1610 }\r
1611 if ((Weight[M(Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) {\r
1612 if (MtrrLibGetNumberOfTypes (\r
1613 Ranges, RangeCount, Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address, &Type\r
1614 ) == TypeCount) {\r
1615 //\r
1616 // Update the Weight[Start, Stop] using subtractive path.\r
1617 //\r
1618 MtrrLibCalculateSubtractivePath (\r
1619 DefaultType, A0,\r
1620 Ranges, RangeCount,\r
1621 (UINT16)VectorCount, Vector, Weight,\r
1622 Start, Stop, Type, TypeCount,\r
1623 NULL, 0, NULL\r
1624 );\r
1625 } else if (TypeCount == 2) {\r
1626 //\r
1627 // Pick up a new Start when we expect 2-type range, but 3-type range is met.\r
1628 // Because no matter how Stop is increased, we always meet 3-type range.\r
1629 //\r
1630 break;\r
1631 }\r
1632 }\r
1633 }\r
1634 }\r
8051302a
RN
1635 }\r
1636\r
2bbd7e2f
RN
1637 Status = RETURN_SUCCESS;\r
1638 MtrrLibCalculateLeastMtrrs ((UINT16) VectorCount, Vector, Weight, 0, (UINT16) VectorCount - 1, FALSE);\r
1639 Stop = (UINT16) VectorCount - 1;\r
1640 while (Stop != 0) {\r
1641 Start = Vector[Stop].Previous;\r
1642 TypeCount = MAX_UINT8;\r
1643 Type = 0;\r
1644 if (Weight[M(Start, Stop)] != 0) {\r
1645 TypeCount = MtrrLibGetNumberOfTypes (Ranges, RangeCount, Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address, &Type);\r
1646 Status = MtrrLibAppendVariableMtrr (\r
1647 Mtrrs, MtrrCapacity, MtrrCount,\r
1648 Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address, \r
1649 MtrrLibLowestType (Type)\r
1650 );\r
1651 if (RETURN_ERROR (Status)) {\r
1652 break;\r
8051302a
RN
1653 }\r
1654 }\r
1655\r
2bbd7e2f
RN
1656 if (Start != Stop - 1) {\r
1657 //\r
1658 // substractive path\r
1659 //\r
1660 if (TypeCount == MAX_UINT8) {\r
1661 TypeCount = MtrrLibGetNumberOfTypes (\r
1662 Ranges, RangeCount, Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address, &Type\r
1663 );\r
1664 }\r
1665 Status = MtrrLibCalculateSubtractivePath (\r
1666 DefaultType, A0,\r
1667 Ranges, RangeCount,\r
1668 (UINT16) VectorCount, Vector, Weight, Start, Stop,\r
1669 Type, TypeCount,\r
1670 Mtrrs, MtrrCapacity, MtrrCount\r
1671 );\r
1672 if (RETURN_ERROR (Status)) {\r
1673 break;\r
1674 }\r
8051302a 1675 }\r
2bbd7e2f
RN
1676 Stop = Start;\r
1677 }\r
1678 return Status;\r
1679}\r
1680\r
8051302a 1681\r
2bbd7e2f
RN
1682/**\r
1683 Apply the variable MTRR settings to memory range array.\r
1684\r
1685 @param Fixed The fixed MTRR settings.\r
1686 @param Ranges Return the memory range array holding memory type\r
1687 settings for all memory address.\r
1688 @param RangeCapacity The capacity of memory range array.\r
1689 @param RangeCount Return the count of memory range.\r
1690\r
1691 @retval RETURN_SUCCESS The memory range array is returned successfully.\r
1692 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.\r
1693**/\r
1694RETURN_STATUS\r
1695MtrrLibApplyFixedMtrrs (\r
1696 IN MTRR_FIXED_SETTINGS *Fixed,\r
1697 IN OUT MTRR_MEMORY_RANGE *Ranges,\r
1698 IN UINTN RangeCapacity,\r
1699 IN OUT UINTN *RangeCount\r
1700 )\r
1701{\r
1702 RETURN_STATUS Status;\r
1703 UINTN MsrIndex;\r
1704 UINTN Index;\r
1705 MTRR_MEMORY_CACHE_TYPE MemoryType;\r
1706 UINT64 Base;\r
1707\r
1708 Base = 0;\r
1709 for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
1710 ASSERT (Base == mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress);\r
1711 for (Index = 0; Index < sizeof (UINT64); Index++) {\r
1712 MemoryType = (MTRR_MEMORY_CACHE_TYPE)((UINT8 *)(&Fixed->Mtrr[MsrIndex]))[Index];\r
1713 Status = MtrrLibSetMemoryType (\r
1714 Ranges, RangeCapacity, RangeCount, Base, mMtrrLibFixedMtrrTable[MsrIndex].Length, MemoryType\r
1715 );\r
1716 if (Status == RETURN_OUT_OF_RESOURCES) {\r
1717 return Status;\r
1718 }\r
1719 Base += mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
1720 }\r
8051302a 1721 }\r
2bbd7e2f 1722 ASSERT (Base == BASE_1MB);\r
8051302a
RN
1723 return RETURN_SUCCESS;\r
1724}\r
1725\r
1726/**\r
2bbd7e2f 1727 Apply the variable MTRR settings to memory range array.\r
8051302a 1728\r
8051302a
RN
1729 @param VariableMtrr The variable MTRR array.\r
1730 @param VariableMtrrCount The count of variable MTRRs.\r
2bbd7e2f 1731 @param Ranges Return the memory range array with new MTRR settings applied.\r
8051302a
RN
1732 @param RangeCapacity The capacity of memory range array.\r
1733 @param RangeCount Return the count of memory range.\r
1734\r
1735 @retval RETURN_SUCCESS The memory range array is returned successfully.\r
1736 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.\r
1737**/\r
1738RETURN_STATUS\r
2bbd7e2f
RN
1739MtrrLibApplyVariableMtrrs (\r
1740 IN CONST MTRR_MEMORY_RANGE *VariableMtrr,\r
1741 IN UINT32 VariableMtrrCount,\r
1742 IN OUT MTRR_MEMORY_RANGE *Ranges,\r
1743 IN UINTN RangeCapacity,\r
1744 IN OUT UINTN *RangeCount\r
1745 )\r
8051302a
RN
1746{\r
1747 RETURN_STATUS Status;\r
1748 UINTN Index;\r
1749\r
1750 //\r
1751 // WT > WB\r
1752 // UC > *\r
1753 // UC > * (except WB, UC) > WB\r
1754 //\r
1755\r
8051302a
RN
1756 //\r
1757 // 1. Set WB\r
1758 //\r
1759 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
2bbd7e2f 1760 if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheWriteBack)) {\r
8051302a
RN
1761 Status = MtrrLibSetMemoryType (\r
1762 Ranges, RangeCapacity, RangeCount,\r
2bbd7e2f 1763 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
8051302a 1764 );\r
2bbd7e2f 1765 if (Status == RETURN_OUT_OF_RESOURCES) {\r
8051302a
RN
1766 return Status;\r
1767 }\r
1768 }\r
1769 }\r
1770\r
1771 //\r
1772 // 2. Set other types than WB or UC\r
1773 //\r
1774 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
2bbd7e2f
RN
1775 if ((VariableMtrr[Index].Length != 0) && \r
1776 (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable)) {\r
8051302a 1777 Status = MtrrLibSetMemoryType (\r
2bbd7e2f
RN
1778 Ranges, RangeCapacity, RangeCount,\r
1779 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
1780 );\r
1781 if (Status == RETURN_OUT_OF_RESOURCES) {\r
8051302a
RN
1782 return Status;\r
1783 }\r
1784 }\r
1785 }\r
1786\r
1787 //\r
1788 // 3. Set UC\r
1789 //\r
1790 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
2bbd7e2f 1791 if (VariableMtrr[Index].Length != 0 && VariableMtrr[Index].Type == CacheUncacheable) {\r
8051302a 1792 Status = MtrrLibSetMemoryType (\r
2bbd7e2f
RN
1793 Ranges, RangeCapacity, RangeCount,\r
1794 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
1795 );\r
1796 if (Status == RETURN_OUT_OF_RESOURCES) {\r
8051302a
RN
1797 return Status;\r
1798 }\r
1799 }\r
1800 }\r
1801 return RETURN_SUCCESS;\r
1802}\r
16c2d37e 1803\r
85b7f65b 1804/**\r
2bbd7e2f 1805 Return the memory type bit mask that's compatible to first type in the Ranges.\r
85b7f65b 1806\r
2bbd7e2f
RN
1807 @param Ranges Memory range array holding the memory type\r
1808 settings for all memory address.\r
1809 @param RangeCount Count of memory ranges.\r
b970ed68 1810\r
2bbd7e2f
RN
1811 @return Compatible memory type bit mask.\r
1812**/\r
1813UINT8\r
1814MtrrLibGetCompatibleTypes (\r
1815 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1816 IN UINTN RangeCount\r
1817 )\r
1818{\r
1819 ASSERT (RangeCount != 0);\r
1820\r
1821 switch (Ranges[0].Type) {\r
1822 case CacheWriteBack:\r
1823 case CacheWriteThrough:\r
1824 return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable);\r
1825 break;\r
1826\r
1827 case CacheWriteCombining:\r
1828 case CacheWriteProtected:\r
1829 return (1 << Ranges[0].Type) | (1 << CacheUncacheable);\r
1830 break;\r
1831\r
1832 case CacheUncacheable:\r
1833 if (RangeCount == 1) {\r
1834 return (1 << CacheUncacheable);\r
1835 }\r
1836 return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1);\r
1837 break;\r
85b7f65b 1838\r
2bbd7e2f
RN
1839 case CacheInvalid:\r
1840 default:\r
1841 ASSERT (FALSE);\r
1842 break;\r
1843 }\r
1844 return 0;\r
1845}\r
85b7f65b 1846\r
2bbd7e2f
RN
1847/**\r
1848 Overwrite the destination MTRR settings with the source MTRR settings.\r
1849 This routine is to make sure the modification to destination MTRR settings\r
1850 is as small as possible.\r
1851\r
1852 @param DstMtrrs Destination MTRR settings.\r
1853 @param DstMtrrCount Count of destination MTRR settings.\r
1854 @param SrcMtrrs Source MTRR settings.\r
1855 @param SrcMtrrCount Count of source MTRR settings.\r
1856 @param Modified Flag array to indicate which destination MTRR setting is modified.\r
85b7f65b 1857**/\r
2bbd7e2f
RN
1858VOID\r
1859MtrrLibMergeVariableMtrr (\r
1860 MTRR_MEMORY_RANGE *DstMtrrs,\r
1861 UINT32 DstMtrrCount,\r
1862 MTRR_MEMORY_RANGE *SrcMtrrs,\r
1863 UINT32 SrcMtrrCount,\r
1864 BOOLEAN *Modified\r
85b7f65b
MK
1865 )\r
1866{\r
2bbd7e2f
RN
1867 UINT32 DstIndex;\r
1868 UINT32 SrcIndex;\r
8051302a 1869\r
2bbd7e2f 1870 ASSERT (SrcMtrrCount <= DstMtrrCount);\r
8051302a 1871\r
2bbd7e2f
RN
1872 for (DstIndex = 0; DstIndex < DstMtrrCount; DstIndex++) {\r
1873 Modified[DstIndex] = FALSE;\r
85b7f65b 1874\r
2bbd7e2f
RN
1875 if (DstMtrrs[DstIndex].Length == 0) {\r
1876 continue;\r
1877 }\r
1878 for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {\r
1879 if (DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress &&\r
1880 DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length &&\r
1881 DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type) {\r
1882 break;\r
1883 }\r
1884 }\r
85b7f65b 1885\r
2bbd7e2f
RN
1886 if (SrcIndex == SrcMtrrCount) {\r
1887 //\r
1888 // Remove the one from DstMtrrs which is not in SrcMtrrs\r
1889 //\r
1890 DstMtrrs[DstIndex].Length = 0;\r
1891 Modified[DstIndex] = TRUE;\r
1892 } else {\r
1893 //\r
1894 // Remove the one from SrcMtrrs which is also in DstMtrrs\r
1895 //\r
1896 SrcMtrrs[SrcIndex].Length = 0;\r
1897 }\r
85b7f65b
MK
1898 }\r
1899\r
2bbd7e2f
RN
1900 //\r
1901 // Now valid MTRR only exists in either DstMtrrs or SrcMtrrs.\r
1902 // Merge MTRRs from SrcMtrrs to DstMtrrs\r
1903 //\r
1904 DstIndex = 0;\r
1905 for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {\r
1906 if (SrcMtrrs[SrcIndex].Length != 0) {\r
85b7f65b 1907\r
2bbd7e2f
RN
1908 //\r
1909 // Find the empty slot in DstMtrrs\r
1910 //\r
1911 while (DstIndex < DstMtrrCount) {\r
1912 if (DstMtrrs[DstIndex].Length == 0) {\r
1913 break;\r
1914 }\r
1915 DstIndex++;\r
1916 }\r
1917 ASSERT (DstIndex < DstMtrrCount);\r
1918 CopyMem (&DstMtrrs[DstIndex], &SrcMtrrs[SrcIndex], sizeof (SrcMtrrs[0]));\r
1919 Modified[DstIndex] = TRUE;\r
1920 }\r
85b7f65b 1921 }\r
2bbd7e2f
RN
1922}\r
1923\r
1924/**\r
1925 Calculate the variable MTRR settings for all memory ranges.\r
85b7f65b 1926\r
2bbd7e2f
RN
1927 @param DefaultType Default memory type.\r
1928 @param A0 Alignment to use when base address is 0.\r
1929 @param Ranges Memory range array holding the memory type\r
1930 settings for all memory address.\r
1931 @param RangeCount Count of memory ranges.\r
1932 @param Scratch Scratch buffer to be used in MTRR calculation.\r
1933 @param ScratchSize Pointer to the size of scratch buffer.\r
1934 @param VariableMtrr Array holding all MTRR settings.\r
1935 @param VariableMtrrCapacity Capacity of the MTRR array.\r
1936 @param VariableMtrrCount The count of MTRR settings in array.\r
1937\r
1938 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.\r
1939 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.\r
1940 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
1941 The required scratch buffer size is returned through ScratchSize.\r
1942**/\r
1943RETURN_STATUS\r
1944MtrrLibSetMemoryRanges (\r
1945 IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
1946 IN UINT64 A0,\r
1947 IN MTRR_MEMORY_RANGE *Ranges,\r
1948 IN UINTN RangeCount,\r
1949 IN VOID *Scratch,\r
1950 IN OUT UINTN *ScratchSize,\r
1951 OUT MTRR_MEMORY_RANGE *VariableMtrr,\r
1952 IN UINT32 VariableMtrrCapacity,\r
1953 OUT UINT32 *VariableMtrrCount\r
1954 )\r
1955{\r
1956 RETURN_STATUS Status;\r
1957 UINT32 Index;\r
1958 UINT64 Base0;\r
1959 UINT64 Base1;\r
1960 UINT64 Alignment;\r
1961 UINT8 CompatibleTypes;\r
1962 UINT64 Length;\r
1963 UINT32 End;\r
1964 UINTN ActualScratchSize;\r
1965 UINTN BiggestScratchSize;\r
1966\r
1967 *VariableMtrrCount = 0;\r
1968 \r
85b7f65b 1969 //\r
2bbd7e2f
RN
1970 // Since the whole ranges need multiple calls of MtrrLibCalculateMtrrs().\r
1971 // Each call needs different scratch buffer size.\r
1972 // When the provided scratch buffer size is not sufficient in any call,\r
1973 // set the GetActualScratchSize to TRUE, and following calls will only\r
1974 // calculate the actual scratch size for the caller.\r
85b7f65b 1975 //\r
2bbd7e2f
RN
1976 BiggestScratchSize = 0;\r
1977\r
1978 for (Index = 0; Index < RangeCount;) {\r
1979 Base0 = Ranges[Index].BaseAddress;\r
1980\r
1981 //\r
1982 // Full step is optimal\r
1983 //\r
1984 while (Index < RangeCount) {\r
1985 ASSERT (Ranges[Index].BaseAddress == Base0);\r
1986 Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
1987 while (Base0 + Alignment <= Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
1988 if ((BiggestScratchSize <= *ScratchSize) && (Ranges[Index].Type != DefaultType)) {\r
1989 Status = MtrrLibAppendVariableMtrr (\r
1990 VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
1991 Base0, Alignment, Ranges[Index].Type\r
1992 );\r
1993 if (RETURN_ERROR (Status)) {\r
1994 return Status;\r
1995 }\r
1996 }\r
1997 Base0 += Alignment;\r
1998 Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
fa25cf38 1999 }\r
2bbd7e2f
RN
2000\r
2001 //\r
2002 // Remove the above range from Ranges[Index]\r
2003 //\r
2004 Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress;\r
2005 Ranges[Index].BaseAddress = Base0;\r
2006 if (Ranges[Index].Length != 0) {\r
2007 break;\r
b970ed68 2008 } else {\r
2bbd7e2f 2009 Index++;\r
fa25cf38 2010 }\r
85b7f65b 2011 }\r
85b7f65b 2012\r
2bbd7e2f
RN
2013 if (Index == RangeCount) {\r
2014 break;\r
2015 }\r
2016\r
2017 //\r
2018 // Find continous ranges [Base0, Base1) which could be combined by MTRR.\r
2019 // Per SDM, the compatible types between[B0, B1) are:\r
2020 // UC, *\r
2021 // WB, WT\r
2022 // UC, WB, WT\r
2023 //\r
2024 CompatibleTypes = MtrrLibGetCompatibleTypes (&Ranges[Index], RangeCount - Index);\r
2025\r
2026 End = Index; // End points to last one that matches the CompatibleTypes.\r
2027 while (End + 1 < RangeCount) {\r
2028 if (((1 << Ranges[End + 1].Type) & CompatibleTypes) == 0) {\r
2029 break;\r
2030 }\r
2031 End++;\r
2032 }\r
2033 Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
2034 Length = GetPowerOfTwo64 (Ranges[End].BaseAddress + Ranges[End].Length - Base0);\r
2035 Base1 = Base0 + MIN (Alignment, Length);\r
2036\r
2037 //\r
2038 // Base1 may not in Ranges[End]. Update End to the range Base1 belongs to.\r
2039 //\r
2040 End = Index;\r
2041 while (End + 1 < RangeCount) {\r
2042 if (Base1 <= Ranges[End + 1].BaseAddress) {\r
2043 break;\r
2044 }\r
2045 End++;\r
2046 }\r
2047\r
2048 Length = Ranges[End].Length;\r
2049 Ranges[End].Length = Base1 - Ranges[End].BaseAddress;\r
2050 ActualScratchSize = *ScratchSize;\r
2051 Status = MtrrLibCalculateMtrrs (\r
2052 DefaultType, A0,\r
2053 &Ranges[Index], End + 1 - Index,\r
2054 Scratch, &ActualScratchSize,\r
2055 VariableMtrr, VariableMtrrCapacity, VariableMtrrCount\r
2056 );\r
2057 if (Status == RETURN_BUFFER_TOO_SMALL) {\r
2058 BiggestScratchSize = MAX (BiggestScratchSize, ActualScratchSize);\r
fa25cf38 2059 //\r
2bbd7e2f
RN
2060 // Ignore this error, because we need to calculate the biggest\r
2061 // scratch buffer size.\r
fa25cf38 2062 //\r
2bbd7e2f
RN
2063 Status = RETURN_SUCCESS;\r
2064 }\r
2065 if (RETURN_ERROR (Status)) {\r
2066 return Status;\r
2067 }\r
2068\r
2069 if (Length != Ranges[End].Length) {\r
2070 Ranges[End].BaseAddress = Base1;\r
2071 Ranges[End].Length = Length - Ranges[End].Length;\r
2072 Index = End;\r
2073 } else {\r
2074 Index = End + 1;\r
fa25cf38 2075 }\r
85b7f65b
MK
2076 }\r
2077\r
2bbd7e2f
RN
2078 if (*ScratchSize < BiggestScratchSize) {\r
2079 *ScratchSize = BiggestScratchSize;\r
2080 return RETURN_BUFFER_TOO_SMALL;\r
2081 }\r
2082 return RETURN_SUCCESS;\r
2083}\r
85b7f65b 2084\r
2bbd7e2f
RN
2085/**\r
2086 Set the below-1MB memory attribute to fixed MTRR buffer.\r
2087 Modified flag array indicates which fixed MTRR is modified.\r
2088\r
2089 @param [in, out] FixedSettings Fixed MTRR buffer.\r
2090 @param [out] Modified Flag array indicating which MTRR is modified.\r
2091 @param [in] BaseAddress Base address.\r
2092 @param [in] Length Length.\r
2093 @param [in] Type Memory type.\r
2094\r
2095 @retval RETURN_SUCCESS The memory attribute is set successfully.\r
2096 @retval RETURN_UNSUPPORTED The requested range or cache type was invalid\r
2097 for the fixed MTRRs.\r
2098**/\r
2099RETURN_STATUS\r
2100MtrrLibSetBelow1MBMemoryAttribute (\r
2101 IN OUT MTRR_FIXED_SETTINGS *FixedSettings,\r
2102 OUT BOOLEAN *Modified,\r
2103 IN PHYSICAL_ADDRESS BaseAddress,\r
2104 IN UINT64 Length,\r
2105 IN MTRR_MEMORY_CACHE_TYPE Type\r
2106 )\r
2107{\r
2108 RETURN_STATUS Status;\r
2109 UINT32 MsrIndex;\r
2110 UINT64 ClearMask;\r
2111 UINT64 OrMask;\r
2112 UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
2113 UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
2114\r
2115 ASSERT (BaseAddress < BASE_1MB);\r
2116\r
2117 MsrIndex = (UINT32)-1;\r
2118 while ((BaseAddress < BASE_1MB) && (Length != 0)) {\r
2119 Status = MtrrLibProgramFixedMtrr (Type, &BaseAddress, &Length, &MsrIndex, &ClearMask, &OrMask);\r
2120 if (RETURN_ERROR (Status)) {\r
2121 return Status;\r
2122 }\r
2123 ClearMasks[MsrIndex] = ClearMask;\r
2124 OrMasks[MsrIndex] = OrMask;\r
2125 Modified[MsrIndex] = TRUE;\r
e50466da 2126 }\r
8051302a 2127\r
2bbd7e2f
RN
2128 for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
2129 if (Modified[MsrIndex]) {\r
2130 FixedSettings->Mtrr[MsrIndex] = (FixedSettings->Mtrr[MsrIndex] & ~ClearMasks[MsrIndex]) | OrMasks[MsrIndex];\r
2131 }\r
2132 }\r
2133 return RETURN_SUCCESS;\r
2134}\r
2135\r
2136/**\r
2137 This function attempts to set the attributes into MTRR setting buffer for multiple memory ranges.\r
8051302a 2138\r
2bbd7e2f
RN
2139 @param[in, out] MtrrSetting MTRR setting buffer to be set.\r
2140 @param[in] Scratch A temporary scratch buffer that is used to perform the calculation.\r
2141 @param[in, out] ScratchSize Pointer to the size in bytes of the scratch buffer.\r
2142 It may be updated to the actual required size when the calculation\r
2143 needs more scratch buffer.\r
2144 @param[in] Ranges Pointer to an array of MTRR_MEMORY_RANGE.\r
2145 When range overlap happens, the last one takes higher priority.\r
2146 When the function returns, either all the attributes are set successfully,\r
2147 or none of them is set.\r
2148 @param[in] Count of MTRR_MEMORY_RANGE.\r
2149\r
2150 @retval RETURN_SUCCESS The attributes were set for all the memory ranges.\r
2151 @retval RETURN_INVALID_PARAMETER Length in any range is zero.\r
2152 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the\r
2153 memory resource range specified by BaseAddress and Length in any range.\r
2154 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource\r
2155 range specified by BaseAddress and Length in any range.\r
2156 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
2157 the memory resource ranges.\r
2158 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by\r
2159 BaseAddress and Length cannot be modified.\r
2160 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
2161**/\r
2162RETURN_STATUS\r
2163EFIAPI\r
2164MtrrSetMemoryAttributesInMtrrSettings (\r
2165 IN OUT MTRR_SETTINGS *MtrrSetting,\r
2166 IN VOID *Scratch,\r
2167 IN OUT UINTN *ScratchSize,\r
2168 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
2169 IN UINTN RangeCount\r
2170 )\r
2171{\r
2172 RETURN_STATUS Status;\r
2173 UINT32 Index;\r
2174 UINT64 BaseAddress;\r
2175 UINT64 Length;\r
2176 BOOLEAN Above1MbExist;\r
2177\r
2178 UINT64 MtrrValidBitsMask;\r
2179 UINT64 MtrrValidAddressMask;\r
2180 MTRR_MEMORY_CACHE_TYPE DefaultType;\r
2181 MTRR_VARIABLE_SETTINGS VariableSettings;\r
2182 MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2];\r
2183 UINTN WorkingRangeCount;\r
2184 BOOLEAN Modified;\r
2185 MTRR_VARIABLE_SETTING VariableSetting;\r
2186 UINT32 OriginalVariableMtrrCount;\r
2187 UINT32 FirmwareVariableMtrrCount;\r
2188 UINT32 WorkingVariableMtrrCount;\r
2189 MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
2190 MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
2191 BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
2192\r
2193 BOOLEAN FixedSettingsModified[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
2194 MTRR_FIXED_SETTINGS WorkingFixedSettings;\r
2195\r
2196 MTRR_CONTEXT MtrrContext;\r
2197 BOOLEAN MtrrContextValid;\r
2198\r
2199 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
e50466da 2200\r
2201 //\r
2bbd7e2f 2202 // TRUE indicating the accordingly Variable setting needs modificaiton in OriginalVariableMtrr.\r
e50466da 2203 //\r
2bbd7e2f 2204 SetMem (VariableSettingModified, ARRAY_SIZE (VariableSettingModified), FALSE);\r
8051302a 2205 //\r
2bbd7e2f 2206 // TRUE indicating the accordingly Fixed setting needs modification in WorkingFixedSettings.\r
8051302a 2207 //\r
2bbd7e2f
RN
2208 SetMem (FixedSettingsModified, ARRAY_SIZE (FixedSettingsModified), FALSE);\r
2209\r
2210 //\r
2211 // TRUE indicating the caller requests to set variable MTRRs.\r
2212 //\r
2213 Above1MbExist = FALSE;\r
2214 OriginalVariableMtrrCount = 0;\r
e50466da 2215\r
2bbd7e2f
RN
2216 //\r
2217 // 1. Validate the parameters.\r
2218 //\r
8051302a 2219 for (Index = 0; Index < RangeCount; Index++) {\r
2bbd7e2f
RN
2220 if (Ranges[Index].Length == 0) {\r
2221 return RETURN_INVALID_PARAMETER;\r
2222 }\r
2223 if (((Ranges[Index].BaseAddress & ~MtrrValidAddressMask) != 0) ||\r
2224 ((Ranges[Index].Length & ~MtrrValidAddressMask) != 0)\r
2225 ) {\r
2226 return RETURN_UNSUPPORTED;\r
2227 }\r
2228 if ((Ranges[Index].Type != CacheUncacheable) &&\r
2229 (Ranges[Index].Type != CacheWriteCombining) &&\r
2230 (Ranges[Index].Type != CacheWriteThrough) &&\r
2231 (Ranges[Index].Type != CacheWriteProtected) &&\r
2232 (Ranges[Index].Type != CacheWriteBack)) {\r
2233 return RETURN_INVALID_PARAMETER;\r
2234 }\r
2235 if (Ranges[Index].BaseAddress + Ranges[Index].Length > BASE_1MB) {\r
2236 Above1MbExist = TRUE;\r
8051302a 2237 }\r
1a2ad6fc 2238 }\r
e50466da 2239\r
1a2ad6fc 2240 //\r
2bbd7e2f 2241 // 2. Apply the above-1MB memory attribute settings.\r
1a2ad6fc 2242 //\r
2bbd7e2f
RN
2243 if (Above1MbExist) {\r
2244 //\r
2245 // 2.1. Read all variable MTRRs and convert to Ranges.\r
2246 //\r
2247 OriginalVariableMtrrCount = GetVariableMtrrCountWorker ();\r
2248 MtrrGetVariableMtrrWorker (MtrrSetting, OriginalVariableMtrrCount, &VariableSettings);\r
2249 MtrrLibGetRawVariableRanges (\r
2250 &VariableSettings, OriginalVariableMtrrCount,\r
2251 MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr\r
2252 );\r
1a2ad6fc 2253\r
2bbd7e2f
RN
2254 DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);\r
2255 WorkingRangeCount = 1;\r
2256 WorkingRanges[0].BaseAddress = 0;\r
2257 WorkingRanges[0].Length = MtrrValidBitsMask + 1;\r
2258 WorkingRanges[0].Type = DefaultType;\r
1a2ad6fc 2259\r
2bbd7e2f
RN
2260 Status = MtrrLibApplyVariableMtrrs (\r
2261 OriginalVariableMtrr, OriginalVariableMtrrCount,\r
2262 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount);\r
2263 ASSERT_RETURN_ERROR (Status);\r
1a2ad6fc 2264\r
2bbd7e2f
RN
2265 ASSERT (OriginalVariableMtrrCount >= PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs));\r
2266 FirmwareVariableMtrrCount = OriginalVariableMtrrCount - PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);\r
2267 ASSERT (WorkingRangeCount <= 2 * FirmwareVariableMtrrCount + 1);\r
1a2ad6fc 2268\r
8051302a 2269 //\r
2bbd7e2f 2270 // 2.2. Force [0, 1M) to UC, so that it doesn't impact subtraction algorithm.\r
8051302a 2271 //\r
2bbd7e2f
RN
2272 Status = MtrrLibSetMemoryType (\r
2273 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,\r
2274 0, SIZE_1MB, CacheUncacheable\r
2275 );\r
2276 ASSERT (Status != RETURN_OUT_OF_RESOURCES);\r
8051302a 2277\r
2bbd7e2f
RN
2278 //\r
2279 // 2.3. Apply the new memory attribute settings to Ranges.\r
2280 //\r
2281 Modified = FALSE;\r
2282 for (Index = 0; Index < RangeCount; Index++) {\r
2283 BaseAddress = Ranges[Index].BaseAddress;\r
2284 Length = Ranges[Index].Length;\r
2285 if (BaseAddress < BASE_1MB) {\r
2286 if (Length <= BASE_1MB - BaseAddress) {\r
2287 continue;\r
1a2ad6fc 2288 }\r
2bbd7e2f
RN
2289 Length -= BASE_1MB - BaseAddress;\r
2290 BaseAddress = BASE_1MB;\r
1a2ad6fc 2291 }\r
2bbd7e2f
RN
2292 Status = MtrrLibSetMemoryType (\r
2293 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,\r
2294 BaseAddress, Length, Ranges[Index].Type\r
2295 );\r
2296 if (Status == RETURN_ALREADY_STARTED) {\r
2297 Status = RETURN_SUCCESS;\r
2298 } else if (Status == RETURN_OUT_OF_RESOURCES) {\r
2299 return Status;\r
8051302a 2300 } else {\r
2bbd7e2f
RN
2301 ASSERT_RETURN_ERROR (Status);\r
2302 Modified = TRUE;\r
8051302a 2303 }\r
1a2ad6fc 2304 }\r
1a2ad6fc 2305\r
2bbd7e2f
RN
2306 if (Modified) {\r
2307 //\r
2308 // 2.4. Calculate the Variable MTRR settings based on the Ranges.\r
2309 // Buffer Too Small may be returned if the scratch buffer size is insufficient.\r
2310 //\r
2311 Status = MtrrLibSetMemoryRanges (\r
2312 DefaultType, LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)), WorkingRanges, WorkingRangeCount,\r
2313 Scratch, ScratchSize,\r
2314 WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariableMtrrCount\r
2315 );\r
2316 if (RETURN_ERROR (Status)) {\r
2317 return Status;\r
2318 }\r
e50466da 2319\r
2bbd7e2f
RN
2320 //\r
2321 // 2.5. Remove the [0, 1MB) MTRR if it still exists (not merged with other range)\r
2322 //\r
2323 for (Index = 0; Index < WorkingVariableMtrrCount; Index++) {\r
2324 if (WorkingVariableMtrr[Index].BaseAddress == 0 && WorkingVariableMtrr[Index].Length == SIZE_1MB) {\r
2325 ASSERT (WorkingVariableMtrr[Index].Type == CacheUncacheable);\r
2326 WorkingVariableMtrrCount--;\r
2327 CopyMem (\r
2328 &WorkingVariableMtrr[Index], &WorkingVariableMtrr[Index + 1],\r
2329 (WorkingVariableMtrrCount - Index) * sizeof (WorkingVariableMtrr[0])\r
2330 );\r
2331 break;\r
c9b44921 2332 }\r
85b7f65b 2333 }\r
2bbd7e2f
RN
2334\r
2335 if (WorkingVariableMtrrCount > FirmwareVariableMtrrCount) {\r
2336 return RETURN_OUT_OF_RESOURCES;\r
2337 }\r
2338\r
2339 //\r
2340 // 2.6. Merge the WorkingVariableMtrr to OriginalVariableMtrr\r
2341 // Make sure least modification is made to OriginalVariableMtrr.\r
2342 //\r
2343 MtrrLibMergeVariableMtrr (\r
2344 OriginalVariableMtrr, OriginalVariableMtrrCount,\r
2345 WorkingVariableMtrr, WorkingVariableMtrrCount,\r
2346 VariableSettingModified\r
2347 );\r
85b7f65b 2348 }\r
e50466da 2349 }\r
2350\r
8051302a 2351 //\r
2bbd7e2f 2352 // 3. Apply the below-1MB memory attribute settings.\r
8051302a 2353 //\r
2bbd7e2f
RN
2354 for (Index = 0; Index < RangeCount; Index++) {\r
2355 if (Ranges[Index].BaseAddress >= BASE_1MB) {\r
2356 continue;\r
85b7f65b 2357 }\r
85b7f65b 2358\r
2bbd7e2f
RN
2359 Status = MtrrLibSetBelow1MBMemoryAttribute (\r
2360 &WorkingFixedSettings, FixedSettingsModified,\r
2361 Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type\r
2362 );\r
2363 if (RETURN_ERROR (Status)) {\r
2364 return Status;\r
2365 }\r
8051302a 2366 }\r
fa25cf38 2367\r
8051302a 2368 MtrrContextValid = FALSE;\r
fa25cf38 2369 //\r
2bbd7e2f 2370 // 4. Write fixed MTRRs that have been modified\r
fa25cf38 2371 //\r
2bbd7e2f 2372 for (Index = 0; Index < ARRAY_SIZE (FixedSettingsModified); Index++) {\r
fa25cf38 2373 if (FixedSettingsModified[Index]) {\r
2bbd7e2f
RN
2374 if (MtrrSetting != NULL) {\r
2375 MtrrSetting->Fixed.Mtrr[Index] = WorkingFixedSettings.Mtrr[Index];\r
2376 } else {\r
2377 if (!MtrrContextValid) {\r
2378 MtrrLibPreMtrrChange (&MtrrContext);\r
2379 MtrrContextValid = TRUE;\r
2380 }\r
2381 AsmWriteMsr64 (\r
2382 mMtrrLibFixedMtrrTable[Index].Msr,\r
2383 WorkingFixedSettings.Mtrr[Index]\r
fa25cf38 2384 );\r
2bbd7e2f 2385 }\r
fa25cf38
MK
2386 }\r
2387 }\r
2388\r
b0fa5d29 2389 //\r
2bbd7e2f 2390 // 5. Write variable MTRRs that have been modified\r
b0fa5d29 2391 //\r
8051302a
RN
2392 for (Index = 0; Index < OriginalVariableMtrrCount; Index++) {\r
2393 if (VariableSettingModified[Index]) {\r
2bbd7e2f
RN
2394 if (OriginalVariableMtrr[Index].Length != 0) {\r
2395 VariableSetting.Base = (OriginalVariableMtrr[Index].BaseAddress & MtrrValidAddressMask)\r
2396 | (UINT8)OriginalVariableMtrr[Index].Type;\r
2397 VariableSetting.Mask = ((~(OriginalVariableMtrr[Index].Length - 1)) & MtrrValidAddressMask) | BIT11;\r
2398 } else {\r
2399 VariableSetting.Base = 0;\r
2400 VariableSetting.Mask = 0;\r
2401 }\r
2402 if (MtrrSetting != NULL) {\r
2403 CopyMem (&MtrrSetting->Variables.Mtrr[Index], &VariableSetting, sizeof (VariableSetting));\r
2404 } else {\r
2405 if (!MtrrContextValid) {\r
2406 MtrrLibPreMtrrChange (&MtrrContext);\r
2407 MtrrContextValid = TRUE;\r
2408 }\r
2409 AsmWriteMsr64 (\r
2410 MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),\r
2411 VariableSetting.Base\r
2412 );\r
2413 AsmWriteMsr64 (\r
2414 MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),\r
2415 VariableSetting.Mask\r
2416 );\r
b0fa5d29
MK
2417 }\r
2418 }\r
2419 }\r
2bbd7e2f
RN
2420\r
2421 if (MtrrSetting != NULL) {\r
2422 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1;\r
2423 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.FE = 1;\r
2424 } else {\r
2425 if (MtrrContextValid) {\r
2426 MtrrLibPostMtrrChange (&MtrrContext);\r
2427 }\r
fa25cf38
MK
2428 }\r
2429\r
4ef6c385 2430 return RETURN_SUCCESS;\r
31b3597e 2431}\r
b970ed68
MK
2432\r
2433/**\r
2bbd7e2f 2434 This function attempts to set the attributes into MTRR setting buffer for a memory range.\r
b970ed68 2435\r
2bbd7e2f
RN
2436 @param[in, out] MtrrSetting MTRR setting buffer to be set.\r
2437 @param[in] BaseAddress The physical address that is the start address\r
2438 of a memory range.\r
2439 @param[in] Length The size in bytes of the memory range.\r
2440 @param[in] Attribute The bit mask of attributes to set for the\r
2441 memory range.\r
b970ed68 2442\r
2bbd7e2f 2443 @retval RETURN_SUCCESS The attributes were set for the memory range.\r
b970ed68 2444 @retval RETURN_INVALID_PARAMETER Length is zero.\r
2bbd7e2f
RN
2445 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the\r
2446 memory resource range specified by BaseAddress and Length.\r
2447 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource\r
2448 range specified by BaseAddress and Length.\r
2449 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by\r
2450 BaseAddress and Length cannot be modified.\r
2451 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
2452 the memory resource range.\r
2453 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
b970ed68
MK
2454**/\r
2455RETURN_STATUS\r
2456EFIAPI\r
2bbd7e2f
RN
2457MtrrSetMemoryAttributeInMtrrSettings (\r
2458 IN OUT MTRR_SETTINGS *MtrrSetting,\r
b970ed68
MK
2459 IN PHYSICAL_ADDRESS BaseAddress,\r
2460 IN UINT64 Length,\r
2461 IN MTRR_MEMORY_CACHE_TYPE Attribute\r
2462 )\r
2463{\r
8051302a 2464 RETURN_STATUS Status;\r
2bbd7e2f
RN
2465 UINT8 Scratch[SCRATCH_BUFFER_SIZE];\r
2466 UINTN ScratchSize;\r
2467 MTRR_MEMORY_RANGE Range;\r
8051302a
RN
2468\r
2469 if (!IsMtrrSupported ()) {\r
2470 return RETURN_UNSUPPORTED;\r
2471 }\r
2472\r
2bbd7e2f
RN
2473 Range.BaseAddress = BaseAddress;\r
2474 Range.Length = Length;\r
2475 Range.Type = Attribute;\r
2476 ScratchSize = sizeof (Scratch);\r
2477 Status = MtrrSetMemoryAttributesInMtrrSettings (MtrrSetting, Scratch, &ScratchSize, &Range, 1);\r
2478 DEBUG ((DEBUG_CACHE, "MtrrSetMemoryAttribute(MtrrSettings = %p) %s: [%016lx, %016lx) - %x\n",\r
2479 MtrrSetting,\r
8051302a
RN
2480 mMtrrMemoryCacheTypeShortName[Attribute], BaseAddress, BaseAddress + Length, Status));\r
2481\r
2482 if (!RETURN_ERROR (Status)) {\r
2bbd7e2f 2483 MtrrDebugPrintAllMtrrsWorker (MtrrSetting);\r
8051302a
RN
2484 }\r
2485 return Status;\r
b970ed68
MK
2486}\r
2487\r
2488/**\r
2bbd7e2f 2489 This function attempts to set the attributes for a memory range.\r
b970ed68 2490\r
2bbd7e2f
RN
2491 @param[in] BaseAddress The physical address that is the start\r
2492 address of a memory range.\r
2493 @param[in] Length The size in bytes of the memory range.\r
2494 @param[in] Attributes The bit mask of attributes to set for the\r
2495 memory range.\r
b970ed68 2496\r
2bbd7e2f
RN
2497 @retval RETURN_SUCCESS The attributes were set for the memory\r
2498 range.\r
b970ed68 2499 @retval RETURN_INVALID_PARAMETER Length is zero.\r
2bbd7e2f
RN
2500 @retval RETURN_UNSUPPORTED The processor does not support one or\r
2501 more bytes of the memory resource range\r
2502 specified by BaseAddress and Length.\r
2503 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support\r
2504 for the memory resource range specified\r
2505 by BaseAddress and Length.\r
2506 @retval RETURN_ACCESS_DENIED The attributes for the memory resource\r
2507 range specified by BaseAddress and Length\r
2508 cannot be modified.\r
2509 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to\r
2510 modify the attributes of the memory\r
2511 resource range.\r
2512 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
b970ed68
MK
2513**/\r
2514RETURN_STATUS\r
2515EFIAPI\r
2bbd7e2f 2516MtrrSetMemoryAttribute (\r
b970ed68
MK
2517 IN PHYSICAL_ADDRESS BaseAddress,\r
2518 IN UINT64 Length,\r
2519 IN MTRR_MEMORY_CACHE_TYPE Attribute\r
2520 )\r
2521{\r
2bbd7e2f 2522 return MtrrSetMemoryAttributeInMtrrSettings (NULL, BaseAddress, Length, Attribute);\r
b970ed68
MK
2523}\r
2524\r
e50466da 2525/**\r
2526 Worker function setting variable MTRRs\r
2527\r
76b4cae3 2528 @param[in] VariableSettings A buffer to hold variable MTRRs content.\r
e50466da 2529\r
2530**/\r
2531VOID\r
2532MtrrSetVariableMtrrWorker (\r
2533 IN MTRR_VARIABLE_SETTINGS *VariableSettings\r
2534 )\r
2535{\r
2536 UINT32 Index;\r
3b9be416 2537 UINT32 VariableMtrrCount;\r
e50466da 2538\r
acf431e6 2539 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
2bbd7e2f 2540 ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));\r
5bdfa4e5 2541\r
3b9be416 2542 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
e50466da 2543 AsmWriteMsr64 (\r
af838805 2544 MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),\r
e50466da 2545 VariableSettings->Mtrr[Index].Base\r
2546 );\r
2547 AsmWriteMsr64 (\r
af838805 2548 MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),\r
e50466da 2549 VariableSettings->Mtrr[Index].Mask\r
2550 );\r
2551 }\r
2552}\r
2553\r
2554\r
2555/**\r
2556 This function sets variable MTRRs\r
2557\r
76b4cae3 2558 @param[in] VariableSettings A buffer to hold variable MTRRs content.\r
e50466da 2559\r
2560 @return The pointer of VariableSettings\r
2561\r
2562**/\r
2563MTRR_VARIABLE_SETTINGS*\r
2564EFIAPI\r
2565MtrrSetVariableMtrr (\r
2566 IN MTRR_VARIABLE_SETTINGS *VariableSettings\r
2567 )\r
2568{\r
c878cee4 2569 MTRR_CONTEXT MtrrContext;\r
e50466da 2570\r
947a573a 2571 if (!IsMtrrSupported ()) {\r
2572 return VariableSettings;\r
2573 }\r
2574\r
b8f01599 2575 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2576 MtrrSetVariableMtrrWorker (VariableSettings);\r
b8f01599 2577 MtrrLibPostMtrrChange (&MtrrContext);\r
e518b80d
MK
2578 MtrrDebugPrintAllMtrrs ();\r
2579\r
e50466da 2580 return VariableSettings;\r
2581}\r
2582\r
e50466da 2583/**\r
2584 Worker function setting fixed MTRRs\r
2585\r
acf431e6 2586 @param[in] FixedSettings A buffer to hold fixed MTRRs content.\r
e50466da 2587\r
2588**/\r
2589VOID\r
2590MtrrSetFixedMtrrWorker (\r
2591 IN MTRR_FIXED_SETTINGS *FixedSettings\r
2592 )\r
2593{\r
2594 UINT32 Index;\r
2595\r
2596 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
2597 AsmWriteMsr64 (\r
f877f300 2598 mMtrrLibFixedMtrrTable[Index].Msr,\r
e50466da 2599 FixedSettings->Mtrr[Index]\r
2600 );\r
2601 }\r
2602}\r
2603\r
2604\r
2605/**\r
2606 This function sets fixed MTRRs\r
2607\r
acf431e6 2608 @param[in] FixedSettings A buffer to hold fixed MTRRs content.\r
e50466da 2609\r
2610 @retval The pointer of FixedSettings\r
2611\r
2612**/\r
2613MTRR_FIXED_SETTINGS*\r
2614EFIAPI\r
2615MtrrSetFixedMtrr (\r
2616 IN MTRR_FIXED_SETTINGS *FixedSettings\r
2617 )\r
2618{\r
c878cee4 2619 MTRR_CONTEXT MtrrContext;\r
e50466da 2620\r
947a573a 2621 if (!IsMtrrSupported ()) {\r
2622 return FixedSettings;\r
2623 }\r
2624\r
b8f01599 2625 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2626 MtrrSetFixedMtrrWorker (FixedSettings);\r
b8f01599 2627 MtrrLibPostMtrrChange (&MtrrContext);\r
e518b80d 2628 MtrrDebugPrintAllMtrrs ();\r
e50466da 2629\r
2630 return FixedSettings;\r
2631}\r
2632\r
2633\r
2634/**\r
2635 This function gets the content in all MTRRs (variable and fixed)\r
2636\r
acf431e6 2637 @param[out] MtrrSetting A buffer to hold all MTRRs content.\r
e50466da 2638\r
2639 @retval the pointer of MtrrSetting\r
2640\r
2641**/\r
2642MTRR_SETTINGS *\r
2643EFIAPI\r
2644MtrrGetAllMtrrs (\r
2645 OUT MTRR_SETTINGS *MtrrSetting\r
2646 )\r
2647{\r
947a573a 2648 if (!IsMtrrSupported ()) {\r
2649 return MtrrSetting;\r
2650 }\r
2651\r
e50466da 2652 //\r
2653 // Get fixed MTRRs\r
2654 //\r
acf431e6 2655 MtrrGetFixedMtrrWorker (&MtrrSetting->Fixed);\r
e50466da 2656\r
2657 //\r
2658 // Get variable MTRRs\r
2659 //\r
acf431e6 2660 MtrrGetVariableMtrrWorker (\r
5abd5ed4 2661 NULL,\r
acf431e6
MK
2662 GetVariableMtrrCountWorker (),\r
2663 &MtrrSetting->Variables\r
2664 );\r
e50466da 2665\r
2666 //\r
2667 // Get MTRR_DEF_TYPE value\r
2668 //\r
af838805 2669 MtrrSetting->MtrrDefType = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
e50466da 2670\r
2671 return MtrrSetting;\r
2672}\r
2673\r
2674\r
2675/**\r
2676 This function sets all MTRRs (variable and fixed)\r
2677\r
76b4cae3 2678 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
e50466da 2679\r
2680 @retval The pointer of MtrrSetting\r
2681\r
2682**/\r
2683MTRR_SETTINGS *\r
2684EFIAPI\r
2685MtrrSetAllMtrrs (\r
2686 IN MTRR_SETTINGS *MtrrSetting\r
2687 )\r
2688{\r
c878cee4 2689 MTRR_CONTEXT MtrrContext;\r
e50466da 2690\r
947a573a 2691 if (!IsMtrrSupported ()) {\r
2692 return MtrrSetting;\r
2693 }\r
2694\r
b8f01599 2695 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2696\r
2697 //\r
2698 // Set fixed MTRRs\r
2699 //\r
2700 MtrrSetFixedMtrrWorker (&MtrrSetting->Fixed);\r
2701\r
2702 //\r
2703 // Set variable MTRRs\r
2704 //\r
2705 MtrrSetVariableMtrrWorker (&MtrrSetting->Variables);\r
2706\r
2707 //\r
2708 // Set MTRR_DEF_TYPE value\r
2709 //\r
af838805 2710 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);\r
e50466da 2711\r
b8f01599 2712 MtrrLibPostMtrrChangeEnableCache (&MtrrContext);\r
e50466da 2713\r
2714 return MtrrSetting;\r
2715}\r
2716\r
e518b80d 2717\r
947a573a 2718/**\r
2719 Checks if MTRR is supported.\r
2720\r
2721 @retval TRUE MTRR is supported.\r
2722 @retval FALSE MTRR is not supported.\r
2723\r
2724**/\r
2725BOOLEAN\r
2726EFIAPI\r
2727IsMtrrSupported (\r
2728 VOID\r
2729 )\r
2730{\r
3bb13d35
RN
2731 CPUID_VERSION_INFO_EDX Edx;\r
2732 MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
947a573a 2733\r
2734 //\r
2735 // Check CPUID(1).EDX[12] for MTRR capability\r
2736 //\r
3bb13d35
RN
2737 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);\r
2738 if (Edx.Bits.MTRR == 0) {\r
947a573a 2739 return FALSE;\r
2740 }\r
2741\r
2742 //\r
3bb13d35
RN
2743 // Check number of variable MTRRs and fixed MTRRs existence.\r
2744 // If number of variable MTRRs is zero, or fixed MTRRs do not\r
947a573a 2745 // exist, return false.\r
2746 //\r
3bb13d35
RN
2747 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
2748 if ((MtrrCap.Bits.VCNT == 0) || (MtrrCap.Bits.FIX == 0)) {\r
947a573a 2749 return FALSE;\r
2750 }\r
947a573a 2751 return TRUE;\r
2752}\r
8051302a 2753\r
2bbd7e2f
RN
2754\r
2755/**\r
2756 Worker function prints all MTRRs for debugging.\r
2757\r
2758 If MtrrSetting is not NULL, print MTRR settings from input MTRR\r
2759 settings buffer.\r
2760 If MtrrSetting is NULL, print MTRR settings from MTRRs.\r
2761\r
2762 @param MtrrSetting A buffer holding all MTRRs content.\r
2763**/\r
2764VOID\r
2765MtrrDebugPrintAllMtrrsWorker (\r
2766 IN MTRR_SETTINGS *MtrrSetting\r
2767 )\r
2768{\r
2769 DEBUG_CODE (\r
2770 MTRR_SETTINGS LocalMtrrs;\r
2771 MTRR_SETTINGS *Mtrrs;\r
2772 UINTN Index;\r
2773 UINTN RangeCount;\r
2774 UINT64 MtrrValidBitsMask;\r
2775 UINT64 MtrrValidAddressMask;\r
2776 MTRR_MEMORY_RANGE Ranges[\r
2777 ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1\r
2778 ];\r
2779 MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];\r
2780\r
2781 if (!IsMtrrSupported ()) {\r
2782 return;\r
2783 }\r
2784\r
2785 if (MtrrSetting != NULL) {\r
2786 Mtrrs = MtrrSetting;\r
2787 } else {\r
2788 MtrrGetAllMtrrs (&LocalMtrrs);\r
2789 Mtrrs = &LocalMtrrs;\r
2790 }\r
2791\r
2792 //\r
2793 // Dump RAW MTRR contents\r
2794 //\r
2795 DEBUG((DEBUG_CACHE, "MTRR Settings\n"));\r
2796 DEBUG((DEBUG_CACHE, "=============\n"));\r
2797 DEBUG((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));\r
2798 for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) {\r
2799 DEBUG((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));\r
2800 }\r
2801\r
2802 for (Index = 0; Index < ARRAY_SIZE (Mtrrs->Variables.Mtrr); Index++) {\r
2803 if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {\r
2804 //\r
2805 // If mask is not valid, then do not display range\r
2806 //\r
2807 continue;\r
2808 }\r
2809 DEBUG ((DEBUG_CACHE, "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",\r
2810 Index,\r
2811 Mtrrs->Variables.Mtrr[Index].Base,\r
2812 Mtrrs->Variables.Mtrr[Index].Mask\r
2813 ));\r
2814 }\r
2815 DEBUG((DEBUG_CACHE, "\n"));\r
2816\r
2817 //\r
2818 // Dump MTRR setting in ranges\r
2819 //\r
2820 DEBUG((DEBUG_CACHE, "MTRR Ranges\n"));\r
2821 DEBUG((DEBUG_CACHE, "====================================\n"));\r
2822 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
2823 Ranges[0].BaseAddress = 0;\r
2824 Ranges[0].Length = MtrrValidBitsMask + 1;\r
2825 Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs);\r
2826 RangeCount = 1;\r
2827\r
2828 MtrrLibGetRawVariableRanges (\r
2829 &Mtrrs->Variables, ARRAY_SIZE (Mtrrs->Variables.Mtrr),\r
2830 MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges\r
2831 );\r
2832 MtrrLibApplyVariableMtrrs (\r
2833 RawVariableRanges, ARRAY_SIZE (RawVariableRanges),\r
2834 Ranges, ARRAY_SIZE (Ranges), &RangeCount\r
2835 );\r
2836\r
2837 MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount);\r
2838\r
2839 for (Index = 0; Index < RangeCount; Index++) {\r
2840 DEBUG ((DEBUG_CACHE, "%a:%016lx-%016lx\n",\r
2841 mMtrrMemoryCacheTypeShortName[Ranges[Index].Type],\r
2842 Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1\r
2843 ));\r
2844 }\r
2845 );\r
2846}\r
2847\r
2848/**\r
2849 This function prints all MTRRs for debugging.\r
2850**/\r
2851VOID\r
2852EFIAPI\r
2853MtrrDebugPrintAllMtrrs (\r
2854 VOID\r
2855 )\r
2856{\r
2857 MtrrDebugPrintAllMtrrsWorker (NULL);\r
2858}\r