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e50466da 1/** @file\r
2 MTRR setting library\r
3\r
81f56049
JF
4 @par Note: \r
5 Most of services in this library instance are suggested to be invoked by BSP only,\r
6 except for MtrrSetAllMtrrs() which is used to sync BSP's MTRR setting to APs.\r
7\r
341fea64 8 Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc 9 This program and the accompanying materials\r
e50466da 10 are licensed and made available under the terms and conditions of the BSD License\r
11 which accompanies this distribution. The full text of the license may be found at\r
12 http://opensource.org/licenses/bsd-license.php\r
13\r
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
16\r
17**/\r
18\r
19#include <Base.h>\r
20\r
3bb13d35
RN
21#include <Register/Cpuid.h>\r
22#include <Register/Msr.h>\r
23\r
e50466da 24#include <Library/MtrrLib.h>\r
25#include <Library/BaseLib.h>\r
26#include <Library/CpuLib.h>\r
27#include <Library/BaseMemoryLib.h>\r
28#include <Library/DebugLib.h>\r
29\r
eecad349
JF
30#define OR_SEED 0x0101010101010101ull\r
31#define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull\r
07e88920 32\r
8051302a 33#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B);\r
c878cee4 34//\r
35// Context to save and restore when MTRRs are programmed\r
36//\r
37typedef struct {\r
38 UINTN Cr4;\r
39 BOOLEAN InterruptState;\r
40} MTRR_CONTEXT;\r
41\r
8051302a
RN
42typedef struct {\r
43 UINT64 BaseAddress;\r
44 UINT64 Length;\r
45 MTRR_MEMORY_CACHE_TYPE Type;\r
46} MEMORY_RANGE;\r
47\r
e50466da 48//\r
49// This table defines the offset, base and length of the fixed MTRRs\r
50//\r
f877f300 51CONST FIXED_MTRR mMtrrLibFixedMtrrTable[] = {\r
e50466da 52 {\r
af838805 53 MSR_IA32_MTRR_FIX64K_00000,\r
e50466da 54 0,\r
55 SIZE_64KB\r
56 },\r
57 {\r
af838805 58 MSR_IA32_MTRR_FIX16K_80000,\r
e50466da 59 0x80000,\r
60 SIZE_16KB\r
61 },\r
62 {\r
af838805 63 MSR_IA32_MTRR_FIX16K_A0000,\r
e50466da 64 0xA0000,\r
65 SIZE_16KB\r
66 },\r
67 {\r
af838805 68 MSR_IA32_MTRR_FIX4K_C0000,\r
e50466da 69 0xC0000,\r
70 SIZE_4KB\r
71 },\r
72 {\r
af838805 73 MSR_IA32_MTRR_FIX4K_C8000,\r
e50466da 74 0xC8000,\r
75 SIZE_4KB\r
76 },\r
77 {\r
af838805 78 MSR_IA32_MTRR_FIX4K_D0000,\r
e50466da 79 0xD0000,\r
80 SIZE_4KB\r
81 },\r
82 {\r
af838805 83 MSR_IA32_MTRR_FIX4K_D8000,\r
e50466da 84 0xD8000,\r
85 SIZE_4KB\r
86 },\r
87 {\r
af838805 88 MSR_IA32_MTRR_FIX4K_E0000,\r
e50466da 89 0xE0000,\r
90 SIZE_4KB\r
91 },\r
92 {\r
af838805 93 MSR_IA32_MTRR_FIX4K_E8000,\r
e50466da 94 0xE8000,\r
95 SIZE_4KB\r
96 },\r
97 {\r
af838805 98 MSR_IA32_MTRR_FIX4K_F0000,\r
e50466da 99 0xF0000,\r
100 SIZE_4KB\r
101 },\r
102 {\r
af838805 103 MSR_IA32_MTRR_FIX4K_F8000,\r
e50466da 104 0xF8000,\r
105 SIZE_4KB\r
76b4cae3 106 }\r
e50466da 107};\r
108\r
f877f300 109//\r
110// Lookup table used to print MTRRs\r
111//\r
112GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {\r
113 "UC", // CacheUncacheable\r
114 "WC", // CacheWriteCombining\r
115 "R*", // Invalid\r
116 "R*", // Invalid\r
117 "WT", // CacheWriteThrough\r
118 "WP", // CacheWriteProtected\r
119 "WB", // CacheWriteBack\r
120 "R*" // Invalid\r
121};\r
122\r
31b3597e
MK
123/**\r
124 Worker function returns the variable MTRR count for the CPU.\r
125\r
126 @return Variable MTRR count\r
127\r
128**/\r
129UINT32\r
130GetVariableMtrrCountWorker (\r
131 VOID\r
132 )\r
133{\r
386f5785 134 MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
31b3597e 135\r
386f5785
RN
136 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
137 ASSERT (MtrrCap.Bits.VCNT <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
138 return MtrrCap.Bits.VCNT;\r
31b3597e
MK
139}\r
140\r
3b9be416
JY
141/**\r
142 Returns the variable MTRR count for the CPU.\r
143\r
144 @return Variable MTRR count\r
145\r
146**/\r
147UINT32\r
ed8dfd7b 148EFIAPI\r
3b9be416
JY
149GetVariableMtrrCount (\r
150 VOID\r
151 )\r
152{\r
947a573a 153 if (!IsMtrrSupported ()) {\r
154 return 0;\r
155 }\r
31b3597e 156 return GetVariableMtrrCountWorker ();\r
3b9be416
JY
157}\r
158\r
159/**\r
31b3597e 160 Worker function returns the firmware usable variable MTRR count for the CPU.\r
3b9be416
JY
161\r
162 @return Firmware usable variable MTRR count\r
163\r
164**/\r
165UINT32\r
31b3597e 166GetFirmwareVariableMtrrCountWorker (\r
3b9be416
JY
167 VOID\r
168 )\r
169{\r
947a573a 170 UINT32 VariableMtrrCount;\r
46309b11 171 UINT32 ReservedMtrrNumber;\r
947a573a 172\r
31b3597e 173 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
46309b11
JF
174 ReservedMtrrNumber = PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);\r
175 if (VariableMtrrCount < ReservedMtrrNumber) {\r
947a573a 176 return 0;\r
177 }\r
178\r
46309b11 179 return VariableMtrrCount - ReservedMtrrNumber;\r
3b9be416 180}\r
e50466da 181\r
31b3597e
MK
182/**\r
183 Returns the firmware usable variable MTRR count for the CPU.\r
184\r
185 @return Firmware usable variable MTRR count\r
186\r
187**/\r
188UINT32\r
189EFIAPI\r
190GetFirmwareVariableMtrrCount (\r
191 VOID\r
192 )\r
193{\r
194 if (!IsMtrrSupported ()) {\r
195 return 0;\r
196 }\r
197 return GetFirmwareVariableMtrrCountWorker ();\r
198}\r
199\r
200/**\r
201 Worker function returns the default MTRR cache type for the system.\r
202\r
5abd5ed4
MK
203 If MtrrSetting is not NULL, returns the default MTRR cache type from input\r
204 MTRR settings buffer.\r
205 If MtrrSetting is NULL, returns the default MTRR cache type from MSR.\r
206\r
207 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
208\r
31b3597e
MK
209 @return The default MTRR cache type.\r
210\r
211**/\r
212MTRR_MEMORY_CACHE_TYPE\r
213MtrrGetDefaultMemoryTypeWorker (\r
5abd5ed4 214 IN MTRR_SETTINGS *MtrrSetting\r
31b3597e
MK
215 )\r
216{\r
af838805
RN
217 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
218\r
5abd5ed4 219 if (MtrrSetting == NULL) {\r
af838805 220 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
5abd5ed4 221 } else {\r
af838805 222 DefType.Uint64 = MtrrSetting->MtrrDefType;\r
5abd5ed4 223 }\r
af838805
RN
224\r
225 return (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
31b3597e
MK
226}\r
227\r
228\r
e50466da 229/**\r
230 Returns the default MTRR cache type for the system.\r
231\r
91ec7824 232 @return The default MTRR cache type.\r
e50466da 233\r
234**/\r
91ec7824 235MTRR_MEMORY_CACHE_TYPE\r
236EFIAPI\r
237MtrrGetDefaultMemoryType (\r
e50466da 238 VOID\r
91ec7824 239 )\r
e50466da 240{\r
91ec7824 241 if (!IsMtrrSupported ()) {\r
242 return CacheUncacheable;\r
243 }\r
5abd5ed4 244 return MtrrGetDefaultMemoryTypeWorker (NULL);\r
91ec7824 245}\r
e50466da 246\r
247/**\r
248 Preparation before programming MTRR.\r
249\r
250 This function will do some preparation for programming MTRRs:\r
251 disable cache, invalid cache and disable MTRR caching functionality\r
252\r
a5953380 253 @param[out] MtrrContext Pointer to context to save\r
e50466da 254\r
255**/\r
c878cee4 256VOID\r
b8f01599 257MtrrLibPreMtrrChange (\r
c878cee4 258 OUT MTRR_CONTEXT *MtrrContext\r
e50466da 259 )\r
260{\r
af838805 261 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
c878cee4 262 //\r
263 // Disable interrupts and save current interrupt state\r
264 //\r
265 MtrrContext->InterruptState = SaveAndDisableInterrupts();\r
76b4cae3 266\r
e50466da 267 //\r
268 // Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)\r
269 //\r
58b23d90 270 AsmDisableCache ();\r
271\r
e50466da 272 //\r
58b23d90 273 // Save original CR4 value and clear PGE flag (Bit 7)\r
e50466da 274 //\r
c878cee4 275 MtrrContext->Cr4 = AsmReadCr4 ();\r
276 AsmWriteCr4 (MtrrContext->Cr4 & (~BIT7));\r
58b23d90 277\r
e50466da 278 //\r
279 // Flush all TLBs\r
280 //\r
281 CpuFlushTlb ();\r
58b23d90 282\r
e50466da 283 //\r
76b4cae3 284 // Disable MTRRs\r
e50466da 285 //\r
af838805
RN
286 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
287 DefType.Bits.E = 0;\r
288 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);\r
e50466da 289}\r
290\r
e50466da 291/**\r
292 Cleaning up after programming MTRRs.\r
293\r
294 This function will do some clean up after programming MTRRs:\r
0779e5bf 295 Flush all TLBs, re-enable caching, restore CR4.\r
e50466da 296\r
a5953380 297 @param[in] MtrrContext Pointer to context to restore\r
e50466da 298\r
299**/\r
300VOID\r
b8f01599 301MtrrLibPostMtrrChangeEnableCache (\r
c878cee4 302 IN MTRR_CONTEXT *MtrrContext\r
e50466da 303 )\r
304{\r
e50466da 305 //\r
76b4cae3 306 // Flush all TLBs\r
e50466da 307 //\r
e50466da 308 CpuFlushTlb ();\r
309\r
310 //\r
311 // Enable Normal Mode caching CD=NW=0, CD(Bit30), NW(Bit29)\r
312 //\r
58b23d90 313 AsmEnableCache ();\r
e50466da 314\r
58b23d90 315 //\r
316 // Restore original CR4 value\r
317 //\r
c878cee4 318 AsmWriteCr4 (MtrrContext->Cr4);\r
76b4cae3 319\r
c878cee4 320 //\r
321 // Restore original interrupt state\r
322 //\r
323 SetInterruptState (MtrrContext->InterruptState);\r
e50466da 324}\r
325\r
0779e5bf 326/**\r
327 Cleaning up after programming MTRRs.\r
328\r
329 This function will do some clean up after programming MTRRs:\r
330 enable MTRR caching functionality, and enable cache\r
331\r
a5953380 332 @param[in] MtrrContext Pointer to context to restore\r
0779e5bf 333\r
334**/\r
335VOID\r
b8f01599 336MtrrLibPostMtrrChange (\r
c878cee4 337 IN MTRR_CONTEXT *MtrrContext\r
0779e5bf 338 )\r
339{\r
af838805 340 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
0779e5bf 341 //\r
342 // Enable Cache MTRR\r
343 //\r
af838805
RN
344 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
345 DefType.Bits.E = 1;\r
346 DefType.Bits.FE = 1;\r
347 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);\r
0779e5bf 348\r
b8f01599 349 MtrrLibPostMtrrChangeEnableCache (MtrrContext);\r
0779e5bf 350}\r
351\r
85b7f65b
MK
352/**\r
353 Worker function gets the content in fixed MTRRs\r
354\r
355 @param[out] FixedSettings A buffer to hold fixed MTRRs content.\r
356\r
357 @retval The pointer of FixedSettings\r
358\r
359**/\r
360MTRR_FIXED_SETTINGS*\r
361MtrrGetFixedMtrrWorker (\r
362 OUT MTRR_FIXED_SETTINGS *FixedSettings\r
363 )\r
364{\r
365 UINT32 Index;\r
366\r
367 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
368 FixedSettings->Mtrr[Index] =\r
369 AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
370 }\r
371\r
372 return FixedSettings;\r
373}\r
374\r
375\r
376/**\r
377 This function gets the content in fixed MTRRs\r
378\r
379 @param[out] FixedSettings A buffer to hold fixed MTRRs content.\r
380\r
381 @retval The pointer of FixedSettings\r
382\r
383**/\r
384MTRR_FIXED_SETTINGS*\r
385EFIAPI\r
386MtrrGetFixedMtrr (\r
387 OUT MTRR_FIXED_SETTINGS *FixedSettings\r
388 )\r
389{\r
390 if (!IsMtrrSupported ()) {\r
391 return FixedSettings;\r
392 }\r
393\r
394 return MtrrGetFixedMtrrWorker (FixedSettings);\r
395}\r
396\r
397\r
398/**\r
399 Worker function will get the raw value in variable MTRRs\r
400\r
5abd5ed4
MK
401 If MtrrSetting is not NULL, gets the variable MTRRs raw value from input\r
402 MTRR settings buffer.\r
403 If MtrrSetting is NULL, gets the variable MTRRs raw value from MTRRs.\r
404\r
405 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
406 @param[in] VariableMtrrCount Number of variable MTRRs.\r
85b7f65b
MK
407 @param[out] VariableSettings A buffer to hold variable MTRRs content.\r
408\r
409 @return The VariableSettings input pointer\r
410\r
411**/\r
412MTRR_VARIABLE_SETTINGS*\r
413MtrrGetVariableMtrrWorker (\r
5abd5ed4 414 IN MTRR_SETTINGS *MtrrSetting,\r
acf431e6 415 IN UINT32 VariableMtrrCount,\r
85b7f65b
MK
416 OUT MTRR_VARIABLE_SETTINGS *VariableSettings\r
417 )\r
418{\r
419 UINT32 Index;\r
85b7f65b 420\r
85b7f65b
MK
421 ASSERT (VariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
422\r
423 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
5abd5ed4
MK
424 if (MtrrSetting == NULL) {\r
425 VariableSettings->Mtrr[Index].Base =\r
af838805 426 AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));\r
5abd5ed4 427 VariableSettings->Mtrr[Index].Mask =\r
af838805 428 AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));\r
5abd5ed4
MK
429 } else {\r
430 VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base;\r
431 VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask;\r
432 }\r
85b7f65b
MK
433 }\r
434\r
435 return VariableSettings;\r
436}\r
437\r
438/**\r
439 This function will get the raw value in variable MTRRs\r
440\r
441 @param[out] VariableSettings A buffer to hold variable MTRRs content.\r
442\r
443 @return The VariableSettings input pointer\r
444\r
445**/\r
446MTRR_VARIABLE_SETTINGS*\r
447EFIAPI\r
448MtrrGetVariableMtrr (\r
449 OUT MTRR_VARIABLE_SETTINGS *VariableSettings\r
450 )\r
451{\r
452 if (!IsMtrrSupported ()) {\r
453 return VariableSettings;\r
454 }\r
455\r
456 return MtrrGetVariableMtrrWorker (\r
5abd5ed4 457 NULL,\r
acf431e6 458 GetVariableMtrrCountWorker (),\r
85b7f65b
MK
459 VariableSettings\r
460 );\r
461}\r
e50466da 462\r
463/**\r
464 Programs fixed MTRRs registers.\r
465\r
94240f1b 466 @param[in] Type The memory type to set.\r
76b4cae3
MK
467 @param[in, out] Base The base address of memory range.\r
468 @param[in, out] Length The length of memory range.\r
0f354122
JF
469 @param[in, out] LastMsrNum On input, the last index of the fixed MTRR MSR to program.\r
470 On return, the current index of the fixed MTRR MSR to program.\r
fa25cf38
MK
471 @param[out] ReturnClearMask The bits to clear in the fixed MTRR MSR.\r
472 @param[out] ReturnOrMask The bits to set in the fixed MTRR MSR.\r
e50466da 473\r
474 @retval RETURN_SUCCESS The cache type was updated successfully\r
475 @retval RETURN_UNSUPPORTED The requested range or cache type was invalid\r
476 for the fixed MTRRs.\r
477\r
478**/\r
479RETURN_STATUS\r
94240f1b
RN
480MtrrLibProgramFixedMtrr (\r
481 IN MTRR_MEMORY_CACHE_TYPE Type,\r
482 IN OUT UINT64 *Base,\r
483 IN OUT UINT64 *Length,\r
484 IN OUT UINT32 *LastMsrNum,\r
485 OUT UINT64 *ReturnClearMask,\r
486 OUT UINT64 *ReturnOrMask\r
e50466da 487 )\r
488{\r
489 UINT32 MsrNum;\r
eecad349
JF
490 UINT32 LeftByteShift;\r
491 UINT32 RightByteShift;\r
492 UINT64 OrMask;\r
493 UINT64 ClearMask;\r
07e88920 494 UINT64 SubLength;\r
e50466da 495\r
eecad349
JF
496 //\r
497 // Find the fixed MTRR index to be programmed\r
498 //\r
0f354122 499 for (MsrNum = *LastMsrNum + 1; MsrNum < MTRR_NUMBER_OF_FIXED_MTRR; MsrNum++) {\r
f877f300 500 if ((*Base >= mMtrrLibFixedMtrrTable[MsrNum].BaseAddress) &&\r
e50466da 501 (*Base <\r
502 (\r
f877f300 503 mMtrrLibFixedMtrrTable[MsrNum].BaseAddress +\r
504 (8 * mMtrrLibFixedMtrrTable[MsrNum].Length)\r
e50466da 505 )\r
506 )\r
507 ) {\r
508 break;\r
509 }\r
510 }\r
511\r
94240f1b 512 if (MsrNum == MTRR_NUMBER_OF_FIXED_MTRR) {\r
e50466da 513 return RETURN_UNSUPPORTED;\r
514 }\r
515\r
516 //\r
eecad349 517 // Find the begin offset in fixed MTRR and calculate byte offset of left shift\r
e50466da 518 //\r
eecad349 519 LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrNum].BaseAddress)\r
aaa1e579 520 / mMtrrLibFixedMtrrTable[MsrNum].Length;\r
e50466da 521\r
eecad349 522 if (LeftByteShift >= 8) {\r
e50466da 523 return RETURN_UNSUPPORTED;\r
524 }\r
525\r
eecad349
JF
526 //\r
527 // Find the end offset in fixed MTRR and calculate byte offset of right shift\r
528 //\r
529 SubLength = mMtrrLibFixedMtrrTable[MsrNum].Length * (8 - LeftByteShift);\r
530 if (*Length >= SubLength) {\r
531 RightByteShift = 0;\r
07e88920 532 } else {\r
eecad349
JF
533 RightByteShift = 8 - LeftByteShift -\r
534 (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrNum].Length;\r
535 if ((LeftByteShift >= 8) ||\r
536 (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrNum].Length) != 0)\r
537 ) {\r
538 return RETURN_UNSUPPORTED;\r
539 }\r
540 //\r
541 // Update SubLength by actual length\r
542 //\r
543 SubLength = *Length;\r
e50466da 544 }\r
545\r
eecad349 546 ClearMask = CLEAR_SEED;\r
94240f1b 547 OrMask = MultU64x32 (OR_SEED, (UINT32) Type);\r
eecad349
JF
548\r
549 if (LeftByteShift != 0) {\r
550 //\r
551 // Clear the low bits by LeftByteShift\r
552 //\r
553 ClearMask &= LShiftU64 (ClearMask, LeftByteShift * 8);\r
554 OrMask &= LShiftU64 (OrMask, LeftByteShift * 8);\r
555 }\r
556\r
557 if (RightByteShift != 0) {\r
558 //\r
559 // Clear the high bits by RightByteShift\r
560 //\r
561 ClearMask &= RShiftU64 (ClearMask, RightByteShift * 8);\r
562 OrMask &= RShiftU64 (OrMask, RightByteShift * 8);\r
e50466da 563 }\r
564\r
07e88920
JF
565 *Length -= SubLength;\r
566 *Base += SubLength;\r
567\r
0f354122 568 *LastMsrNum = MsrNum;\r
eecad349
JF
569 *ReturnClearMask = ClearMask;\r
570 *ReturnOrMask = OrMask;\r
fa25cf38 571\r
e50466da 572 return RETURN_SUCCESS;\r
573}\r
574\r
575\r
d0baed7d
MK
576/**\r
577 Worker function gets the attribute of variable MTRRs.\r
578\r
579 This function shadows the content of variable MTRRs into an\r
580 internal array: VariableMtrr.\r
581\r
10c361ad
RN
582 @param[in] VariableSettings The variable MTRR values to shadow\r
583 @param[in] VariableMtrrCount The number of variable MTRRs\r
584 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
585 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
586 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
d0baed7d 587\r
10c361ad 588 @return Number of MTRRs which has been used.\r
d0baed7d
MK
589\r
590**/\r
591UINT32\r
592MtrrGetMemoryAttributeInVariableMtrrWorker (\r
593 IN MTRR_VARIABLE_SETTINGS *VariableSettings,\r
10c361ad 594 IN UINTN VariableMtrrCount,\r
d0baed7d
MK
595 IN UINT64 MtrrValidBitsMask,\r
596 IN UINT64 MtrrValidAddressMask,\r
597 OUT VARIABLE_MTRR *VariableMtrr\r
598 )\r
599{\r
600 UINTN Index;\r
601 UINT32 UsedMtrr;\r
602\r
603 ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * MTRR_NUMBER_OF_VARIABLE_MTRR);\r
10c361ad 604 for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {\r
af838805 605 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
d0baed7d
MK
606 VariableMtrr[Index].Msr = (UINT32)Index;\r
607 VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);\r
608 VariableMtrr[Index].Length = ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
609 VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff);\r
610 VariableMtrr[Index].Valid = TRUE;\r
611 VariableMtrr[Index].Used = TRUE;\r
612 UsedMtrr++;\r
613 }\r
614 }\r
615 return UsedMtrr;\r
616}\r
617\r
618\r
e50466da 619/**\r
76b4cae3 620 Gets the attribute of variable MTRRs.\r
e50466da 621\r
3ba736f3
JY
622 This function shadows the content of variable MTRRs into an\r
623 internal array: VariableMtrr.\r
e50466da 624\r
76b4cae3
MK
625 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
626 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
627 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
e50466da 628\r
438f1766 629 @return The return value of this parameter indicates the\r
3ba736f3 630 number of MTRRs which has been used.\r
e50466da 631\r
632**/\r
3ba736f3 633UINT32\r
e50466da 634EFIAPI\r
635MtrrGetMemoryAttributeInVariableMtrr (\r
636 IN UINT64 MtrrValidBitsMask,\r
637 IN UINT64 MtrrValidAddressMask,\r
638 OUT VARIABLE_MTRR *VariableMtrr\r
639 )\r
640{\r
d0baed7d 641 MTRR_VARIABLE_SETTINGS VariableSettings;\r
3b9be416 642\r
947a573a 643 if (!IsMtrrSupported ()) {\r
644 return 0;\r
645 }\r
646\r
d0baed7d 647 MtrrGetVariableMtrrWorker (\r
5abd5ed4 648 NULL,\r
d0baed7d
MK
649 GetVariableMtrrCountWorker (),\r
650 &VariableSettings\r
651 );\r
e50466da 652\r
d0baed7d
MK
653 return MtrrGetMemoryAttributeInVariableMtrrWorker (\r
654 &VariableSettings,\r
655 GetFirmwareVariableMtrrCountWorker (),\r
656 MtrrValidBitsMask,\r
657 MtrrValidAddressMask,\r
658 VariableMtrr\r
659 );\r
e50466da 660}\r
661\r
e50466da 662/**\r
8051302a 663 Return the least alignment of address.\r
e50466da 664\r
8051302a
RN
665 @param Address The address to return the alignment.\r
666 @param Alignment0 The alignment to return when Address is 0.\r
e50466da 667\r
8051302a 668 @return The least alignment of the Address.\r
e50466da 669**/\r
8051302a
RN
670UINT64\r
671MtrrLibLeastAlignment (\r
672 UINT64 Address,\r
673 UINT64 Alignment0\r
674)\r
e50466da 675{\r
8051302a
RN
676 if (Address == 0) {\r
677 return Alignment0;\r
e50466da 678 }\r
679\r
8051302a 680 return LShiftU64 (1, (UINTN) LowBitSet64 (Address));\r
e50466da 681}\r
682\r
e50466da 683/**\r
8051302a
RN
684 Return the number of required variable MTRRs to positively cover the\r
685 specified range.\r
e50466da 686\r
8051302a
RN
687 @param BaseAddress Base address of the range.\r
688 @param Length Length of the range.\r
689 @param Alignment0 Alignment of 0.\r
e50466da 690\r
8051302a 691 @return The number of the required variable MTRRs.\r
e50466da 692**/\r
8051302a
RN
693UINT32\r
694MtrrLibGetPositiveMtrrNumber (\r
695 IN UINT64 BaseAddress,\r
696 IN UINT64 Length,\r
697 IN UINT64 Alignment0\r
698)\r
e50466da 699{\r
8051302a
RN
700 UINT64 SubLength;\r
701 UINT32 MtrrNumber;\r
702 BOOLEAN UseLeastAlignment;\r
e50466da 703\r
8051302a 704 UseLeastAlignment = TRUE;\r
e50466da 705\r
8051302a
RN
706 //\r
707 // Calculate the alignment of the base address.\r
708 //\r
709 for (MtrrNumber = 0; Length != 0; MtrrNumber++) {\r
710 if (UseLeastAlignment) {\r
711 SubLength = MtrrLibLeastAlignment (BaseAddress, Alignment0);\r
e50466da 712\r
8051302a
RN
713 if (SubLength > Length) {\r
714 //\r
715 // Set a flag when remaining length is too small\r
716 // so that MtrrLibLeastAlignment() is not called in following loops.\r
717 //\r
718 UseLeastAlignment = FALSE;\r
e50466da 719 }\r
e50466da 720 }\r
721\r
8051302a
RN
722 if (!UseLeastAlignment) {\r
723 SubLength = GetPowerOfTwo64 (Length);\r
e50466da 724 }\r
e50466da 725\r
8051302a
RN
726 BaseAddress += SubLength;\r
727 Length -= SubLength;\r
1e60a0ec 728 }\r
729\r
8051302a 730 return MtrrNumber;\r
e50466da 731}\r
732\r
e50466da 733/**\r
8051302a 734 Return whether the left MTRR type precedes the right MTRR type.\r
76b4cae3 735\r
8051302a 736 The MTRR type precedence rules are:\r
10c361ad
RN
737 1. UC precedes any other type\r
738 2. WT precedes WB\r
739 For further details, please refer the IA32 Software Developer's Manual,\r
740 Volume 3, Section "MTRR Precedences".\r
e50466da 741\r
8051302a
RN
742 @param Left The left MTRR type.\r
743 @param Right The right MTRR type.\r
e50466da 744\r
8051302a
RN
745 @retval TRUE Left precedes Right.\r
746 @retval FALSE Left doesn't precede Right.\r
e50466da 747**/\r
8051302a
RN
748BOOLEAN\r
749MtrrLibTypeLeftPrecedeRight (\r
750 IN MTRR_MEMORY_CACHE_TYPE Left,\r
751 IN MTRR_MEMORY_CACHE_TYPE Right\r
752)\r
e50466da 753{\r
8051302a 754 return (BOOLEAN) (Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));\r
e50466da 755}\r
756\r
757\r
758/**\r
8051302a
RN
759 Return whether the type of the specified range can precede the specified type.\r
760\r
761 @param Ranges Memory range array holding memory type settings for all\r
762 the memory address.\r
763 @param RangeCount Count of memory ranges.\r
764 @param Type Type to check precedence.\r
765 @param SubBase Base address of the specified range.\r
766 @param SubLength Length of the specified range.\r
767\r
768 @retval TRUE The type of the specified range can precede the Type.\r
769 @retval FALSE The type of the specified range cannot precede the Type.\r
770 So the subtraction is not applicable.\r
771**/\r
772BOOLEAN\r
773MtrrLibSubstractable (\r
774 IN CONST MEMORY_RANGE *Ranges,\r
775 IN UINT32 RangeCount,\r
776 IN MTRR_MEMORY_CACHE_TYPE Type,\r
777 IN UINT64 SubBase,\r
778 IN UINT64 SubLength\r
779)\r
780{\r
781 UINT32 Index;\r
782 UINT64 Length;\r
783 // WT > WB\r
784 // UC > *\r
785 for (Index = 0; Index < RangeCount; Index++) {\r
786 if (Ranges[Index].BaseAddress <= SubBase && SubBase < Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
e50466da 787\r
8051302a
RN
788 if (Ranges[Index].BaseAddress + Ranges[Index].Length >= SubBase + SubLength) {\r
789 return MtrrLibTypeLeftPrecedeRight (Ranges[Index].Type, Type);\r
e50466da 790\r
8051302a
RN
791 } else {\r
792 if (!MtrrLibTypeLeftPrecedeRight (Ranges[Index].Type, Type)) {\r
793 return FALSE;\r
794 }\r
1a2ad6fc 795\r
8051302a
RN
796 Length = Ranges[Index].BaseAddress + Ranges[Index].Length - SubBase;\r
797 SubBase += Length;\r
798 SubLength -= Length;\r
799 }\r
800 }\r
801 }\r
e50466da 802\r
8051302a
RN
803 ASSERT (FALSE);\r
804 return FALSE;\r
805}\r
e50466da 806\r
8051302a
RN
807/**\r
808 Return the number of required variable MTRRs to cover the specified range.\r
809\r
810 The routine considers subtraction in the both side of the range to find out\r
811 the most optimal solution (which uses the least MTRRs).\r
812\r
813 @param Ranges Array holding memory type settings of all memory\r
814 address.\r
815 @param RangeCount Count of memory ranges.\r
816 @param VariableMtrr Array holding allocated variable MTRRs.\r
817 @param VariableMtrrCount Count of allocated variable MTRRs.\r
818 @param BaseAddress Base address of the specified range.\r
819 @param Length Length of the specified range.\r
820 @param Type MTRR type of the specified range.\r
821 @param Alignment0 Alignment of 0.\r
822 @param SubLeft Return the count of left subtraction.\r
823 @param SubRight Return the count of right subtraction.\r
824\r
825 @return Number of required variable MTRRs.\r
e50466da 826**/\r
8051302a
RN
827UINT32\r
828MtrrLibGetMtrrNumber (\r
829 IN CONST MEMORY_RANGE *Ranges,\r
830 IN UINT32 RangeCount,\r
831 IN CONST VARIABLE_MTRR *VariableMtrr,\r
832 IN UINT32 VariableMtrrCount,\r
833 IN UINT64 BaseAddress,\r
834 IN UINT64 Length,\r
835 IN MTRR_MEMORY_CACHE_TYPE Type,\r
836 IN UINT64 Alignment0,\r
837 OUT UINT32 *SubLeft, // subtractive from BaseAddress to get more aligned address, to save MTRR\r
838 OUT UINT32 *SubRight // subtractive from BaseAddress + Length, to save MTRR\r
839)\r
e50466da 840{\r
1a2ad6fc 841 UINT64 Alignment;\r
8051302a
RN
842 UINT32 LeastLeftMtrrNumber;\r
843 UINT32 MiddleMtrrNumber;\r
844 UINT32 LeastRightMtrrNumber;\r
845 UINT32 CurrentMtrrNumber;\r
846 UINT32 SubtractiveCount;\r
847 UINT32 SubtractiveMtrrNumber;\r
848 UINT32 LeastSubtractiveMtrrNumber;\r
849 UINT64 SubtractiveBaseAddress;\r
850 UINT64 SubtractiveLength;\r
851 UINT64 BaseAlignment;\r
852 UINT32 Index;\r
e50466da 853\r
8051302a
RN
854 *SubLeft = 0;\r
855 *SubRight = 0;\r
856 LeastSubtractiveMtrrNumber = 0;\r
1a2ad6fc 857\r
8051302a
RN
858 //\r
859 // Get the optimal left subtraction solution.\r
860 //\r
1a2ad6fc 861 if (BaseAddress != 0) {\r
8051302a
RN
862 //\r
863 // Get the MTRR number needed without left subtraction.\r
864 //\r
865 LeastLeftMtrrNumber = MtrrLibGetPositiveMtrrNumber (BaseAddress, Length, Alignment0);\r
866\r
867 //\r
868 // Left subtraction bit by bit, to find the optimal left subtraction solution.\r
869 //\r
870 for (SubtractiveMtrrNumber = 0, SubtractiveCount = 1; BaseAddress != 0; SubtractiveCount++) {\r
871 Alignment = MtrrLibLeastAlignment (BaseAddress, Alignment0);\r
872\r
1a2ad6fc 873 //\r
8051302a
RN
874 // Check whether the memory type of [BaseAddress - Alignment, BaseAddress) can override Type.\r
875 // IA32 Manual defines the following override rules:\r
876 // WT > WB\r
877 // UC > * (any)\r
1a2ad6fc 878 //\r
8051302a 879 if (!MtrrLibSubstractable (Ranges, RangeCount, Type, BaseAddress - Alignment, Alignment)) {\r
1a2ad6fc 880 break;\r
881 }\r
882\r
8051302a
RN
883 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
884 if ((VariableMtrr[Index].BaseAddress == BaseAddress - Alignment) &&\r
885 (VariableMtrr[Index].Length == Alignment)) {\r
886 break;\r
887 }\r
888 }\r
889 if (Index == VariableMtrrCount) {\r
890 //\r
891 // Increment SubtractiveMtrrNumber when [BaseAddress - Alignment, BaseAddress) is not be planed as a MTRR\r
892 //\r
893 SubtractiveMtrrNumber++;\r
894 }\r
e50466da 895\r
8051302a
RN
896 BaseAddress -= Alignment;\r
897 Length += Alignment;\r
e50466da 898\r
8051302a
RN
899 CurrentMtrrNumber = SubtractiveMtrrNumber + MtrrLibGetPositiveMtrrNumber (BaseAddress, Length, Alignment0);\r
900 if (CurrentMtrrNumber <= LeastLeftMtrrNumber) {\r
901 LeastLeftMtrrNumber = CurrentMtrrNumber;\r
902 LeastSubtractiveMtrrNumber = SubtractiveMtrrNumber;\r
903 *SubLeft = SubtractiveCount;\r
904 SubtractiveBaseAddress = BaseAddress;\r
905 SubtractiveLength = Length;\r
906 }\r
907 }\r
e50466da 908\r
8051302a
RN
909 //\r
910 // If left subtraction is better, subtract BaseAddress to left, and enlarge Length\r
911 //\r
912 if (*SubLeft != 0) {\r
913 BaseAddress = SubtractiveBaseAddress;\r
914 Length = SubtractiveLength;\r
915 }\r
e50466da 916 }\r
e50466da 917\r
8051302a
RN
918 //\r
919 // Increment BaseAddress greedily until (BaseAddress + Alignment) exceeds (BaseAddress + Length)\r
920 //\r
921 MiddleMtrrNumber = 0;\r
922 while (Length != 0) {\r
923 BaseAlignment = MtrrLibLeastAlignment (BaseAddress, Alignment0);\r
924 if (BaseAlignment > Length) {\r
925 break;\r
e50466da 926 }\r
8051302a
RN
927 BaseAddress += BaseAlignment;\r
928 Length -= BaseAlignment;\r
929 MiddleMtrrNumber++;\r
e50466da 930 }\r
e50466da 931\r
932\r
8051302a
RN
933 if (Length == 0) {\r
934 return LeastSubtractiveMtrrNumber + MiddleMtrrNumber;\r
935 }\r
e50466da 936\r
e50466da 937\r
938 //\r
8051302a 939 // Get the optimal right subtraction solution.\r
e50466da 940 //\r
e50466da 941\r
942 //\r
8051302a 943 // Get the MTRR number needed without right subtraction.\r
e50466da 944 //\r
8051302a
RN
945 LeastRightMtrrNumber = MtrrLibGetPositiveMtrrNumber (BaseAddress, Length, Alignment0);\r
946\r
947 for (SubtractiveCount = 1; Length < BaseAlignment; SubtractiveCount++) {\r
948 Alignment = MtrrLibLeastAlignment (BaseAddress + Length, Alignment0);\r
949 if (!MtrrLibSubstractable (Ranges, RangeCount, Type, BaseAddress + Length, Alignment)) {\r
950 break;\r
951 }\r
952\r
953 Length += Alignment;\r
954\r
955 //\r
956 // SubtractiveCount = Number of MTRRs used for subtraction\r
957 //\r
958 CurrentMtrrNumber = SubtractiveCount + MtrrLibGetPositiveMtrrNumber (BaseAddress, Length, Alignment0);\r
959 if (CurrentMtrrNumber <= LeastRightMtrrNumber) {\r
960 LeastRightMtrrNumber = CurrentMtrrNumber;\r
961 *SubRight = SubtractiveCount;\r
962 SubtractiveLength = Length;\r
963 }\r
964 }\r
965\r
966 return LeastSubtractiveMtrrNumber + MiddleMtrrNumber + LeastRightMtrrNumber;\r
e50466da 967}\r
968\r
e50466da 969/**\r
970 Initializes the valid bits mask and valid address mask for MTRRs.\r
971\r
972 This function initializes the valid bits mask and valid address mask for MTRRs.\r
973\r
76b4cae3
MK
974 @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
975 @param[out] MtrrValidAddressMask The valid address mask for the MTRR\r
e50466da 976\r
977**/\r
e50466da 978VOID\r
979MtrrLibInitializeMtrrMask (\r
980 OUT UINT64 *MtrrValidBitsMask,\r
981 OUT UINT64 *MtrrValidAddressMask\r
982 )\r
983{\r
012f4054
RN
984 UINT32 MaxExtendedFunction;\r
985 CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;\r
e50466da 986\r
e50466da 987\r
012f4054 988 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);\r
e50466da 989\r
012f4054
RN
990 if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
991 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);\r
e50466da 992 } else {\r
012f4054 993 VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
e50466da 994 }\r
012f4054
RN
995\r
996 *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
997 *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;\r
e50466da 998}\r
999\r
1000\r
1001/**\r
76b4cae3 1002 Determines the real attribute of a memory range.\r
e50466da 1003\r
1004 This function is to arbitrate the real attribute of the memory when\r
10c361ad 1005 there are 2 MTRRs covers the same memory range. For further details,\r
e50466da 1006 please refer the IA32 Software Developer's Manual, Volume 3,\r
10c361ad 1007 Section "MTRR Precedences".\r
e50466da 1008\r
76b4cae3
MK
1009 @param[in] MtrrType1 The first kind of Memory type\r
1010 @param[in] MtrrType2 The second kind of memory type\r
e50466da 1011\r
1012**/\r
10c361ad 1013MTRR_MEMORY_CACHE_TYPE\r
b8f01599 1014MtrrLibPrecedence (\r
10c361ad
RN
1015 IN MTRR_MEMORY_CACHE_TYPE MtrrType1,\r
1016 IN MTRR_MEMORY_CACHE_TYPE MtrrType2\r
e50466da 1017 )\r
1018{\r
10c361ad
RN
1019 if (MtrrType1 == MtrrType2) {\r
1020 return MtrrType1;\r
e50466da 1021 }\r
1022\r
10c361ad
RN
1023 ASSERT (\r
1024 MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) ||\r
1025 MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1)\r
1026 );\r
1027\r
1028 if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) {\r
1029 return MtrrType1;\r
1030 } else {\r
1031 return MtrrType2;\r
e50466da 1032 }\r
e50466da 1033}\r
1034\r
e50466da 1035/**\r
5abd5ed4 1036 Worker function will get the memory cache type of the specific address.\r
e50466da 1037\r
5abd5ed4
MK
1038 If MtrrSetting is not NULL, gets the memory cache type from input\r
1039 MTRR settings buffer.\r
1040 If MtrrSetting is NULL, gets the memory cache type from MTRRs.\r
e50466da 1041\r
5abd5ed4 1042 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
85b7f65b
MK
1043 @param[in] Address The specific address\r
1044\r
1045 @return Memory cache type of the specific address\r
e50466da 1046\r
1047**/\r
85b7f65b 1048MTRR_MEMORY_CACHE_TYPE\r
5abd5ed4
MK
1049MtrrGetMemoryAttributeByAddressWorker (\r
1050 IN MTRR_SETTINGS *MtrrSetting,\r
85b7f65b 1051 IN PHYSICAL_ADDRESS Address\r
e50466da 1052 )\r
1053{\r
10c361ad
RN
1054 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
1055 UINT64 FixedMtrr;\r
1056 UINTN Index;\r
1057 UINTN SubIndex;\r
1058 MTRR_MEMORY_CACHE_TYPE MtrrType;\r
1059 VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
1060 UINT64 MtrrValidBitsMask;\r
1061 UINT64 MtrrValidAddressMask;\r
1062 UINT32 VariableMtrrCount;\r
1063 MTRR_VARIABLE_SETTINGS VariableSettings;\r
f877f300 1064\r
e50466da 1065 //\r
85b7f65b 1066 // Check if MTRR is enabled, if not, return UC as attribute\r
e50466da 1067 //\r
5abd5ed4 1068 if (MtrrSetting == NULL) {\r
10c361ad 1069 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
5abd5ed4 1070 } else {\r
10c361ad 1071 DefType.Uint64 = MtrrSetting->MtrrDefType;\r
5abd5ed4 1072 }\r
e50466da 1073\r
10c361ad 1074 if (DefType.Bits.E == 0) {\r
85b7f65b 1075 return CacheUncacheable;\r
e50466da 1076 }\r
1077\r
1078 //\r
85b7f65b 1079 // If address is less than 1M, then try to go through the fixed MTRR\r
e50466da 1080 //\r
85b7f65b 1081 if (Address < BASE_1MB) {\r
10c361ad 1082 if (DefType.Bits.FE != 0) {\r
85b7f65b
MK
1083 //\r
1084 // Go through the fixed MTRR\r
1085 //\r
1086 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
10c361ad
RN
1087 if (Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress &&\r
1088 Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +\r
1089 (mMtrrLibFixedMtrrTable[Index].Length * 8)) {\r
1090 SubIndex =\r
1091 ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /\r
1092 mMtrrLibFixedMtrrTable[Index].Length;\r
1093 if (MtrrSetting == NULL) {\r
1094 FixedMtrr = AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
1095 } else {\r
1096 FixedMtrr = MtrrSetting->Fixed.Mtrr[Index];\r
1097 }\r
1098 return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);\r
1099 }\r
85b7f65b 1100 }\r
e50466da 1101 }\r
1102 }\r
d0baed7d 1103\r
10c361ad
RN
1104 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
1105 ASSERT (VariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
1106 MtrrGetVariableMtrrWorker (MtrrSetting, VariableMtrrCount, &VariableSettings);\r
e50466da 1107\r
10c361ad 1108 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
d0baed7d 1109 MtrrGetMemoryAttributeInVariableMtrrWorker (\r
10c361ad
RN
1110 &VariableSettings,\r
1111 VariableMtrrCount,\r
1112 MtrrValidBitsMask,\r
1113 MtrrValidAddressMask,\r
1114 VariableMtrr\r
1115 );\r
d0baed7d 1116\r
e50466da 1117 //\r
85b7f65b 1118 // Go through the variable MTRR\r
e50466da 1119 //\r
10c361ad 1120 MtrrType = CacheInvalid;\r
85b7f65b
MK
1121 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
1122 if (VariableMtrr[Index].Valid) {\r
1123 if (Address >= VariableMtrr[Index].BaseAddress &&\r
10c361ad
RN
1124 Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length) {\r
1125 if (MtrrType == CacheInvalid) {\r
1126 MtrrType = (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type;\r
1127 } else {\r
1128 MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type);\r
1129 }\r
85b7f65b
MK
1130 }\r
1131 }\r
e50466da 1132 }\r
1133\r
10c361ad
RN
1134 //\r
1135 // If there is no MTRR which covers the Address, use the default MTRR type.\r
1136 //\r
1137 if (MtrrType == CacheInvalid) {\r
1138 MtrrType = (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
1139 }\r
1140\r
1141 return MtrrType;\r
85b7f65b
MK
1142}\r
1143\r
1144\r
5abd5ed4
MK
1145/**\r
1146 This function will get the memory cache type of the specific address.\r
1147\r
1148 This function is mainly for debug purpose.\r
1149\r
1150 @param[in] Address The specific address\r
1151\r
1152 @return Memory cache type of the specific address\r
1153\r
1154**/\r
1155MTRR_MEMORY_CACHE_TYPE\r
1156EFIAPI\r
1157MtrrGetMemoryAttribute (\r
1158 IN PHYSICAL_ADDRESS Address\r
1159 )\r
1160{\r
1161 if (!IsMtrrSupported ()) {\r
1162 return CacheUncacheable;\r
1163 }\r
1164\r
1165 return MtrrGetMemoryAttributeByAddressWorker (NULL, Address);\r
1166}\r
1167\r
85b7f65b 1168/**\r
16c2d37e
MK
1169 Worker function prints all MTRRs for debugging.\r
1170\r
341fea64 1171 If MtrrSetting is not NULL, print MTRR settings from input MTRR\r
16c2d37e
MK
1172 settings buffer.\r
1173 If MtrrSetting is NULL, print MTRR settings from MTRRs.\r
1174\r
1175 @param MtrrSetting A buffer holding all MTRRs content.\r
85b7f65b
MK
1176**/\r
1177VOID\r
16c2d37e
MK
1178MtrrDebugPrintAllMtrrsWorker (\r
1179 IN MTRR_SETTINGS *MtrrSetting\r
85b7f65b
MK
1180 )\r
1181{\r
1182 DEBUG_CODE (\r
16c2d37e
MK
1183 MTRR_SETTINGS LocalMtrrs;\r
1184 MTRR_SETTINGS *Mtrrs;\r
85b7f65b
MK
1185 UINTN Index;\r
1186 UINTN Index1;\r
1187 UINTN VariableMtrrCount;\r
1188 UINT64 Base;\r
1189 UINT64 Limit;\r
1190 UINT64 MtrrBase;\r
1191 UINT64 MtrrLimit;\r
1192 UINT64 RangeBase;\r
1193 UINT64 RangeLimit;\r
1194 UINT64 NoRangeBase;\r
1195 UINT64 NoRangeLimit;\r
1196 UINT32 RegEax;\r
1197 UINTN MemoryType;\r
1198 UINTN PreviousMemoryType;\r
1199 BOOLEAN Found;\r
1200\r
1201 if (!IsMtrrSupported ()) {\r
1202 return;\r
1203 }\r
1204\r
1205 DEBUG((DEBUG_CACHE, "MTRR Settings\n"));\r
1206 DEBUG((DEBUG_CACHE, "=============\n"));\r
1207\r
16c2d37e
MK
1208 if (MtrrSetting != NULL) {\r
1209 Mtrrs = MtrrSetting;\r
1210 } else {\r
1211 MtrrGetAllMtrrs (&LocalMtrrs);\r
1212 Mtrrs = &LocalMtrrs;\r
1213 }\r
1214\r
1215 DEBUG((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));\r
85b7f65b 1216 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
16c2d37e 1217 DEBUG((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));\r
85b7f65b
MK
1218 }\r
1219\r
1220 VariableMtrrCount = GetVariableMtrrCount ();\r
1221 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
1222 DEBUG((DEBUG_CACHE, "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",\r
1223 Index,\r
16c2d37e
MK
1224 Mtrrs->Variables.Mtrr[Index].Base,\r
1225 Mtrrs->Variables.Mtrr[Index].Mask\r
85b7f65b
MK
1226 ));\r
1227 }\r
1228 DEBUG((DEBUG_CACHE, "\n"));\r
1229 DEBUG((DEBUG_CACHE, "MTRR Ranges\n"));\r
1230 DEBUG((DEBUG_CACHE, "====================================\n"));\r
1231\r
1232 Base = 0;\r
1233 PreviousMemoryType = MTRR_CACHE_INVALID_TYPE;\r
1234 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
1235 Base = mMtrrLibFixedMtrrTable[Index].BaseAddress;\r
1236 for (Index1 = 0; Index1 < 8; Index1++) {\r
16c2d37e 1237 MemoryType = (UINTN)(RShiftU64 (Mtrrs->Fixed.Mtrr[Index], Index1 * 8) & 0xff);\r
85b7f65b
MK
1238 if (MemoryType > CacheWriteBack) {\r
1239 MemoryType = MTRR_CACHE_INVALID_TYPE;\r
1240 }\r
1241 if (MemoryType != PreviousMemoryType) {\r
1242 if (PreviousMemoryType != MTRR_CACHE_INVALID_TYPE) {\r
1243 DEBUG((DEBUG_CACHE, "%016lx\n", Base - 1));\r
1244 }\r
1245 PreviousMemoryType = MemoryType;\r
1246 DEBUG((DEBUG_CACHE, "%a:%016lx-", mMtrrMemoryCacheTypeShortName[MemoryType], Base));\r
1247 }\r
1248 Base += mMtrrLibFixedMtrrTable[Index].Length;\r
1249 }\r
1250 }\r
1251 DEBUG((DEBUG_CACHE, "%016lx\n", Base - 1));\r
1252\r
1253 VariableMtrrCount = GetVariableMtrrCount ();\r
1254\r
1255 Limit = BIT36 - 1;\r
1256 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
1257 if (RegEax >= 0x80000008) {\r
1258 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
1259 Limit = LShiftU64 (1, RegEax & 0xff) - 1;\r
1260 }\r
1261 Base = BASE_1MB;\r
1262 PreviousMemoryType = MTRR_CACHE_INVALID_TYPE;\r
1263 do {\r
16c2d37e 1264 MemoryType = MtrrGetMemoryAttributeByAddressWorker (Mtrrs, Base);\r
85b7f65b
MK
1265 if (MemoryType > CacheWriteBack) {\r
1266 MemoryType = MTRR_CACHE_INVALID_TYPE;\r
1267 }\r
1268\r
1269 if (MemoryType != PreviousMemoryType) {\r
1270 if (PreviousMemoryType != MTRR_CACHE_INVALID_TYPE) {\r
1271 DEBUG((DEBUG_CACHE, "%016lx\n", Base - 1));\r
1272 }\r
1273 PreviousMemoryType = MemoryType;\r
1274 DEBUG((DEBUG_CACHE, "%a:%016lx-", mMtrrMemoryCacheTypeShortName[MemoryType], Base));\r
1275 }\r
1276\r
1277 RangeBase = BASE_1MB;\r
1278 NoRangeBase = BASE_1MB;\r
1279 RangeLimit = Limit;\r
1280 NoRangeLimit = Limit;\r
1281\r
1282 for (Index = 0, Found = FALSE; Index < VariableMtrrCount; Index++) {\r
16c2d37e 1283 if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {\r
85b7f65b
MK
1284 //\r
1285 // If mask is not valid, then do not display range\r
1286 //\r
1287 continue;\r
1288 }\r
16c2d37e
MK
1289 MtrrBase = (Mtrrs->Variables.Mtrr[Index].Base & (~(SIZE_4KB - 1)));\r
1290 MtrrLimit = MtrrBase + ((~(Mtrrs->Variables.Mtrr[Index].Mask & (~(SIZE_4KB - 1)))) & Limit);\r
85b7f65b
MK
1291\r
1292 if (Base >= MtrrBase && Base < MtrrLimit) {\r
1293 Found = TRUE;\r
1294 }\r
1295\r
1296 if (Base >= MtrrBase && MtrrBase > RangeBase) {\r
1297 RangeBase = MtrrBase;\r
1298 }\r
1299 if (Base > MtrrLimit && MtrrLimit > RangeBase) {\r
1300 RangeBase = MtrrLimit + 1;\r
1301 }\r
1302 if (Base < MtrrBase && MtrrBase < RangeLimit) {\r
1303 RangeLimit = MtrrBase - 1;\r
1304 }\r
1305 if (Base < MtrrLimit && MtrrLimit <= RangeLimit) {\r
1306 RangeLimit = MtrrLimit;\r
1307 }\r
1308\r
1309 if (Base > MtrrLimit && NoRangeBase < MtrrLimit) {\r
1310 NoRangeBase = MtrrLimit + 1;\r
1311 }\r
1312 if (Base < MtrrBase && NoRangeLimit > MtrrBase) {\r
1313 NoRangeLimit = MtrrBase - 1;\r
1314 }\r
1315 }\r
1316\r
1317 if (Found) {\r
1318 Base = RangeLimit + 1;\r
1319 } else {\r
1320 Base = NoRangeLimit + 1;\r
1321 }\r
1322 } while (Base < Limit);\r
1323 DEBUG((DEBUG_CACHE, "%016lx\n\n", Base - 1));\r
1324 );\r
1325}\r
16c2d37e
MK
1326\r
1327\r
1328/**\r
1329 This function prints all MTRRs for debugging.\r
1330**/\r
1331VOID\r
1332EFIAPI\r
1333MtrrDebugPrintAllMtrrs (\r
1334 VOID\r
1335 )\r
1336{\r
1337 MtrrDebugPrintAllMtrrsWorker (NULL);\r
1338}\r
1339\r
8051302a
RN
1340/**\r
1341 Update the Ranges array to change the specified range identified by\r
1342 BaseAddress and Length to Type.\r
1343\r
1344 @param Ranges Array holding memory type settings for all memory regions.\r
1345 @param Capacity The maximum count of memory ranges the array can hold.\r
1346 @param Count Return the new memory range count in the array.\r
1347 @param BaseAddress The base address of the memory range to change type.\r
1348 @param Length The length of the memory range to change type.\r
1349 @param Type The new type of the specified memory range.\r
1350\r
1351 @retval RETURN_SUCCESS The type of the specified memory range is\r
1352 changed successfully.\r
1353 @retval RETURN_OUT_OF_RESOURCES The new type set causes the count of memory\r
1354 range exceeds capacity.\r
1355**/\r
1356RETURN_STATUS\r
1357MtrrLibSetMemoryType (\r
1358 IN MEMORY_RANGE *Ranges,\r
1359 IN UINT32 Capacity,\r
1360 IN OUT UINT32 *Count,\r
1361 IN UINT64 BaseAddress,\r
1362 IN UINT64 Length,\r
1363 IN MTRR_MEMORY_CACHE_TYPE Type\r
1364 )\r
1365{\r
1366 UINT32 Index;\r
1367 UINT64 Limit;\r
1368 UINT64 LengthLeft;\r
1369 UINT64 LengthRight;\r
1370 UINT32 StartIndex;\r
1371 UINT32 EndIndex;\r
1372 UINT32 DeltaCount;\r
1373\r
1374 Limit = BaseAddress + Length;\r
1375 StartIndex = *Count;\r
1376 EndIndex = *Count;\r
1377 for (Index = 0; Index < *Count; Index++) {\r
1378 if ((StartIndex == *Count) &&\r
1379 (Ranges[Index].BaseAddress <= BaseAddress) &&\r
1380 (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
1381 StartIndex = Index;\r
1382 LengthLeft = BaseAddress - Ranges[Index].BaseAddress;\r
1383 }\r
1384\r
1385 if ((EndIndex == *Count) &&\r
1386 (Ranges[Index].BaseAddress < Limit) &&\r
1387 (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
1388 EndIndex = Index;\r
1389 LengthRight = Ranges[Index].BaseAddress + Ranges[Index].Length - Limit;\r
1390 break;\r
1391 }\r
1392 }\r
1393\r
1394 ASSERT (StartIndex != *Count && EndIndex != *Count);\r
1395 if (StartIndex == EndIndex && Ranges[StartIndex].Type == Type) {\r
1396 return RETURN_SUCCESS;\r
1397 }\r
1398\r
1399 //\r
1400 // The type change may cause merging with previous range or next range.\r
1401 // Update the StartIndex, EndIndex, BaseAddress, Length so that following\r
1402 // logic doesn't need to consider merging.\r
1403 //\r
1404 if (StartIndex != 0) {\r
1405 if (LengthLeft == 0 && Ranges[StartIndex - 1].Type == Type) {\r
1406 StartIndex--;\r
1407 Length += Ranges[StartIndex].Length;\r
1408 BaseAddress -= Ranges[StartIndex].Length;\r
1409 }\r
1410 }\r
1411 if (EndIndex != (*Count) - 1) {\r
1412 if (LengthRight == 0 && Ranges[EndIndex + 1].Type == Type) {\r
1413 EndIndex++;\r
1414 Length += Ranges[EndIndex].Length;\r
1415 }\r
1416 }\r
1417\r
1418 //\r
1419 // |- 0 -|- 1 -|- 2 -|- 3 -| StartIndex EndIndex DeltaCount Count (Count = 4)\r
1420 // |++++++++++++++++++| 0 3 1=3-0-2 3\r
1421 // |+++++++| 0 1 -1=1-0-2 5\r
1422 // |+| 0 0 -2=0-0-2 6\r
1423 // |+++| 0 0 -1=0-0-2+1 5\r
1424 //\r
1425 //\r
1426 DeltaCount = EndIndex - StartIndex - 2;\r
1427 if (LengthLeft == 0) {\r
1428 DeltaCount++;\r
1429 }\r
1430 if (LengthRight == 0) {\r
1431 DeltaCount++;\r
1432 }\r
1433 if (*Count - DeltaCount > Capacity) {\r
1434 return RETURN_OUT_OF_RESOURCES;\r
1435 }\r
1436\r
1437 //\r
1438 // Reserve (-DeltaCount) space\r
1439 //\r
1440 CopyMem (&Ranges[EndIndex + 1 - DeltaCount], &Ranges[EndIndex + 1], (*Count - EndIndex - 1) * sizeof (Ranges[0]));\r
1441 *Count -= DeltaCount;\r
1442\r
1443 if (LengthLeft != 0) {\r
1444 Ranges[StartIndex].Length = LengthLeft;\r
1445 StartIndex++;\r
1446 }\r
1447 if (LengthRight != 0) {\r
1448 Ranges[EndIndex - DeltaCount].BaseAddress = BaseAddress + Length;\r
1449 Ranges[EndIndex - DeltaCount].Length = LengthRight;\r
1450 Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type;\r
1451 }\r
1452 Ranges[StartIndex].BaseAddress = BaseAddress;\r
1453 Ranges[StartIndex].Length = Length;\r
1454 Ranges[StartIndex].Type = Type;\r
1455 return RETURN_SUCCESS;\r
1456}\r
1457\r
1458/**\r
1459 Allocate one or more variable MTRR to cover the range identified by\r
1460 BaseAddress and Length.\r
1461\r
1462 @param Ranges Memory range array holding the memory type\r
1463 settings for all memory address.\r
1464 @param RangeCount Count of memory ranges.\r
1465 @param VariableMtrr Variable MTRR array.\r
1466 @param VariableMtrrCapacity Capacity of variable MTRR array.\r
1467 @param VariableMtrrCount Count of variable MTRR.\r
1468 @param BaseAddress Base address of the memory range.\r
1469 @param Length Length of the memory range.\r
1470 @param Type MTRR type of the memory range.\r
1471 @param Alignment0 Alignment of 0.\r
1472\r
1473 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.\r
1474 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.\r
1475**/\r
1476RETURN_STATUS\r
1477MtrrLibSetMemoryAttributeInVariableMtrr (\r
1478 IN CONST MEMORY_RANGE *Ranges,\r
1479 IN UINT32 RangeCount,\r
1480 IN OUT VARIABLE_MTRR *VariableMtrr,\r
1481 IN UINT32 VariableMtrrCapacity,\r
1482 IN OUT UINT32 *VariableMtrrCount,\r
1483 IN UINT64 BaseAddress,\r
1484 IN UINT64 Length,\r
1485 IN MTRR_MEMORY_CACHE_TYPE Type,\r
1486 IN UINT64 Alignment0\r
1487 );\r
1488\r
1489/**\r
1490 Allocate one or more variable MTRR to cover the range identified by\r
1491 BaseAddress and Length.\r
1492\r
1493 The routine recursively calls MtrrLibSetMemoryAttributeInVariableMtrr()\r
1494 to allocate variable MTRRs when the range contains several sub-ranges\r
1495 with different attributes.\r
1496\r
1497 @param Ranges Memory range array holding the memory type\r
1498 settings for all memory address.\r
1499 @param RangeCount Count of memory ranges.\r
1500 @param VariableMtrr Variable MTRR array.\r
1501 @param VariableMtrrCapacity Capacity of variable MTRR array.\r
1502 @param VariableMtrrCount Count of variable MTRR.\r
1503 @param BaseAddress Base address of the memory range.\r
1504 @param Length Length of the memory range.\r
1505 @param Type MTRR type of the range.\r
1506 If it's CacheInvalid, the memory range may\r
1507 contains several sub-ranges with different\r
1508 attributes.\r
1509 @param Alignment0 Alignment of 0.\r
1510\r
1511 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.\r
1512 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.\r
1513**/\r
1514RETURN_STATUS\r
1515MtrrLibAddVariableMtrr (\r
1516 IN CONST MEMORY_RANGE *Ranges,\r
1517 IN UINT32 RangeCount,\r
1518 IN OUT VARIABLE_MTRR *VariableMtrr,\r
1519 IN UINT32 VariableMtrrCapacity,\r
1520 IN OUT UINT32 *VariableMtrrCount,\r
1521 IN PHYSICAL_ADDRESS BaseAddress,\r
1522 IN UINT64 Length,\r
1523 IN MTRR_MEMORY_CACHE_TYPE Type,\r
1524 IN UINT64 Alignment0\r
1525)\r
1526{\r
1527 RETURN_STATUS Status;\r
1528 UINT32 Index;\r
1529 UINT64 SubLength;\r
1530\r
1531 MTRR_LIB_ASSERT_ALIGNED (BaseAddress, Length);\r
1532 if (Type == CacheInvalid) {\r
1533 for (Index = 0; Index < RangeCount; Index++) {\r
1534 if (Ranges[Index].BaseAddress <= BaseAddress && BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
1535\r
1536 //\r
1537 // Because the Length may not be aligned to BaseAddress, below code calls\r
1538 // MtrrLibSetMemoryAttributeInVariableMtrr() instead of itself.\r
1539 // MtrrLibSetMemoryAttributeInVariableMtrr() splits the range to several\r
1540 // aligned ranges.\r
1541 //\r
1542 if (Ranges[Index].BaseAddress + Ranges[Index].Length >= BaseAddress + Length) {\r
1543 return MtrrLibSetMemoryAttributeInVariableMtrr (\r
1544 Ranges, RangeCount, VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
1545 BaseAddress, Length, Ranges[Index].Type, Alignment0\r
1546 );\r
1547 } else {\r
1548 SubLength = Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;\r
1549 Status = MtrrLibSetMemoryAttributeInVariableMtrr (\r
1550 Ranges, RangeCount, VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
1551 BaseAddress, SubLength, Ranges[Index].Type, Alignment0\r
1552 );\r
1553 if (RETURN_ERROR (Status)) {\r
1554 return Status;\r
1555 }\r
1556 BaseAddress += SubLength;\r
1557 Length -= SubLength;\r
1558 }\r
1559 }\r
1560 }\r
1561\r
1562 //\r
1563 // Because memory ranges cover all the memory addresses, it's impossible to be here.\r
1564 //\r
1565 ASSERT (FALSE);\r
1566 return RETURN_DEVICE_ERROR;\r
1567 } else {\r
1568 for (Index = 0; Index < *VariableMtrrCount; Index++) {\r
1569 if (VariableMtrr[Index].BaseAddress == BaseAddress && VariableMtrr[Index].Length == Length) {\r
1570 ASSERT (VariableMtrr[Index].Type == Type);\r
1571 break;\r
1572 }\r
1573 }\r
1574 if (Index == *VariableMtrrCount) {\r
1575 if (*VariableMtrrCount == VariableMtrrCapacity) {\r
1576 return RETURN_OUT_OF_RESOURCES;\r
1577 }\r
1578 VariableMtrr[Index].BaseAddress = BaseAddress;\r
1579 VariableMtrr[Index].Length = Length;\r
1580 VariableMtrr[Index].Type = Type;\r
1581 VariableMtrr[Index].Valid = TRUE;\r
1582 VariableMtrr[Index].Used = TRUE;\r
1583 (*VariableMtrrCount)++;\r
1584 }\r
1585 return RETURN_SUCCESS;\r
1586 }\r
1587}\r
1588\r
1589/**\r
1590 Allocate one or more variable MTRR to cover the range identified by\r
1591 BaseAddress and Length.\r
1592\r
1593 @param Ranges Memory range array holding the memory type\r
1594 settings for all memory address.\r
1595 @param RangeCount Count of memory ranges.\r
1596 @param VariableMtrr Variable MTRR array.\r
1597 @param VariableMtrrCapacity Capacity of variable MTRR array.\r
1598 @param VariableMtrrCount Count of variable MTRR.\r
1599 @param BaseAddress Base address of the memory range.\r
1600 @param Length Length of the memory range.\r
1601 @param Type MTRR type of the memory range.\r
1602 @param Alignment0 Alignment of 0.\r
1603\r
1604 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.\r
1605 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.\r
1606**/\r
1607RETURN_STATUS\r
1608MtrrLibSetMemoryAttributeInVariableMtrr (\r
1609 IN CONST MEMORY_RANGE *Ranges,\r
1610 IN UINT32 RangeCount,\r
1611 IN OUT VARIABLE_MTRR *VariableMtrr,\r
1612 IN UINT32 VariableMtrrCapacity,\r
1613 IN OUT UINT32 *VariableMtrrCount,\r
1614 IN UINT64 BaseAddress,\r
1615 IN UINT64 Length,\r
1616 IN MTRR_MEMORY_CACHE_TYPE Type,\r
1617 IN UINT64 Alignment0\r
1618)\r
1619{\r
1620 UINT64 Alignment;\r
1621 UINT32 MtrrNumber;\r
1622 UINT32 SubtractiveLeft;\r
1623 UINT32 SubtractiveRight;\r
1624 BOOLEAN UseLeastAlignment;\r
1625\r
1626 MtrrNumber = MtrrLibGetMtrrNumber (Ranges, RangeCount, VariableMtrr, *VariableMtrrCount,\r
1627 BaseAddress, Length, Type, Alignment0, &SubtractiveLeft, &SubtractiveRight);\r
1628\r
1629 if (MtrrNumber + *VariableMtrrCount > VariableMtrrCapacity) {\r
1630 return RETURN_OUT_OF_RESOURCES;\r
1631 }\r
1632\r
1633 while (SubtractiveLeft-- != 0) {\r
1634 Alignment = MtrrLibLeastAlignment (BaseAddress, Alignment0);\r
1635 ASSERT (Alignment <= Length);\r
1636\r
1637 MtrrLibAddVariableMtrr (Ranges, RangeCount, VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
1638 BaseAddress - Alignment, Alignment, CacheInvalid, Alignment0);\r
1639 BaseAddress -= Alignment;\r
1640 Length += Alignment;\r
1641 }\r
1642\r
1643 while (Length != 0) {\r
1644 Alignment = MtrrLibLeastAlignment (BaseAddress, Alignment0);\r
1645 if (Alignment > Length) {\r
1646 break;\r
1647 }\r
1648 MtrrLibAddVariableMtrr (NULL, 0, VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
1649 BaseAddress, Alignment, Type, Alignment0);\r
1650 BaseAddress += Alignment;\r
1651 Length -= Alignment;\r
1652 }\r
1653\r
1654 while (SubtractiveRight-- != 0) {\r
1655 Alignment = MtrrLibLeastAlignment (BaseAddress + Length, Alignment0);\r
1656 MtrrLibAddVariableMtrr (Ranges, RangeCount, VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
1657 BaseAddress + Length, Alignment, CacheInvalid, Alignment0);\r
1658 Length += Alignment;\r
1659 }\r
1660\r
1661 UseLeastAlignment = TRUE;\r
1662 while (Length != 0) {\r
1663 if (UseLeastAlignment) {\r
1664 Alignment = MtrrLibLeastAlignment (BaseAddress, Alignment0);\r
1665 if (Alignment > Length) {\r
1666 UseLeastAlignment = FALSE;\r
1667 }\r
1668 }\r
1669\r
1670 if (!UseLeastAlignment) {\r
1671 Alignment = GetPowerOfTwo64 (Length);\r
1672 }\r
1673\r
1674 MtrrLibAddVariableMtrr (NULL, 0, VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
1675 BaseAddress, Alignment, Type, Alignment0);\r
1676 BaseAddress += Alignment;\r
1677 Length -= Alignment;\r
1678 }\r
1679 return RETURN_SUCCESS;\r
1680}\r
1681\r
1682/**\r
1683 Return an array of memory ranges holding memory type settings for all memory\r
1684 address.\r
1685\r
1686 @param DefaultType The default memory type.\r
1687 @param TotalLength The total length of the memory.\r
1688 @param VariableMtrr The variable MTRR array.\r
1689 @param VariableMtrrCount The count of variable MTRRs.\r
1690 @param Ranges Return the memory range array holding memory type\r
1691 settings for all memory address.\r
1692 @param RangeCapacity The capacity of memory range array.\r
1693 @param RangeCount Return the count of memory range.\r
1694\r
1695 @retval RETURN_SUCCESS The memory range array is returned successfully.\r
1696 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.\r
1697**/\r
1698RETURN_STATUS\r
1699MtrrLibGetMemoryTypes (\r
1700 IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
1701 IN UINT64 TotalLength,\r
1702 IN CONST VARIABLE_MTRR *VariableMtrr,\r
1703 IN UINT32 VariableMtrrCount,\r
1704 OUT MEMORY_RANGE *Ranges,\r
1705 IN UINT32 RangeCapacity,\r
1706 OUT UINT32 *RangeCount\r
1707)\r
1708{\r
1709 RETURN_STATUS Status;\r
1710 UINTN Index;\r
1711\r
1712 //\r
1713 // WT > WB\r
1714 // UC > *\r
1715 // UC > * (except WB, UC) > WB\r
1716 //\r
1717\r
1718 //\r
1719 // 0. Set whole range as DefaultType\r
1720 //\r
1721 *RangeCount = 1;\r
1722 Ranges[0].BaseAddress = 0;\r
1723 Ranges[0].Length = TotalLength;\r
1724 Ranges[0].Type = DefaultType;\r
1725\r
1726 //\r
1727 // 1. Set WB\r
1728 //\r
1729 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
1730 if (VariableMtrr[Index].Valid && VariableMtrr[Index].Type == CacheWriteBack) {\r
1731 Status = MtrrLibSetMemoryType (\r
1732 Ranges, RangeCapacity, RangeCount,\r
1733 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type\r
1734 );\r
1735 if (RETURN_ERROR (Status)) {\r
1736 return Status;\r
1737 }\r
1738 }\r
1739 }\r
1740\r
1741 //\r
1742 // 2. Set other types than WB or UC\r
1743 //\r
1744 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
1745 if (VariableMtrr[Index].Valid && VariableMtrr[Index].Type != CacheWriteBack && VariableMtrr[Index].Type != CacheUncacheable) {\r
1746 Status = MtrrLibSetMemoryType (\r
1747 Ranges, RangeCapacity, RangeCount,\r
1748 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type\r
1749 );\r
1750 if (RETURN_ERROR (Status)) {\r
1751 return Status;\r
1752 }\r
1753 }\r
1754 }\r
1755\r
1756 //\r
1757 // 3. Set UC\r
1758 //\r
1759 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
1760 if (VariableMtrr[Index].Valid && VariableMtrr[Index].Type == CacheUncacheable) {\r
1761 Status = MtrrLibSetMemoryType (\r
1762 Ranges, RangeCapacity, RangeCount,\r
1763 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type\r
1764 );\r
1765 if (RETURN_ERROR (Status)) {\r
1766 return Status;\r
1767 }\r
1768 }\r
1769 }\r
1770 return RETURN_SUCCESS;\r
1771}\r
16c2d37e 1772\r
85b7f65b 1773/**\r
16c2d37e 1774 Worker function attempts to set the attributes for a memory range.\r
85b7f65b 1775\r
8051302a 1776 If MtrrSetting is not NULL, set the attributes into the input MTRR\r
b970ed68 1777 settings buffer.\r
8051302a 1778 If MtrrSetting is NULL, set the attributes into MTRRs registers.\r
b970ed68
MK
1779\r
1780 @param[in, out] MtrrSetting A buffer holding all MTRRs content.\r
85b7f65b 1781 @param[in] BaseAddress The physical address that is the start\r
8051302a
RN
1782 address of a memory range.\r
1783 @param[in] Length The size in bytes of the memory range.\r
1784 @param[in] Type The MTRR type to set for the memory range.\r
85b7f65b
MK
1785\r
1786 @retval RETURN_SUCCESS The attributes were set for the memory\r
8051302a 1787 range.\r
85b7f65b
MK
1788 @retval RETURN_INVALID_PARAMETER Length is zero.\r
1789 @retval RETURN_UNSUPPORTED The processor does not support one or\r
1790 more bytes of the memory resource range\r
1791 specified by BaseAddress and Length.\r
8051302a
RN
1792 @retval RETURN_UNSUPPORTED The MTRR type is not support for the\r
1793 memory resource range specified\r
85b7f65b 1794 by BaseAddress and Length.\r
85b7f65b
MK
1795 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to\r
1796 modify the attributes of the memory\r
1797 resource range.\r
1798\r
1799**/\r
1800RETURN_STATUS\r
b970ed68
MK
1801MtrrSetMemoryAttributeWorker (\r
1802 IN OUT MTRR_SETTINGS *MtrrSetting,\r
1803 IN PHYSICAL_ADDRESS BaseAddress,\r
1804 IN UINT64 Length,\r
8051302a 1805 IN MTRR_MEMORY_CACHE_TYPE Type\r
85b7f65b
MK
1806 )\r
1807{\r
85b7f65b 1808 RETURN_STATUS Status;\r
8051302a
RN
1809 UINT32 Index;\r
1810 UINT32 WorkingIndex;\r
1811 //\r
1812 // N variable MTRRs can maximumly separate (2N + 1) Ranges, plus 1 range for [0, 1M).\r
1813 //\r
1814 MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 2];\r
1815 UINT32 RangeCount;\r
85b7f65b
MK
1816 UINT64 MtrrValidBitsMask;\r
1817 UINT64 MtrrValidAddressMask;\r
8051302a 1818 UINT64 Alignment0;\r
85b7f65b 1819 MTRR_CONTEXT MtrrContext;\r
fa25cf38 1820 BOOLEAN MtrrContextValid;\r
8051302a
RN
1821\r
1822 MTRR_MEMORY_CACHE_TYPE DefaultType;\r
1823\r
1824 UINT32 MsrIndex;\r
fa25cf38
MK
1825 UINT64 ClearMask;\r
1826 UINT64 OrMask;\r
1827 UINT64 NewValue;\r
8051302a
RN
1828 BOOLEAN FixedSettingsValid[MTRR_NUMBER_OF_FIXED_MTRR];\r
1829 BOOLEAN FixedSettingsModified[MTRR_NUMBER_OF_FIXED_MTRR];\r
1830 MTRR_FIXED_SETTINGS WorkingFixedSettings;\r
85b7f65b 1831\r
8051302a
RN
1832 UINT32 FirmwareVariableMtrrCount;\r
1833 MTRR_VARIABLE_SETTINGS *VariableSettings;\r
1834 MTRR_VARIABLE_SETTINGS OriginalVariableSettings;\r
1835 UINT32 OriginalVariableMtrrCount;\r
1836 VARIABLE_MTRR OriginalVariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
1837 UINT32 WorkingVariableMtrrCount;\r
1838 VARIABLE_MTRR WorkingVariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
1839 BOOLEAN VariableSettingModified[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
1840 UINTN FreeVariableMtrrCount;\r
85b7f65b 1841\r
8051302a
RN
1842 if (Length == 0) {\r
1843 return RETURN_INVALID_PARAMETER;\r
85b7f65b
MK
1844 }\r
1845\r
b0fa5d29 1846 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
8051302a
RN
1847 if (((BaseAddress & ~MtrrValidAddressMask) != 0) || (Length & ~MtrrValidAddressMask) != 0) {\r
1848 return RETURN_UNSUPPORTED;\r
85b7f65b
MK
1849 }\r
1850\r
8051302a
RN
1851 ZeroMem (&WorkingFixedSettings, sizeof (WorkingFixedSettings));\r
1852 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
1853 FixedSettingsValid[Index] = FALSE;\r
1854 FixedSettingsModified[Index] = FALSE;\r
85b7f65b
MK
1855 }\r
1856\r
1857 //\r
1858 // Check if Fixed MTRR\r
1859 //\r
fa25cf38 1860 if (BaseAddress < BASE_1MB) {\r
8051302a
RN
1861 MsrIndex = (UINT32)-1;\r
1862 while ((BaseAddress < BASE_1MB) && (Length != 0)) {\r
1863 Status = MtrrLibProgramFixedMtrr (Type, &BaseAddress, &Length, &MsrIndex, &ClearMask, &OrMask);\r
fa25cf38 1864 if (RETURN_ERROR (Status)) {\r
8051302a 1865 return Status;\r
fa25cf38 1866 }\r
b970ed68 1867 if (MtrrSetting != NULL) {\r
8051302a
RN
1868 MtrrSetting->Fixed.Mtrr[MsrIndex] = (MtrrSetting->Fixed.Mtrr[MsrIndex] & ~ClearMask) | OrMask;\r
1869 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *) &MtrrSetting->MtrrDefType)->Bits.FE = 1;\r
b970ed68 1870 } else {\r
8051302a
RN
1871 if (!FixedSettingsValid[MsrIndex]) {\r
1872 WorkingFixedSettings.Mtrr[MsrIndex] = AsmReadMsr64 (mMtrrLibFixedMtrrTable[MsrIndex].Msr);\r
1873 FixedSettingsValid[MsrIndex] = TRUE;\r
b970ed68 1874 }\r
8051302a
RN
1875 NewValue = (WorkingFixedSettings.Mtrr[MsrIndex] & ~ClearMask) | OrMask;\r
1876 if (WorkingFixedSettings.Mtrr[MsrIndex] != NewValue) {\r
1877 WorkingFixedSettings.Mtrr[MsrIndex] = NewValue;\r
1878 FixedSettingsModified[MsrIndex] = TRUE;\r
b970ed68 1879 }\r
fa25cf38 1880 }\r
85b7f65b 1881 }\r
85b7f65b 1882\r
fa25cf38
MK
1883 if (Length == 0) {\r
1884 //\r
1885 // A Length of 0 can only make sense for fixed MTTR ranges.\r
1886 // Since we just handled the fixed MTRRs, we can skip the\r
1887 // variable MTRR section.\r
1888 //\r
1889 goto Done;\r
1890 }\r
85b7f65b
MK
1891 }\r
1892\r
1893 //\r
8051302a 1894 // Read the default MTRR type\r
85b7f65b 1895 //\r
8051302a 1896 DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);\r
85b7f65b 1897\r
acf431e6 1898 //\r
8051302a 1899 // Read all variable MTRRs and convert to Ranges.\r
acf431e6 1900 //\r
8051302a
RN
1901 OriginalVariableMtrrCount = GetVariableMtrrCountWorker ();\r
1902 if (MtrrSetting == NULL) {\r
1903 ZeroMem (&OriginalVariableSettings, sizeof (OriginalVariableSettings));\r
1904 MtrrGetVariableMtrrWorker (NULL, OriginalVariableMtrrCount, &OriginalVariableSettings);\r
1905 VariableSettings = &OriginalVariableSettings;\r
b970ed68 1906 } else {\r
8051302a 1907 VariableSettings = &MtrrSetting->Variables;\r
e50466da 1908 }\r
8051302a
RN
1909 MtrrGetMemoryAttributeInVariableMtrrWorker (VariableSettings, OriginalVariableMtrrCount, MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr);\r
1910\r
1911 Status = MtrrLibGetMemoryTypes (\r
1912 DefaultType, MtrrValidBitsMask + 1, OriginalVariableMtrr, OriginalVariableMtrrCount,\r
1913 Ranges, 2 * OriginalVariableMtrrCount + 1, &RangeCount\r
1914 );\r
1915 ASSERT (Status == RETURN_SUCCESS);\r
1916\r
1917 FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCountWorker ();\r
1918 ASSERT (RangeCount <= 2 * FirmwareVariableMtrrCount + 1);\r
e50466da 1919\r
1920 //\r
8051302a 1921 // Force [0, 1M) to UC, so that it doesn't impact left subtraction algorithm.\r
e50466da 1922 //\r
8051302a
RN
1923 Status = MtrrLibSetMemoryType (Ranges, 2 * FirmwareVariableMtrrCount + 2, &RangeCount, 0, SIZE_1MB, CacheUncacheable);\r
1924 ASSERT (Status == RETURN_SUCCESS);\r
1925 //\r
1926 // Apply Type to [BaseAddress, BaseAddress + Length)\r
1927 //\r
1928 Status = MtrrLibSetMemoryType (Ranges, 2 * FirmwareVariableMtrrCount + 2, &RangeCount, BaseAddress, Length, Type);\r
1929 if (RETURN_ERROR (Status)) {\r
1930 return Status;\r
e50466da 1931 }\r
1932\r
8051302a
RN
1933 Alignment0 = LShiftU64 (1, (UINTN) HighBitSet64 (MtrrValidBitsMask));\r
1934 WorkingVariableMtrrCount = 0;\r
1935 ZeroMem (&WorkingVariableMtrr, sizeof (WorkingVariableMtrr));\r
1936 for (Index = 0; Index < RangeCount; Index++) {\r
1937 if (Ranges[Index].Type != DefaultType) {\r
1938 //\r
1939 // Maximum allowed MTRR count is (FirmwareVariableMtrrCount + 1)\r
1940 // Because potentially the range [0, 1MB) is not merged, but can be ignored because fixed MTRR covers that\r
1941 //\r
1942 Status = MtrrLibSetMemoryAttributeInVariableMtrr (\r
1943 Ranges, RangeCount,\r
1944 WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariableMtrrCount,\r
1945 Ranges[Index].BaseAddress, Ranges[Index].Length,\r
1946 Ranges[Index].Type, Alignment0\r
1947 );\r
1948 if (RETURN_ERROR (Status)) {\r
1949 return Status;\r
1950 }\r
1951 }\r
1a2ad6fc 1952 }\r
e50466da 1953\r
1a2ad6fc 1954 //\r
8051302a 1955 // Remove the [0, 1MB) MTRR if it still exists (not merged with other range)\r
1a2ad6fc 1956 //\r
8051302a
RN
1957 if (WorkingVariableMtrr[0].BaseAddress == 0 && WorkingVariableMtrr[0].Length == SIZE_1MB) {\r
1958 ASSERT (WorkingVariableMtrr[0].Type == CacheUncacheable);\r
1959 WorkingVariableMtrrCount--;\r
1960 CopyMem (&WorkingVariableMtrr[0], &WorkingVariableMtrr[1], WorkingVariableMtrrCount * sizeof (VARIABLE_MTRR));\r
1961 }\r
1a2ad6fc 1962\r
8051302a
RN
1963 if (WorkingVariableMtrrCount > FirmwareVariableMtrrCount) {\r
1964 return RETURN_OUT_OF_RESOURCES;\r
1a2ad6fc 1965 }\r
1966\r
8051302a
RN
1967 for (Index = 0; Index < OriginalVariableMtrrCount; Index++) {\r
1968 VariableSettingModified[Index] = FALSE;\r
1a2ad6fc 1969\r
8051302a
RN
1970 if (!OriginalVariableMtrr[Index].Valid) {\r
1971 continue;\r
1972 }\r
1973 for (WorkingIndex = 0; WorkingIndex < WorkingVariableMtrrCount; WorkingIndex++) {\r
1974 if (OriginalVariableMtrr[Index].BaseAddress == WorkingVariableMtrr[WorkingIndex].BaseAddress &&\r
1975 OriginalVariableMtrr[Index].Length == WorkingVariableMtrr[WorkingIndex].Length &&\r
1976 OriginalVariableMtrr[Index].Type == WorkingVariableMtrr[WorkingIndex].Type) {\r
1a2ad6fc 1977 break;\r
1978 }\r
8051302a 1979 }\r
1a2ad6fc 1980\r
8051302a 1981 if (WorkingIndex == WorkingVariableMtrrCount) {\r
1a2ad6fc 1982 //\r
8051302a 1983 // Remove the one from OriginalVariableMtrr which is not in WorkingVariableMtrr\r
1a2ad6fc 1984 //\r
8051302a
RN
1985 OriginalVariableMtrr[Index].Valid = FALSE;\r
1986 VariableSettingModified[Index] = TRUE;\r
1987 } else {\r
1988 //\r
1989 // Remove the one from WorkingVariableMtrr which is also in OriginalVariableMtrr\r
1990 //\r
1991 WorkingVariableMtrr[WorkingIndex].Valid = FALSE;\r
1992 }\r
1993 //\r
1994 // The above two operations cause that valid MTRR only exists in either OriginalVariableMtrr or WorkingVariableMtrr.\r
1995 //\r
1996 }\r
1997\r
1998 //\r
1999 // Merge remaining MTRRs from WorkingVariableMtrr to OriginalVariableMtrr\r
2000 //\r
2001 for (FreeVariableMtrrCount = 0, WorkingIndex = 0, Index = 0; Index < OriginalVariableMtrrCount; Index++) {\r
2002 if (!OriginalVariableMtrr[Index].Valid) {\r
2003 for (; WorkingIndex < WorkingVariableMtrrCount; WorkingIndex++) {\r
2004 if (WorkingVariableMtrr[WorkingIndex].Valid) {\r
1a2ad6fc 2005 break;\r
2006 }\r
2007 }\r
8051302a
RN
2008 if (WorkingIndex == WorkingVariableMtrrCount) {\r
2009 FreeVariableMtrrCount++;\r
2010 } else {\r
2011 CopyMem (&OriginalVariableMtrr[Index], &WorkingVariableMtrr[WorkingIndex], sizeof (VARIABLE_MTRR));\r
2012 VariableSettingModified[Index] = TRUE;\r
2013 WorkingIndex++;\r
2014 }\r
1a2ad6fc 2015 }\r
2016 }\r
8051302a 2017 ASSERT (OriginalVariableMtrrCount - FreeVariableMtrrCount <= FirmwareVariableMtrrCount);\r
1a2ad6fc 2018\r
8051302a
RN
2019 //\r
2020 // Move MTRRs after the FirmwraeVariableMtrrCount position to beginning\r
2021 //\r
2022 WorkingIndex = FirmwareVariableMtrrCount;\r
2023 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
2024 if (!OriginalVariableMtrr[Index].Valid) {\r
2025 //\r
2026 // Found an empty MTRR in WorkingIndex position\r
2027 //\r
2028 for (; WorkingIndex < OriginalVariableMtrrCount; WorkingIndex++) {\r
2029 if (OriginalVariableMtrr[WorkingIndex].Valid) {\r
2030 break;\r
2031 }\r
2032 }\r
e50466da 2033\r
8051302a
RN
2034 if (WorkingIndex != OriginalVariableMtrrCount) {\r
2035 CopyMem (&OriginalVariableMtrr[Index], &OriginalVariableMtrr[WorkingIndex], sizeof (VARIABLE_MTRR));\r
2036 VariableSettingModified[Index] = TRUE;\r
2037 VariableSettingModified[WorkingIndex] = TRUE;\r
2038 OriginalVariableMtrr[WorkingIndex].Valid = FALSE;\r
85b7f65b
MK
2039 }\r
2040 }\r
e50466da 2041 }\r
2042\r
8051302a
RN
2043 //\r
2044 // Convert OriginalVariableMtrr to VariableSettings\r
2045 // NOTE: MTRR from FirmwareVariableMtrr to OriginalVariableMtrr need to update as well.\r
2046 //\r
2047 for (Index = 0; Index < OriginalVariableMtrrCount; Index++) {\r
2048 if (VariableSettingModified[Index]) {\r
2049 if (OriginalVariableMtrr[Index].Valid) {\r
2050 VariableSettings->Mtrr[Index].Base = (OriginalVariableMtrr[Index].BaseAddress & MtrrValidAddressMask) | (UINT8) OriginalVariableMtrr[Index].Type;\r
2051 VariableSettings->Mtrr[Index].Mask = (~(OriginalVariableMtrr[Index].Length - 1)) & MtrrValidAddressMask | BIT11;\r
2052 } else {\r
2053 VariableSettings->Mtrr[Index].Base = 0;\r
2054 VariableSettings->Mtrr[Index].Mask = 0;\r
85b7f65b
MK
2055 }\r
2056 }\r
8051302a 2057 }\r
85b7f65b
MK
2058\r
2059Done:\r
8051302a
RN
2060 if (MtrrSetting != NULL) {\r
2061 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *) &MtrrSetting->MtrrDefType)->Bits.E = 1;\r
2062 return RETURN_SUCCESS;\r
2063 }\r
fa25cf38 2064\r
8051302a 2065 MtrrContextValid = FALSE;\r
fa25cf38
MK
2066 //\r
2067 // Write fixed MTRRs that have been modified\r
2068 //\r
2069 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
2070 if (FixedSettingsModified[Index]) {\r
2071 if (!MtrrContextValid) {\r
b8f01599 2072 MtrrLibPreMtrrChange (&MtrrContext);\r
fa25cf38
MK
2073 MtrrContextValid = TRUE;\r
2074 }\r
2075 AsmWriteMsr64 (\r
2076 mMtrrLibFixedMtrrTable[Index].Msr,\r
2077 WorkingFixedSettings.Mtrr[Index]\r
2078 );\r
2079 }\r
2080 }\r
2081\r
b0fa5d29
MK
2082 //\r
2083 // Write variable MTRRs\r
2084 //\r
8051302a
RN
2085 for (Index = 0; Index < OriginalVariableMtrrCount; Index++) {\r
2086 if (VariableSettingModified[Index]) {\r
2087 if (!MtrrContextValid) {\r
2088 MtrrLibPreMtrrChange (&MtrrContext);\r
2089 MtrrContextValid = TRUE;\r
b0fa5d29 2090 }\r
8051302a
RN
2091 AsmWriteMsr64 (\r
2092 MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),\r
2093 VariableSettings->Mtrr[Index].Base\r
2094 );\r
2095 AsmWriteMsr64 (\r
2096 MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),\r
2097 VariableSettings->Mtrr[Index].Mask\r
2098 );\r
b0fa5d29
MK
2099 }\r
2100 }\r
fa25cf38 2101 if (MtrrContextValid) {\r
b8f01599 2102 MtrrLibPostMtrrChange (&MtrrContext);\r
fa25cf38
MK
2103 }\r
2104\r
85b7f65b 2105 return Status;\r
31b3597e 2106}\r
b970ed68
MK
2107\r
2108/**\r
2109 This function attempts to set the attributes for a memory range.\r
2110\r
2111 @param[in] BaseAddress The physical address that is the start\r
8051302a
RN
2112 address of a memory range.\r
2113 @param[in] Length The size in bytes of the memory range.\r
b970ed68 2114 @param[in] Attributes The bit mask of attributes to set for the\r
8051302a 2115 memory range.\r
b970ed68
MK
2116\r
2117 @retval RETURN_SUCCESS The attributes were set for the memory\r
8051302a 2118 range.\r
b970ed68
MK
2119 @retval RETURN_INVALID_PARAMETER Length is zero.\r
2120 @retval RETURN_UNSUPPORTED The processor does not support one or\r
2121 more bytes of the memory resource range\r
2122 specified by BaseAddress and Length.\r
2123 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support\r
2124 for the memory resource range specified\r
2125 by BaseAddress and Length.\r
2126 @retval RETURN_ACCESS_DENIED The attributes for the memory resource\r
2127 range specified by BaseAddress and Length\r
2128 cannot be modified.\r
2129 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to\r
2130 modify the attributes of the memory\r
2131 resource range.\r
2132\r
2133**/\r
2134RETURN_STATUS\r
2135EFIAPI\r
2136MtrrSetMemoryAttribute (\r
2137 IN PHYSICAL_ADDRESS BaseAddress,\r
2138 IN UINT64 Length,\r
2139 IN MTRR_MEMORY_CACHE_TYPE Attribute\r
2140 )\r
2141{\r
8051302a
RN
2142 RETURN_STATUS Status;\r
2143\r
2144 if (!IsMtrrSupported ()) {\r
2145 return RETURN_UNSUPPORTED;\r
2146 }\r
2147\r
2148 Status = MtrrSetMemoryAttributeWorker (NULL, BaseAddress, Length, Attribute);\r
2149 DEBUG ((DEBUG_CACHE, "MtrrSetMemoryAttribute() %a: [%016lx, %016lx) - %r\n",\r
2150 mMtrrMemoryCacheTypeShortName[Attribute], BaseAddress, BaseAddress + Length, Status));\r
2151\r
2152 if (!RETURN_ERROR (Status)) {\r
2153 MtrrDebugPrintAllMtrrsWorker (NULL);\r
2154 }\r
2155 return Status;\r
b970ed68
MK
2156}\r
2157\r
2158/**\r
2159 This function attempts to set the attributes into MTRR setting buffer for a memory range.\r
2160\r
2161 @param[in, out] MtrrSetting MTRR setting buffer to be set.\r
2162 @param[in] BaseAddress The physical address that is the start address\r
8051302a
RN
2163 of a memory range.\r
2164 @param[in] Length The size in bytes of the memory range.\r
b970ed68 2165 @param[in] Attribute The bit mask of attributes to set for the\r
8051302a 2166 memory range.\r
b970ed68 2167\r
8051302a 2168 @retval RETURN_SUCCESS The attributes were set for the memory range.\r
b970ed68
MK
2169 @retval RETURN_INVALID_PARAMETER Length is zero.\r
2170 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the\r
2171 memory resource range specified by BaseAddress and Length.\r
2172 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource\r
2173 range specified by BaseAddress and Length.\r
2174 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by\r
2175 BaseAddress and Length cannot be modified.\r
2176 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
2177 the memory resource range.\r
2178\r
2179**/\r
2180RETURN_STATUS\r
2181EFIAPI\r
2182MtrrSetMemoryAttributeInMtrrSettings (\r
2183 IN OUT MTRR_SETTINGS *MtrrSetting,\r
2184 IN PHYSICAL_ADDRESS BaseAddress,\r
2185 IN UINT64 Length,\r
2186 IN MTRR_MEMORY_CACHE_TYPE Attribute\r
2187 )\r
2188{\r
8051302a
RN
2189 RETURN_STATUS Status;\r
2190 Status = MtrrSetMemoryAttributeWorker (MtrrSetting, BaseAddress, Length, Attribute);\r
2191 DEBUG((DEBUG_CACHE, "MtrrSetMemoryAttributeMtrrSettings(%p) %a: [%016lx, %016lx) - %r\n",\r
2192 MtrrSetting, mMtrrMemoryCacheTypeShortName[Attribute], BaseAddress, BaseAddress + Length, Status));\r
2193\r
2194 if (!RETURN_ERROR (Status)) {\r
2195 MtrrDebugPrintAllMtrrsWorker (MtrrSetting);\r
2196 }\r
2197\r
2198 return Status;\r
b970ed68
MK
2199}\r
2200\r
e50466da 2201/**\r
2202 Worker function setting variable MTRRs\r
2203\r
76b4cae3 2204 @param[in] VariableSettings A buffer to hold variable MTRRs content.\r
e50466da 2205\r
2206**/\r
2207VOID\r
2208MtrrSetVariableMtrrWorker (\r
2209 IN MTRR_VARIABLE_SETTINGS *VariableSettings\r
2210 )\r
2211{\r
2212 UINT32 Index;\r
3b9be416 2213 UINT32 VariableMtrrCount;\r
e50466da 2214\r
acf431e6 2215 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
5bdfa4e5 2216 ASSERT (VariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
2217\r
3b9be416 2218 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
e50466da 2219 AsmWriteMsr64 (\r
af838805 2220 MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),\r
e50466da 2221 VariableSettings->Mtrr[Index].Base\r
2222 );\r
2223 AsmWriteMsr64 (\r
af838805 2224 MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),\r
e50466da 2225 VariableSettings->Mtrr[Index].Mask\r
2226 );\r
2227 }\r
2228}\r
2229\r
2230\r
2231/**\r
2232 This function sets variable MTRRs\r
2233\r
76b4cae3 2234 @param[in] VariableSettings A buffer to hold variable MTRRs content.\r
e50466da 2235\r
2236 @return The pointer of VariableSettings\r
2237\r
2238**/\r
2239MTRR_VARIABLE_SETTINGS*\r
2240EFIAPI\r
2241MtrrSetVariableMtrr (\r
2242 IN MTRR_VARIABLE_SETTINGS *VariableSettings\r
2243 )\r
2244{\r
c878cee4 2245 MTRR_CONTEXT MtrrContext;\r
e50466da 2246\r
947a573a 2247 if (!IsMtrrSupported ()) {\r
2248 return VariableSettings;\r
2249 }\r
2250\r
b8f01599 2251 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2252 MtrrSetVariableMtrrWorker (VariableSettings);\r
b8f01599 2253 MtrrLibPostMtrrChange (&MtrrContext);\r
e518b80d
MK
2254 MtrrDebugPrintAllMtrrs ();\r
2255\r
e50466da 2256 return VariableSettings;\r
2257}\r
2258\r
e50466da 2259/**\r
2260 Worker function setting fixed MTRRs\r
2261\r
acf431e6 2262 @param[in] FixedSettings A buffer to hold fixed MTRRs content.\r
e50466da 2263\r
2264**/\r
2265VOID\r
2266MtrrSetFixedMtrrWorker (\r
2267 IN MTRR_FIXED_SETTINGS *FixedSettings\r
2268 )\r
2269{\r
2270 UINT32 Index;\r
2271\r
2272 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
2273 AsmWriteMsr64 (\r
f877f300 2274 mMtrrLibFixedMtrrTable[Index].Msr,\r
e50466da 2275 FixedSettings->Mtrr[Index]\r
2276 );\r
2277 }\r
2278}\r
2279\r
2280\r
2281/**\r
2282 This function sets fixed MTRRs\r
2283\r
acf431e6 2284 @param[in] FixedSettings A buffer to hold fixed MTRRs content.\r
e50466da 2285\r
2286 @retval The pointer of FixedSettings\r
2287\r
2288**/\r
2289MTRR_FIXED_SETTINGS*\r
2290EFIAPI\r
2291MtrrSetFixedMtrr (\r
2292 IN MTRR_FIXED_SETTINGS *FixedSettings\r
2293 )\r
2294{\r
c878cee4 2295 MTRR_CONTEXT MtrrContext;\r
e50466da 2296\r
947a573a 2297 if (!IsMtrrSupported ()) {\r
2298 return FixedSettings;\r
2299 }\r
2300\r
b8f01599 2301 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2302 MtrrSetFixedMtrrWorker (FixedSettings);\r
b8f01599 2303 MtrrLibPostMtrrChange (&MtrrContext);\r
e518b80d 2304 MtrrDebugPrintAllMtrrs ();\r
e50466da 2305\r
2306 return FixedSettings;\r
2307}\r
2308\r
2309\r
2310/**\r
2311 This function gets the content in all MTRRs (variable and fixed)\r
2312\r
acf431e6 2313 @param[out] MtrrSetting A buffer to hold all MTRRs content.\r
e50466da 2314\r
2315 @retval the pointer of MtrrSetting\r
2316\r
2317**/\r
2318MTRR_SETTINGS *\r
2319EFIAPI\r
2320MtrrGetAllMtrrs (\r
2321 OUT MTRR_SETTINGS *MtrrSetting\r
2322 )\r
2323{\r
947a573a 2324 if (!IsMtrrSupported ()) {\r
2325 return MtrrSetting;\r
2326 }\r
2327\r
e50466da 2328 //\r
2329 // Get fixed MTRRs\r
2330 //\r
acf431e6 2331 MtrrGetFixedMtrrWorker (&MtrrSetting->Fixed);\r
e50466da 2332\r
2333 //\r
2334 // Get variable MTRRs\r
2335 //\r
acf431e6 2336 MtrrGetVariableMtrrWorker (\r
5abd5ed4 2337 NULL,\r
acf431e6
MK
2338 GetVariableMtrrCountWorker (),\r
2339 &MtrrSetting->Variables\r
2340 );\r
e50466da 2341\r
2342 //\r
2343 // Get MTRR_DEF_TYPE value\r
2344 //\r
af838805 2345 MtrrSetting->MtrrDefType = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
e50466da 2346\r
2347 return MtrrSetting;\r
2348}\r
2349\r
2350\r
2351/**\r
2352 This function sets all MTRRs (variable and fixed)\r
2353\r
76b4cae3 2354 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
e50466da 2355\r
2356 @retval The pointer of MtrrSetting\r
2357\r
2358**/\r
2359MTRR_SETTINGS *\r
2360EFIAPI\r
2361MtrrSetAllMtrrs (\r
2362 IN MTRR_SETTINGS *MtrrSetting\r
2363 )\r
2364{\r
c878cee4 2365 MTRR_CONTEXT MtrrContext;\r
e50466da 2366\r
947a573a 2367 if (!IsMtrrSupported ()) {\r
2368 return MtrrSetting;\r
2369 }\r
2370\r
b8f01599 2371 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2372\r
2373 //\r
2374 // Set fixed MTRRs\r
2375 //\r
2376 MtrrSetFixedMtrrWorker (&MtrrSetting->Fixed);\r
2377\r
2378 //\r
2379 // Set variable MTRRs\r
2380 //\r
2381 MtrrSetVariableMtrrWorker (&MtrrSetting->Variables);\r
2382\r
2383 //\r
2384 // Set MTRR_DEF_TYPE value\r
2385 //\r
af838805 2386 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);\r
e50466da 2387\r
b8f01599 2388 MtrrLibPostMtrrChangeEnableCache (&MtrrContext);\r
e50466da 2389\r
2390 return MtrrSetting;\r
2391}\r
2392\r
e518b80d 2393\r
947a573a 2394/**\r
2395 Checks if MTRR is supported.\r
2396\r
2397 @retval TRUE MTRR is supported.\r
2398 @retval FALSE MTRR is not supported.\r
2399\r
2400**/\r
2401BOOLEAN\r
2402EFIAPI\r
2403IsMtrrSupported (\r
2404 VOID\r
2405 )\r
2406{\r
3bb13d35
RN
2407 CPUID_VERSION_INFO_EDX Edx;\r
2408 MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
947a573a 2409\r
2410 //\r
2411 // Check CPUID(1).EDX[12] for MTRR capability\r
2412 //\r
3bb13d35
RN
2413 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);\r
2414 if (Edx.Bits.MTRR == 0) {\r
947a573a 2415 return FALSE;\r
2416 }\r
2417\r
2418 //\r
3bb13d35
RN
2419 // Check number of variable MTRRs and fixed MTRRs existence.\r
2420 // If number of variable MTRRs is zero, or fixed MTRRs do not\r
947a573a 2421 // exist, return false.\r
2422 //\r
3bb13d35
RN
2423 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
2424 if ((MtrrCap.Bits.VCNT == 0) || (MtrrCap.Bits.FIX == 0)) {\r
947a573a 2425 return FALSE;\r
2426 }\r
947a573a 2427 return TRUE;\r
2428}\r
8051302a 2429\r