[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / Ia32 / SmiException.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php.\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
# Module Name:\r
#\r
#   SmiException.S\r
#\r
# Abstract:\r
#\r
#   Exception handlers used in SM mode\r
#\r
#------------------------------------------------------------------------------\r
\r
ASM_GLOBAL  ASM_PFX(gcStmPsd)\r
\r
ASM_GLOBAL  ASM_PFX(SmmStmExceptionHandler)\r
ASM_GLOBAL  ASM_PFX(SmmStmSetup)\r
ASM_GLOBAL  ASM_PFX(SmmStmTeardown)\r
\r
.equ  MSR_IA32_MISC_ENABLE, 0x1A0\r
.equ  MSR_EFER,             0xc0000080\r
.equ  MSR_EFER_XD,          0x800\r
\r
.equ  CODE_SEL,          0x08\r
.equ  DATA_SEL,          0x20\r
.equ  TSS_SEL,           0x40\r
\r
    .data\r
\r
ASM_PFX(gcStmPsd):\r
            .ascii  "TXTPSSIG"\r
            .word      PSD_SIZE\r
            .word      1              # Version\r
            .long      0              # LocalApicId\r
            .byte      0x5            # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
            .byte      0              # BIOS to STM\r
            .byte      0              # STM to BIOS\r
            .byte      0\r
            .word      CODE_SEL\r
            .word      DATA_SEL\r
            .word      DATA_SEL\r
            .word      DATA_SEL\r
            .word      TSS_SEL\r
            .word      0\r
            .quad      0              # SmmCr3\r
            .long      ASM_PFX(_OnStmSetup)\r
            .long      0\r
            .long      ASM_PFX(_OnStmTeardown)\r
            .long      0\r
            .quad      0              # SmmSmiHandlerRip - SMM guest entrypoint\r
            .quad      0              # SmmSmiHandlerRsp\r
            .quad      0\r
            .long      0\r
            .long      0x80010100     # RequiredStmSmmRevId\r
            .long      ASM_PFX(_OnException)\r
            .long      0\r
            .quad      0              # ExceptionStack\r
            .word      DATA_SEL\r
            .word      0x1F           # ExceptionFilter\r
            .long      0\r
            .quad      0\r
            .quad      0              # BiosHwResourceRequirementsPtr\r
            .quad      0              # AcpiRsdp\r
            .byte      0              # PhysicalAddressBits\r
.equ  PSD_SIZE,  . - ASM_PFX(gcStmPsd)\r
\r
    .text\r
\r
#------------------------------------------------------------------------------\r
# SMM Exception handlers\r
#------------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(_OnException)\r
ASM_PFX(_OnException):\r
    movl  %esp, %ecx\r
    pushl %ecx\r
    call  ASM_PFX(SmmStmExceptionHandler)\r
    addl  $4, %esp\r
\r
    movl  %eax, %ebx\r
    movl  $4, %eax\r
    .byte 0xf, 0x1, 0xc1 # VMCALL\r
    jmp .\r
\r
ASM_GLOBAL ASM_PFX(_OnStmSetup)\r
ASM_PFX(_OnStmSetup):\r
#\r
# Check XD disable bit\r
#\r
    xorl    %esi, %esi\r
    movl    $ASM_PFX(gStmXdSupported), %eax\r
    movb    (%eax), %al\r
    cmpb    $0, %al\r
    jz      StmXdDone1\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    movl    %edx, %esi                     # save MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx                    # MSR_IA32_MISC_ENABLE[34]\r
    jz      L13\r
    andw    $0x0FFFB, %dx                  # clear XD Disable bit if it is set\r
    wrmsr\r
L13:\r
    movl    $MSR_EFER, %ecx\r
    rdmsr\r
    orw     $MSR_EFER_XD,%ax               # enable NXE\r
    wrmsr\r
StmXdDone1:\r
    push    %esi\r
\r
  call ASM_PFX(SmmStmSetup)\r
\r
    movl    $ASM_PFX(gStmXdSupported), %eax\r
    movb    (%eax), %al\r
    cmpb    $0, %al\r
    jz      L14\r
    popl    %edx                        # get saved MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx\r
    jz      L14\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM\r
    wrmsr\r
L14:\r
\r
  rsm\r
\r
ASM_GLOBAL ASM_PFX(_OnStmTeardown)\r
ASM_PFX(_OnStmTeardown):\r
#\r
# Check XD disable bit\r
#\r
    xorl    %esi, %esi\r
    movl    $ASM_PFX(gStmXdSupported), %eax\r
    movb    (%eax), %al\r
    cmpb    $0, %al\r
    jz      StmXdDone2\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    movl    %edx, %esi                     # save MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx                    # MSR_IA32_MISC_ENABLE[34]\r
    jz      L15\r
    andw    $0x0FFFB, %dx                  # clear XD Disable bit if it is set\r
    wrmsr\r
L15:\r
    movl    $MSR_EFER, %ecx\r
    rdmsr\r
    orw     $MSR_EFER_XD,%ax               # enable NXE\r
    wrmsr\r
StmXdDone2:\r
    push    %esi\r
\r
  call ASM_PFX(SmmStmTeardown)\r
\r
    movl    $ASM_PFX(gStmXdSupported), %eax\r
    movb    (%eax), %al\r
    cmpb    $0, %al\r
    jz      L16\r
    popl    %edx                        # get saved MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx\r
    jz      L16\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM\r
    wrmsr\r
L16:\r
\r
  rsm\r
Commit	Line	Data
09119a00 MK	1	#------------------------------------------------------------------------------\r
	2	#\r
	3	# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
	4	# This program and the accompanying materials\r
	5	# are licensed and made available under the terms and conditions of the BSD License\r
	6	# which accompanies this distribution. The full text of the license may be found at\r
	7	# http://opensource.org/licenses/bsd-license.php.\r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	# Module Name:\r
	13	#\r
	14	# SmiException.S\r
	15	#\r
	16	# Abstract:\r
	17	#\r
	18	# Exception handlers used in SM mode\r
	19	#\r
	20	#------------------------------------------------------------------------------\r
	21	\r
	22	ASM_GLOBAL ASM_PFX(gcStmPsd)\r
	23	\r
	24	ASM_GLOBAL ASM_PFX(SmmStmExceptionHandler)\r
	25	ASM_GLOBAL ASM_PFX(SmmStmSetup)\r
	26	ASM_GLOBAL ASM_PFX(SmmStmTeardown)\r
	27	\r
	28	.equ MSR_IA32_MISC_ENABLE, 0x1A0\r
	29	.equ MSR_EFER, 0xc0000080\r
	30	.equ MSR_EFER_XD, 0x800\r
	31	\r
	32	.equ CODE_SEL, 0x08\r
	33	.equ DATA_SEL, 0x20\r
	34	.equ TSS_SEL, 0x40\r
	35	\r
	36	.data\r
	37	\r
	38	ASM_PFX(gcStmPsd):\r
	39	.ascii "TXTPSSIG"\r
	40	.word PSD_SIZE\r
	41	.word 1 # Version\r
	42	.long 0 # LocalApicId\r
	43	.byte 0x5 # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
	44	.byte 0 # BIOS to STM\r
	45	.byte 0 # STM to BIOS\r
	46	.byte 0\r
	47	.word CODE_SEL\r
	48	.word DATA_SEL\r
	49	.word DATA_SEL\r
	50	.word DATA_SEL\r
	51	.word TSS_SEL\r
	52	.word 0\r
	53	.quad 0 # SmmCr3\r
	54	.long ASM_PFX(_OnStmSetup)\r
	55	.long 0\r
	56	.long ASM_PFX(_OnStmTeardown)\r
	57	.long 0\r
	58	.quad 0 # SmmSmiHandlerRip - SMM guest entrypoint\r
	59	.quad 0 # SmmSmiHandlerRsp\r
	60	.quad 0\r
	61	.long 0\r
	62	.long 0x80010100 # RequiredStmSmmRevId\r
	63	.long ASM_PFX(_OnException)\r
	64	.long 0\r
65	.quad 0 # ExceptionStack\r
66	.word DATA_SEL\r
67	.word 0x1F # ExceptionFilter\r
68	.long 0\r
69	.quad 0\r
70	.quad 0 # BiosHwResourceRequirementsPtr\r
71	.quad 0 # AcpiRsdp\r
72	.byte 0 # PhysicalAddressBits\r
73	.equ PSD_SIZE, . - ASM_PFX(gcStmPsd)\r
74	\r
75	.text\r
76	\r
77	#------------------------------------------------------------------------------\r
78	# SMM Exception handlers\r
79	#------------------------------------------------------------------------------\r
80	ASM_GLOBAL ASM_PFX(_OnException)\r
81	ASM_PFX(_OnException):\r
82	movl %esp, %ecx\r
83	pushl %ecx\r
84	call ASM_PFX(SmmStmExceptionHandler)\r
85	addl $4, %esp\r
86	\r
87	movl %eax, %ebx\r
88	movl $4, %eax\r
89	.byte 0xf, 0x1, 0xc1 # VMCALL\r
90	jmp .\r
91	\r
92	ASM_GLOBAL ASM_PFX(_OnStmSetup)\r
93	ASM_PFX(_OnStmSetup):\r
94	#\r
95	# Check XD disable bit\r
96	#\r
97	xorl %esi, %esi\r
98	movl $ASM_PFX(gStmXdSupported), %eax\r
99	movb (%eax), %al\r
100	cmpb $0, %al\r
101	jz StmXdDone1\r
102	movl $MSR_IA32_MISC_ENABLE, %ecx\r
103	rdmsr\r
104	movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]\r
105	testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]\r
106	jz L13\r
107	andw $0x0FFFB, %dx # clear XD Disable bit if it is set\r
108	wrmsr\r
109	L13:\r
110	movl $MSR_EFER, %ecx\r
111	rdmsr\r
112	orw $MSR_EFER_XD,%ax # enable NXE\r
113	wrmsr\r
114	StmXdDone1:\r
115	push %esi\r
116	\r
117	call ASM_PFX(SmmStmSetup)\r
118	\r
119	movl $ASM_PFX(gStmXdSupported), %eax\r
120	movb (%eax), %al\r
121	cmpb $0, %al\r
122	jz L14\r
123	popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]\r
124	testl $BIT2, %edx\r
125	jz L14\r
126	movl $MSR_IA32_MISC_ENABLE, %ecx\r
127	rdmsr\r
128	orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM\r
129	wrmsr\r
130	L14:\r
131	\r
132	rsm\r
133	\r
134	ASM_GLOBAL ASM_PFX(_OnStmTeardown)\r
135	ASM_PFX(_OnStmTeardown):\r
136	#\r
137	# Check XD disable bit\r
138	#\r
139	xorl %esi, %esi\r
140	movl $ASM_PFX(gStmXdSupported), %eax\r
141	movb (%eax), %al\r
142	cmpb $0, %al\r
143	jz StmXdDone2\r
144	movl $MSR_IA32_MISC_ENABLE, %ecx\r
145	rdmsr\r
146	movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]\r
147	testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]\r
148	jz L15\r
149	andw $0x0FFFB, %dx # clear XD Disable bit if it is set\r
150	wrmsr\r
151	L15:\r
152	movl $MSR_EFER, %ecx\r
153	rdmsr\r
154	orw $MSR_EFER_XD,%ax # enable NXE\r
155	wrmsr\r
156	StmXdDone2:\r
157	push %esi\r
158	\r
159	call ASM_PFX(SmmStmTeardown)\r
160	\r
161	movl $ASM_PFX(gStmXdSupported), %eax\r
162	movb (%eax), %al\r
163	cmpb $0, %al\r
164	jz L16\r
165	popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]\r
166	testl $BIT2, %edx\r
167	jz L16\r
168	movl $MSR_IA32_MISC_ENABLE, %ecx\r
169	rdmsr\r
170	orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM\r
171	wrmsr\r
172	L16:\r
173	\r
174	rsm\r