projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 09119a00 | 1 | ;------------------------------------------------------------------------------ ;\r |
| 4c34a8ea | 2 | ; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r |
| 09119a00 MK |
3 | ; This program and the accompanying materials\r |
| 4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
| 5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
| 6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
| 7 | ;\r | |
| 8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 10 | ;\r | |
| 11 | ; Module Name:\r | |
| 12 | ;\r | |
| 13 | ; SmiException.nasm\r | |
| 14 | ;\r | |
| 15 | ; Abstract:\r | |
| 16 | ;\r | |
| 17 | ; Exception handlers used in SM mode\r | |
| 18 | ;\r | |
| 19 | ;-------------------------------------------------------------------------------\r | |
| 20 | \r | |
| 21 | global ASM_PFX(gcStmPsd)\r | |
| 22 | \r | |
| 23 | extern ASM_PFX(SmmStmExceptionHandler)\r | |
| 24 | extern ASM_PFX(SmmStmSetup)\r | |
| 25 | extern ASM_PFX(SmmStmTeardown)\r | |
| 26 | extern ASM_PFX(gStmXdSupported)\r | |
| 27 | extern ASM_PFX(gStmSmiHandlerIdtr)\r | |
| 28 | \r | |
| 29 | %define MSR_IA32_MISC_ENABLE 0x1A0\r | |
| 30 | %define MSR_EFER 0xc0000080\r | |
| 31 | %define MSR_EFER_XD 0x800\r | |
| 32 | \r | |
| 33 | CODE_SEL equ 0x08\r | |
| 34 | DATA_SEL equ 0x20\r | |
| 35 | TSS_SEL equ 0x40\r | |
| 36 | \r | |
| 37 | SECTION .data\r | |
| 38 | \r | |
| 39 | ASM_PFX(gcStmPsd):\r | |
| 40 | DB 'TXTPSSIG'\r | |
| 41 | DW PSD_SIZE\r | |
| 42 | DW 1 ; Version\r | |
| 43 | DD 0 ; LocalApicId\r | |
| 44 | DB 0x05 ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r | |
| 45 | DB 0 ; BIOS to STM\r | |
| 46 | DB 0 ; STM to BIOS\r | |
| 47 | DB 0\r | |
| 48 | DW CODE_SEL\r | |
| 49 | DW DATA_SEL\r | |
| 50 | DW DATA_SEL\r | |
| 51 | DW DATA_SEL\r | |
| 52 | DW TSS_SEL\r | |
| 53 | DW 0\r | |
| 54 | DQ 0 ; SmmCr3\r | |
| 55 | DD ASM_PFX(OnStmSetup)\r | |
| 56 | DD 0\r | |
| 57 | DD ASM_PFX(OnStmTeardown)\r | |
| 58 | DD 0\r | |
| 59 | DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint\r | |
| 60 | DQ 0 ; SmmSmiHandlerRsp\r | |
| 61 | DQ 0\r | |
| 62 | DD 0\r | |
| 63 | DD 0x80010100 ; RequiredStmSmmRevId\r | |
| 64 | DD ASM_PFX(OnException)\r | |
| 65 | DD 0\r | |
| 66 | DQ 0 ; ExceptionStack\r | |
| 67 | DW DATA_SEL\r | |
| 68 | DW 0x01F ; ExceptionFilter\r | |
| 69 | DD 0\r | |
| 70 | DD 0\r | |
| 71 | DD 0\r | |
| 72 | DQ 0 ; BiosHwResourceRequirementsPtr\r | |
| 73 | DQ 0 ; AcpiRsdp\r | |
| 74 | DB 0 ; PhysicalAddressBits\r | |
| 75 | PSD_SIZE equ $ - ASM_PFX(gcStmPsd)\r | |
| 76 | \r | |
| 77 | SECTION .text\r | |
| 78 | ;------------------------------------------------------------------------------\r | |
| 79 | ; SMM Exception handlers\r | |
| 80 | ;------------------------------------------------------------------------------\r | |
| 81 | global ASM_PFX(OnException)\r | |
| 82 | ASM_PFX(OnException):\r | |
| 83 | mov ecx, esp\r | |
| 84 | push ecx\r | |
| 85 | call ASM_PFX(SmmStmExceptionHandler)\r | |
| 86 | add esp, 4\r | |
| 87 | \r | |
| 88 | mov ebx, eax\r | |
| 89 | mov eax, 4\r | |
| 4c34a8ea | 90 | vmcall\r |
| 09119a00 MK |
91 | jmp $\r |
| 92 | \r | |
| 93 | global ASM_PFX(OnStmSetup)\r | |
| 94 | ASM_PFX(OnStmSetup):\r | |
| 95 | ;\r | |
| 96 | ; Check XD disable bit\r | |
| 97 | ;\r | |
| 98 | xor esi, esi\r | |
| 99 | mov eax, ASM_PFX(gStmXdSupported)\r | |
| 100 | mov al, [eax]\r | |
| 101 | cmp al, 0\r | |
| 102 | jz @StmXdDone1\r | |
| 103 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 104 | rdmsr\r | |
| 105 | mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
| 106 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
| 107 | jz .51\r | |
| 108 | and dx, 0xFFFB ; clear XD Disable bit if it is set\r | |
| 109 | wrmsr\r | |
| 110 | .51:\r | |
| 111 | mov ecx, MSR_EFER\r | |
| 112 | rdmsr\r | |
| 113 | or ax, MSR_EFER_XD ; enable NXE\r | |
| 114 | wrmsr\r | |
| 115 | @StmXdDone1:\r | |
| 116 | push esi\r | |
| 117 | \r | |
| 118 | call ASM_PFX(SmmStmSetup)\r | |
| 119 | \r | |
| 120 | mov eax, ASM_PFX(gStmXdSupported)\r | |
| 121 | mov al, [eax]\r | |
| 122 | cmp al, 0\r | |
| 123 | jz .71\r | |
| 124 | pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
| 125 | test edx, BIT2\r | |
| 126 | jz .71\r | |
| 127 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 128 | rdmsr\r | |
| 129 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
| 130 | wrmsr\r | |
| 131 | \r | |
| 132 | .71:\r | |
| 133 | rsm\r | |
| 134 | \r | |
| 135 | global ASM_PFX(OnStmTeardown)\r | |
| 136 | ASM_PFX(OnStmTeardown):\r | |
| 137 | ;\r | |
| 138 | ; Check XD disable bit\r | |
| 139 | ;\r | |
| 140 | xor esi, esi\r | |
| 141 | mov eax, ASM_PFX(gStmXdSupported)\r | |
| 142 | mov al, [eax]\r | |
| 143 | cmp al, 0\r | |
| 144 | jz @StmXdDone2\r | |
| 145 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 146 | rdmsr\r | |
| 147 | mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
| 148 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
| 149 | jz .52\r | |
| 150 | and dx, 0xFFFB ; clear XD Disable bit if it is set\r | |
| 151 | wrmsr\r | |
| 152 | .52:\r | |
| 153 | mov ecx, MSR_EFER\r | |
| 154 | rdmsr\r | |
| 155 | or ax, MSR_EFER_XD ; enable NXE\r | |
| 156 | wrmsr\r | |
| 157 | @StmXdDone2:\r | |
| 158 | push esi\r | |
| 159 | \r | |
| 160 | call ASM_PFX(SmmStmTeardown)\r | |
| 161 | \r | |
| 162 | mov eax, ASM_PFX(gStmXdSupported)\r | |
| 163 | mov al, [eax]\r | |
| 164 | cmp al, 0\r | |
| 165 | jz .72\r | |
| 166 | pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
| 167 | test edx, BIT2\r | |
| 168 | jz .72\r | |
| 169 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 170 | rdmsr\r | |
| 171 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
| 172 | wrmsr\r | |
| 173 | \r | |
| 174 | .72:\r | |
| 175 | rsm\r |