MdeModulePkg NvmExpressDxe: Add BlockIo2 support
[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c
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1/** @file\r
2The CPU specific programming for PiSmmCpuDxeSmm module.\r
3\r
4Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <PiSmm.h>\r
16#include <Library/SmmCpuFeaturesLib.h>\r
17#include <Library/BaseLib.h>\r
18#include <Library/MtrrLib.h>\r
19#include <Library/PcdLib.h>\r
20#include <Library/MemoryAllocationLib.h>\r
21#include <Library/DebugLib.h>\r
22#include <Register/Cpuid.h>\r
23#include <Register/SmramSaveStateMap.h>\r
24\r
25//\r
26// Machine Specific Registers (MSRs)\r
27//\r
28#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE\r
29#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A\r
30#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2\r
31#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3\r
32#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0\r
33#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1\r
34#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
35#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
d26a7a3f 36#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0\r
a9764e68 37\r
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38//\r
39// MSRs required for configuration of SMM Code Access Check\r
40//\r
41#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
42#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
43\r
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44//\r
45// Set default value to assume SMRR is not supported\r
46//\r
47BOOLEAN mSmrrSupported = FALSE;\r
48\r
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49//\r
50// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported\r
51//\r
52BOOLEAN mSmmFeatureControlSupported = FALSE;\r
53\r
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54//\r
55// Set default value to assume IA-32 Architectural MSRs are used\r
56//\r
57UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;\r
58UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;\r
59\r
60//\r
61// Set default value to assume MTRRs need to be configured on each SMI\r
62//\r
63BOOLEAN mNeedConfigureMtrrs = TRUE;\r
64\r
65//\r
66// Array for state of SMRR enable on all CPUs\r
67//\r
68BOOLEAN *mSmrrEnabled;\r
69\r
70/**\r
71 The constructor function\r
72\r
73 @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
74 @param[in] SystemTable A pointer to the EFI System Table.\r
75\r
76 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
77\r
78**/\r
79EFI_STATUS\r
80EFIAPI\r
81SmmCpuFeaturesLibConstructor (\r
82 IN EFI_HANDLE ImageHandle,\r
83 IN EFI_SYSTEM_TABLE *SystemTable\r
84 )\r
85{\r
86 UINT32 RegEax;\r
87 UINT32 RegEdx;\r
88 UINTN FamilyId;\r
89 UINTN ModelId;\r
90\r
91 //\r
92 // Retrieve CPU Family and Model\r
93 //\r
94 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
95 FamilyId = (RegEax >> 8) & 0xf;\r
96 ModelId = (RegEax >> 4) & 0xf;\r
97 if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
98 ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
99 }\r
100\r
101 //\r
102 // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability\r
103 //\r
104 if ((RegEdx & BIT12) != 0) {\r
105 //\r
106 // Check MTRR_CAP MSR bit 11 for SMRR support\r
107 //\r
108 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {\r
109 mSmrrSupported = TRUE;\r
110 }\r
111 }\r
112\r
113 //\r
114 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
115 // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family\r
116 //\r
117 // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then\r
118 // SMRR Physical Base and SMM Physical Mask MSRs are not available.\r
119 //\r
120 if (FamilyId == 0x06) {\r
121 if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {\r
122 mSmrrSupported = FALSE;\r
123 }\r
124 }\r
125\r
126 //\r
127 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
128 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
129 //\r
130 // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2\r
131 // Processor Family MSRs\r
132 //\r
133 if (FamilyId == 0x06) {\r
134 if (ModelId == 0x17 || ModelId == 0x0f) {\r
135 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;\r
136 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;\r
137 }\r
138 }\r
139\r
140 //\r
141 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
142 // Volume 3C, Section 34.4.2 SMRAM Caching\r
143 // An IA-32 processor does not automatically write back and invalidate its\r
144 // caches before entering SMM or before exiting SMM. Because of this behavior,\r
145 // care must be taken in the placement of the SMRAM in system memory and in\r
146 // the caching of the SMRAM to prevent cache incoherence when switching back\r
147 // and forth between SMM and protected mode operation.\r
148 //\r
149 // An IA-32 processor is a processor that does not support the Intel 64\r
150 // Architecture. Support for the Intel 64 Architecture can be detected from\r
151 // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]\r
152 //\r
153 // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,\r
154 // so caches are flushed on SMI entry and SMI exit, the interrupted code\r
155 // MTRRs are saved/restored, and MTRRs for SMM are loaded.\r
156 //\r
157 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
158 if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r
159 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r
160 if ((RegEdx & BIT29) != 0) {\r
161 mNeedConfigureMtrrs = FALSE;\r
162 }\r
163 }\r
164\r
165 //\r
166 // Allocate array for state of SMRR enable on all CPUs\r
167 //\r
168 mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
169 ASSERT (mSmrrEnabled != NULL);\r
170\r
171 return EFI_SUCCESS;\r
172}\r
173\r
174/**\r
175 Called during the very first SMI into System Management Mode to initialize\r
176 CPU features, including SMBASE, for the currently executing CPU. Since this\r
177 is the first SMI, the SMRAM Save State Map is at the default address of\r
178 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
179 CPU is specified by CpuIndex and CpuIndex can be used to access information\r
180 about the currently executing CPU in the ProcessorInfo array and the\r
181 HotPlugCpuData data structure.\r
182\r
183 @param[in] CpuIndex The index of the CPU to initialize. The value\r
184 must be between 0 and the NumberOfCpus field in\r
185 the System Management System Table (SMST).\r
186 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
187 was elected as monarch during System Management\r
188 Mode initialization.\r
189 FALSE if the CpuIndex is not the index of the CPU\r
190 that was elected as monarch during System\r
191 Management Mode initialization.\r
192 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
193 structures. ProcessorInfo[CpuIndex] contains the\r
194 information for the currently executing CPU.\r
195 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
196 contains the ApidId and SmBase arrays.\r
197**/\r
198VOID\r
199EFIAPI\r
200SmmCpuFeaturesInitializeProcessor (\r
201 IN UINTN CpuIndex,\r
202 IN BOOLEAN IsMonarch,\r
203 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
204 IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
205 )\r
206{\r
207 SMRAM_SAVE_STATE_MAP *CpuState;\r
208 UINT64 FeatureControl;\r
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209 UINT32 RegEax;\r
210 UINT32 RegEdx;\r
211 UINTN FamilyId;\r
212 UINTN ModelId;\r
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213\r
214 //\r
215 // Configure SMBASE.\r
216 //\r
217 CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
218 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
219\r
220 //\r
221 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
222 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
223 //\r
224 // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then\r
225 // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before\r
226 // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)\r
227 // is set, then the MSR is locked and can not be modified.\r
228 //\r
229 if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {\r
230 FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);\r
231 if ((FeatureControl & BIT3) == 0) {\r
232 if ((FeatureControl & BIT0) == 0) {\r
233 AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);\r
234 } else {\r
235 mSmrrSupported = FALSE;\r
236 }\r
237 }\r
238 }\r
239\r
240 //\r
241 // If SMRR is supported, then program SMRR base/mask MSRs.\r
242 // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.\r
243 // The code that initializes SMM environment is running in normal mode\r
244 // from SMRAM region. If SMRR is enabled here, then the SMRAM region\r
245 // is protected and the normal mode code execution will fail.\r
246 //\r
247 if (mSmrrSupported) {\r
248 AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
249 AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
250 mSmrrEnabled[CpuIndex] = FALSE;\r
251 }\r
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252\r
253 //\r
254 // Retrieve CPU Family and Model\r
255 //\r
256 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
257 FamilyId = (RegEax >> 8) & 0xf;\r
258 ModelId = (RegEax >> 4) & 0xf;\r
259 if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
260 ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
261 }\r
262\r
263 //\r
264 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
265 // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
266 // Processor Family.\r
267 //\r
268 // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
269 // Intel(R) Core(TM) Processor Family MSRs.\r
270 //\r
271 if (FamilyId == 0x06) {\r
272 if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
273 //\r
274 // Check to see if the CPU supports the SMM Code Access Check feature\r
275 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
276 //\r
277 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {\r
278 mSmmFeatureControlSupported = TRUE;\r
279 }\r
280 }\r
281 }\r
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282}\r
283\r
284/**\r
285 This function updates the SMRAM save state on the currently executing CPU\r
286 to resume execution at a specific address after an RSM instruction. This\r
287 function must evaluate the SMRAM save state to determine the execution mode\r
288 the RSM instruction resumes and update the resume execution address with\r
289 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
290 flag in the SMRAM save state must always be cleared. This function returns\r
291 the value of the instruction pointer from the SMRAM save state that was\r
292 replaced. If this function returns 0, then the SMRAM save state was not\r
293 modified.\r
294\r
295 This function is called during the very first SMI on each CPU after\r
296 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
297 to signal that the SMBASE of each CPU has been updated before the default\r
298 SMBASE address is used for the first SMI to the next CPU.\r
299\r
300 @param[in] CpuIndex The index of the CPU to hook. The value\r
301 must be between 0 and the NumberOfCpus\r
302 field in the System Management System Table\r
303 (SMST).\r
304 @param[in] CpuState Pointer to SMRAM Save State Map for the\r
305 currently executing CPU.\r
306 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
307 32-bit execution mode from 64-bit SMM.\r
308 @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
309 same execution mode as SMM.\r
310\r
311 @retval 0 This function did modify the SMRAM save state.\r
312 @retval > 0 The original instruction pointer value from the SMRAM save state\r
313 before it was replaced.\r
314**/\r
315UINT64\r
316EFIAPI\r
317SmmCpuFeaturesHookReturnFromSmm (\r
318 IN UINTN CpuIndex,\r
319 IN SMRAM_SAVE_STATE_MAP *CpuState,\r
320 IN UINT64 NewInstructionPointer32,\r
321 IN UINT64 NewInstructionPointer\r
322 )\r
323{\r
324 return 0;\r
325}\r
326\r
327/**\r
328 Hook point in normal execution mode that allows the one CPU that was elected\r
329 as monarch during System Management Mode initialization to perform additional\r
330 initialization actions immediately after all of the CPUs have processed their\r
331 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
332 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
333**/\r
334VOID\r
335EFIAPI\r
336SmmCpuFeaturesSmmRelocationComplete (\r
337 VOID\r
338 )\r
339{\r
340}\r
341\r
342/**\r
343 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r
344 returned, then a custom SMI handler is not provided by this library,\r
345 and the default SMI handler must be used.\r
346\r
347 @retval 0 Use the default SMI handler.\r
348 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
349 The caller is required to allocate enough SMRAM for each CPU to\r
350 support the size of the custom SMI handler.\r
351**/\r
352UINTN\r
353EFIAPI\r
354SmmCpuFeaturesGetSmiHandlerSize (\r
355 VOID\r
356 )\r
357{\r
358 return 0;\r
359}\r
360\r
361/**\r
362 Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
363 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
364 than zero and is called by the CPU that was elected as monarch during System\r
365 Management Mode initialization.\r
366\r
367 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
368 The value must be between 0 and the NumberOfCpus field\r
369 in the System Management System Table (SMST).\r
370 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
371 @param[in] SmiStack The stack to use when an SMI is processed by the\r
372 the CPU specified by CpuIndex.\r
373 @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
374 processed by the CPU specified by CpuIndex.\r
375 @param[in] GdtBase The base address of the GDT to use when an SMI is\r
376 processed by the CPU specified by CpuIndex.\r
377 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
378 processed by the CPU specified by CpuIndex.\r
379 @param[in] IdtBase The base address of the IDT to use when an SMI is\r
380 processed by the CPU specified by CpuIndex.\r
381 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
382 processed by the CPU specified by CpuIndex.\r
383 @param[in] Cr3 The base address of the page tables to use when an SMI\r
384 is processed by the CPU specified by CpuIndex.\r
385**/\r
386VOID\r
387EFIAPI\r
388SmmCpuFeaturesInstallSmiHandler (\r
389 IN UINTN CpuIndex,\r
390 IN UINT32 SmBase,\r
391 IN VOID *SmiStack,\r
392 IN UINTN StackSize,\r
393 IN UINTN GdtBase,\r
394 IN UINTN GdtSize,\r
395 IN UINTN IdtBase,\r
396 IN UINTN IdtSize,\r
397 IN UINT32 Cr3\r
398 )\r
399{\r
400}\r
401\r
402/**\r
403 Determines if MTRR registers must be configured to set SMRAM cache-ability\r
404 when executing in System Management Mode.\r
405\r
406 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
407 @retval FALSE MTRR registers do not need to be configured to set SMRAM\r
408 cache-ability.\r
409**/\r
410BOOLEAN\r
411EFIAPI\r
412SmmCpuFeaturesNeedConfigureMtrrs (\r
413 VOID\r
414 )\r
415{\r
416 return mNeedConfigureMtrrs;\r
417}\r
418\r
419/**\r
420 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
421 returns TRUE.\r
422**/\r
423VOID\r
424EFIAPI\r
425SmmCpuFeaturesDisableSmrr (\r
426 VOID\r
427 )\r
428{\r
429 if (mSmrrSupported && mNeedConfigureMtrrs) {\r
430 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
431 }\r
432}\r
433\r
434/**\r
435 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
436 returns TRUE.\r
437**/\r
438VOID\r
439EFIAPI\r
440SmmCpuFeaturesReenableSmrr (\r
441 VOID\r
442 )\r
443{\r
444 if (mSmrrSupported && mNeedConfigureMtrrs) {\r
445 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
446 }\r
447}\r
448\r
449/**\r
450 Processor specific hook point each time a CPU enters System Management Mode.\r
451\r
452 @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
453 must be between 0 and the NumberOfCpus field in the\r
454 System Management System Table (SMST).\r
455**/\r
456VOID\r
457EFIAPI\r
458SmmCpuFeaturesRendezvousEntry (\r
459 IN UINTN CpuIndex\r
460 )\r
461{\r
462 //\r
463 // If SMRR is supported and this is the first normal SMI, then enable SMRR\r
464 //\r
465 if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) {\r
466 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
467 mSmrrEnabled[CpuIndex] = TRUE;\r
468 }\r
469}\r
470\r
471/**\r
472 Processor specific hook point each time a CPU exits System Management Mode.\r
473\r
474 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
475 be between 0 and the NumberOfCpus field in the System\r
476 Management System Table (SMST).\r
477**/\r
478VOID\r
479EFIAPI\r
480SmmCpuFeaturesRendezvousExit (\r
481 IN UINTN CpuIndex\r
482 )\r
483{\r
484}\r
485\r
486/**\r
487 Check to see if an SMM register is supported by a specified CPU.\r
488\r
489 @param[in] CpuIndex The index of the CPU to check for SMM register support.\r
490 The value must be between 0 and the NumberOfCpus field\r
491 in the System Management System Table (SMST).\r
492 @param[in] RegName Identifies the SMM register to check for support.\r
493\r
494 @retval TRUE The SMM register specified by RegName is supported by the CPU\r
495 specified by CpuIndex.\r
496 @retval FALSE The SMM register specified by RegName is not supported by the\r
497 CPU specified by CpuIndex.\r
498**/\r
499BOOLEAN\r
500EFIAPI\r
501SmmCpuFeaturesIsSmmRegisterSupported (\r
502 IN UINTN CpuIndex,\r
503 IN SMM_REG_NAME RegName\r
504 )\r
505{\r
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506 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
507 return TRUE;\r
508 }\r
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509 return FALSE;\r
510}\r
511\r
512/**\r
513 Returns the current value of the SMM register for the specified CPU.\r
514 If the SMM register is not supported, then 0 is returned.\r
515\r
516 @param[in] CpuIndex The index of the CPU to read the SMM register. The\r
517 value must be between 0 and the NumberOfCpus field in\r
518 the System Management System Table (SMST).\r
519 @param[in] RegName Identifies the SMM register to read.\r
520\r
521 @return The value of the SMM register specified by RegName from the CPU\r
522 specified by CpuIndex.\r
523**/\r
524UINT64\r
525EFIAPI\r
526SmmCpuFeaturesGetSmmRegister (\r
527 IN UINTN CpuIndex,\r
528 IN SMM_REG_NAME RegName\r
529 )\r
530{\r
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531 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
532 return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
533 }\r
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534 return 0;\r
535}\r
536\r
537/**\r
538 Sets the value of an SMM register on a specified CPU.\r
539 If the SMM register is not supported, then no action is performed.\r
540\r
541 @param[in] CpuIndex The index of the CPU to write the SMM register. The\r
542 value must be between 0 and the NumberOfCpus field in\r
543 the System Management System Table (SMST).\r
544 @param[in] RegName Identifies the SMM register to write.\r
545 registers are read-only.\r
546 @param[in] Value The value to write to the SMM register.\r
547**/\r
548VOID\r
549EFIAPI\r
550SmmCpuFeaturesSetSmmRegister (\r
551 IN UINTN CpuIndex,\r
552 IN SMM_REG_NAME RegName,\r
553 IN UINT64 Value\r
554 )\r
555{\r
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556 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
557 AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
558 }\r
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559}\r
560\r
561/**\r
562 Read an SMM Save State register on the target processor. If this function\r
563 returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
564 SMM Save Sate register.\r
565\r
566 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
567 value must be between 0 and the NumberOfCpus field in\r
568 the System Management System Table (SMST).\r
569 @param[in] Register The SMM Save State register to read.\r
570 @param[in] Width The number of bytes to read from the CPU save state.\r
571 @param[out] Buffer Upon return, this holds the CPU register value read\r
572 from the save state.\r
573\r
574 @retval EFI_SUCCESS The register was read from Save State.\r
575 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
576 @retval EFI_UNSUPPORTED This function does not support reading Register.\r
577\r
578**/\r
579EFI_STATUS\r
580EFIAPI\r
581SmmCpuFeaturesReadSaveStateRegister (\r
582 IN UINTN CpuIndex,\r
583 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
584 IN UINTN Width,\r
585 OUT VOID *Buffer\r
586 )\r
587{\r
588 return EFI_UNSUPPORTED;\r
589}\r
590\r
591/**\r
592 Writes an SMM Save State register on the target processor. If this function\r
593 returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
594 SMM Save Sate register.\r
595\r
596 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
597 value must be between 0 and the NumberOfCpus field in\r
598 the System Management System Table (SMST).\r
599 @param[in] Register The SMM Save State register to write.\r
600 @param[in] Width The number of bytes to write to the CPU save state.\r
601 @param[in] Buffer Upon entry, this holds the new CPU register value.\r
602\r
603 @retval EFI_SUCCESS The register was written to Save State.\r
604 @retval EFI_INVALID_PARAMTER Buffer is NULL.\r
605 @retval EFI_UNSUPPORTED This function does not support writing Register.\r
606**/\r
607EFI_STATUS\r
608EFIAPI\r
609SmmCpuFeaturesWriteSaveStateRegister (\r
610 IN UINTN CpuIndex,\r
611 IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
612 IN UINTN Width,\r
613 IN CONST VOID *Buffer\r
614 )\r
615{\r
616 return EFI_UNSUPPORTED;\r
617}\r
b095a540
JY
618\r
619/**\r
620 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
621 notification is completely processed.\r
622**/\r
623VOID\r
624EFIAPI\r
625SmmCpuFeaturesCompleteSmmReadyToLock (\r
626 VOID\r
627 )\r
628{\r
629}\r
630\r
631/**\r
632 This API provides a method for a CPU to allocate a specific region for storing page tables.\r
633\r
634 This API can be called more once to allocate memory for page tables.\r
635\r
636 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
637 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
638 is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
639 returned.\r
640\r
641 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
642\r
643 @param Pages The number of 4 KB pages to allocate.\r
644\r
645 @return A pointer to the allocated buffer for page tables.\r
646 @retval NULL Fail to allocate a specific region for storing page tables,\r
647 Or there is no preference on where the page tables are allocated in SMRAM.\r
648\r
649**/\r
650VOID *\r
651EFIAPI\r
652SmmCpuFeaturesAllocatePageTableMemory (\r
653 IN UINTN Pages\r
654 )\r
655{\r
656 return NULL;\r
657}\r
658\r