[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / X64 / SmiException.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php.\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
# Module Name:\r
#\r
#   SmiException.S\r
#\r
# Abstract:\r
#\r
#   Exception handlers used in SM mode\r
#\r
#------------------------------------------------------------------------------\r
\r
ASM_GLOBAL  ASM_PFX(gcStmPsd)\r
\r
ASM_GLOBAL  ASM_PFX(SmmStmExceptionHandler)\r
ASM_GLOBAL  ASM_PFX(SmmStmSetup)\r
ASM_GLOBAL  ASM_PFX(SmmStmTeardown)\r
\r
.equ  CODE_SEL,             0x38\r
.equ  DATA_SEL,             0x20\r
.equ  TR_SEL,               0x40\r
\r
.equ  MSR_IA32_MISC_ENABLE, 0x1A0\r
.equ  MSR_EFER,             0x0c0000080\r
.equ  MSR_EFER_XD,          0x0800\r
\r
    .data\r
\r
#\r
# This structure serves as a template for all processors.\r
#\r
ASM_PFX(gcStmPsd):\r
            .ascii     "TXTPSSIG"\r
            .word      PSD_SIZE\r
            .word      1              # Version\r
            .long      0              # LocalApicId\r
            .byte      0xF            # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
            .byte      0              # BIOS to STM\r
            .byte      0              # STM to BIOS\r
            .byte      0\r
            .word      CODE_SEL\r
            .word      DATA_SEL\r
            .word      DATA_SEL\r
            .word      DATA_SEL\r
            .word      TR_SEL\r
            .word      0\r
            .quad      0              # SmmCr3\r
            .quad      ASM_PFX(_OnStmSetup)\r
            .quad      ASM_PFX(_OnStmTeardown)\r
            .quad      0              # SmmSmiHandlerRip - SMM guest entrypoint\r
            .quad      0              # SmmSmiHandlerRsp\r
            .quad      0\r
            .long      0\r
            .long      0x80010100     # RequiredStmSmmRevId\r
            .quad      ASM_PFX(_OnException)\r
            .quad      0              # ExceptionStack\r
            .word      DATA_SEL\r
            .word      0x1F           # ExceptionFilter\r
            .long      0\r
            .quad      0\r
            .quad      0              # BiosHwResourceRequirementsPtr\r
            .quad      0              # AcpiRsdp\r
            .byte      0              # PhysicalAddressBits\r
.equ  PSD_SIZE,  . - ASM_PFX(gcStmPsd)\r
\r
    .text\r
#------------------------------------------------------------------------------\r
# SMM Exception handlers\r
#------------------------------------------------------------------------------\r
\r
ASM_GLOBAL ASM_PFX(_OnException)\r
ASM_PFX(_OnException):\r
    movq %rsp, %rcx\r
    subq $0x28, %rsp\r
    call ASM_PFX(SmmStmExceptionHandler)\r
    addq $0x28, %rsp\r
    movl %eax, %ebx\r
    movl $4, %eax\r
    .byte  0xf, 0x1, 0xc1 # VMCALL\r
    jmp .\r
\r
ASM_GLOBAL ASM_PFX(_OnStmSetup)\r
ASM_PFX(_OnStmSetup):\r
#\r
# Check XD disable bit\r
#\r
    xorq    %r8, %r8\r
    movabsq $ASM_PFX(gStmXdSupported), %rax\r
    movb    (%rax), %al\r
    cmpb    $0, %al\r
    jz      StmXdDone1\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    movq    %rdx, %r8                  # save MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx                # MSR_IA32_MISC_ENABLE[34]\r
    jz      L13\r
    andw    $0x0FFFB, %dx              # clear XD Disable bit if it is set\r
    wrmsr\r
L13:\r
    movl    $MSR_EFER, %ecx\r
    rdmsr\r
    orw     $MSR_EFER_XD,%ax            # enable NXE\r
    wrmsr\r
StmXdDone1:\r
    pushq   %r8\r
\r
  subq $0x20, %rsp\r
  call ASM_PFX(SmmStmSetup)\r
  addq 0x20, %rsp\r
\r
    movabsq $ASM_PFX(gStmXdSupported), %rax\r
    movb    (%rax), %al\r
    cmpb    $0, %al\r
    jz      L14\r
    popq    %rdx                        # get saved MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx\r
    jz      L14\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM\r
    wrmsr\r
L14:\r
\r
  rsm\r
\r
ASM_GLOBAL ASM_PFX(_OnStmTeardown)\r
ASM_PFX(_OnStmTeardown):\r
#\r
# Check XD disable bit\r
#\r
    xorq    %r8, %r8\r
    movabsq $ASM_PFX(gStmXdSupported), %rax\r
    movb    (%rax), %al\r
    cmpb    $0, %al\r
    jz      StmXdDone2\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    movq    %rdx, %r8                  # save MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx                # MSR_IA32_MISC_ENABLE[34]\r
    jz      L15\r
    andw    $0x0FFFB, %dx              # clear XD Disable bit if it is set\r
    wrmsr\r
L15:\r
    movl    $MSR_EFER, %ecx\r
    rdmsr\r
    orw     $MSR_EFER_XD,%ax            # enable NXE\r
    wrmsr\r
StmXdDone2:\r
    pushq   %r8\r
\r
  subq $0x20, %rsp\r
  call ASM_PFX(SmmStmTeardown)\r
  addq $0x20, %rsp\r
\r
    movabsq $ASM_PFX(gStmXdSupported), %rax\r
    movb    (%rax), %al\r
    cmpb    $0, %al\r
    jz      L16\r
    popq    %rdx                        # get saved MSR_IA32_MISC_ENABLE[63-32]\r
    testl   $BIT2, %edx\r
    jz      L16\r
    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
    rdmsr\r
    orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM\r
    wrmsr\r
L16:\r
\r
  rsm\r
\r
Commit	Line	Data
09119a00 MK	1	#------------------------------------------------------------------------------\r
	2	#\r
	3	# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
	4	# This program and the accompanying materials\r
	5	# are licensed and made available under the terms and conditions of the BSD License\r
	6	# which accompanies this distribution. The full text of the license may be found at\r
	7	# http://opensource.org/licenses/bsd-license.php.\r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	# Module Name:\r
	13	#\r
	14	# SmiException.S\r
	15	#\r
	16	# Abstract:\r
	17	#\r
	18	# Exception handlers used in SM mode\r
	19	#\r
	20	#------------------------------------------------------------------------------\r
	21	\r
	22	ASM_GLOBAL ASM_PFX(gcStmPsd)\r
	23	\r
	24	ASM_GLOBAL ASM_PFX(SmmStmExceptionHandler)\r
	25	ASM_GLOBAL ASM_PFX(SmmStmSetup)\r
	26	ASM_GLOBAL ASM_PFX(SmmStmTeardown)\r
	27	\r
	28	.equ CODE_SEL, 0x38\r
	29	.equ DATA_SEL, 0x20\r
	30	.equ TR_SEL, 0x40\r
	31	\r
	32	.equ MSR_IA32_MISC_ENABLE, 0x1A0\r
	33	.equ MSR_EFER, 0x0c0000080\r
	34	.equ MSR_EFER_XD, 0x0800\r
	35	\r
	36	.data\r
	37	\r
	38	#\r
	39	# This structure serves as a template for all processors.\r
	40	#\r
	41	ASM_PFX(gcStmPsd):\r
	42	.ascii "TXTPSSIG"\r
	43	.word PSD_SIZE\r
	44	.word 1 # Version\r
	45	.long 0 # LocalApicId\r
	46	.byte 0xF # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
	47	.byte 0 # BIOS to STM\r
	48	.byte 0 # STM to BIOS\r
	49	.byte 0\r
	50	.word CODE_SEL\r
	51	.word DATA_SEL\r
	52	.word DATA_SEL\r
	53	.word DATA_SEL\r
	54	.word TR_SEL\r
	55	.word 0\r
	56	.quad 0 # SmmCr3\r
	57	.quad ASM_PFX(_OnStmSetup)\r
	58	.quad ASM_PFX(_OnStmTeardown)\r
	59	.quad 0 # SmmSmiHandlerRip - SMM guest entrypoint\r
	60	.quad 0 # SmmSmiHandlerRsp\r
	61	.quad 0\r
	62	.long 0\r
	63	.long 0x80010100 # RequiredStmSmmRevId\r
	64	.quad ASM_PFX(_OnException)\r
65	.quad 0 # ExceptionStack\r
66	.word DATA_SEL\r
67	.word 0x1F # ExceptionFilter\r
68	.long 0\r
69	.quad 0\r
70	.quad 0 # BiosHwResourceRequirementsPtr\r
71	.quad 0 # AcpiRsdp\r
72	.byte 0 # PhysicalAddressBits\r
73	.equ PSD_SIZE, . - ASM_PFX(gcStmPsd)\r
74	\r
75	.text\r
76	#------------------------------------------------------------------------------\r
77	# SMM Exception handlers\r
78	#------------------------------------------------------------------------------\r
79	\r
80	ASM_GLOBAL ASM_PFX(_OnException)\r
81	ASM_PFX(_OnException):\r
82	movq %rsp, %rcx\r
83	subq $0x28, %rsp\r
84	call ASM_PFX(SmmStmExceptionHandler)\r
85	addq $0x28, %rsp\r
86	movl %eax, %ebx\r
87	movl $4, %eax\r
88	.byte 0xf, 0x1, 0xc1 # VMCALL\r
89	jmp .\r
90	\r
91	ASM_GLOBAL ASM_PFX(_OnStmSetup)\r
92	ASM_PFX(_OnStmSetup):\r
93	#\r
94	# Check XD disable bit\r
95	#\r
96	xorq %r8, %r8\r
97	movabsq $ASM_PFX(gStmXdSupported), %rax\r
98	movb (%rax), %al\r
99	cmpb $0, %al\r
100	jz StmXdDone1\r
101	movl $MSR_IA32_MISC_ENABLE, %ecx\r
102	rdmsr\r
103	movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]\r
104	testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]\r
105	jz L13\r
106	andw $0x0FFFB, %dx # clear XD Disable bit if it is set\r
107	wrmsr\r
108	L13:\r
109	movl $MSR_EFER, %ecx\r
110	rdmsr\r
111	orw $MSR_EFER_XD,%ax # enable NXE\r
112	wrmsr\r
113	StmXdDone1:\r
114	pushq %r8\r
115	\r
116	subq $0x20, %rsp\r
117	call ASM_PFX(SmmStmSetup)\r
118	addq 0x20, %rsp\r
119	\r
120	movabsq $ASM_PFX(gStmXdSupported), %rax\r
121	movb (%rax), %al\r
122	cmpb $0, %al\r
123	jz L14\r
124	popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]\r
125	testl $BIT2, %edx\r
126	jz L14\r
127	movl $MSR_IA32_MISC_ENABLE, %ecx\r
128	rdmsr\r
129	orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM\r
130	wrmsr\r
131	L14:\r
132	\r
133	rsm\r
134	\r
135	ASM_GLOBAL ASM_PFX(_OnStmTeardown)\r
136	ASM_PFX(_OnStmTeardown):\r
137	#\r
138	# Check XD disable bit\r
139	#\r
140	xorq %r8, %r8\r
141	movabsq $ASM_PFX(gStmXdSupported), %rax\r
142	movb (%rax), %al\r
143	cmpb $0, %al\r
144	jz StmXdDone2\r
145	movl $MSR_IA32_MISC_ENABLE, %ecx\r
146	rdmsr\r
147	movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]\r
148	testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]\r
149	jz L15\r
150	andw $0x0FFFB, %dx # clear XD Disable bit if it is set\r
151	wrmsr\r
152	L15:\r
153	movl $MSR_EFER, %ecx\r
154	rdmsr\r
155	orw $MSR_EFER_XD,%ax # enable NXE\r
156	wrmsr\r
157	StmXdDone2:\r
158	pushq %r8\r
159	\r
160	subq $0x20, %rsp\r
161	call ASM_PFX(SmmStmTeardown)\r
162	addq $0x20, %rsp\r
163	\r
164	movabsq $ASM_PFX(gStmXdSupported), %rax\r
165	movb (%rax), %al\r
166	cmpb $0, %al\r
167	jz L16\r
168	popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]\r
169	testl $BIT2, %edx\r
170	jz L16\r
171	movl $MSR_IA32_MISC_ENABLE, %ecx\r
172	rdmsr\r
173	orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM\r
174	wrmsr\r
175	L16:\r
176	\r
177	rsm\r
178	\r