projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 09119a00 MK |
1 | ;------------------------------------------------------------------------------ ;\r |
| 2 | ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 3 | ; This program and the accompanying materials\r | |
| 4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
| 5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
| 6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
| 7 | ;\r | |
| 8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 10 | ;\r | |
| 11 | ; Module Name:\r | |
| 12 | ;\r | |
| 13 | ; SmiException.asm\r | |
| 14 | ;\r | |
| 15 | ; Abstract:\r | |
| 16 | ;\r | |
| 17 | ; Exception handlers used in SM mode\r | |
| 18 | ;\r | |
| 19 | ;-------------------------------------------------------------------------------\r | |
| 20 | \r | |
| 21 | EXTERNDEF gcStmPsd:BYTE\r | |
| 22 | \r | |
| 23 | EXTERNDEF SmmStmExceptionHandler:PROC\r | |
| 24 | EXTERNDEF SmmStmSetup:PROC\r | |
| 25 | EXTERNDEF SmmStmTeardown:PROC\r | |
| 26 | EXTERNDEF gStmXdSupported:BYTE\r | |
| 27 | \r | |
| 28 | CODE_SEL EQU 38h\r | |
| 29 | DATA_SEL EQU 20h\r | |
| 30 | TR_SEL EQU 40h\r | |
| 31 | \r | |
| 32 | MSR_IA32_MISC_ENABLE EQU 1A0h\r | |
| 33 | MSR_EFER EQU 0c0000080h\r | |
| 34 | MSR_EFER_XD EQU 0800h\r | |
| 35 | \r | |
| 36 | .data\r | |
| 37 | \r | |
| 38 | ;\r | |
| 39 | ; This structure serves as a template for all processors.\r | |
| 40 | ;\r | |
| 41 | gcStmPsd LABEL BYTE\r | |
| 42 | DB 'TXTPSSIG'\r | |
| 43 | DW PSD_SIZE\r | |
| 44 | DW 1 ; Version\r | |
| 45 | DD 0 ; LocalApicId\r | |
| 46 | DB 0Fh ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r | |
| 47 | DB 0 ; BIOS to STM\r | |
| 48 | DB 0 ; STM to BIOS\r | |
| 49 | DB 0\r | |
| 50 | DW CODE_SEL\r | |
| 51 | DW DATA_SEL\r | |
| 52 | DW DATA_SEL\r | |
| 53 | DW DATA_SEL\r | |
| 54 | DW TR_SEL\r | |
| 55 | DW 0\r | |
| 56 | DQ 0 ; SmmCr3\r | |
| 57 | DQ _OnStmSetup\r | |
| 58 | DQ _OnStmTeardown\r | |
| 59 | DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint\r | |
| 60 | DQ 0 ; SmmSmiHandlerRsp\r | |
| 61 | DQ 0\r | |
| 62 | DD 0\r | |
| 63 | DD 80010100h ; RequiredStmSmmRevId\r | |
| 64 | DQ _OnException\r | |
| 65 | DQ 0 ; ExceptionStack\r | |
| 66 | DW DATA_SEL\r | |
| 67 | DW 01Fh ; ExceptionFilter\r | |
| 68 | DD 0\r | |
| 69 | DQ 0\r | |
| 70 | DQ 0 ; BiosHwResourceRequirementsPtr\r | |
| 71 | DQ 0 ; AcpiRsdp\r | |
| 72 | DB 0 ; PhysicalAddressBits\r | |
| 73 | PSD_SIZE = $ - offset gcStmPsd\r | |
| 74 | \r | |
| 75 | .code\r | |
| 76 | ;------------------------------------------------------------------------------\r | |
| 77 | ; SMM Exception handlers\r | |
| 78 | ;------------------------------------------------------------------------------\r | |
| 79 | _OnException PROC\r | |
| 80 | mov rcx, rsp\r | |
| 81 | add rsp, -28h\r | |
| 82 | call SmmStmExceptionHandler\r | |
| 83 | add rsp, 28h\r | |
| 84 | mov ebx, eax\r | |
| 85 | mov eax, 4\r | |
| 86 | DB 0fh, 01h, 0c1h ; VMCALL\r | |
| 87 | jmp $\r | |
| 88 | _OnException ENDP\r | |
| 89 | \r | |
| 90 | _OnStmSetup PROC\r | |
| 91 | ;\r | |
| 92 | ; Check XD disable bit\r | |
| 93 | ;\r | |
| 94 | xor r8, r8\r | |
| 95 | mov rax, offset ASM_PFX(gStmXdSupported)\r | |
| 96 | mov al, [rax]\r | |
| 97 | cmp al, 0\r | |
| 98 | jz @StmXdDone1\r | |
| 99 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 100 | rdmsr\r | |
| 101 | mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
| 102 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
| 103 | jz @f\r | |
| 104 | and dx, 0FFFBh ; clear XD Disable bit if it is set\r | |
| 105 | wrmsr\r | |
| 106 | @@:\r | |
| 107 | mov ecx, MSR_EFER\r | |
| 108 | rdmsr\r | |
| 109 | or ax, MSR_EFER_XD ; enable NXE\r | |
| 110 | wrmsr\r | |
| 111 | @StmXdDone1:\r | |
| 112 | push r8\r | |
| 113 | \r | |
| 114 | add rsp, -20h\r | |
| 115 | call SmmStmSetup\r | |
| 116 | add rsp, 20h\r | |
| 117 | \r | |
| 118 | mov rax, offset ASM_PFX(gStmXdSupported)\r | |
| 119 | mov al, [rax]\r | |
| 120 | cmp al, 0\r | |
| 121 | jz @f\r | |
| 122 | pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
| 123 | test edx, BIT2\r | |
| 124 | jz @f\r | |
| 125 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 126 | rdmsr\r | |
| 127 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
| 128 | wrmsr\r | |
| 129 | @@:\r | |
| 130 | \r | |
| 131 | rsm\r | |
| 132 | _OnStmSetup ENDP\r | |
| 133 | \r | |
| 134 | _OnStmTeardown PROC\r | |
| 135 | ;\r | |
| 136 | ; Check XD disable bit\r | |
| 137 | ;\r | |
| 138 | xor r8, r8\r | |
| 139 | mov rax, offset ASM_PFX(gStmXdSupported)\r | |
| 140 | mov al, [rax]\r | |
| 141 | cmp al, 0\r | |
| 142 | jz @StmXdDone2\r | |
| 143 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 144 | rdmsr\r | |
| 145 | mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
| 146 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
| 147 | jz @f\r | |
| 148 | and dx, 0FFFBh ; clear XD Disable bit if it is set\r | |
| 149 | wrmsr\r | |
| 150 | @@:\r | |
| 151 | mov ecx, MSR_EFER\r | |
| 152 | rdmsr\r | |
| 153 | or ax, MSR_EFER_XD ; enable NXE\r | |
| 154 | wrmsr\r | |
| 155 | @StmXdDone2:\r | |
| 156 | push r8\r | |
| 157 | \r | |
| 158 | add rsp, -20h\r | |
| 159 | call SmmStmTeardown\r | |
| 160 | add rsp, 20h\r | |
| 161 | \r | |
| 162 | mov rax, offset ASM_PFX(gStmXdSupported)\r | |
| 163 | mov al, [rax]\r | |
| 164 | cmp al, 0\r | |
| 165 | jz @f\r | |
| 166 | pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
| 167 | test edx, BIT2\r | |
| 168 | jz @f\r | |
| 169 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 170 | rdmsr\r | |
| 171 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
| 172 | wrmsr\r | |
| 173 | @@:\r | |
| 174 | \r | |
| 175 | rsm\r | |
| 176 | _OnStmTeardown ENDP\r | |
| 177 | \r | |
| 178 | END\r |