projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 09119a00 | 1 | ;------------------------------------------------------------------------------ ;\r |
| 1c7a65eb | 2 | ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 0acd8697 | 3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 09119a00 MK |
4 | ;\r |
| 5 | ; Module Name:\r | |
| 6 | ;\r | |
| 7 | ; SmiException.nasm\r | |
| 8 | ;\r | |
| 9 | ; Abstract:\r | |
| 10 | ;\r | |
| 11 | ; Exception handlers used in SM mode\r | |
| 12 | ;\r | |
| 13 | ;-------------------------------------------------------------------------------\r | |
| 14 | \r | |
| ada4a003 | 15 | %include "StuffRsbNasm.inc"\r |
| 0df50560 | 16 | \r |
| 09119a00 MK |
17 | global ASM_PFX(gcStmPsd)\r |
| 18 | \r | |
| 19 | extern ASM_PFX(SmmStmExceptionHandler)\r | |
| 20 | extern ASM_PFX(SmmStmSetup)\r | |
| 21 | extern ASM_PFX(SmmStmTeardown)\r | |
| 22 | extern ASM_PFX(gStmXdSupported)\r | |
| 23 | extern ASM_PFX(gStmSmiHandlerIdtr)\r | |
| 24 | \r | |
| 25 | %define MSR_IA32_MISC_ENABLE 0x1A0\r | |
| 26 | %define MSR_EFER 0xc0000080\r | |
| 27 | %define MSR_EFER_XD 0x800\r | |
| 28 | \r | |
| 29 | CODE_SEL equ 0x38\r | |
| 30 | DATA_SEL equ 0x20\r | |
| 31 | TR_SEL equ 0x40\r | |
| 32 | \r | |
| 33 | SECTION .data\r | |
| 34 | \r | |
| 35 | ;\r | |
| 36 | ; This structure serves as a template for all processors.\r | |
| 37 | ;\r | |
| 38 | ASM_PFX(gcStmPsd):\r | |
| 39 | DB 'TXTPSSIG'\r | |
| 40 | DW PSD_SIZE\r | |
| 41 | DW 1 ; Version\r | |
| 42 | DD 0 ; LocalApicId\r | |
| 43 | DB 0x0F ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r | |
| 44 | DB 0 ; BIOS to STM\r | |
| 45 | DB 0 ; STM to BIOS\r | |
| 46 | DB 0\r | |
| 47 | DW CODE_SEL\r | |
| 48 | DW DATA_SEL\r | |
| 49 | DW DATA_SEL\r | |
| 50 | DW DATA_SEL\r | |
| 51 | DW TR_SEL\r | |
| 52 | DW 0\r | |
| 53 | DQ 0 ; SmmCr3\r | |
| 54 | DQ ASM_PFX(OnStmSetup)\r | |
| 55 | DQ ASM_PFX(OnStmTeardown)\r | |
| 56 | DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint\r | |
| 57 | DQ 0 ; SmmSmiHandlerRsp\r | |
| 58 | DQ 0\r | |
| 59 | DD 0\r | |
| 60 | DD 0x80010100 ; RequiredStmSmmRevId\r | |
| 61 | DQ ASM_PFX(OnException)\r | |
| 62 | DQ 0 ; ExceptionStack\r | |
| 63 | DW DATA_SEL\r | |
| 64 | DW 0x01F ; ExceptionFilter\r | |
| 65 | DD 0\r | |
| 66 | DQ 0\r | |
| 67 | DQ 0 ; BiosHwResourceRequirementsPtr\r | |
| 68 | DQ 0 ; AcpiRsdp\r | |
| 69 | DB 0 ; PhysicalAddressBits\r | |
| 70 | PSD_SIZE equ $ - ASM_PFX(gcStmPsd)\r | |
| 71 | \r | |
| 72 | DEFAULT REL\r | |
| 73 | SECTION .text\r | |
| 74 | ;------------------------------------------------------------------------------\r | |
| 75 | ; SMM Exception handlers\r | |
| 76 | ;------------------------------------------------------------------------------\r | |
| 77 | global ASM_PFX(OnException)\r | |
| 78 | ASM_PFX(OnException):\r | |
| 79 | mov rcx, rsp\r | |
| 80 | add rsp, -0x28\r | |
| 81 | call ASM_PFX(SmmStmExceptionHandler)\r | |
| 82 | add rsp, 0x28\r | |
| 83 | mov ebx, eax\r | |
| 84 | mov eax, 4\r | |
| 4c34a8ea | 85 | vmcall\r |
| 09119a00 MK |
86 | jmp $\r |
| 87 | \r | |
| 88 | global ASM_PFX(OnStmSetup)\r | |
| 89 | ASM_PFX(OnStmSetup):\r | |
| 90 | ;\r | |
| 91 | ; Check XD disable bit\r | |
| 92 | ;\r | |
| 93 | xor r8, r8\r | |
| 1c7a65eb | 94 | lea rax, [ASM_PFX(gStmXdSupported)]\r |
| 09119a00 MK |
95 | mov al, [rax]\r |
| 96 | cmp al, 0\r | |
| 97 | jz @StmXdDone1\r | |
| 98 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 99 | rdmsr\r | |
| 100 | mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
| 101 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
| 102 | jz .01\r | |
| 103 | and dx, 0xFFFB ; clear XD Disable bit if it is set\r | |
| 104 | wrmsr\r | |
| 105 | .01:\r | |
| 106 | mov ecx, MSR_EFER\r | |
| 107 | rdmsr\r | |
| 108 | or ax, MSR_EFER_XD ; enable NXE\r | |
| 109 | wrmsr\r | |
| 110 | @StmXdDone1:\r | |
| 111 | push r8\r | |
| 112 | \r | |
| 113 | add rsp, -0x20\r | |
| 114 | call ASM_PFX(SmmStmSetup)\r | |
| 115 | add rsp, 0x20\r | |
| 116 | \r | |
| 1c7a65eb | 117 | lea rax, [ASM_PFX(gStmXdSupported)]\r |
| 09119a00 MK |
118 | mov al, [rax]\r |
| 119 | cmp al, 0\r | |
| 120 | jz .11\r | |
| 121 | pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
| 122 | test edx, BIT2\r | |
| 123 | jz .11\r | |
| 124 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 125 | rdmsr\r | |
| 126 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
| 127 | wrmsr\r | |
| 128 | \r | |
| 129 | .11:\r | |
| 0df50560 HW |
130 | StuffRsb64\r |
| 131 | rsm\r | |
| 09119a00 MK |
132 | \r |
| 133 | global ASM_PFX(OnStmTeardown)\r | |
| 134 | ASM_PFX(OnStmTeardown):\r | |
| 135 | ;\r | |
| 136 | ; Check XD disable bit\r | |
| 137 | ;\r | |
| 138 | xor r8, r8\r | |
| 1c7a65eb | 139 | lea rax, [ASM_PFX(gStmXdSupported)]\r |
| 09119a00 MK |
140 | mov al, [rax]\r |
| 141 | cmp al, 0\r | |
| 142 | jz @StmXdDone2\r | |
| 143 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 144 | rdmsr\r | |
| 145 | mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
| 146 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
| 147 | jz .02\r | |
| 148 | and dx, 0xFFFB ; clear XD Disable bit if it is set\r | |
| 149 | wrmsr\r | |
| 150 | .02:\r | |
| 151 | mov ecx, MSR_EFER\r | |
| 152 | rdmsr\r | |
| 153 | or ax, MSR_EFER_XD ; enable NXE\r | |
| 154 | wrmsr\r | |
| 155 | @StmXdDone2:\r | |
| 156 | push r8\r | |
| 157 | \r | |
| 158 | add rsp, -0x20\r | |
| 159 | call ASM_PFX(SmmStmTeardown)\r | |
| 160 | add rsp, 0x20\r | |
| 161 | \r | |
| 1c7a65eb | 162 | lea rax, [ASM_PFX(gStmXdSupported)]\r |
| 09119a00 MK |
163 | mov al, [rax]\r |
| 164 | cmp al, 0\r | |
| 165 | jz .12\r | |
| 166 | pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
| 167 | test edx, BIT2\r | |
| 168 | jz .12\r | |
| 169 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
| 170 | rdmsr\r | |
| 171 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
| 172 | wrmsr\r | |
| 173 | \r | |
| 174 | .12:\r | |
| 0df50560 HW |
175 | StuffRsb64\r |
| 176 | rsm\r |