projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 09119a00 MK |
1 | /** @file\r |
| 2 | SMM STM support functions\r | |
| 3 | \r | |
| 4 | Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 5 | This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php.\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #include <PiSmm.h>\r | |
| 16 | #include <Library/DebugLib.h>\r | |
| 17 | \r | |
| 18 | #include "SmmStm.h"\r | |
| 19 | \r | |
| 20 | ///\r | |
| 21 | /// Page Table Entry\r | |
| 22 | ///\r | |
| 23 | #define IA32_PG_P BIT0\r | |
| 24 | #define IA32_PG_RW BIT1\r | |
| 25 | #define IA32_PG_PS BIT7\r | |
| 26 | \r | |
| 27 | /**\r | |
| 28 | \r | |
| 29 | Create 4G page table for STM.\r | |
| 30 | 2M PAE page table in X64 version.\r | |
| 31 | \r | |
| 32 | @param PageTableBase The page table base in MSEG\r | |
| 33 | \r | |
| 34 | **/\r | |
| 35 | VOID\r | |
| 36 | StmGen4GPageTable (\r | |
| 37 | IN UINTN PageTableBase\r | |
| 38 | )\r | |
| 39 | {\r | |
| 40 | UINTN Index;\r | |
| 41 | UINTN SubIndex;\r | |
| 42 | UINT64 *Pde;\r | |
| 43 | UINT64 *Pte;\r | |
| 44 | UINT64 *Pml4;\r | |
| 45 | \r | |
| 46 | Pml4 = (UINT64*)(UINTN)PageTableBase;\r | |
| 47 | PageTableBase += SIZE_4KB;\r | |
| 48 | *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;\r | |
| 49 | \r | |
| 50 | Pde = (UINT64*)(UINTN)PageTableBase;\r | |
| 51 | PageTableBase += SIZE_4KB;\r | |
| 52 | Pte = (UINT64 *)(UINTN)PageTableBase;\r | |
| 53 | \r | |
| 54 | for (Index = 0; Index < 4; Index++) {\r | |
| 55 | *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P;\r | |
| 56 | Pde++;\r | |
| 57 | PageTableBase += SIZE_4KB;\r | |
| 58 | \r | |
| 59 | for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) {\r | |
| 60 | *Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;\r | |
| 61 | Pte++;\r | |
| 62 | }\r | |
| 63 | }\r | |
| 64 | }\r | |
| 65 | \r | |
| 66 | /**\r | |
| 67 | This is SMM exception handle.\r | |
| 68 | Consumed by STM when exception happen.\r | |
| 69 | \r | |
| 70 | @param Context STM protection exception stack frame\r | |
| 71 | \r | |
| 72 | @return the EBX value for STM reference.\r | |
| 73 | EBX = 0: resume SMM guest using register state found on exception stack.\r | |
| 74 | EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the\r | |
| 75 | TXT.ERRORCODE register and subsequently reset the system via\r | |
| 76 | TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as\r | |
| 77 | follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC\r | |
| 78 | EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.\r | |
| 79 | \r | |
| 80 | **/\r | |
| 81 | UINT32\r | |
| 82 | EFIAPI\r | |
| 83 | SmmStmExceptionHandler (\r | |
| 84 | IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context\r | |
| 85 | )\r | |
| 86 | {\r | |
| 87 | // TBD - SmmStmExceptionHandler, record information\r | |
| 88 | DEBUG ((DEBUG_ERROR, "SmmStmExceptionHandler ...\n"));\r | |
| 89 | //\r | |
| 90 | // Skip this instruction and continue;\r | |
| 91 | //\r | |
| 92 | Context.X64StackFrame->Rip += Context.X64StackFrame->VmcsExitInstructionLength;\r | |
| 93 | \r | |
| 94 | return 0;\r | |
| 95 | }\r |