Install LoadedImage protocol for PiSmmCore.

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.asm

;------------------------------------------------------------------------------ ;\r
; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution.  The full text of the license may be found at\r
; http://opensource.org/licenses/bsd-license.php.\r
;\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
; Module Name:\r
;\r
;   SmiEntry.asm\r
;\r
; Abstract:\r
;\r
;   Code template of the SMI handler for a particular processor\r
;\r
;-------------------------------------------------------------------------------\r
\r
    .686p\r
    .model  flat,C\r
    .xmm\r
\r
DSC_OFFSET    EQU     0fb00h\r
DSC_GDTPTR    EQU     30h\r
DSC_GDTSIZ    EQU     38h\r
DSC_CS        EQU     14\r
DSC_DS        EQU     16\r
DSC_SS        EQU     18\r
DSC_OTHERSEG  EQU     20\r
\r
PROTECT_MODE_CS EQU   08h\r
PROTECT_MODE_DS EQU   20h\r
TSS_SEGMENT     EQU   40h\r
\r
SmiRendezvous   PROTO   C\r
\r
EXTERNDEF   gcSmiHandlerTemplate:BYTE\r
EXTERNDEF   gcSmiHandlerSize:WORD\r
EXTERNDEF   gSmiCr3:DWORD\r
EXTERNDEF   gSmiStack:DWORD\r
EXTERNDEF   gSmbase:DWORD\r
EXTERNDEF   FeaturePcdGet (PcdCpuSmmDebug):BYTE\r
EXTERNDEF   FeaturePcdGet (PcdCpuSmmStackGuard):BYTE\r
EXTERNDEF   gSmiHandlerIdtr:FWORD\r
\r
    .code\r
\r
gcSmiHandlerTemplate    LABEL   BYTE\r
\r
_SmiEntryPoint:\r
    DB      0bbh                        ; mov bx, imm16\r
    DW      offset _GdtDesc - _SmiEntryPoint + 8000h\r
    DB      2eh, 0a1h                   ; mov ax, cs:[offset16]\r
    DW      DSC_OFFSET + DSC_GDTSIZ\r
    dec     eax\r
    mov     cs:[edi], eax               ; mov cs:[bx], ax\r
    DB      66h, 2eh, 0a1h              ; mov eax, cs:[offset16]\r
    DW      DSC_OFFSET + DSC_GDTPTR\r
    mov     cs:[edi + 2], ax            ; mov cs:[bx + 2], eax\r
    mov     bp, ax                      ; ebp = GDT base\r
    DB      66h\r
    lgdt    fword ptr cs:[edi]          ; lgdt fword ptr cs:[bx]\r
; Patch ProtectedMode Segment\r
    DB      0b8h                        ; mov ax, imm16\r
    DW      PROTECT_MODE_CS             ; set AX for segment directly\r
    mov     cs:[edi - 2], eax           ; mov cs:[bx - 2], ax\r
; Patch ProtectedMode entry\r
    DB      66h, 0bfh                   ; mov edi, SMBASE\r
gSmbase    DD    ?\r
    DB      67h\r
    lea     ax, [edi + (@32bit - _SmiEntryPoint) + 8000h]\r
    mov     cs:[edi - 6], ax            ; mov cs:[bx - 6], eax\r
    mov     ebx, cr0\r
    DB      66h\r
    and     ebx, 9ffafff3h\r
    DB      66h\r
    or      ebx, 23h\r
    mov     cr0, ebx\r
    DB      66h, 0eah\r
    DD      ?\r
    DW      ?\r
_GdtDesc    FWORD   ?\r
\r
@32bit:\r
    mov     ax, PROTECT_MODE_DS\r
    mov     ds, ax\r
    mov     es, ax\r
    mov     fs, ax\r
    mov     gs, ax\r
    mov     ss, ax\r
    DB      0bch                   ; mov esp, imm32\r
gSmiStack   DD      ?\r
    mov     eax, offset gSmiHandlerIdtr\r
    lidt    fword ptr [eax]\r
    jmp     ProtFlatMode\r
\r
ProtFlatMode:\r
    DB      0b8h                        ; mov eax, imm32\r
gSmiCr3     DD      ?\r
    mov     cr3, eax\r
;\r
; Need to test for CR4 specific bit support\r
;\r
    mov     eax, 1\r
    cpuid                               ; use CPUID to determine if specific CR4 bits are supported\r
    xor     eax, eax                    ; Clear EAX\r
    test    edx, BIT2                   ; Check for DE capabilities\r
    jz      @f\r
    or      eax, BIT3\r
@@:\r
    test    edx, BIT6                   ; Check for PAE capabilities\r
    jz      @f\r
    or      eax, BIT5\r
@@:\r
    test    edx, BIT7                   ; Check for MCE capabilities\r
    jz      @f\r
    or      eax, BIT6\r
@@:\r
    test    edx, BIT24                  ; Check for FXSR capabilities\r
    jz      @f\r
    or      eax, BIT9\r
@@:\r
    test    edx, BIT25                  ; Check for SSE capabilities\r
    jz      @f\r
    or      eax, BIT10\r
@@:                                     ; as cr4.PGE is not set here, refresh cr3\r
    mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.\r
    mov     ebx, cr0\r
    or      ebx, 080000000h             ; enable paging\r
    mov     cr0, ebx\r
    lea     ebx, [edi + DSC_OFFSET]\r
    mov     ax, [ebx + DSC_DS]\r
    mov     ds, eax\r
    mov     ax, [ebx + DSC_OTHERSEG]\r
    mov     es, eax\r
    mov     fs, eax\r
    mov     gs, eax\r
    mov     ax, [ebx + DSC_SS]\r
    mov     ss, eax\r
\r
    cmp     FeaturePcdGet (PcdCpuSmmStackGuard), 0\r
    jz      @F\r
\r
; Load TSS\r
    mov     byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r
    mov     eax, TSS_SEGMENT\r
    ltr     ax\r
@@:\r
;   jmp     _SmiHandler                 ; instruction is not needed\r
\r
_SmiHandler PROC\r
    cmp     FeaturePcdGet (PcdCpuSmmDebug), 0\r
    jz      @3\r
    call    @1\r
@1:\r
    pop     ebp\r
    mov     eax, 80000001h\r
    cpuid\r
    bt      edx, 29                     ; check cpuid to identify X64 or IA32\r
    lea     edi, [ebp - (@1 - _SmiEntryPoint) + 7fc8h]\r
    lea     esi, [edi + 4]\r
    jnc     @2\r
    add     esi, 4\r
@2:\r
    mov     ecx, [esi]\r
    mov     edx, [edi]\r
@5:\r
    mov     dr6, ecx\r
    mov     dr7, edx                    ; restore DR6 & DR7 before running C code\r
@3:\r
    mov     ecx, [esp]                  ; CPU Index\r
\r
    push    ecx\r
    mov     eax, SmiRendezvous\r
    call    eax\r
    pop     ecx\r
\r
    cmp     FeaturePcdGet (PcdCpuSmmDebug), 0\r
    jz      @4\r
\r
    mov     ecx, dr6\r
    mov     edx, dr7\r
    mov     [esi], ecx\r
    mov     [edi], edx\r
@4:\r
    rsm\r
_SmiHandler ENDP\r
\r
gcSmiHandlerSize    DW      $ - _SmiEntryPoint\r
\r
    END\r