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63a4f460 | 1 | ;------------------------------------------------------------------------------ ;\r |
e21e355e | 2 | ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
63a4f460 LG |
3 | ; This program and the accompanying materials\r |
4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
7 | ;\r | |
8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
10 | ;\r | |
11 | ; Module Name:\r | |
12 | ;\r | |
13 | ; SmiEntry.nasm\r | |
14 | ;\r | |
15 | ; Abstract:\r | |
16 | ;\r | |
17 | ; Code template of the SMI handler for a particular processor\r | |
18 | ;\r | |
19 | ;-------------------------------------------------------------------------------\r | |
20 | \r | |
02f7fd15 HW |
21 | %include "StuffRsb.inc"\r |
22 | \r | |
717fb604 JY |
23 | %define MSR_IA32_MISC_ENABLE 0x1A0\r |
24 | %define MSR_EFER 0xc0000080\r | |
25 | %define MSR_EFER_XD 0x800\r | |
26 | \r | |
f12367a0 MK |
27 | ;\r |
28 | ; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r | |
29 | ;\r | |
63a4f460 LG |
30 | %define DSC_OFFSET 0xfb00\r |
31 | %define DSC_GDTPTR 0x30\r | |
32 | %define DSC_GDTSIZ 0x38\r | |
33 | %define DSC_CS 14\r | |
34 | %define DSC_DS 16\r | |
35 | %define DSC_SS 18\r | |
36 | %define DSC_OTHERSEG 20\r | |
37 | \r | |
38 | %define PROTECT_MODE_CS 0x8\r | |
39 | %define PROTECT_MODE_DS 0x20\r | |
40 | %define TSS_SEGMENT 0x40\r | |
41 | \r | |
42 | extern ASM_PFX(SmiRendezvous)\r | |
43 | extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r | |
44 | extern ASM_PFX(CpuSmmDebugEntry)\r | |
45 | extern ASM_PFX(CpuSmmDebugExit)\r | |
46 | \r | |
47 | global ASM_PFX(gcSmiHandlerTemplate)\r | |
48 | global ASM_PFX(gcSmiHandlerSize)\r | |
c455687f | 49 | global ASM_PFX(gPatchSmiCr3)\r |
fc504fde | 50 | global ASM_PFX(gPatchSmiStack)\r |
5a1bfda4 | 51 | global ASM_PFX(gPatchSmbase)\r |
3c5ce64f LE |
52 | extern ASM_PFX(mXdSupported)\r |
53 | global ASM_PFX(gPatchXdSupported)\r | |
63a4f460 LG |
54 | extern ASM_PFX(gSmiHandlerIdtr)\r |
55 | \r | |
56 | SECTION .text\r | |
57 | \r | |
58 | BITS 16\r | |
59 | ASM_PFX(gcSmiHandlerTemplate):\r | |
60 | _SmiEntryPoint:\r | |
61 | mov bx, _GdtDesc - _SmiEntryPoint + 0x8000\r | |
62 | mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]\r | |
63 | dec ax\r | |
64 | mov [cs:bx], ax\r | |
65 | mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]\r | |
66 | mov [cs:bx + 2], eax\r | |
67 | mov ebp, eax ; ebp = GDT base\r | |
68 | o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r | |
69 | mov ax, PROTECT_MODE_CS\r | |
717fb604 | 70 | mov [cs:bx-0x2],ax\r |
5a1bfda4 LE |
71 | mov edi, strict dword 0 ; source operand will be patched\r |
72 | ASM_PFX(gPatchSmbase):\r | |
63a4f460 LG |
73 | lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]\r |
74 | mov [cs:bx-0x6],eax\r | |
75 | mov ebx, cr0\r | |
76 | and ebx, 0x9ffafff3\r | |
77 | or ebx, 0x23\r | |
78 | mov cr0, ebx\r | |
79 | jmp dword 0x0:0x0\r | |
717fb604 | 80 | _GdtDesc:\r |
63a4f460 LG |
81 | DW 0\r |
82 | DD 0\r | |
83 | \r | |
84 | BITS 32\r | |
85 | @32bit:\r | |
86 | mov ax, PROTECT_MODE_DS\r | |
87 | o16 mov ds, ax\r | |
88 | o16 mov es, ax\r | |
89 | o16 mov fs, ax\r | |
90 | o16 mov gs, ax\r | |
91 | o16 mov ss, ax\r | |
fc504fde LE |
92 | mov esp, strict dword 0 ; source operand will be patched\r |
93 | ASM_PFX(gPatchSmiStack):\r | |
63a4f460 LG |
94 | mov eax, ASM_PFX(gSmiHandlerIdtr)\r |
95 | lidt [eax]\r | |
96 | jmp ProtFlatMode\r | |
97 | \r | |
98 | ProtFlatMode:\r | |
c455687f LE |
99 | mov eax, strict dword 0 ; source operand will be patched\r |
100 | ASM_PFX(gPatchSmiCr3):\r | |
63a4f460 LG |
101 | mov cr3, eax\r |
102 | ;\r | |
103 | ; Need to test for CR4 specific bit support\r | |
104 | ;\r | |
105 | mov eax, 1\r | |
106 | cpuid ; use CPUID to determine if specific CR4 bits are supported\r | |
107 | xor eax, eax ; Clear EAX\r | |
108 | test edx, BIT2 ; Check for DE capabilities\r | |
109 | jz .0\r | |
110 | or eax, BIT3\r | |
111 | .0:\r | |
112 | test edx, BIT6 ; Check for PAE capabilities\r | |
113 | jz .1\r | |
114 | or eax, BIT5\r | |
115 | .1:\r | |
116 | test edx, BIT7 ; Check for MCE capabilities\r | |
117 | jz .2\r | |
118 | or eax, BIT6\r | |
119 | .2:\r | |
120 | test edx, BIT24 ; Check for FXSR capabilities\r | |
121 | jz .3\r | |
122 | or eax, BIT9\r | |
123 | .3:\r | |
124 | test edx, BIT25 ; Check for SSE capabilities\r | |
125 | jz .4\r | |
126 | or eax, BIT10\r | |
127 | .4: ; as cr4.PGE is not set here, refresh cr3\r | |
128 | mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r | |
717fb604 JY |
129 | \r |
130 | cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r | |
131 | jz .6\r | |
132 | ; Load TSS\r | |
133 | mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag\r | |
134 | mov eax, TSS_SEGMENT\r | |
135 | ltr ax\r | |
136 | .6:\r | |
137 | \r | |
138 | ; enable NXE if supported\r | |
3c5ce64f LE |
139 | mov al, strict byte 1 ; source operand may be patched\r |
140 | ASM_PFX(gPatchXdSupported):\r | |
717fb604 JY |
141 | cmp al, 0\r |
142 | jz @SkipXd\r | |
143 | ;\r | |
144 | ; Check XD disable bit\r | |
145 | ;\r | |
146 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
147 | rdmsr\r | |
148 | push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
149 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
150 | jz .5\r | |
151 | and dx, 0xFFFB ; clear XD Disable bit if it is set\r | |
152 | wrmsr\r | |
153 | .5:\r | |
154 | mov ecx, MSR_EFER\r | |
155 | rdmsr\r | |
156 | or ax, MSR_EFER_XD ; enable NXE\r | |
157 | wrmsr\r | |
158 | jmp @XdDone\r | |
159 | @SkipXd:\r | |
160 | sub esp, 4\r | |
161 | @XdDone:\r | |
162 | \r | |
63a4f460 | 163 | mov ebx, cr0\r |
717fb604 | 164 | or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE\r |
63a4f460 LG |
165 | mov cr0, ebx\r |
166 | lea ebx, [edi + DSC_OFFSET]\r | |
167 | mov ax, [ebx + DSC_DS]\r | |
168 | mov ds, eax\r | |
169 | mov ax, [ebx + DSC_OTHERSEG]\r | |
170 | mov es, eax\r | |
171 | mov fs, eax\r | |
172 | mov gs, eax\r | |
173 | mov ax, [ebx + DSC_SS]\r | |
174 | mov ss, eax\r | |
175 | \r | |
63a4f460 LG |
176 | ; jmp _SmiHandler ; instruction is not needed\r |
177 | \r | |
178 | global ASM_PFX(SmiHandler)\r | |
179 | ASM_PFX(SmiHandler):\r | |
717fb604 | 180 | mov ebx, [esp + 4] ; CPU Index\r |
63a4f460 LG |
181 | push ebx\r |
182 | mov eax, ASM_PFX(CpuSmmDebugEntry)\r | |
183 | call eax\r | |
717fb604 | 184 | add esp, 4\r |
63a4f460 LG |
185 | \r |
186 | push ebx\r | |
187 | mov eax, ASM_PFX(SmiRendezvous)\r | |
188 | call eax\r | |
717fb604 JY |
189 | add esp, 4\r |
190 | \r | |
63a4f460 LG |
191 | push ebx\r |
192 | mov eax, ASM_PFX(CpuSmmDebugExit)\r | |
193 | call eax\r | |
717fb604 JY |
194 | add esp, 4\r |
195 | \r | |
196 | mov eax, ASM_PFX(mXdSupported)\r | |
197 | mov al, [eax]\r | |
198 | cmp al, 0\r | |
199 | jz .7\r | |
200 | pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
201 | test edx, BIT2\r | |
202 | jz .7\r | |
203 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
204 | rdmsr\r | |
205 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
206 | wrmsr\r | |
207 | \r | |
208 | .7:\r | |
02f7fd15 | 209 | StuffRsb32\r |
63a4f460 LG |
210 | rsm\r |
211 | \r | |
212 | ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r | |
213 | \r | |
e21e355e LG |
214 | global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r |
215 | ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r | |
216 | ret\r |