UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiEntry.asm to NASM
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.nasm
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1;------------------------------------------------------------------------------ ;\r
2; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
3; This program and the accompanying materials\r
4; are licensed and made available under the terms and conditions of the BSD License\r
5; which accompanies this distribution. The full text of the license may be found at\r
6; http://opensource.org/licenses/bsd-license.php.\r
7;\r
8; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
9; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
10;\r
11; Module Name:\r
12;\r
13; SmiEntry.nasm\r
14;\r
15; Abstract:\r
16;\r
17; Code template of the SMI handler for a particular processor\r
18;\r
19;-------------------------------------------------------------------------------\r
20\r
21%define DSC_OFFSET 0xfb00\r
22%define DSC_GDTPTR 0x30\r
23%define DSC_GDTSIZ 0x38\r
24%define DSC_CS 14\r
25%define DSC_DS 16\r
26%define DSC_SS 18\r
27%define DSC_OTHERSEG 20\r
28\r
29%define PROTECT_MODE_CS 0x8\r
30%define PROTECT_MODE_DS 0x20\r
31%define TSS_SEGMENT 0x40\r
32\r
33extern ASM_PFX(SmiRendezvous)\r
34extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r
35extern ASM_PFX(CpuSmmDebugEntry)\r
36extern ASM_PFX(CpuSmmDebugExit)\r
37\r
38global ASM_PFX(gcSmiHandlerTemplate)\r
39global ASM_PFX(gcSmiHandlerSize)\r
40global ASM_PFX(gSmiCr3)\r
41global ASM_PFX(gSmiStack)\r
42global ASM_PFX(gSmbase)\r
43extern ASM_PFX(gSmiHandlerIdtr)\r
44\r
45 SECTION .text\r
46\r
47BITS 16\r
48ASM_PFX(gcSmiHandlerTemplate):\r
49_SmiEntryPoint:\r
50 mov bx, _GdtDesc - _SmiEntryPoint + 0x8000\r
51 mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]\r
52 dec ax\r
53 mov [cs:bx], ax\r
54 mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]\r
55 mov [cs:bx + 2], eax\r
56 mov ebp, eax ; ebp = GDT base\r
57o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
58 mov ax, PROTECT_MODE_CS\r
59 mov [cs:bx-0x2],ax \r
60 DB 0x66, 0xbf ; mov edi, SMBASE\r
61ASM_PFX(gSmbase): DD 0\r
62 lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]\r
63 mov [cs:bx-0x6],eax\r
64 mov ebx, cr0\r
65 and ebx, 0x9ffafff3\r
66 or ebx, 0x23\r
67 mov cr0, ebx\r
68 jmp dword 0x0:0x0\r
69_GdtDesc: \r
70 DW 0\r
71 DD 0\r
72\r
73BITS 32\r
74@32bit:\r
75 mov ax, PROTECT_MODE_DS\r
76o16 mov ds, ax\r
77o16 mov es, ax\r
78o16 mov fs, ax\r
79o16 mov gs, ax\r
80o16 mov ss, ax\r
81 DB 0xbc ; mov esp, imm32\r
82ASM_PFX(gSmiStack): DD 0\r
83 mov eax, ASM_PFX(gSmiHandlerIdtr)\r
84 lidt [eax]\r
85 jmp ProtFlatMode\r
86\r
87ProtFlatMode:\r
88 DB 0xb8 ; mov eax, imm32\r
89ASM_PFX(gSmiCr3): DD 0\r
90 mov cr3, eax\r
91;\r
92; Need to test for CR4 specific bit support\r
93;\r
94 mov eax, 1\r
95 cpuid ; use CPUID to determine if specific CR4 bits are supported\r
96 xor eax, eax ; Clear EAX\r
97 test edx, BIT2 ; Check for DE capabilities\r
98 jz .0\r
99 or eax, BIT3\r
100.0:\r
101 test edx, BIT6 ; Check for PAE capabilities\r
102 jz .1\r
103 or eax, BIT5\r
104.1:\r
105 test edx, BIT7 ; Check for MCE capabilities\r
106 jz .2\r
107 or eax, BIT6\r
108.2:\r
109 test edx, BIT24 ; Check for FXSR capabilities\r
110 jz .3\r
111 or eax, BIT9\r
112.3:\r
113 test edx, BIT25 ; Check for SSE capabilities\r
114 jz .4\r
115 or eax, BIT10\r
116.4: ; as cr4.PGE is not set here, refresh cr3\r
117 mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
118 mov ebx, cr0\r
119 or ebx, 0x080010000 ; enable paging + WP\r
120 mov cr0, ebx\r
121 lea ebx, [edi + DSC_OFFSET]\r
122 mov ax, [ebx + DSC_DS]\r
123 mov ds, eax\r
124 mov ax, [ebx + DSC_OTHERSEG]\r
125 mov es, eax\r
126 mov fs, eax\r
127 mov gs, eax\r
128 mov ax, [ebx + DSC_SS]\r
129 mov ss, eax\r
130\r
131 cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
132 jz .5\r
133\r
134; Load TSS\r
135 mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag\r
136 mov eax, TSS_SEGMENT\r
137 ltr ax\r
138.5:\r
139; jmp _SmiHandler ; instruction is not needed\r
140\r
141global ASM_PFX(SmiHandler)\r
142ASM_PFX(SmiHandler):\r
143 mov ebx, [esp] ; CPU Index\r
144\r
145 push ebx\r
146 mov eax, ASM_PFX(CpuSmmDebugEntry)\r
147 call eax\r
148 pop ecx\r
149\r
150 push ebx\r
151 mov eax, ASM_PFX(SmiRendezvous)\r
152 call eax\r
153 pop ecx\r
154 \r
155 push ebx\r
156 mov eax, ASM_PFX(CpuSmmDebugExit)\r
157 call eax\r
158 pop ecx\r
159\r
160 rsm\r
161\r
162ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
163\r