[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.nasm

;------------------------------------------------------------------------------ ;\r
; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;\r
;   SmiEntry.nasm\r
;\r
; Abstract:\r
;\r
;   Code template of the SMI handler for a particular processor\r
;\r
;-------------------------------------------------------------------------------\r
\r
%include "StuffRsbNasm.inc"\r
%include "Nasm.inc"\r
\r
%define MSR_IA32_S_CET                     0x6A2\r
%define   MSR_IA32_CET_SH_STK_EN             0x1\r
%define   MSR_IA32_CET_WR_SHSTK_EN           0x2\r
%define   MSR_IA32_CET_ENDBR_EN              0x4\r
%define   MSR_IA32_CET_LEG_IW_EN             0x8\r
%define   MSR_IA32_CET_NO_TRACK_EN           0x10\r
%define   MSR_IA32_CET_SUPPRESS_DIS          0x20\r
%define   MSR_IA32_CET_SUPPRESS              0x400\r
%define   MSR_IA32_CET_TRACKER               0x800\r
%define MSR_IA32_PL0_SSP                   0x6A4\r
\r
%define CR4_CET                            0x800000\r
\r
%define MSR_IA32_MISC_ENABLE 0x1A0\r
%define MSR_EFER      0xc0000080\r
%define MSR_EFER_XD   0x800\r
\r
;\r
; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
;\r
%define DSC_OFFSET 0xfb00\r
%define DSC_GDTPTR 0x30\r
%define DSC_GDTSIZ 0x38\r
%define DSC_CS 14\r
%define DSC_DS 16\r
%define DSC_SS 18\r
%define DSC_OTHERSEG 20\r
\r
%define PROTECT_MODE_CS 0x8\r
%define PROTECT_MODE_DS 0x20\r
%define TSS_SEGMENT 0x40\r
\r
extern ASM_PFX(SmiRendezvous)\r
extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r
extern ASM_PFX(CpuSmmDebugEntry)\r
extern ASM_PFX(CpuSmmDebugExit)\r
\r
global ASM_PFX(gcSmiHandlerTemplate)\r
global ASM_PFX(gcSmiHandlerSize)\r
global ASM_PFX(gPatchSmiCr3)\r
global ASM_PFX(gPatchSmiStack)\r
global ASM_PFX(gPatchSmbase)\r
extern ASM_PFX(mXdSupported)\r
global ASM_PFX(gPatchXdSupported)\r
global ASM_PFX(gPatchMsrIa32MiscEnableSupported)\r
extern ASM_PFX(gSmiHandlerIdtr)\r
\r
extern ASM_PFX(mCetSupported)\r
global ASM_PFX(mPatchCetSupported)\r
global ASM_PFX(mPatchCetPl0Ssp)\r
global ASM_PFX(mPatchCetInterruptSsp)\r
\r
    SECTION .text\r
\r
BITS 16\r
ASM_PFX(gcSmiHandlerTemplate):\r
_SmiEntryPoint:\r
    mov     bx, _GdtDesc - _SmiEntryPoint + 0x8000\r
    mov     ax,[cs:DSC_OFFSET + DSC_GDTSIZ]\r
    dec     ax\r
    mov     [cs:bx], ax\r
    mov     eax, [cs:DSC_OFFSET + DSC_GDTPTR]\r
    mov     [cs:bx + 2], eax\r
    mov     ebp, eax                      ; ebp = GDT base\r
o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]\r
    mov     ax, PROTECT_MODE_CS\r
    mov     [cs:bx-0x2],ax\r
    mov     edi, strict dword 0           ; source operand will be patched\r
ASM_PFX(gPatchSmbase):\r
    lea     eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]\r
    mov     [cs:bx-0x6],eax\r
    mov     ebx, cr0\r
    and     ebx, 0x9ffafff3\r
    or      ebx, 0x23\r
    mov     cr0, ebx\r
    jmp     dword 0x0:0x0\r
_GdtDesc:\r
    DW 0\r
    DD 0\r
\r
BITS 32\r
@32bit:\r
    mov     ax, PROTECT_MODE_DS\r
o16 mov     ds, ax\r
o16 mov     es, ax\r
o16 mov     fs, ax\r
o16 mov     gs, ax\r
o16 mov     ss, ax\r
    mov esp, strict dword 0               ; source operand will be patched\r
ASM_PFX(gPatchSmiStack):\r
    mov     eax, ASM_PFX(gSmiHandlerIdtr)\r
    lidt    [eax]\r
    jmp     ProtFlatMode\r
\r
ProtFlatMode:\r
    mov eax, strict dword 0               ; source operand will be patched\r
ASM_PFX(gPatchSmiCr3):\r
    mov     cr3, eax\r
;\r
; Need to test for CR4 specific bit support\r
;\r
    mov     eax, 1\r
    cpuid                               ; use CPUID to determine if specific CR4 bits are supported\r
    xor     eax, eax                    ; Clear EAX\r
    test    edx, BIT2                   ; Check for DE capabilities\r
    jz      .0\r
    or      eax, BIT3\r
.0:\r
    test    edx, BIT6                   ; Check for PAE capabilities\r
    jz      .1\r
    or      eax, BIT5\r
.1:\r
    test    edx, BIT7                   ; Check for MCE capabilities\r
    jz      .2\r
    or      eax, BIT6\r
.2:\r
    test    edx, BIT24                  ; Check for FXSR capabilities\r
    jz      .3\r
    or      eax, BIT9\r
.3:\r
    test    edx, BIT25                  ; Check for SSE capabilities\r
    jz      .4\r
    or      eax, BIT10\r
.4:                                     ; as cr4.PGE is not set here, refresh cr3\r
    mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.\r
\r
    cmp     byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
    jz      .6\r
; Load TSS\r
    mov     byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag\r
    mov     eax, TSS_SEGMENT\r
    ltr     ax\r
.6:\r
\r
; enable NXE if supported\r
    mov     al, strict byte 1           ; source operand may be patched\r
ASM_PFX(gPatchXdSupported):\r
    cmp     al, 0\r
    jz      @SkipXd\r
\r
; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit\r
    mov     al, strict byte 1           ; source operand may be patched\r
ASM_PFX(gPatchMsrIa32MiscEnableSupported):\r
    cmp     al, 1\r
    jz      MsrIa32MiscEnableSupported\r
\r
; MSR_IA32_MISC_ENABLE not supported\r
    xor     edx, edx\r
    push    edx                         ; don't try to restore the XD Disable bit just before RSM\r
    jmp     EnableNxe\r
\r
;\r
; Check XD disable bit\r
;\r
MsrIa32MiscEnableSupported:\r
    mov     ecx, MSR_IA32_MISC_ENABLE\r
    rdmsr\r
    push    edx                        ; save MSR_IA32_MISC_ENABLE[63-32]\r
    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]\r
    jz      EnableNxe\r
    and     dx, 0xFFFB                 ; clear XD Disable bit if it is set\r
    wrmsr\r
EnableNxe:\r
    mov     ecx, MSR_EFER\r
    rdmsr\r
    or      ax, MSR_EFER_XD             ; enable NXE\r
    wrmsr\r
    jmp     @XdDone\r
@SkipXd:\r
    sub     esp, 4\r
@XdDone:\r
\r
    mov     ebx, cr0\r
    or      ebx, 0x80010023             ; enable paging + WP + NE + MP + PE\r
    mov     cr0, ebx\r
    lea     ebx, [edi + DSC_OFFSET]\r
    mov     ax, [ebx + DSC_DS]\r
    mov     ds, eax\r
    mov     ax, [ebx + DSC_OTHERSEG]\r
    mov     es, eax\r
    mov     fs, eax\r
    mov     gs, eax\r
    mov     ax, [ebx + DSC_SS]\r
    mov     ss, eax\r
\r
    mov     ebx, [esp + 4]                  ; ebx <- CpuIndex\r
\r
; enable CET if supported\r
    mov     al, strict byte 1           ; source operand may be patched\r
ASM_PFX(mPatchCetSupported):\r
    cmp     al, 0\r
    jz      CetDone\r
\r
    mov     ecx, MSR_IA32_S_CET\r
    rdmsr\r
    push    edx\r
    push    eax\r
\r
    mov     ecx, MSR_IA32_PL0_SSP\r
    rdmsr\r
    push    edx\r
    push    eax\r
\r
    mov     ecx, MSR_IA32_S_CET\r
    mov     eax, MSR_IA32_CET_SH_STK_EN\r
    xor     edx, edx\r
    wrmsr\r
\r
    mov     ecx, MSR_IA32_PL0_SSP\r
    mov     eax, strict dword 0         ; source operand will be patched\r
ASM_PFX(mPatchCetPl0Ssp):\r
    xor     edx, edx\r
    wrmsr\r
    mov     ecx, cr0\r
    btr     ecx, 16                     ; clear WP\r
    mov     cr0, ecx\r
    mov     [eax], eax                  ; reload SSP, and clear busyflag.\r
    xor     ecx, ecx\r
    mov     [eax + 4], ecx\r
\r
    mov     eax, strict dword 0         ; source operand will be patched\r
ASM_PFX(mPatchCetInterruptSsp):\r
    cmp     eax, 0\r
    jz      CetInterruptDone\r
    mov     [eax], eax                  ; reload SSP, and clear busyflag.\r
    xor     ecx, ecx\r
    mov     [eax + 4], ecx\r
CetInterruptDone:\r
\r
    mov     ecx, cr0\r
    bts     ecx, 16                     ; set WP\r
    mov     cr0, ecx\r
\r
    mov     eax, 0x668 | CR4_CET\r
    mov     cr4, eax\r
\r
    SETSSBSY\r
\r
CetDone:\r
\r
    push    ebx\r
    mov     eax, ASM_PFX(CpuSmmDebugEntry)\r
    call    eax\r
    add     esp, 4\r
\r
    push    ebx\r
    mov     eax, ASM_PFX(SmiRendezvous)\r
    call    eax\r
    add     esp, 4\r
\r
    push    ebx\r
    mov     eax, ASM_PFX(CpuSmmDebugExit)\r
    call    eax\r
    add     esp, 4\r
\r
    mov     eax, ASM_PFX(mCetSupported)\r
    mov     al, [eax]\r
    cmp     al, 0\r
    jz      CetDone2\r
\r
    mov     eax, 0x668\r
    mov     cr4, eax       ; disable CET\r
\r
    mov     ecx, MSR_IA32_PL0_SSP\r
    pop     eax\r
    pop     edx\r
    wrmsr\r
\r
    mov     ecx, MSR_IA32_S_CET\r
    pop     eax\r
    pop     edx\r
    wrmsr\r
CetDone2:\r
\r
    mov     eax, ASM_PFX(mXdSupported)\r
    mov     al, [eax]\r
    cmp     al, 0\r
    jz      .7\r
    pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
    test    edx, BIT2\r
    jz      .7\r
    mov     ecx, MSR_IA32_MISC_ENABLE\r
    rdmsr\r
    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM\r
    wrmsr\r
\r
.7:\r
\r
    StuffRsb32\r
    rsm\r
\r
ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
\r
global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
    ret\r
Commit	Line	Data
63a4f460	1	;------------------------------------------------------------------------------ ;\r
3eb69b08	2	; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
bdafda8c	3	; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
0acd8697	4	; SPDX-License-Identifier: BSD-2-Clause-Patent\r
63a4f460 LG	5	;\r
	6	; Module Name:\r
	7	;\r
	8	; SmiEntry.nasm\r
	9	;\r
	10	; Abstract:\r
	11	;\r
	12	; Code template of the SMI handler for a particular processor\r
	13	;\r
	14	;-------------------------------------------------------------------------------\r
	15	\r
ada4a003	16	%include "StuffRsbNasm.inc"\r
3eb69b08 JY	17	%include "Nasm.inc"\r
	18	\r
	19	%define MSR_IA32_S_CET 0x6A2\r
	20	%define MSR_IA32_CET_SH_STK_EN 0x1\r
	21	%define MSR_IA32_CET_WR_SHSTK_EN 0x2\r
	22	%define MSR_IA32_CET_ENDBR_EN 0x4\r
	23	%define MSR_IA32_CET_LEG_IW_EN 0x8\r
	24	%define MSR_IA32_CET_NO_TRACK_EN 0x10\r
	25	%define MSR_IA32_CET_SUPPRESS_DIS 0x20\r
	26	%define MSR_IA32_CET_SUPPRESS 0x400\r
	27	%define MSR_IA32_CET_TRACKER 0x800\r
	28	%define MSR_IA32_PL0_SSP 0x6A4\r
	29	\r
	30	%define CR4_CET 0x800000\r
02f7fd15	31	\r
717fb604 JY	32	%define MSR_IA32_MISC_ENABLE 0x1A0\r
	33	%define MSR_EFER 0xc0000080\r
	34	%define MSR_EFER_XD 0x800\r
	35	\r
f12367a0 MK	36	;\r
	37	; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
	38	;\r
63a4f460 LG	39	%define DSC_OFFSET 0xfb00\r
	40	%define DSC_GDTPTR 0x30\r
	41	%define DSC_GDTSIZ 0x38\r
	42	%define DSC_CS 14\r
	43	%define DSC_DS 16\r
	44	%define DSC_SS 18\r
	45	%define DSC_OTHERSEG 20\r
	46	\r
	47	%define PROTECT_MODE_CS 0x8\r
	48	%define PROTECT_MODE_DS 0x20\r
	49	%define TSS_SEGMENT 0x40\r
	50	\r
	51	extern ASM_PFX(SmiRendezvous)\r
	52	extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r
	53	extern ASM_PFX(CpuSmmDebugEntry)\r
	54	extern ASM_PFX(CpuSmmDebugExit)\r
	55	\r
	56	global ASM_PFX(gcSmiHandlerTemplate)\r
	57	global ASM_PFX(gcSmiHandlerSize)\r
c455687f	58	global ASM_PFX(gPatchSmiCr3)\r
fc504fde	59	global ASM_PFX(gPatchSmiStack)\r
5a1bfda4	60	global ASM_PFX(gPatchSmbase)\r
3c5ce64f LE	61	extern ASM_PFX(mXdSupported)\r
3c5ce64f LE	62	global ASM_PFX(gPatchXdSupported)\r
bdafda8c	63	global ASM_PFX(gPatchMsrIa32MiscEnableSupported)\r
63a4f460 LG	64	extern ASM_PFX(gSmiHandlerIdtr)\r
63a4f460 LG	65	\r
3eb69b08 JY	66	extern ASM_PFX(mCetSupported)\r
	67	global ASM_PFX(mPatchCetSupported)\r
	68	global ASM_PFX(mPatchCetPl0Ssp)\r
	69	global ASM_PFX(mPatchCetInterruptSsp)\r
	70	\r
63a4f460 LG	71	SECTION .text\r
	72	\r
	73	BITS 16\r
	74	ASM_PFX(gcSmiHandlerTemplate):\r
	75	_SmiEntryPoint:\r
	76	mov bx, _GdtDesc - _SmiEntryPoint + 0x8000\r
	77	mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]\r
	78	dec ax\r
	79	mov [cs:bx], ax\r
	80	mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]\r
	81	mov [cs:bx + 2], eax\r
	82	mov ebp, eax ; ebp = GDT base\r
	83	o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
	84	mov ax, PROTECT_MODE_CS\r
717fb604	85	mov [cs:bx-0x2],ax\r
5a1bfda4 LE	86	mov edi, strict dword 0 ; source operand will be patched\r
5a1bfda4 LE	87	ASM_PFX(gPatchSmbase):\r
63a4f460 LG	88	lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]\r
	89	mov [cs:bx-0x6],eax\r
	90	mov ebx, cr0\r
	91	and ebx, 0x9ffafff3\r
	92	or ebx, 0x23\r
	93	mov cr0, ebx\r
	94	jmp dword 0x0:0x0\r
717fb604	95	_GdtDesc:\r
63a4f460 LG	96	DW 0\r
	97	DD 0\r
	98	\r
	99	BITS 32\r
	100	@32bit:\r
	101	mov ax, PROTECT_MODE_DS\r
	102	o16 mov ds, ax\r
	103	o16 mov es, ax\r
	104	o16 mov fs, ax\r
	105	o16 mov gs, ax\r
	106	o16 mov ss, ax\r
fc504fde LE	107	mov esp, strict dword 0 ; source operand will be patched\r
fc504fde LE	108	ASM_PFX(gPatchSmiStack):\r
63a4f460 LG	109	mov eax, ASM_PFX(gSmiHandlerIdtr)\r
	110	lidt [eax]\r
	111	jmp ProtFlatMode\r
	112	\r
	113	ProtFlatMode:\r
c455687f LE	114	mov eax, strict dword 0 ; source operand will be patched\r
c455687f LE	115	ASM_PFX(gPatchSmiCr3):\r
63a4f460 LG	116	mov cr3, eax\r
	117	;\r
	118	; Need to test for CR4 specific bit support\r
	119	;\r
	120	mov eax, 1\r
	121	cpuid ; use CPUID to determine if specific CR4 bits are supported\r
	122	xor eax, eax ; Clear EAX\r
	123	test edx, BIT2 ; Check for DE capabilities\r
	124	jz .0\r
	125	or eax, BIT3\r
	126	.0:\r
	127	test edx, BIT6 ; Check for PAE capabilities\r
	128	jz .1\r
	129	or eax, BIT5\r
	130	.1:\r
	131	test edx, BIT7 ; Check for MCE capabilities\r
	132	jz .2\r
	133	or eax, BIT6\r
	134	.2:\r
	135	test edx, BIT24 ; Check for FXSR capabilities\r
	136	jz .3\r
	137	or eax, BIT9\r
	138	.3:\r
	139	test edx, BIT25 ; Check for SSE capabilities\r
	140	jz .4\r
	141	or eax, BIT10\r
	142	.4: ; as cr4.PGE is not set here, refresh cr3\r
	143	mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
717fb604 JY	144	\r
	145	cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
	146	jz .6\r
	147	; Load TSS\r
	148	mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag\r
	149	mov eax, TSS_SEGMENT\r
	150	ltr ax\r
	151	.6:\r
	152	\r
	153	; enable NXE if supported\r
3c5ce64f LE	154	mov al, strict byte 1 ; source operand may be patched\r
3c5ce64f LE	155	ASM_PFX(gPatchXdSupported):\r
717fb604 JY	156	cmp al, 0\r
717fb604 JY	157	jz @SkipXd\r
bdafda8c KG	158	\r
	159	; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit\r
	160	mov al, strict byte 1 ; source operand may be patched\r
	161	ASM_PFX(gPatchMsrIa32MiscEnableSupported):\r
	162	cmp al, 1\r
	163	jz MsrIa32MiscEnableSupported\r
	164	\r
	165	; MSR_IA32_MISC_ENABLE not supported\r
	166	xor edx, edx\r
	167	push edx ; don't try to restore the XD Disable bit just before RSM\r
	168	jmp EnableNxe\r
	169	\r
717fb604 JY	170	;\r
	171	; Check XD disable bit\r
	172	;\r
bdafda8c	173	MsrIa32MiscEnableSupported:\r
717fb604 JY	174	mov ecx, MSR_IA32_MISC_ENABLE\r
	175	rdmsr\r
	176	push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
	177	test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
bdafda8c	178	jz EnableNxe\r
717fb604 JY	179	and dx, 0xFFFB ; clear XD Disable bit if it is set\r
717fb604 JY	180	wrmsr\r
bdafda8c	181	EnableNxe:\r
717fb604 JY	182	mov ecx, MSR_EFER\r
	183	rdmsr\r
	184	or ax, MSR_EFER_XD ; enable NXE\r
	185	wrmsr\r
	186	jmp @XdDone\r
	187	@SkipXd:\r
	188	sub esp, 4\r
	189	@XdDone:\r
	190	\r
63a4f460	191	mov ebx, cr0\r
717fb604	192	or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE\r
63a4f460 LG	193	mov cr0, ebx\r
	194	lea ebx, [edi + DSC_OFFSET]\r
	195	mov ax, [ebx + DSC_DS]\r
	196	mov ds, eax\r
	197	mov ax, [ebx + DSC_OTHERSEG]\r
	198	mov es, eax\r
	199	mov fs, eax\r
	200	mov gs, eax\r
	201	mov ax, [ebx + DSC_SS]\r
	202	mov ss, eax\r
	203	\r
3eb69b08 JY	204	mov ebx, [esp + 4] ; ebx <- CpuIndex\r
	205	\r
	206	; enable CET if supported\r
	207	mov al, strict byte 1 ; source operand may be patched\r
	208	ASM_PFX(mPatchCetSupported):\r
	209	cmp al, 0\r
	210	jz CetDone\r
	211	\r
	212	mov ecx, MSR_IA32_S_CET\r
	213	rdmsr\r
	214	push edx\r
	215	push eax\r
	216	\r
	217	mov ecx, MSR_IA32_PL0_SSP\r
	218	rdmsr\r
	219	push edx\r
	220	push eax\r
	221	\r
	222	mov ecx, MSR_IA32_S_CET\r
	223	mov eax, MSR_IA32_CET_SH_STK_EN\r
	224	xor edx, edx\r
	225	wrmsr\r
	226	\r
	227	mov ecx, MSR_IA32_PL0_SSP\r
	228	mov eax, strict dword 0 ; source operand will be patched\r
	229	ASM_PFX(mPatchCetPl0Ssp):\r
	230	xor edx, edx\r
	231	wrmsr\r
	232	mov ecx, cr0\r
	233	btr ecx, 16 ; clear WP\r
	234	mov cr0, ecx\r
	235	mov [eax], eax ; reload SSP, and clear busyflag.\r
	236	xor ecx, ecx\r
	237	mov [eax + 4], ecx\r
	238	\r
	239	mov eax, strict dword 0 ; source operand will be patched\r
	240	ASM_PFX(mPatchCetInterruptSsp):\r
	241	cmp eax, 0\r
	242	jz CetInterruptDone\r
	243	mov [eax], eax ; reload SSP, and clear busyflag.\r
	244	xor ecx, ecx\r
	245	mov [eax + 4], ecx\r
	246	CetInterruptDone:\r
	247	\r
	248	mov ecx, cr0\r
	249	bts ecx, 16 ; set WP\r
	250	mov cr0, ecx\r
	251	\r
	252	mov eax, 0x668 \| CR4_CET\r
	253	mov cr4, eax\r
	254	\r
	255	SETSSBSY\r
	256	\r
	257	CetDone:\r
63a4f460	258	\r
63a4f460 LG	259	push ebx\r
	260	mov eax, ASM_PFX(CpuSmmDebugEntry)\r
	261	call eax\r
717fb604	262	add esp, 4\r
63a4f460 LG	263	\r
	264	push ebx\r
	265	mov eax, ASM_PFX(SmiRendezvous)\r
	266	call eax\r
717fb604 JY	267	add esp, 4\r
717fb604 JY	268	\r
63a4f460 LG	269	push ebx\r
	270	mov eax, ASM_PFX(CpuSmmDebugExit)\r
	271	call eax\r
717fb604 JY	272	add esp, 4\r
717fb604 JY	273	\r
3eb69b08 JY	274	mov eax, ASM_PFX(mCetSupported)\r
	275	mov al, [eax]\r
	276	cmp al, 0\r
	277	jz CetDone2\r
	278	\r
	279	mov eax, 0x668\r
	280	mov cr4, eax ; disable CET\r
	281	\r
	282	mov ecx, MSR_IA32_PL0_SSP\r
	283	pop eax\r
	284	pop edx\r
	285	wrmsr\r
	286	\r
	287	mov ecx, MSR_IA32_S_CET\r
	288	pop eax\r
	289	pop edx\r
	290	wrmsr\r
	291	CetDone2:\r
	292	\r
717fb604 JY	293	mov eax, ASM_PFX(mXdSupported)\r
	294	mov al, [eax]\r
	295	cmp al, 0\r
	296	jz .7\r
	297	pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
	298	test edx, BIT2\r
	299	jz .7\r
	300	mov ecx, MSR_IA32_MISC_ENABLE\r
	301	rdmsr\r
	302	or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
	303	wrmsr\r
	304	\r
	305	.7:\r
3eb69b08	306	\r
02f7fd15	307	StuffRsb32\r
63a4f460 LG	308	rsm\r
	309	\r
	310	ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
	311	\r
e21e355e LG	312	global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
	313	ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
	314	ret\r