Commit | Line | Data |
---|---|---|
fe5f1949 JY |
1 | /** @file\r |
2 | SMM CPU misc functions for Ia32 arch specific.\r | |
3 | \r | |
6e601a41 | 4 | Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r |
fe5f1949 JY |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "PiSmmCpuDxeSmm.h"\r | |
16 | \r | |
717fb604 JY |
17 | extern UINT64 gTaskGateDescriptor;\r |
18 | \r | |
19 | EFI_PHYSICAL_ADDRESS mGdtBuffer;\r | |
20 | UINTN mGdtBufferSize;\r | |
21 | \r | |
22 | /**\r | |
23 | Initialize IDT for SMM Stack Guard.\r | |
24 | \r | |
25 | **/\r | |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | InitializeIDTSmmStackGuard (\r | |
29 | VOID\r | |
30 | )\r | |
31 | {\r | |
32 | IA32_IDT_GATE_DESCRIPTOR *IdtGate;\r | |
33 | \r | |
34 | //\r | |
35 | // If SMM Stack Guard feature is enabled, the Page Fault Exception entry in IDT\r | |
36 | // is a Task Gate Descriptor so that when a Page Fault Exception occurs,\r | |
37 | // the processors can use a known good stack in case stack is ran out.\r | |
38 | //\r | |
39 | IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r | |
40 | IdtGate += EXCEPT_IA32_PAGE_FAULT;\r | |
41 | IdtGate->Uint64 = gTaskGateDescriptor;\r | |
42 | }\r | |
43 | \r | |
fe5f1949 JY |
44 | /**\r |
45 | Initialize Gdt for all processors.\r | |
46 | \r | |
47 | @param[in] Cr3 CR3 value.\r | |
48 | @param[out] GdtStepSize The step size for GDT table.\r | |
49 | \r | |
50 | @return GdtBase for processor 0.\r | |
51 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
52 | **/\r | |
53 | VOID *\r | |
54 | InitGdt (\r | |
55 | IN UINTN Cr3,\r | |
56 | OUT UINTN *GdtStepSize\r | |
57 | )\r | |
58 | {\r | |
59 | UINTN Index;\r | |
60 | IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;\r | |
61 | UINTN TssBase;\r | |
62 | UINTN GdtTssTableSize;\r | |
63 | UINT8 *GdtTssTables;\r | |
64 | UINTN GdtTableStepSize;\r | |
65 | \r | |
66 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r | |
67 | //\r | |
68 | // For IA32 SMM, if SMM Stack Guard feature is enabled, we use 2 TSS.\r | |
69 | // in this case, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention\r | |
70 | // on each SMI entry.\r | |
71 | //\r | |
72 | \r | |
73 | //\r | |
74 | // Enlarge GDT to contain 2 TSS descriptors\r | |
75 | //\r | |
76 | gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR));\r | |
77 | \r | |
78 | GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE * 2 + 7) & ~7; // 8 bytes aligned\r | |
717fb604 | 79 | mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r |
6e601a41 SZ |
80 | //\r |
81 | // IA32 Stack Guard need use task switch to switch stack that need\r | |
82 | // write GDT and TSS, so AllocateCodePages() could not be used here\r | |
83 | // as code pages will be set to RO. \r | |
84 | //\r | |
85 | GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r | |
fe5f1949 | 86 | ASSERT (GdtTssTables != NULL);\r |
717fb604 | 87 | mGdtBuffer = (UINTN)GdtTssTables;\r |
fe5f1949 JY |
88 | GdtTableStepSize = GdtTssTableSize;\r |
89 | \r | |
90 | for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r | |
91 | CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE * 2);\r | |
92 | //\r | |
93 | // Fixup TSS descriptors\r | |
94 | //\r | |
95 | TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r | |
96 | GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r | |
97 | GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;\r | |
98 | GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);\r | |
99 | GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r | |
100 | \r | |
101 | TssBase += TSS_SIZE;\r | |
102 | GdtDescriptor++;\r | |
103 | GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;\r | |
104 | GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);\r | |
105 | GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r | |
106 | //\r | |
107 | // Fixup TSS segments\r | |
108 | //\r | |
109 | // ESP as known good stack\r | |
110 | //\r | |
111 | *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;\r | |
112 | *(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3;\r | |
113 | }\r | |
114 | } else {\r | |
115 | //\r | |
116 | // Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory.\r | |
117 | //\r | |
118 | GdtTssTableSize = gcSmiGdtr.Limit + 1;\r | |
717fb604 JY |
119 | mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r |
120 | GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r | |
fe5f1949 | 121 | ASSERT (GdtTssTables != NULL);\r |
717fb604 | 122 | mGdtBuffer = (UINTN)GdtTssTables;\r |
fe5f1949 JY |
123 | GdtTableStepSize = GdtTssTableSize;\r |
124 | \r | |
125 | for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r | |
126 | CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);\r | |
127 | }\r | |
128 | }\r | |
129 | \r | |
130 | *GdtStepSize = GdtTableStepSize;\r | |
131 | return GdtTssTables;\r | |
132 | }\r | |
4a0f88dd JF |
133 | \r |
134 | /**\r | |
135 | Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r | |
136 | \r | |
672b80c8 MK |
137 | @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r |
138 | @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r | |
139 | @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r | |
4a0f88dd JF |
140 | \r |
141 | **/\r | |
142 | VOID\r | |
143 | TransferApToSafeState (\r | |
672b80c8 MK |
144 | IN UINTN ApHltLoopCode,\r |
145 | IN UINTN TopOfStack,\r | |
146 | IN UINTN NumberToFinishAddress\r | |
4a0f88dd JF |
147 | )\r |
148 | {\r | |
149 | SwitchStack (\r | |
672b80c8 MK |
150 | (SWITCH_STACK_ENTRY_POINT)ApHltLoopCode,\r |
151 | (VOID *)NumberToFinishAddress,\r | |
4a0f88dd | 152 | NULL,\r |
672b80c8 | 153 | (VOID *)TopOfStack\r |
4a0f88dd JF |
154 | );\r |
155 | //\r | |
156 | // It should never reach here\r | |
157 | //\r | |
158 | ASSERT (FALSE);\r | |
159 | }\r |