Commit | Line | Data |
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246cd908 | 1 | ;------------------------------------------------------------------------------ ;\r |
e21e355e | 2 | ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
246cd908 LG |
3 | ; This program and the accompanying materials\r |
4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
7 | ;\r | |
8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
10 | ;\r | |
11 | ; Module Name:\r | |
12 | ;\r | |
13 | ; SmmInit.nasm\r | |
14 | ;\r | |
15 | ; Abstract:\r | |
16 | ;\r | |
17 | ; Functions for relocating SMBASE's for all processors\r | |
18 | ;\r | |
19 | ;-------------------------------------------------------------------------------\r | |
20 | \r | |
21 | extern ASM_PFX(SmmInitHandler)\r | |
22 | extern ASM_PFX(mRebasedFlag)\r | |
23 | extern ASM_PFX(mSmmRelocationOriginalAddress)\r | |
24 | \r | |
6b0841c1 | 25 | global ASM_PFX(gPatchSmmCr3)\r |
351b49c1 | 26 | global ASM_PFX(gPatchSmmCr4)\r |
f0053e83 | 27 | global ASM_PFX(gPatchSmmCr0)\r |
246cd908 LG |
28 | global ASM_PFX(gSmmInitStack)\r |
29 | global ASM_PFX(gcSmiInitGdtr)\r | |
30 | global ASM_PFX(gcSmmInitSize)\r | |
31 | global ASM_PFX(gcSmmInitTemplate)\r | |
32 | \r | |
33 | %define PROTECT_MODE_CS 0x8\r | |
34 | %define PROTECT_MODE_DS 0x20\r | |
35 | \r | |
36 | SECTION .text\r | |
37 | \r | |
38 | ASM_PFX(gcSmiInitGdtr):\r | |
39 | DW 0\r | |
40 | DQ 0\r | |
41 | \r | |
42 | global ASM_PFX(SmmStartup)\r | |
e75ee972 LE |
43 | \r |
44 | BITS 16\r | |
246cd908 | 45 | ASM_PFX(SmmStartup):\r |
d4d87596 JW |
46 | mov eax, 0x80000001 ; read capability\r |
47 | cpuid\r | |
d4d87596 | 48 | mov ebx, edx ; rdmsr will change edx. keep it in ebx.\r |
8d4d55b1 LE |
49 | and ebx, BIT20 ; extract NX capability bit\r |
50 | shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position\r | |
6b0841c1 LE |
51 | mov eax, strict dword 0 ; source operand will be patched\r |
52 | ASM_PFX(gPatchSmmCr3):\r | |
246cd908 | 53 | mov cr3, eax\r |
e75ee972 | 54 | o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r |
351b49c1 LE |
55 | mov eax, strict dword 0 ; source operand will be patched\r |
56 | ASM_PFX(gPatchSmmCr4):\r | |
246cd908 | 57 | mov cr4, eax\r |
d4d87596 JW |
58 | mov ecx, 0xc0000080 ; IA32_EFER MSR\r |
59 | rdmsr\r | |
8d4d55b1 | 60 | or eax, ebx ; set NXE bit if NX is available\r |
d4d87596 | 61 | wrmsr\r |
f0053e83 LE |
62 | mov eax, strict dword 0 ; source operand will be patched\r |
63 | ASM_PFX(gPatchSmmCr0):\r | |
e75ee972 | 64 | mov di, PROTECT_MODE_DS\r |
246cd908 | 65 | mov cr0, eax\r |
456c4cca | 66 | jmp PROTECT_MODE_CS : dword @32bit\r |
e75ee972 LE |
67 | \r |
68 | BITS 32\r | |
246cd908 LG |
69 | @32bit:\r |
70 | mov ds, edi\r | |
71 | mov es, edi\r | |
72 | mov fs, edi\r | |
73 | mov gs, edi\r | |
74 | mov ss, edi\r | |
75 | DB 0xbc ; mov esp, imm32\r | |
76 | ASM_PFX(gSmmInitStack): DD 0\r | |
77 | call ASM_PFX(SmmInitHandler)\r | |
78 | rsm\r | |
79 | \r | |
80 | BITS 16\r | |
81 | ASM_PFX(gcSmmInitTemplate):\r | |
82 | mov ebp, ASM_PFX(SmmStartup)\r | |
83 | sub ebp, 0x30000\r | |
84 | jmp ebp\r | |
85 | \r | |
86 | ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r | |
87 | \r | |
88 | BITS 32\r | |
89 | global ASM_PFX(SmmRelocationSemaphoreComplete)\r | |
90 | ASM_PFX(SmmRelocationSemaphoreComplete):\r | |
91 | push eax\r | |
92 | mov eax, [ASM_PFX(mRebasedFlag)]\r | |
93 | mov byte [eax], 1\r | |
94 | pop eax\r | |
95 | jmp [ASM_PFX(mSmmRelocationOriginalAddress)]\r | |
e21e355e LG |
96 | \r |
97 | global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r | |
98 | ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r | |
99 | ret\r |