UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr3" with PatchInstructionX86()
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmmInit.nasm
CommitLineData
246cd908 1;------------------------------------------------------------------------------ ;\r
e21e355e 2; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
246cd908
LG
3; This program and the accompanying materials\r
4; are licensed and made available under the terms and conditions of the BSD License\r
5; which accompanies this distribution. The full text of the license may be found at\r
6; http://opensource.org/licenses/bsd-license.php.\r
7;\r
8; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
9; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
10;\r
11; Module Name:\r
12;\r
13; SmmInit.nasm\r
14;\r
15; Abstract:\r
16;\r
17; Functions for relocating SMBASE's for all processors\r
18;\r
19;-------------------------------------------------------------------------------\r
20\r
21extern ASM_PFX(SmmInitHandler)\r
22extern ASM_PFX(mRebasedFlag)\r
23extern ASM_PFX(mSmmRelocationOriginalAddress)\r
24\r
6b0841c1 25global ASM_PFX(gPatchSmmCr3)\r
246cd908
LG
26global ASM_PFX(gSmmCr4)\r
27global ASM_PFX(gSmmCr0)\r
28global ASM_PFX(gSmmJmpAddr)\r
29global ASM_PFX(gSmmInitStack)\r
30global ASM_PFX(gcSmiInitGdtr)\r
31global ASM_PFX(gcSmmInitSize)\r
32global ASM_PFX(gcSmmInitTemplate)\r
33\r
34%define PROTECT_MODE_CS 0x8\r
35%define PROTECT_MODE_DS 0x20\r
36\r
37 SECTION .text\r
38\r
39ASM_PFX(gcSmiInitGdtr):\r
40 DW 0\r
41 DQ 0\r
42\r
43global ASM_PFX(SmmStartup)\r
e75ee972
LE
44\r
45BITS 16\r
246cd908 46ASM_PFX(SmmStartup):\r
d4d87596
JW
47 mov eax, 0x80000001 ; read capability\r
48 cpuid\r
d4d87596 49 mov ebx, edx ; rdmsr will change edx. keep it in ebx.\r
8d4d55b1
LE
50 and ebx, BIT20 ; extract NX capability bit\r
51 shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position\r
6b0841c1
LE
52 mov eax, strict dword 0 ; source operand will be patched\r
53ASM_PFX(gPatchSmmCr3):\r
246cd908 54 mov cr3, eax\r
e75ee972 55o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
994df209 56 DB 0x66, 0xb8 ; mov eax, imm32\r
246cd908
LG
57ASM_PFX(gSmmCr4): DD 0\r
58 mov cr4, eax\r
d4d87596
JW
59 mov ecx, 0xc0000080 ; IA32_EFER MSR\r
60 rdmsr\r
8d4d55b1 61 or eax, ebx ; set NXE bit if NX is available\r
d4d87596 62 wrmsr\r
994df209 63 DB 0x66, 0xb8 ; mov eax, imm32\r
246cd908 64ASM_PFX(gSmmCr0): DD 0\r
e75ee972 65 mov di, PROTECT_MODE_DS\r
246cd908 66 mov cr0, eax\r
994df209 67 DB 0x66, 0xea ; jmp far [ptr48]\r
246cd908
LG
68ASM_PFX(gSmmJmpAddr):\r
69 DD @32bit\r
70 DW PROTECT_MODE_CS\r
e75ee972
LE
71\r
72BITS 32\r
246cd908
LG
73@32bit:\r
74 mov ds, edi\r
75 mov es, edi\r
76 mov fs, edi\r
77 mov gs, edi\r
78 mov ss, edi\r
79 DB 0xbc ; mov esp, imm32\r
80ASM_PFX(gSmmInitStack): DD 0\r
81 call ASM_PFX(SmmInitHandler)\r
82 rsm\r
83\r
84BITS 16\r
85ASM_PFX(gcSmmInitTemplate):\r
86 mov ebp, ASM_PFX(SmmStartup)\r
87 sub ebp, 0x30000\r
88 jmp ebp\r
89\r
90ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r
91\r
92BITS 32\r
93global ASM_PFX(SmmRelocationSemaphoreComplete)\r
94ASM_PFX(SmmRelocationSemaphoreComplete):\r
95 push eax\r
96 mov eax, [ASM_PFX(mRebasedFlag)]\r
97 mov byte [eax], 1\r
98 pop eax\r
99 jmp [ASM_PFX(mSmmRelocationOriginalAddress)]\r
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LG
100\r
101global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
102ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
103 ret\r