[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
//\r
// SMM CPU Private Data structure that contains SMM Configuration Protocol\r
// along its supporting fields.\r
//\r
SMM_CPU_PRIVATE_DATA  mSmmCpuPrivateData = {\r
  SMM_CPU_PRIVATE_DATA_SIGNATURE,               // Signature\r
  NULL,                                         // SmmCpuHandle\r
  NULL,                                         // Pointer to ProcessorInfo array\r
  NULL,                                         // Pointer to Operation array\r
  NULL,                                         // Pointer to CpuSaveStateSize array\r
  NULL,                                         // Pointer to CpuSaveState array\r
  { {0} },                                      // SmmReservedSmramRegion\r
  {\r
    SmmStartupThisAp,                           // SmmCoreEntryContext.SmmStartupThisAp\r
    0,                                          // SmmCoreEntryContext.CurrentlyExecutingCpu\r
    0,                                          // SmmCoreEntryContext.NumberOfCpus\r
    NULL,                                       // SmmCoreEntryContext.CpuSaveStateSize\r
    NULL                                        // SmmCoreEntryContext.CpuSaveState\r
  },\r
  NULL,                                         // SmmCoreEntry\r
  {\r
    mSmmCpuPrivateData.SmmReservedSmramRegion,  // SmmConfiguration.SmramReservedRegions\r
    RegisterSmmEntry                            // SmmConfiguration.RegisterSmmEntry\r
  },\r
};\r
\r
CPU_HOT_PLUG_DATA mCpuHotPlugData = {\r
  CPU_HOT_PLUG_DATA_REVISION_1,                 // Revision\r
  0,                                            // Array Length of SmBase and APIC ID\r
  NULL,                                         // Pointer to APIC ID array\r
  NULL,                                         // Pointer to SMBASE array\r
  0,                                            // Reserved\r
  0,                                            // SmrrBase\r
  0                                             // SmrrSize\r
};\r
\r
//\r
// Global pointer used to access mSmmCpuPrivateData from outside and inside SMM\r
//\r
SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate = &mSmmCpuPrivateData;\r
\r
//\r
// SMM Relocation variables\r
//\r
volatile BOOLEAN  *mRebased;\r
volatile BOOLEAN  mIsBsp;\r
\r
///\r
/// Handle for the SMM CPU Protocol\r
///\r
EFI_HANDLE  mSmmCpuHandle = NULL;\r
\r
///\r
/// SMM CPU Protocol instance\r
///\r
EFI_SMM_CPU_PROTOCOL  mSmmCpu  = {\r
  SmmReadSaveState,\r
  SmmWriteSaveState\r
};\r
\r
EFI_CPU_INTERRUPT_HANDLER   mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
\r
///\r
/// SMM CPU Save State Protocol instance\r
///\r
EFI_SMM_CPU_SAVE_STATE_PROTOCOL  mSmmCpuSaveState = {\r
  NULL\r
};\r
\r
//\r
// SMM stack information\r
//\r
UINTN mSmmStackArrayBase;\r
UINTN mSmmStackArrayEnd;\r
UINTN mSmmStackSize;\r
\r
//\r
// Pointer to structure used during S3 Resume\r
//\r
SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;\r
\r
UINTN mMaxNumberOfCpus = 1;\r
UINTN mNumberOfCpus = 1;\r
\r
//\r
// SMM ready to lock flag\r
//\r
BOOLEAN mSmmReadyToLock = FALSE;\r
\r
//\r
// Global used to cache PCD for SMM Code Access Check enable\r
//\r
BOOLEAN                  mSmmCodeAccessCheckEnable = FALSE;\r
\r
//\r
// Spin lock used to serialize setting of SMM Code Access Check feature\r
//\r
SPIN_LOCK                mConfigSmmCodeAccessCheckLock;\r
\r
/**\r
  Initialize IDT to setup exception handlers for SMM.\r
\r
**/\r
VOID\r
InitializeSmmIdt (\r
  VOID\r
  )\r
{\r
  EFI_STATUS               Status;\r
  BOOLEAN                  InterruptState;\r
  IA32_DESCRIPTOR          DxeIdtr;\r
  //\r
  // Disable Interrupt and save DXE IDT table\r
  //\r
  InterruptState = SaveAndDisableInterrupts ();\r
  AsmReadIdtr (&DxeIdtr);\r
  //\r
  // Load SMM temporary IDT table\r
  //\r
  AsmWriteIdtr (&gcSmiIdtr);\r
  //\r
  // Setup SMM default exception handlers, SMM IDT table\r
  // will be updated and saved in gcSmiIdtr\r
  //\r
  Status = InitializeCpuExceptionHandlers (NULL);\r
  ASSERT_EFI_ERROR (Status);\r
  //\r
  // Restore DXE IDT table and CPU interrupt\r
  //\r
  AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);\r
  SetInterruptState (InterruptState);\r
}\r
\r
/**\r
  Search module name by input IP address and output it.\r
\r
  @param CallerIpAddress   Caller instruction pointer.\r
\r
**/\r
VOID\r
DumpModuleInfoByIp (\r
  IN  UINTN              CallerIpAddress\r
  )\r
{\r
  UINTN                                Pe32Data;\r
  EFI_IMAGE_DOS_HEADER                 *DosHdr;\r
  EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION  Hdr;\r
  VOID                                 *PdbPointer;\r
  UINT64                               DumpIpAddress;\r
\r
  //\r
  // Find Image Base\r
  //\r
  Pe32Data = CallerIpAddress & ~(SIZE_4KB - 1);\r
  while (Pe32Data != 0) {\r
    DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;\r
    if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {\r
      //\r
      // DOS image header is present, so read the PE header after the DOS image header.\r
      //\r
      Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));\r
      //\r
      // Make sure PE header address does not overflow and is less than the initial address.\r
      //\r
      if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CallerIpAddress)) {\r
        if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
          //\r
          // It's PE image.\r
          //\r
          break;\r
        }\r
      }\r
    }\r
\r
    //\r
    // Not found the image base, check the previous aligned address\r
    //\r
    Pe32Data -= SIZE_4KB;\r
  }\r
\r
  DumpIpAddress = CallerIpAddress;\r
  DEBUG ((EFI_D_ERROR, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress));\r
\r
  if (Pe32Data != 0) {\r
    PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);\r
    if (PdbPointer != NULL) {\r
      DEBUG ((EFI_D_ERROR, " in module (%a)", PdbPointer));\r
    }\r
  }\r
}\r
\r
/**\r
  Read information from the CPU save state.\r
\r
  @param  This      EFI_SMM_CPU_PROTOCOL instance\r
  @param  Width     The number of bytes to read from the CPU save state.\r
  @param  Register  Specifies the CPU register to read form the save state.\r
  @param  CpuIndex  Specifies the zero-based index of the CPU save state.\r
  @param  Buffer    Upon return, this holds the CPU register value read from the save state.\r
\r
  @retval EFI_SUCCESS   The register was read from Save State\r
  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
  @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmReadSaveState (\r
  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
  IN UINTN                              Width,\r
  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
  IN UINTN                              CpuIndex,\r
  OUT VOID                              *Buffer\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Retrieve pointer to the specified CPU's SMM Save State buffer\r
  //\r
  if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r
    //\r
    // The pseudo-register only supports the 64-bit size specified by Width.\r
    //\r
    if (Width != sizeof (UINT64)) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
    //\r
    // If the processor is in SMM at the time the SMI occurred,\r
    // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.\r
    // Otherwise, EFI_NOT_FOUND is returned.\r
    //\r
    if (mSmmMpSyncData->CpuData[CpuIndex].Present) {\r
      *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;\r
      return EFI_SUCCESS;\r
    } else {\r
      return EFI_NOT_FOUND;\r
    }\r
  }\r
\r
  if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  if (Status == EFI_UNSUPPORTED) {\r
    Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  }\r
  return Status;\r
}\r
\r
/**\r
  Write data to the CPU save state.\r
\r
  @param  This      EFI_SMM_CPU_PROTOCOL instance\r
  @param  Width     The number of bytes to read from the CPU save state.\r
  @param  Register  Specifies the CPU register to write to the save state.\r
  @param  CpuIndex  Specifies the zero-based index of the CPU save state\r
  @param  Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS   The register was written from Save State\r
  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
  @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmWriteSaveState (\r
  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
  IN UINTN                              Width,\r
  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
  IN UINTN                              CpuIndex,\r
  IN CONST VOID                         *Buffer\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Retrieve pointer to the specified CPU's SMM Save State buffer\r
  //\r
  if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  if (Status == EFI_UNSUPPORTED) {\r
    Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  }\r
  return Status;\r
}\r
\r
\r
/**\r
  C function for SMI handler. To change all processor's SMMBase Register.\r
\r
**/\r
VOID\r
EFIAPI\r
SmmInitHandler (\r
  VOID\r
  )\r
{\r
  UINT32                            ApicId;\r
  UINTN                             Index;\r
\r
  //\r
  // Update SMM IDT entries' code segment and load IDT\r
  //\r
  AsmWriteIdtr (&gcSmiIdtr);\r
  ApicId = GetApicId ();\r
\r
  ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
\r
  for (Index = 0; Index < mNumberOfCpus; Index++) {\r
    if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r
      //\r
      // Initialize SMM specific features on the currently executing CPU\r
      //\r
      SmmCpuFeaturesInitializeProcessor (\r
        Index,\r
        mIsBsp,\r
        gSmmCpuPrivate->ProcessorInfo,\r
        &mCpuHotPlugData\r
        );\r
\r
      if (mIsBsp) {\r
        //\r
        // BSP rebase is already done above.\r
        // Initialize private data during S3 resume\r
        //\r
        InitializeMpSyncData ();\r
      }\r
\r
      //\r
      // Hook return after RSM to set SMM re-based flag\r
      //\r
      SemaphoreHook (Index, &mRebased[Index]);\r
\r
      return;\r
    }\r
  }\r
  ASSERT (FALSE);\r
}\r
\r
/**\r
  Relocate SmmBases for each processor.\r
\r
  Execute on first boot and all S3 resumes\r
\r
**/\r
VOID\r
EFIAPI\r
SmmRelocateBases (\r
  VOID\r
  )\r
{\r
  UINT8                 BakBuf[BACK_BUF_SIZE];\r
  SMRAM_SAVE_STATE_MAP  BakBuf2;\r
  SMRAM_SAVE_STATE_MAP  *CpuStatePtr;\r
  UINT8                 *U8Ptr;\r
  UINT32                ApicId;\r
  UINTN                 Index;\r
  UINTN                 BspIndex;\r
\r
  //\r
  // Make sure the reserved size is large enough for procedure SmmInitTemplate.\r
  //\r
  ASSERT (sizeof (BakBuf) >= gcSmmInitSize);\r
\r
  //\r
  // Patch ASM code template with current CR0, CR3, and CR4 values\r
  //\r
  gSmmCr0 = (UINT32)AsmReadCr0 ();\r
  gSmmCr3 = (UINT32)AsmReadCr3 ();\r
  gSmmCr4 = (UINT32)AsmReadCr4 ();\r
\r
  //\r
  // Patch GDTR for SMM base relocation\r
  //\r
  gcSmiInitGdtr.Base  = gcSmiGdtr.Base;\r
  gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;\r
\r
  U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);\r
  CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
\r
  //\r
  // Backup original contents at address 0x38000\r
  //\r
  CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));\r
  CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));\r
\r
  //\r
  // Load image for relocation\r
  //\r
  CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);\r
\r
  //\r
  // Retrieve the local APIC ID of current processor\r
  //\r
  ApicId = GetApicId ();\r
\r
  //\r
  // Relocate SM bases for all APs\r
  // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate\r
  //\r
  mIsBsp   = FALSE;\r
  BspIndex = (UINTN)-1;\r
  for (Index = 0; Index < mNumberOfCpus; Index++) {\r
    mRebased[Index] = FALSE;\r
    if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r
      SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);\r
      //\r
      // Wait for this AP to finish its 1st SMI\r
      //\r
      while (!mRebased[Index]);\r
    } else {\r
      //\r
      // BSP will be Relocated later\r
      //\r
      BspIndex = Index;\r
    }\r
  }\r
\r
  //\r
  // Relocate BSP's SMM base\r
  //\r
  ASSERT (BspIndex != (UINTN)-1);\r
  mIsBsp = TRUE;\r
  SendSmiIpi (ApicId);\r
  //\r
  // Wait for the BSP to finish its 1st SMI\r
  //\r
  while (!mRebased[BspIndex]);\r
\r
  //\r
  // Restore contents at address 0x38000\r
  //\r
  CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));\r
  CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));\r
}\r
\r
/**\r
  Perform SMM initialization for all processors in the S3 boot path.\r
\r
  For a native platform, MP initialization in the S3 boot path is also performed in this function.\r
**/\r
VOID\r
EFIAPI\r
SmmRestoreCpu (\r
  VOID\r
  )\r
{\r
  SMM_S3_RESUME_STATE           *SmmS3ResumeState;\r
  IA32_DESCRIPTOR               Ia32Idtr;\r
  IA32_DESCRIPTOR               X64Idtr;\r
  IA32_IDT_GATE_DESCRIPTOR      IdtEntryTable[EXCEPTION_VECTOR_NUMBER];\r
  EFI_STATUS                    Status;\r
\r
  DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));\r
\r
  //\r
  // See if there is enough context to resume PEI Phase\r
  //\r
  if (mSmmS3ResumeState == NULL) {\r
    DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));\r
    CpuDeadLoop ();\r
  }\r
\r
  SmmS3ResumeState = mSmmS3ResumeState;\r
  ASSERT (SmmS3ResumeState != NULL);\r
\r
  if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {\r
    //\r
    // Save the IA32 IDT Descriptor\r
    //\r
    AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
\r
    //\r
    // Setup X64 IDT table\r
    //\r
    ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);\r
    X64Idtr.Base = (UINTN) IdtEntryTable;\r
    X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);\r
    AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);\r
\r
    //\r
    // Setup the default exception handler\r
    //\r
    Status = InitializeCpuExceptionHandlers (NULL);\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Initialize Debug Agent to support source level debug\r
    //\r
    InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);\r
  }\r
\r
  //\r
  // Do below CPU things for native platform only\r
  //\r
  if (!FeaturePcdGet(PcdFrameworkCompatibilitySupport)) {\r
    //\r
    // Skip initialization if mAcpiCpuData is not valid\r
    //\r
    if (mAcpiCpuData.NumberOfCpus > 0) {\r
      //\r
      // First time microcode load and restore MTRRs\r
      //\r
      EarlyInitializeCpu ();\r
    }\r
  }\r
\r
  //\r
  // Restore SMBASE for BSP and all APs\r
  //\r
  SmmRelocateBases ();\r
\r
  //\r
  // Do below CPU things for native platform only\r
  //\r
  if (!FeaturePcdGet(PcdFrameworkCompatibilitySupport)) {\r
    //\r
    // Skip initialization if mAcpiCpuData is not valid\r
    //\r
    if (mAcpiCpuData.NumberOfCpus > 0) {\r
      //\r
      // Restore MSRs for BSP and all APs\r
      //\r
      InitializeCpu ();\r
    }\r
  }\r
\r
  //\r
  // Set a flag to restore SMM configuration in S3 path.\r
  //\r
  mRestoreSmmConfigurationInS3 = TRUE;\r
\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return CS                = %x\n", SmmS3ResumeState->ReturnCs));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point       = %x\n", SmmS3ResumeState->ReturnEntryPoint));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Context1          = %x\n", SmmS3ResumeState->ReturnContext1));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Context2          = %x\n", SmmS3ResumeState->ReturnContext2));\r
  DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer     = %x\n", SmmS3ResumeState->ReturnStackPointer));\r
\r
  //\r
  // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase\r
  //\r
  if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {\r
    DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));\r
\r
    SwitchStack (\r
      (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,\r
      (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,\r
      (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,\r
      (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer\r
      );\r
  }\r
\r
  //\r
  // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase\r
  //\r
  if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {\r
    DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));\r
    //\r
    // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.\r
    //\r
    SaveAndSetDebugTimerInterrupt (FALSE);\r
    //\r
    // Restore IA32 IDT table\r
    //\r
    AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
    AsmDisablePaging64 (\r
      SmmS3ResumeState->ReturnCs,\r
      (UINT32)SmmS3ResumeState->ReturnEntryPoint,\r
      (UINT32)SmmS3ResumeState->ReturnContext1,\r
      (UINT32)SmmS3ResumeState->ReturnContext2,\r
      (UINT32)SmmS3ResumeState->ReturnStackPointer\r
      );\r
  }\r
\r
  //\r
  // Can not resume PEI Phase\r
  //\r
  DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));\r
  CpuDeadLoop ();\r
}\r
\r
/**\r
  Copy register table from ACPI NVS memory into SMRAM.\r
\r
  @param[in] DestinationRegisterTableList  Points to destination register table.\r
  @param[in] SourceRegisterTableList       Points to source register table.\r
  @param[in] NumberOfCpus                  Number of CPUs.\r
\r
**/\r
VOID\r
CopyRegisterTable (\r
  IN CPU_REGISTER_TABLE         *DestinationRegisterTableList,\r
  IN CPU_REGISTER_TABLE         *SourceRegisterTableList,\r
  IN UINT32                     NumberOfCpus\r
  )\r
{\r
  UINTN                      Index;\r
  UINTN                      Index1;\r
  CPU_REGISTER_TABLE_ENTRY   *RegisterTableEntry;\r
\r
  CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
  for (Index = 0; Index < NumberOfCpus; Index++) {\r
    DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);\r
    ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);\r
    CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);\r
    //\r
    // Go though all MSRs in register table to initialize MSR spin lock\r
    //\r
    RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;\r
    for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {\r
      if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {\r
        //\r
        // Initialize MSR spin lock only for those MSRs need bit field writing\r
        //\r
        InitMsrSpinLockByIndex (RegisterTableEntry->Index);\r
      }\r
    }\r
  }\r
}\r
\r
/**\r
  SMM Ready To Lock event notification handler.\r
\r
  The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to\r
  perform additional lock actions that must be performed from SMM on the next SMI.\r
\r
  @param[in] Protocol   Points to the protocol's unique identifier.\r
  @param[in] Interface  Points to the interface instance.\r
  @param[in] Handle     The handle on which the interface was installed.\r
\r
  @retval EFI_SUCCESS   Notification handler runs successfully.\r
 **/\r
EFI_STATUS\r
EFIAPI\r
SmmReadyToLockEventNotify (\r
  IN CONST EFI_GUID  *Protocol,\r
  IN VOID            *Interface,\r
  IN EFI_HANDLE      Handle\r
  )\r
{\r
  ACPI_CPU_DATA              *AcpiCpuData;\r
  IA32_DESCRIPTOR            *Gdtr;\r
  IA32_DESCRIPTOR            *Idtr;\r
\r
  //\r
  // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0\r
  //\r
  mAcpiCpuData.NumberOfCpus = 0;\r
\r
  //\r
  // If FrameworkCompatibilitySspport is enabled, then do not copy CPU S3 Data into SMRAM\r
  //\r
  if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
    goto Done;\r
  }\r
\r
  //\r
  // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM\r
  //\r
  AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);\r
  if (AcpiCpuData == 0) {\r
    goto Done;\r
  }\r
\r
  //\r
  // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.\r
  //\r
  CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));\r
\r
  mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));\r
  ASSERT (mAcpiCpuData.MtrrTable != 0);\r
\r
  CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));\r
\r
  mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));\r
  ASSERT (mAcpiCpuData.GdtrProfile != 0);\r
\r
  CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));\r
\r
  mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));\r
  ASSERT (mAcpiCpuData.IdtrProfile != 0);\r
\r
  CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));\r
\r
  mAcpiCpuData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
  ASSERT (mAcpiCpuData.PreSmmInitRegisterTable != 0);\r
\r
  CopyRegisterTable (\r
    (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable,\r
    (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->PreSmmInitRegisterTable,\r
    mAcpiCpuData.NumberOfCpus\r
    );\r
\r
  mAcpiCpuData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
  ASSERT (mAcpiCpuData.RegisterTable != 0);\r
\r
  CopyRegisterTable (\r
    (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable,\r
    (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTable,\r
    mAcpiCpuData.NumberOfCpus\r
    );\r
\r
  //\r
  // Copy AP's GDT, IDT and Machine Check handler into SMRAM.\r
  //\r
  Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;\r
  Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;\r
\r
  mGdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) +  mAcpiCpuData.ApMachineCheckHandlerSize);\r
  ASSERT (mGdtForAp != NULL);\r
  mIdtForAp = (VOID *) ((UINTN)mGdtForAp + (Gdtr->Limit + 1));\r
  mMachineCheckHandlerForAp = (VOID *) ((UINTN)mIdtForAp + (Idtr->Limit + 1));\r
\r
  CopyMem (mGdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);\r
  CopyMem (mIdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);\r
  CopyMem (mMachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);\r
\r
Done:\r
  //\r
  // Set SMM ready to lock flag and return\r
  //\r
  mSmmReadyToLock = TRUE;\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  The module Entry Point of the CPU SMM driver.\r
\r
  @param  ImageHandle    The firmware allocated handle for the EFI image.\r
  @param  SystemTable    A pointer to the EFI System Table.\r
\r
  @retval EFI_SUCCESS    The entry point is executed successfully.\r
  @retval Other          Some error occurs when executing this entry point.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PiCpuSmmEntry (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS                 Status;\r
  EFI_MP_SERVICES_PROTOCOL   *MpServices;\r
  UINTN                      NumberOfEnabledProcessors;\r
  UINTN                      Index;\r
  VOID                       *Buffer;\r
  UINTN                      TileSize;\r
  VOID                       *GuidHob;\r
  EFI_SMRAM_DESCRIPTOR       *SmramDescriptor;\r
  SMM_S3_RESUME_STATE        *SmmS3ResumeState;\r
  UINT8                      *Stacks;\r
  VOID                       *Registration;\r
  UINT32                     RegEax;\r
  UINT32                     RegEdx;\r
  UINTN                      FamilyId;\r
  UINTN                      ModelId;\r
  UINT32                     Cr3;\r
\r
  //\r
  // Initialize Debug Agent to support source level debug in SMM code\r
  //\r
  InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);\r
\r
  //\r
  // Report the start of CPU SMM initialization.\r
  //\r
  REPORT_STATUS_CODE (\r
    EFI_PROGRESS_CODE,\r
    EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT\r
    );\r
\r
  //\r
  // Fix segment address of the long-mode-switch jump\r
  //\r
  if (sizeof (UINTN) == sizeof (UINT64)) {\r
    gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;\r
  }\r
\r
  //\r
  // Find out SMRR Base and SMRR Size\r
  //\r
  FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);\r
\r
  //\r
  // Get MP Services Protocol\r
  //\r
  Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Use MP Services Protocol to retrieve the number of processors and number of enabled processors\r
  //\r
  Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);\r
  ASSERT_EFI_ERROR (Status);\r
  ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
\r
  //\r
  // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.\r
  // A constant BSP index makes no sense because it may be hot removed.\r
  //\r
  DEBUG_CODE (\r
    if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
\r
      ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));\r
    }\r
  );\r
\r
  //\r
  // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.\r
  //\r
  mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);\r
  DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));\r
\r
  //\r
  // If support CPU hot plug, we need to allocate resources for possibly hot-added processors\r
  //\r
  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
    mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
  } else {\r
    mMaxNumberOfCpus = mNumberOfCpus;\r
  }\r
  gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;\r
\r
  //\r
  // The CPU save state and code for the SMI entry point are tiled within an SMRAM\r
  // allocated buffer.  The minimum size of this buffer for a uniprocessor system\r
  // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area\r
  // just below SMBASE + 64KB.  If more than one CPU is present in the platform,\r
  // then the SMI entry point and the CPU save state areas can be tiles to minimize\r
  // the total amount SMRAM required for all the CPUs.  The tile size can be computed\r
  // by adding the   // CPU save state size, any extra CPU specific context, and\r
  // the size of code that must be placed at the SMI entry point to transfer\r
  // control to a C function in the native SMM execution mode.  This size is\r
  // rounded up to the nearest power of 2 to give the tile size for a each CPU.\r
  // The total amount of memory required is the maximum number of CPUs that\r
  // platform supports times the tile size.  The picture below shows the tiling,\r
  // where m is the number of tiles that fit in 32KB.\r
  //\r
  //  +-----------------------------+  <-- 2^n offset from Base of allocated buffer\r
  //  |   CPU m+1 Save State        |\r
  //  +-----------------------------+\r
  //  |   CPU m+1 Extra Data        |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 2m  SMI Entry         |\r
  //  +#############################+  <-- Base of allocated buffer + 64 KB\r
  //  |   CPU m-1 Save State        |\r
  //  +-----------------------------+\r
  //  |   CPU m-1 Extra Data        |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 2m-1 SMI Entry        |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   . . . . . . . . . . . .   |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   CPU 2 Save State          |\r
  //  +-----------------------------+\r
  //  |   CPU 2 Extra Data          |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU m+1 SMI Entry         |\r
  //  +=============================+  <-- Base of allocated buffer + 32 KB\r
  //  |   CPU 1 Save State          |\r
  //  +-----------------------------+\r
  //  |   CPU 1 Extra Data          |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU m SMI Entry           |\r
  //  +#############################+  <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB\r
  //  |   CPU 0 Save State          |\r
  //  +-----------------------------+\r
  //  |   CPU 0 Extra Data          |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU m-1 SMI Entry         |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   . . . . . . . . . . . .   |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 1 SMI Entry           |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 0 SMI Entry           |\r
  //  +#############################+  <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB\r
  //\r
\r
  //\r
  // Retrieve CPU Family\r
  //\r
  AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
  FamilyId = (RegEax >> 8) & 0xf;\r
  ModelId = (RegEax >> 4) & 0xf;\r
  if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
    ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
  }\r
\r
  //\r
  // Determine the mode of the CPU at the time an SMI occurs\r
  //   Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
  //   Volume 3C, Section 34.4.1.1\r
  //\r
  mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;\r
  if ((RegEdx & BIT29) != 0) {\r
    mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r
  }\r
  if (FamilyId == 0x06) {\r
    if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {\r
      mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r
    }\r
  }\r
\r
  //\r
  // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU\r
  // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point.  This size\r
  // is rounded up to nearest power of 2.\r
  //\r
  TileSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR) + GetSmiHandlerSize () - 1;\r
  TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
  DEBUG ((EFI_D_INFO, "SMRAM TileSize = %08x\n", TileSize));\r
\r
  //\r
  // If the TileSize is larger than space available for the SMI Handler of CPU[i],\r
  // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],\r
  // the ASSERT().  If this ASSERT() is triggered, then the SMI Handler size must be\r
  // reduced.\r
  //\r
  ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));\r
\r
  //\r
  // Allocate buffer for all of the tiles.\r
  //\r
  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
  // Volume 3C, Section 34.11 SMBASE Relocation\r
  //   For Pentium and Intel486 processors, the SMBASE values must be\r
  //   aligned on a 32-KByte boundary or the processor will enter shutdown\r
  //   state during the execution of a RSM instruction.\r
  //\r
  // Intel486 processors: FamilyId is 4\r
  // Pentium processors : FamilyId is 5\r
  //\r
  if ((FamilyId == 4) || (FamilyId == 5)) {\r
    Buffer = AllocateAlignedPages (EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)), SIZE_32KB);\r
  } else {\r
    Buffer = AllocatePages (EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)));\r
  }\r
  ASSERT (Buffer != NULL);\r
\r
  //\r
  // Allocate buffer for pointers to array in  SMM_CPU_PRIVATE_DATA.\r
  //\r
  gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);\r
\r
  gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->Operation != NULL);\r
\r
  gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);\r
\r
  gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);\r
\r
  mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;\r
  mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState     = gSmmCpuPrivate->CpuSaveState;\r
  mSmmCpuSaveState.CpuSaveState = (EFI_SMM_CPU_STATE **)gSmmCpuPrivate->CpuSaveState;\r
\r
  //\r
  // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.\r
  //\r
  mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);\r
  ASSERT (mCpuHotPlugData.ApicId != NULL);\r
  mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r
  ASSERT (mCpuHotPlugData.SmBase != NULL);\r
  mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;\r
\r
  //\r
  // Retrieve APIC ID of each enabled processor from the MP Services protocol.\r
  // Also compute the SMBASE address, CPU Save State address, and CPU Save state\r
  // size for each CPU in the platform\r
  //\r
  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
    mCpuHotPlugData.SmBase[Index]          = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;\r
    gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);\r
    gSmmCpuPrivate->CpuSaveState[Index]     = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);\r
    gSmmCpuPrivate->Operation[Index] = SmmCpuNone;\r
\r
    if (Index < mNumberOfCpus) {\r
      Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);\r
      ASSERT_EFI_ERROR (Status);\r
      mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;\r
\r
      DEBUG ((EFI_D_INFO, "CPU[%03x]  APIC ID=%04x  SMBASE=%08x  SaveState=%08x  Size=%08x\n",\r
        Index,\r
        (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,\r
        mCpuHotPlugData.SmBase[Index],\r
        gSmmCpuPrivate->CpuSaveState[Index],\r
        gSmmCpuPrivate->CpuSaveStateSize[Index]\r
        ));\r
    } else {\r
      gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;\r
      mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;\r
    }\r
  }\r
\r
  //\r
  // Allocate SMI stacks for all processors.\r
  //\r
  if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
    //\r
    // 2 more pages is allocated for each processor.\r
    // one is guard page and the other is known good stack.\r
    //\r
    // +-------------------------------------------+-----+-------------------------------------------+\r
    // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |\r
    // +-------------------------------------------+-----+-------------------------------------------+\r
    // |                                           |     |                                           |\r
    // |<-------------- Processor 0 -------------->|     |<-------------- Processor n -------------->|\r
    //\r
    mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2);\r
    Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2));\r
    ASSERT (Stacks != NULL);\r
    mSmmStackArrayBase = (UINTN)Stacks;\r
    mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize - 1;\r
  } else {\r
    mSmmStackSize = PcdGet32 (PcdCpuSmmStackSize);\r
    Stacks = (UINT8 *) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize));\r
    ASSERT (Stacks != NULL);\r
  }\r
\r
  //\r
  // Set SMI stack for SMM base relocation\r
  //\r
  gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));\r
\r
  //\r
  // Initialize IDT\r
  //\r
  InitializeSmmIdt ();\r
\r
  //\r
  // Relocate SMM Base addresses to the ones allocated from SMRAM\r
  //\r
  mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);\r
  ASSERT (mRebased != NULL);\r
  SmmRelocateBases ();\r
\r
  //\r
  // Call hook for BSP to perform extra actions in normal mode after all\r
  // SMM base addresses have been relocated on all CPUs\r
  //\r
  SmmCpuFeaturesSmmRelocationComplete ();\r
\r
  //\r
  // SMM Time initialization\r
  //\r
  InitializeSmmTimer ();\r
\r
  //\r
  // Initialize MP globals\r
  //\r
  Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize);\r
\r
  //\r
  // Fill in SMM Reserved Regions\r
  //\r
  gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;\r
  gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize  = 0;\r
\r
  //\r
  // Install the SMM Configuration Protocol onto a new handle on the handle database.\r
  // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer\r
  // to an SMRAM address will be present in the handle database\r
  //\r
  Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (\r
                                        &gSmmCpuPrivate->SmmCpuHandle,\r
                                        &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,\r
                                        NULL\r
                                        );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Install the SMM CPU Protocol into SMM protocol database\r
  //\r
  Status = gSmst->SmmInstallProtocolInterface (\r
                    &mSmmCpuHandle,\r
                    &gEfiSmmCpuProtocolGuid,\r
                    EFI_NATIVE_INTERFACE,\r
                    &mSmmCpu\r
                    );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.\r
  //\r
  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
    Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  //\r
  // Initialize SMM CPU Services Support\r
  //\r
  Status = InitializeSmmCpuServices (mSmmCpuHandle);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
    //\r
    // Install Framework SMM Save State Protocol into UEFI protocol database for backward compatibility\r
    //\r
    Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (\r
                                          &gSmmCpuPrivate->SmmCpuHandle,\r
                                          &gEfiSmmCpuSaveStateProtocolGuid,\r
                                          &mSmmCpuSaveState,\r
                                          NULL\r
                                          );\r
    ASSERT_EFI_ERROR (Status);\r
    //\r
    // The SmmStartupThisAp service in Framework SMST should always be non-null.\r
    // Update SmmStartupThisAp pointer in PI SMST here so that PI/Framework SMM thunk\r
    // can have it ready when constructing Framework SMST.\r
    //\r
    gSmst->SmmStartupThisAp = SmmStartupThisAp;\r
  }\r
\r
  //\r
  // register SMM Ready To Lock Protocol notification\r
  //\r
  Status = gSmst->SmmRegisterProtocolNotify (\r
                    &gEfiSmmReadyToLockProtocolGuid,\r
                    SmmReadyToLockEventNotify,\r
                    &Registration\r
                    );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);\r
  if (GuidHob != NULL) {\r
    SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);\r
\r
    DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));\r
    DEBUG ((EFI_D_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));\r
\r
    SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;\r
    ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));\r
\r
    mSmmS3ResumeState = SmmS3ResumeState;\r
    SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;\r
\r
    SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;\r
\r
    SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;\r
    SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));\r
    if (SmmS3ResumeState->SmmS3StackBase == 0) {\r
      SmmS3ResumeState->SmmS3StackSize = 0;\r
    }\r
\r
    SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;\r
    SmmS3ResumeState->SmmS3Cr3 = Cr3;\r
    SmmS3ResumeState->SmmS3Cr4 = gSmmCr4;\r
\r
    if (sizeof (UINTN) == sizeof (UINT64)) {\r
      SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;\r
    }\r
    if (sizeof (UINTN) == sizeof (UINT32)) {\r
      SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;\r
    }\r
  }\r
\r
  //\r
  // Check XD and BTS features\r
  //\r
  CheckProcessorFeature ();\r
\r
  //\r
  // Initialize SMM Profile feature\r
  //\r
  InitSmmProfile (Cr3);\r
\r
  //\r
  // Patch SmmS3ResumeState->SmmS3Cr3\r
  //\r
  InitSmmS3Cr3 ();\r
\r
  DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
\r
  Find out SMRAM information including SMRR base and SMRR size.\r
\r
  @param          SmrrBase          SMRR base\r
  @param          SmrrSize          SMRR size\r
\r
**/\r
VOID\r
FindSmramInfo (\r
  OUT UINT32   *SmrrBase,\r
  OUT UINT32   *SmrrSize\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  UINTN                             Size;\r
  EFI_SMM_ACCESS2_PROTOCOL          *SmmAccess;\r
  EFI_SMRAM_DESCRIPTOR              *CurrentSmramRange;\r
  EFI_SMRAM_DESCRIPTOR              *SmramRanges;\r
  UINTN                             SmramRangeCount;\r
  UINTN                             Index;\r
  UINT64                            MaxSize;\r
  BOOLEAN                           Found;\r
\r
  //\r
  // Get SMM Access Protocol\r
  //\r
  Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Get SMRAM information\r
  //\r
  Size = 0;\r
  Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r
  ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
\r
  SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r
  ASSERT (SmramRanges != NULL);\r
\r
  Status = SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r
\r
  //\r
  // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size\r
  //\r
  CurrentSmramRange = NULL;\r
  for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < SmramRangeCount; Index++) {\r
    //\r
    // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r
    //\r
    if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
      continue;\r
    }\r
\r
    if (SmramRanges[Index].CpuStart >= BASE_1MB) {\r
      if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <= BASE_4GB) {\r
        if (SmramRanges[Index].PhysicalSize >= MaxSize) {\r
          MaxSize = SmramRanges[Index].PhysicalSize;\r
          CurrentSmramRange = &SmramRanges[Index];\r
        }\r
      }\r
    }\r
  }\r
\r
  ASSERT (CurrentSmramRange != NULL);\r
\r
  *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;\r
  *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;\r
\r
  do {\r
    Found = FALSE;\r
    for (Index = 0; Index < SmramRangeCount; Index++) {\r
      if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase == (SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) {\r
        *SmrrBase = (UINT32)SmramRanges[Index].CpuStart;\r
        *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);\r
        Found = TRUE;\r
      } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart && SmramRanges[Index].PhysicalSize > 0) {\r
        *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);\r
        Found = TRUE;\r
      }\r
    }\r
  } while (Found);\r
\r
  DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));\r
}\r
\r
/**\r
Configure SMM Code Access Check feature on an AP.\r
SMM Feature Control MSR will be locked after configuration.\r
\r
@param[in,out] Buffer  Pointer to private data buffer.\r
**/\r
VOID\r
EFIAPI\r
ConfigSmmCodeAccessCheckOnCurrentProcessor (\r
  IN OUT VOID  *Buffer\r
  )\r
{\r
  UINTN   CpuIndex;\r
  UINT64  SmmFeatureControlMsr;\r
  UINT64  NewSmmFeatureControlMsr;\r
\r
  //\r
  // Retrieve the CPU Index from the context passed in\r
  //\r
  CpuIndex = *(UINTN *)Buffer;\r
\r
  //\r
  // Get the current SMM Feature Control MSR value\r
  //\r
  SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);\r
\r
  //\r
  // Compute the new SMM Feature Control MSR value\r
  //\r
  NewSmmFeatureControlMsr = SmmFeatureControlMsr;\r
  if (mSmmCodeAccessCheckEnable) {\r
    NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;\r
  }\r
  if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r
    NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;\r
  }\r
\r
  //\r
  // Only set the SMM Feature Control MSR value if the new value is different than the current value\r
  //\r
  if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {\r
    SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);\r
  }\r
\r
  //\r
  // Release the spin lock user to serialize the updates to the SMM Feature Control MSR\r
  //\r
  ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock);\r
}\r
\r
/**\r
Configure SMM Code Access Check feature for all processors.\r
SMM Feature Control MSR will be locked after configuration.\r
**/\r
VOID\r
ConfigSmmCodeAccessCheck (\r
  VOID\r
  )\r
{\r
  UINTN       Index;\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Check to see if the Feature Control MSR is supported on this CPU\r
  //\r
  Index = gSmst->CurrentlyExecutingCpu;\r
  if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {\r
    mSmmCodeAccessCheckEnable = FALSE;\r
    return;\r
  }\r
\r
  //\r
  // Check to see if the CPU supports the SMM Code Access Check feature\r
  // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
  //\r
  if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {\r
    mSmmCodeAccessCheckEnable = FALSE;\r
  }\r
\r
  //\r
  // If the SMM Code Access Check feature is disabled and the Feature Control MSR\r
  // is not being locked, then no additional work is required\r
  //\r
  if (!mSmmCodeAccessCheckEnable && !FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r
    return;\r
  }\r
\r
  //\r
  // Initialize the lock used to serialize the MSR programming in BSP and all APs\r
  //\r
  InitializeSpinLock (&mConfigSmmCodeAccessCheckLock);\r
\r
  //\r
  // Acquire Config SMM Code Access Check spin lock.  The BSP will release the\r
  // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r
  //\r
  AcquireSpinLock (&mConfigSmmCodeAccessCheckLock);\r
\r
  //\r
  // Enable SMM Code Access Check feature on the BSP.\r
  //\r
  ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);\r
\r
  //\r
  // Enable SMM Code Access Check feature for the APs.\r
  //\r
  for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
    if (Index != gSmst->CurrentlyExecutingCpu) {\r
\r
      //\r
      // Acquire Config SMM Code Access Check spin lock.  The AP will release the\r
      // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r
      //\r
      AcquireSpinLock (&mConfigSmmCodeAccessCheckLock);\r
\r
      //\r
      // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.\r
      //\r
      Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);\r
      ASSERT_EFI_ERROR (Status);\r
\r
      //\r
      // Wait for the AP to release the Config SMM Code Access Check spin lock.\r
      //\r
      while (!AcquireSpinLockOrFail (&mConfigSmmCodeAccessCheckLock)) {\r
        CpuPause ();\r
      }\r
\r
      //\r
      // Release the Config SMM Code Access Check spin lock.\r
      //\r
      ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock);\r
    }\r
  }\r
}\r
\r
/**\r
  Perform the remaining tasks.\r
\r
**/\r
VOID\r
PerformRemainingTasks (\r
  VOID\r
  )\r
{\r
  if (mSmmReadyToLock) {\r
    //\r
    // Start SMM Profile feature\r
    //\r
    if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
      SmmProfileStart ();\r
    }\r
    //\r
    // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.\r
    //\r
    InitPaging ();\r
    //\r
    // Configure SMM Code Access Check feature if available.\r
    //\r
    ConfigSmmCodeAccessCheck ();\r
\r
    //\r
    // Clean SMM ready to lock flag\r
    //\r
    mSmmReadyToLock = FALSE;\r
  }\r
}\r